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Angel_CY
UMA Schematics Document
IVY Bridge
D D

co Intel PCH
nfi
de
nti

m
al,

.co
C C

DY :None Installed ANNIE: ONLY FOR ANNIE solution.


DIS:DIS installed
re PSL: KBC795 PSL circuit for 10mW solution installed.

fix
10mW: External circuit for 10mW solution installed.

DIS_PX:BOTH DIS or PX installed fer


DIS_Muxless :BOTH DIS or Muxless installed 65W: for 65W adaptor installed.
90W: for 90W adaptor installed.

se
DIS_PX_Muxless:DIS or PX or Muxless installed.
Muxless: Muxless installed.(PX4.0) by
.ro An
PX:MUX installed.(PX3.0)
B PX_Muxless:BOTH PX or Muxless installed.
w B

UMA:UMA installed
nie
w
UMA_Muxless:BOTH UMA or Muxless installed
UMA_PX_Muxless:UMA or PX or Muxless installed
CS
w

D
Wistron Confidential document, Anyone can not Duplicate,
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Wistron permission

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Wistron Corporation
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Title

Cover Page
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 1 of 102
5 4 3 2 1
5 4 3 2 1

SYSTEM DC/DC
Project code : 91.4LJ01.001 BQ24727 40
INPUTS OUTPUTS
PCB P/N :
DCBATOUT BT+
Revision : 12313-1 SYSTEM DC/DC

D
Angel-CY Block Diagram INPUTS
TPS51225
OUTPUTS
41

co
5V_AUX_S5
RAM x 16 14 3D3V_AUX_S5
DCBATOUT 5V_S5
3D3V_S5

Intel CPU CPU DC/DC

nfi
RAM x 16 14 42~44
DDR3L-SO DIMM DDRIII 1066/1333 Channel B DDRIII 1066/1333 Channel A
TPS51640
15 INPUTS OUTPUTS
IVY-Bridge VCC_CORE

de
RAM x 16 14 DCBATOUT
FSB: 1066 MHz VCC_GFXCORE

RAM x 16 14
SYSTEM DC/DC
TPS51363 45

Panel 49
eDP

nti 4,5,6,7,8,9,10,11,12,13
INPUTS
DCBATOUT
OUTPUTS
1D05V_VTT

al,
SYSTEM DC/DC
RT8207 46

C
FDIx4x2 DMIx4 INPUTS OUTPUTS C
1D35V_S3
DCBATOUT 0D675V_S0

r
DDR_VREF_S3

efe
26
SYSTEM DC/DC
DP
Intel PCIE x1 WLAN on Board SYW232 47
USB x1 802.11a/b/g 3 INPUTS OUTPUTS
mDP
PCH HM77

r
USB3.0 x 1+ USB2.0 x 1 3D3V_S0 1D8V_S0
52 Cougar Point SYSTEM LOD

by
USB 3.0 ports (4) Card Reader S-1339D 47
USB x 1
USB 2.0 ports (14) SD/MMC INPUTS OUTPUTS
RTS5170
USB3.0 x 1 High Definition Audio
2 1D8V_S0 1D5V_S0
SATA ports (6)

An
USB 3.0x 1 SYSTEM DC/DC
PCIE 2.0 ports (8)
USB2.0 x 1 SY8037 48
63 LPC I/F
INPUTS OUTPUTS
B ACPI 1.1 SATA x1 HDD 56 B
5V_S5 0D85V_S0

Camera / Touch Sensor


49
USB2.0 x 1

17,18,19,20,21,22,23,24,25,26
nie PCB LAYER
L1:Top
L2:VCC
L3:Signal
L5:Signal
L6:Signal
L7:GND

CS
L4:GND L8:Bottom
USB 2.0x 1 USB2.0 x 1 AZALIA
SPI

LPC Bus

D
Combo Mic
82 Flash ROM LPC debug port
Azalia 8MB 60 71

CODEC Wistron Confidential document, Anyone can not Duplicate,


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A <Variant Name> A

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Speaker(1W) Title
Thermal
Touch Int. NCT7718W Block Diagram
Fan 28 Size Document Number Rev
PAD69 KB69 28 A3
25 Angel-CY 1
Date: Monday, April 22, 2013 Sheet 2 of 102
5 4 3 2 1
A B C D E
PCH Strapping Huron River Schematic Checklist Rev.0_7 Processor Strapping Huron River Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ CFG[2] PCI-Express Static 1: Normal Operation.
- 10-kΩ weak pull-up resistor. Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Lane Reversal 0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
4 GNT2#/GPIO53 Mobile: Used as GPIO only 0 4

co
GNT1#/GPIO51 Pull-up resistors are not required on these signals. Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. 10 : x8, x8 - Device 1 function 1 enabled ;

nfi
Port Bifurcation
SPI_MOSI function 2 disabled
Straps 11
Disable Danbury:Left floating, no pull-down required. 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2

de
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
0: PEG Wait for BIOS for training
Disable Danbury:Leave floating (internal pull-down)

NC_CLE

nti
DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,

al,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
/GPIO[33]
3 the desired settings. If a jumper option is used to tie this signal to GND as 5V_S0
3D3V_S0
5V
3.3V 3
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V

r
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal

efe
0D85V_S0 0.95 - 0.85V
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 0D75V_S0 0.75V
strapping functions. VCC_CORE 0.35V to 1.5V
VCC_GFXCORE 0.4 to 1.25V S0
1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V CPU Core Rail
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1V_VGA_S0 1V Graphics Core Rail

r
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5V_USBX_S3 5V
GPIO15 1D5V_S3 1.5V S3

by
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher DDR_VREF_S3 0.75V
suite with confidentiality
Note : This is an un-muxed signal.
BT+ 6V-14.1V AC Brick Mode only
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. DCBATOUT 6V-14.1V
Sampled at rising edge of RSMRST#. 5V_S5 5V All S states
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_AUX_S5 5V

An
3D3V_S5 3.3V
3D3V_AUX_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
2 2

nie
Default = Do not connect (floating) 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
High(1) = Enables the internal VccVRM to have a clean supply for
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter Powered by Li Coin Cell in G3
circuits for analog rails. 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx

CS
USB Table
Pair Device
SMBus ADDRESSES
PCIE Routing 0 Touch Panel / 3G SIM

D
1 USB Ext. port 1 (HS) I 2 C / SMBus Addresses
HURON RIVER ORB
2 Fingerprint Device Ref Des Address Hex Bus
LANE1 Mini Card2(WWAN)
3 BLUETOOTH EC SMBus 1 BAT_SCL/BAT_SDA
LANE2 Mini Card1(WLAN) SATA Table 4 Mini Card2 (WWAN) Battery BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA
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6 X PCH
Pair Device SML1_CLK/SML1_DATA
LANE4 Onboard LAN 7 X
eDP
SML1_CLK/SML1_DATA
1 <Variant Name>
1
0 HDD1 8 USB Ext. port 4 / E-SATA /USB CHARGER
LANE5 USB3.0
1 HDD2 9 USB Ext. port 2 PCH SMBus
PCH_SMBDATA/PCH_SMBCLK
Wistron Corporation
SO-DIMMA (SPD) 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
LANE6 Intel GBE LAN 2 N/A 10 EDP CAMERA SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
Digital Pot PCH_SMBDATA/PCH_SMBCLK
G-Sensor PCH_SMBDATA/PCH_SMBCLK Title
LANE7 Dock 3 N/A 11 Mini Card1 (WLAN) MINI PCH_SMBDATA/PCH_SMBCLK
4 ODD 12 CAMERA PCH_SMBDATA/PCH_SMBCLK Table of Content
Size Document Number Rev
LANE8 New Card 5 ESATA 13 New Card A3
1
Angel-CY
Monday, April 22, 2013
Date: Sheet 3 of 102
5 4 3 2 1
SSID = CPU

1D05V_VTT

CPU2A 1 OF 9
G3 PEG_IRCOMP_R 1 R401 2
PEG_ICOMPI 24D9R2F-L-GP
19 DMI_TXN[3:0] PEG_ICOMPO G1
D DMI_TXN0
DMI_TXN1
M2
P6
DMI_RX#0 PEG_RCOMPO G4 D
DMI_TXN2 DMI_RX#1
P1 DMI_RX#2
DMI_TXN3 P10 H22
DMI_RX#3 PEG_RX#0
19 DMI_TXP[3:0] PEG_RX#1 J21
DMI_TXP0 N3 B22
DMI_TXP1 DMI_RX0 PEG_RX#2
P7 DMI_RX1 PEG_RX#3 D21

DMI
DMI_TXP2 P3 A19
DMI_TXP3 DMI_RX2 PEG_RX#4
P11 DMI_RX3 PEG_RX#5 D17
19 DMI_RXN[3:0] PEG_RX#6 B14
DMI_RXN0 K1 D13
DMI_RXN1 DMI_TX#0 PEG_RX#7
M8 DMI_TX#1 PEG_RX#8 A11
DMI_RXN2 N4 B10
DMI_RXN3 DMI_TX#2 PEG_RX#9
R2 DMI_TX#3 PEG_RX#10 G8
19 DMI_RXP[3:0] PEG_RX#11 A8
DMI_RXP0 K3 B6
DMI_RXP1 DMI_TX0 PEG_RX#12
M7 DMI_TX1 PEG_RX#13 H8
DMI_RXP2 P4 E5
DMI_RXP3 DMI_TX2 PEG_RX#14
T3 DMI_TX3 PEG_RX#15 K7

PEG_RX0 K22
PEG_RX1 K19
19 FDI_TXN[7:0] PEG_RX2 C21
FDI_TXN0 U7 D19
FDI_TXN1 FDI0_TX#0 PEG_RX3
W11 FDI0_TX#1 PEG_RX4 C19
FDI_TXN2 W1 D16
FDI_TXN3 FDI0_TX#2 PEG_RX5
AA6 FDI0_TX#3 PEG_RX6 C13
FDI_TXN4 W6 D12
FDI_TXN5 FDI1_TX#0 PEG_RX7
V4 FDI1_TX#1 PEG_RX8 C11
C FDI_TXN6
C

PCI EXPRESS -- GRAPHICS


Y2 FDI1_TX#2 PEG_RX9 C9
FDI_TXN7 AC9 F8
FDI1_TX#3 PEG_RX10

Intel(R) FDI
PEG_RX11 C8
19 FDI_TXP[7:0] PEG_RX12 C5
FDI_TXP0 U6 H6
FDI_TXP1 FDI0_TX0 PEG_RX13
W10 FDI0_TX1 PEG_RX14 F6
FDI_TXP2 W3 K6
FDI_TXP3 FDI0_TX2 PEG_RX15
AA7 FDI0_TX3
FDI_TXP4 W7 G22
FDI_TXP5 FDI1_TX0 PEG_TX#0
T4 FDI1_TX1 PEG_TX#1 C23
FDI_TXP6 AA3 D23
FDI_TXP7 FDI1_TX2 PEG_TX#2
AC8 FDI1_TX3 PEG_TX#3 F21
PEG_TX#4 H19
19 FDI_FSYNC0 AA11 FDI0_FSYNC PEG_TX#5 C17
19 FDI_FSYNC1 AC12 FDI1_FSYNC PEG_TX#6 K15
PEG_TX#7 F17
19 FDI_INT U11 FDI_INT PEG_TX#8 F14
PEG_TX#9 A15
19 FDI_LSYNC0 AA10 FDI0_LSYNC PEG_TX#10 J14
19 FDI_LSYNC1 AG8 FDI1_LSYNC PEG_TX#11 H13
PEG_TX#12 M10
PEG_TX#13 F10
PEG_TX#14 D9
PEG_TX#15 J4
1D05V_VTT 1 R402 2 DP_COMP AF3 EDP_COMPIO
24D9R2F-L-GP AD2 F22
1D05V_VTT EDP_ICOMPO PEG_TX0
49 CPU_EDP_HPD# AG11 EDP_HPD# PEG_TX1 A23
PEG_TX2 D24
PEG_TX3 E21
AG4 G19
B 49 CPU_EDP_AUXN EDP_AUX# PEG_TX4 B
1

49 CPU_EDP_AUXP AF4 EDP_AUX PEG_TX5 B18


R403 K17
PEG_TX6

eDP
1KR2F-L1-GP PEG_TX7 G17
49 CPU_EDP_DATA0# AC3 EDP_TX#0 PEG_TX8 E14
49 CPU_EDP_DATA1# AC4 C15
2

EDP_TX#1 PEG_TX9
AE11 EDP_TX#2 PEG_TX10 K13
CPU_EDP_HPD# AE7 G13
EDP_TX#3 PEG_TX11
PEG_TX12 K10
49 CPU_EDP_DATA0 AC1 EDP_TX0 PEG_TX13 G10
49 CPU_EDP_DATA1 AA4 EDP_TX1 PEG_TX14 D8
AE10 EDP_TX2 PEG_TX15 K4
AE6 EDP_TX3

IVY-BRIDGE-GP-NF 71.00IVY.A0U

Wistron Confidential document, Anyone can not Duplicate,


Modify, Forward or any other purpose application without get
Wistron permission

A <Variant Name>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (PCIE/DMI/FDI)
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 4 of 102
5 4 3 2 1
SSID = CPU CPU2B 2 OF 9

BCLK J3 CLK_EXP_P 20
BCLK# H2 CLK_EXP_N 20

MISC

CLOCKS
1D05V_VTT F49
22 H_SNB_IVB# PROC_SELECT#
DPLL_REF_CLK AG3 CLK_DP_P 20
DPLL_REF_CLK# AG1 CLK_DP_N 20
1 R501 2 H_PROCHOT# C57 PROC_DETECT#
62R2J-GP 1
C502
SC47P50V2JN-3GP
D D
2

C49 CATERR#

THERMAL
SM_DRAMRST# 37

27 H_PECI A48 PECI SM_DRAMRST# AT30 2 R502 1


4K99R2F-L-GP

BF44 SM_RCOMP_0 R506 1 2 140R2F-GP


SM_RCOMP0

DDR3
MISC
27,40,42 H_PROCHOT# 1 R513 2 H_PROCHOT#_R C45 PROCHOT# SM_RCOMP1 BE43 SM_RCOMP_1 R507 1 2 25D5R2F-GP
56R2J-L1-GP BG43 SM_RCOMP_2 R508 1 2 200R2F-L1-GP
SM_RCOMP2

22,36 H_THERMTRIP# D45 THERMTRIP#

PRDY# N53
PREQ# N55

TCK L56
TMS L55

PWR MANAGEMENT
J58 XDP_TRST# 1D05V_VTT
TRST#

JTAG & BPM


C48 M60 XDP_TDO 2 3
19 H_PM_SYNC PM_SYNC TDI
L59 XDP_TDO XDP_TRST# 1 4
TDO
RN502
22,97 H_CPUPW RGD B46 SRN51J-GP
UNCOREPWRGOOD XDP_DBRESET#
DBR# K58
C 1 R503 2
10KR2J-L-GP C
37 VDDPW RGOOD BE45 SM_DRAMPWROK BPM#0 G58
BPM#1 E55
BPM#2 E59
BPM#3 G55
BPM#4 G59
BUF_CPU_RST# D44 H60
RESET# BPM#5
BPM#6 J59
BPM#7 J61

IVY-BRIDGE-GP-NF 71.00IVY.A0U
3D3V_S0

XDP_DBRESET# 1 8
2 7
3 6
18,27,36,65,71,77,97 PLT_RST# 4 5 BUF_CPU_RST#

RN503
SRN1K5J-1-GP

B B

Wistron Confidential document, Anyone can not Duplicate,


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A <Variant Name>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (THERMAL/CLOCK/PM )
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 5 of 102
5 4 3 2 1

SSID = CPU

CPU2C 3 OF 9
CPU2D 4 OF 9
14 M_A_DQ[63:0]
M_A_DQ0 AG6 SA_DQ0 15 M_B_DQ[63:0]
D M_A_DQ1 AJ6 AU36 M_B_DQ0 AL4 D
SA_DQ1 SA_CK0 M_A_DIM0_CLK_DDR0 14 SB_DQ0
M_A_DQ2 AP11 AV36 M_B_DQ1 AL1 BA34
SA_DQ2 SA_CK#0 M_A_DIM0_CLK_DDR#0 14 SB_DQ1 SB_CK0 M_B_DIM0_CLK_DDR0 15
M_A_DQ3 AL6 AY26 M_B_DQ2 AN3 AY34
SA_DQ3 SA_CKE0 M_A_DIM0_CKE0 14 SB_DQ2 SB_CK#0 M_B_DIM0_CLK_DDR#0 15
M_A_DQ4 AJ10 M_B_DQ3 AR4 AR22
M_A_DQ5 SA_DQ4 M_B_DQ4 SB_DQ3 SB_CKE0 M_B_DIM0_CKE0 15
AJ8 SA_DQ5 AK4 SB_DQ4
M_A_DQ6 AL8 M_B_DQ5 AK3
M_A_DQ7 SA_DQ6 M_B_DQ6 SB_DQ5
AL7 SA_DQ7 AN4 SB_DQ6
M_A_DQ8 AR11 M_B_DQ7 AR1
M_A_DQ9 SA_DQ8 M_B_DQ8 SB_DQ7
AP6 SA_DQ9 SA_CK1 AT40 AU4 SB_DQ8
M_A_DQ10 AU6 AU40 M_B_DQ9 AT2 BA36
M_A_DQ11 SA_DQ10 SA_CK#1 M_B_DQ10 SB_DQ9 SB_CK1 M_B_DIM0_CLK_DDR1 15
AV9 SA_DQ11 SA_CKE1 BB26 AV4 SB_DQ10 SB_CK#1 BB36 M_B_DIM0_CLK_DDR#1 15
M_A_DQ12 AR6 M_B_DQ11 BA4 BF27
M_A_DQ13 SA_DQ12 M_B_DQ12 SB_DQ11 SB_CKE1 M_B_DIM0_CKE1 15
AP8 SA_DQ13 AU3 SB_DQ12
M_A_DQ14 AT13 M_B_DQ13 AR3
M_A_DQ15 SA_DQ14 M_B_DQ14 SB_DQ13
AU13 SA_DQ15 AY2 SB_DQ14
M_A_DQ16 BC7 M_B_DQ15 BA3
M_A_DQ17 SA_DQ16 M_B_DQ16 SB_DQ15
BB7 SA_DQ17 SA_CS#0 BB40 M_A_DIM0_CS#0 14 BE9 SB_DQ16
M_A_DQ18 BA13 BC41 M_B_DQ17 BD9 BE41
M_A_DQ19 SA_DQ18 SA_CS#1 M_B_DQ18 SB_DQ17 SB_CS#0 M_B_DIM0_CS#0 15
BB11 SA_DQ19 BD13 SB_DQ18 SB_CS#1 BE47 M_B_DIM0_CS#1 15
M_A_DQ20 BA7 M_B_DQ19 BF12
M_A_DQ21 SA_DQ20 M_B_DQ20 SB_DQ19
BA9 SA_DQ21 BF8 SB_DQ20
M_A_DQ22 BB9 M_B_DQ21 BD10
M_A_DQ23 SA_DQ22 M_B_DQ22 SB_DQ21
AY13 SA_DQ23 BD14 SB_DQ22
M_A_DQ24 AV14 AY40 M_B_DQ23 BE13
SA_DQ24 SA_ODT0 M_A_DIM0_ODT0 14 SB_DQ23
M_A_DQ25 AR14 BA41 M_B_DQ24 BF16 AT43
M_A_DQ26 SA_DQ25 SA_ODT1 M_B_DQ25 SB_DQ24 SB_ODT0 M_B_DIM0_ODT0 15
AY17 SA_DQ26 BE17 SB_DQ25 SB_ODT1 BG47 M_B_DIM0_ODT1 15
M_A_DQ27 AR19 M_B_DQ26 BE18
M_A_DQ28 SA_DQ27 M_B_DQ27 SB_DQ26
BA14 SA_DQ28 BE21 SB_DQ27
M_A_DQ29 AU14 M_B_DQ28 BE14
C M_A_DQ30 SA_DQ29 M_B_DQ29 SB_DQ28 C
BB14 SA_DQ30 M_A_DQS#[7:0] 14 BG14 SB_DQ29
M_A_DQ31 BB17 AL11 M_A_DQS#0 M_B_DQ30 BG18 M_B_DQS#[7:0] 15
M_A_DQ32 SA_DQ31 SA_DQS#0 M_A_DQS#1 M_B_DQ31 SB_DQ30 M_B_DQS#0
BA45 SA_DQ32 SA_DQS#1 AR8 BF19 SB_DQ31 SB_DQS#0 AL3
M_A_DQ33 AR43 AV11 M_A_DQS#2 M_B_DQ32 BD50 AV3 M_B_DQS#1
M_A_DQ34 SA_DQ33 SA_DQS#2 M_A_DQS#3 M_B_DQ33 SB_DQ32 SB_DQS#1 M_B_DQS#2
AW48 SA_DQ34 SA_DQS#3 AT17 BF48 SB_DQ33 SB_DQS#2 BG11
M_A_DQ35 BC48 AV45 M_A_DQS#4 M_B_DQ34 BD53 BD17 M_B_DQS#3
M_A_DQ36 SA_DQ35 SA_DQS#4 M_A_DQS#5 M_B_DQ35 SB_DQ34 SB_DQS#3 M_B_DQS#4
BC45 SA_DQ36 SA_DQS#5 AY51 BF52 SB_DQ35 SB_DQS#4 BG51
M_A_DQ37 AR45 AT55 M_A_DQS#6 M_B_DQ36 BD49 BA59 M_B_DQS#5
SA_DQ37 SA_DQS#6 SB_DQ36 SB_DQS#5
DDR SYSTEM MEMORY A

M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ37 BE49 AT60 M_B_DQS#6


SA_DQ38 SA_DQS#7 SB_DQ37 SB_DQS#6

DDR SYSTEM MEMORY B


M_A_DQ39 AY48 M_B_DQ38 BD54 AK59 M_B_DQS#7
M_A_DQ40 SA_DQ39 M_B_DQ39 SB_DQ38 SB_DQS#7
BA49 SA_DQ40 BE53 SB_DQ39
M_A_DQ41 AV49 M_B_DQ40 BF56
M_A_DQ42 SA_DQ41 M_B_DQ41 SB_DQ40
BB51 SA_DQ42 BE57 SB_DQ41
M_A_DQ43 AY53 M_B_DQ42 BC59
M_A_DQ44 SA_DQ43 M_B_DQ43 SB_DQ42
BB49 SA_DQ44 M_A_DQS[7:0] 14 AY60 SB_DQ43
M_A_DQ45 AU49 AJ11 M_A_DQS0 M_B_DQ44 BE54
M_A_DQ46 SA_DQ45 SA_DQS0 M_A_DQS1 M_B_DQ45 SB_DQ44
BA53 SA_DQ46 SA_DQS1 AR10 BG54 SB_DQ45 M_B_DQS[7:0] 15
M_A_DQ47 BB55 AY11 M_A_DQS2 M_B_DQ46 BA58 AM2 M_B_DQS0
M_A_DQ48 SA_DQ47 SA_DQS2 M_A_DQS3 M_B_DQ47 SB_DQ46 SB_DQS0 M_B_DQS1
BA55 SA_DQ48 SA_DQS3 AU17 AW59 SB_DQ47 SB_DQS1 AV1
M_A_DQ49 AV56 AW45 M_A_DQS4 M_B_DQ48 AW58 BE11 M_B_DQS2
M_A_DQ50 SA_DQ49 SA_DQS4 M_A_DQS5 M_B_DQ49 SB_DQ48 SB_DQS2 M_B_DQS3
AP50 SA_DQ50 SA_DQS5 AV51 AU58 SB_DQ49 SB_DQS3 BD18
M_A_DQ51 AP53 AT56 M_A_DQS6 M_B_DQ50 AN61 BE51 M_B_DQS4
M_A_DQ52 SA_DQ51 SA_DQS6 M_A_DQS7 M_B_DQ51 SB_DQ50 SB_DQS4 M_B_DQS5
AV54 SA_DQ52 SA_DQS7 AK54 AN59 SB_DQ51 SB_DQS5 BA61
M_A_DQ53 AT54 M_B_DQ52 AU59 AR59 M_B_DQS6
M_A_DQ54 SA_DQ53 M_B_DQ53 SB_DQ52 SB_DQS6 M_B_DQS7
AP56 SA_DQ54 AU61 SB_DQ53 SB_DQS7 AK61
M_A_DQ55 AP52 M_B_DQ54 AN58
M_A_DQ56 SA_DQ55 M_B_DQ55 SB_DQ54
AN57 SA_DQ56 AR58 SB_DQ55
M_A_DQ57 AN53 M_B_DQ56 AK58
M_A_DQ58 SA_DQ57 M_B_DQ57 SB_DQ56
AG56 SA_DQ58 AL58 SB_DQ57
B M_A_DQ59 M_B_DQ58 B
AG53 SA_DQ59 AG58 SB_DQ58
M_A_DQ60 AN55 M_B_DQ59 AG59
SA_DQ60 M_A_A[15:0] 14 SB_DQ59
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ60 AM60
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 15
AG55 SA_DQ62 SA_MA1 BB34 AL59 SB_DQ61 SB_MA0 BF32
M_A_DQ63 AK56 BE35 M_A_A2 M_B_DQ62 AF61 BE33 M_B_A1
SA_DQ63 SA_MA2 M_A_A3 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
SA_MA3 BD35 AH60 SB_DQ63 SB_MA2 BD33
AT34 M_A_A4 AU30 M_B_A3
SA_MA4 M_A_A5 SB_MA3 M_B_A4
SA_MA5 AU34 SB_MA4 BD30
BB32 M_A_A6 AV30 M_B_A5
SA_MA6 M_A_A7 SB_MA5 M_B_A6
14 M_A_BS0 BD37 SA_BS0 SA_MA7 AT32 SB_MA6 BG30
BF36 AY32 M_A_A8 BG39 BD29 M_B_A7
14 M_A_BS1 SA_BS1 SA_MA8 M_A_A9 15 M_B_BS0 SB_BS0 SB_MA7 M_B_A8
14 M_A_BS2 BA28 SA_BS2 SA_MA9 AV32 15 M_B_BS1 BD42 SB_BS1 SB_MA8 BE30
BE37 M_A_A10 AT22 BE28 M_B_A9
SA_MA10 M_A_A11 15 M_B_BS2 SB_BS2 SB_MA9 M_B_A10
SA_MA11 BA30 SB_MA10 BD43
BC30 M_A_A12 AT28 M_B_A11
SA_MA12 M_A_A13 SB_MA11 M_B_A12
14 M_A_CAS# BE39 SA_CAS# SA_MA13 AW41 SB_MA12 AV28
BD39 AY28 M_A_A14 AV43 BD46 M_B_A13
14 M_A_RAS# SA_RAS# SA_MA14 M_A_A15 15 M_B_CAS# SB_CAS# SB_MA13 M_B_A14
14 M_A_W E# AT41 SA_WE# SA_MA15 AU26 15 M_B_RAS# BF40 SB_RAS# SB_MA14 AT26
BD45 AU22 M_B_A15
15 M_B_W E# SB_WE# SB_MA15

IVY-BRIDGE-GP-NF
IVY-BRIDGE-GP-NF
Wistron Confidential document, Anyone can not Duplicate,
Modify, Forward or any other purpose application without get
Wistron permission
<Variant Name>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (DDR)
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 6 of 102

5 4 3 2 1
5 4 3 2 1

SSID = CPU

D D

CPU2E 5 OF 9

B50 CFG0 BCLK_ITP N59


C51 CFG1 BCLK_ITP# N58
B54 CFG2
D53 CFG3 Pin Name Strap Description Configuration (Default value for each bit is 1 unless specified otherwise) Default Value
CFG4 A51 N42
CFG4 RSVD30
C53 CFG5 RSVD31 L42

1
C55 CFG6 RSVD32 L45
R702 H49 L47 Connect a series 1 kOhms resistor on the critical CFG[0
1KR2J-L2-GP CFG7 RSVD33
A55 CFG8 trace in a manner which does not introduce any stubs
H51 CFG9
K49 M13 CFG[0] to CFG[0] trace.
2
CFG10 RSVD34
K53 CFG11 RSVD35 M14 Route as needed from the opposite side of this series
F53 CFG12 RSVD36 U14 isolation resistor to the debug port.
G53 CFG13 RSVD37 W14
L51 P13 ITP will drive the net to GND.
CFG14 RSVD38
F51 CFG15
D52 CFG16
L53 CFG17 RSVD39 AT49
RSVD40 K24 1: Normal Operation;
PCIe Static x16 Lane Lane # definition matches socket pin map definition
C H43 CFG[2] 0 C

RESERVED
K43
VCC_VAL_SENSE
AH2
Numbering Reversal.
VSS_VAL_SENSE RSVD41
RSVD42 AG13 0:Lane Reversed
RSVD43 AM14
H45 VAXG_VAL_SENSE RSVD44 AM15
K45 VSSAXG_VAL_SENSE 1:Disabled - No Physical Display Port attached to
Embedded DisplayPort
RSVD45 N50
F48 VCC_DIE_SENSE No connect for disable
G48 RSVD47 Display Port
CFG[4] Presence strap 0:Enabled - An external Display Port device is connected to
H48 RSVD6 the Embedded Display Port 0
K48 RSVD7
DC_TEST_A4 A4
DC_TEST_C4 C4 Pull-down to GND through a 1KΩ ± 5%
BA19 RSVD8 DC_TEST_D3 D3 resistor to enable port
AV19 RSVD9 DC_TEST_D1 D1
AT21 RSVD10 DC_TEST_A58 A58
BB21 RSVD11 DC_TEST_A59 A59
BB19 RSVD12 DC_TEST_C59 C59 PCI-Express 00 = 1 x 8, 2 x 4 PCI Express
AY21 RSVD13 DC_TEST_A61 A61 CFG[6:5] Port Bifurcation 01 = reserved
BA22 RSVD14 DC_TEST_C61 C61
AY22 D61 Straps 10 = 2 x 8 PCI Express 00
RSVD15 DC_TEST_D61
AU19 RSVD16 DC_TEST_BD61 BD61 11 = 1 x 16 PCI Express
AU21 RSVD17 DC_TEST_BE61 BE61
BD21 RSVD18 DC_TEST_BE59 BE59
BD22 RSVD19 DC_TEST_BG61 BG61
BD25 RSVD20 DC_TEST_BG59 BG59 Reserved configuration
BD26 RSVD21 DC_TEST_BG58 BG58 lands. A test point may
B B
BG22 RSVD22 DC_TEST_BG4 BG4
BE22 BG3 CFG[17:7] be placed on the board
RSVD23 DC_TEST_BG3
BG26 RSVD24 DC_TEST_BE3 BE3 for these lands.
BE26 RSVD25 DC_TEST_BG1 BG1
BF23 RSVD26 DC_TEST_BE1 BE1
BE24 RSVD27 DC_TEST_BD1 BD1

IVY-BRIDGE-GP-NF 71.00IVY.A0U

Wistron Confidential document, Anyone can not Duplicate,


Modify, Forward or any other purpose application without get
Wistron permission

<Variant Name>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (RESERVED)
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 7 of 102

5 4 3 2 1
5 4 3 2 1

SSID = CPU CPU2F POWER 6 OF 9


ULV:17W
Iccmax:33A Iccmax:8.5A 1D05V_VTT
VCC_CORE
ICC_TDC:25A VCCIO1
AF46 ICC_TDC:8.5A
VCC_CORE AG48
VCCIO3

C805
SC10U6D3V3MX-L-GP

C810
SC10U6D3V3MX-L-GP

C838
SC10U6D3V3MX-L-GP

C840
SC10U6D3V3MX-L-GP

C829
SC10U6D3V3MX-L-GP

C830
SC10U6D3V3MX-L-GP

C843
SC10U6D3V3MX-L-GP

C844
SC10U6D3V3MX-L-GP

C845
SC10U6D3V3MX-L-GP
AG50

1
VCCIO4
A26 AG51
VCC1 VCCIO5
A29 AJ17
VCC2 VCCIO6
A31 AJ21

2
VCC3 VCCIO7
A34
VCC4 VCCIO8
AJ25 DY DY DY DY
C801
SC2D2U6D3V2KX-GP

C802
SC2D2U6D3V2KX-GP

C803
SC2D2U6D3V2KX-GP

C804
SC2D2U6D3V2KX-GP

C808
SC2D2U6D3V2KX-GP

C811
SC2D2U6D3V2KX-GP
A35 AJ43
1

1
VCC5 VCCIO9
A38 AJ47
VCC6 VCCIO10
A39 AK50
VCC7 VCCIO11
A42 AK51
2

2
VCC8 VCCIO12
DY C26
VCC9 VCCIO13
AL14
D C27 AL15 D
VCC10 VCCIO14
C32 AL16
VCC11 VCCIO15
C34 AL20
VCC12 VCCIO16
C37 AL22
VCC13 VCCIO17
C39 AL26
VCC14 VCCIO18
C42 AL45
VCC15 VCCIO19
D27 AL48
VCC16 VCCIO20
D32 AM16
VCC17 VCCIO21
D34 AM17
VCC18 VCCIO22
D37 AM21
VCC19 VCCIO23
C815
SC2D2U6D3V2KX-GP

C816
SC2D2U6D3V2KX-GP

C817
SC2D2U6D3V2KX-GP

C818
SC2D2U6D3V2KX-GP

C819
SC2D2U6D3V2KX-GP

C820
SC2D2U6D3V2KX-GP
D39 AM43

PEG IO AND DDR IO


1

1
VCC20 VCCIO24
D42 AM47
VCC21 VCCIO25
E26 AN20
VCC22 VCCIO26
E28 AN42
2

2
VCC23 VCCIO27
DY DY DY DY E32
VCC24 VCCIO28
AN45
E34 AN48
VCC25 VCCIO29
E37
VCC26
E38
VCC27

CORE SUPPLY
F25
VCC28
F26
VCC29
F28
VCC30 1D05V_VTT
F32
VCC31
F34
VCC32
F37 AA14
VCC33 VCCIO30
F38 AA15
VCC34 VCCIO31
C825
SC10U6D3V3MX-L-GP

C826
SC10U6D3V3MX-L-GP

C827
SC10U6D3V3MX-L-GP

C828
SC10U6D3V3MX-L-GP

C831
SC10U6D3V3MX-L-GP

F42 AB17
1

1
VCC35 VCCIO32

C806
SC1U6D3V2KX-L-1-GP

C807
SC1U6D3V2KX-L-1-GP

C809
SC1U6D3V2KX-L-1-GP

C812
SC1U6D3V2KX-L-1-GP

C813
SC1U6D3V2KX-L-1-GP

C814
SC1U6D3V2KX-L-1-GP

C821
SC1U6D3V2KX-L-1-GP

C822
SC1U6D3V2KX-L-1-GP

C823
SC1U6D3V2KX-L-1-GP

C824
SC1U6D3V2KX-L-1-GP
G42 AB20
VCC36 VCCIO33
H25 AC13
VCC37 VCCIO34
H26 AD16
2

2
VCC38 VCCIO35
DY H28
VCC39 VCCIO36
AD18 DY DY
H29 AD21
VCC40 VCCIO37
H32 AE14
VCC41 VCCIO38
H34 AE15
VCC42 VCCIO39
H35 AF16
VCC43 VCCIO40
H37 AF18
VCC44 VCCIO41
H38 AF20
VCC45 VCCIO42
H40 AG15
VCC46 VCCIO43
J25 AG16
VCC47 VCCIO44
J26 AG17
VCC48 VCCIO45
J28 AG20
VCC49 VCCIO46
C835
SC10U6D3V3MX-L-GP

C832
SC10U6D3V3MX-L-GP

C833
SC10U6D3V3MX-L-GP

C834
SC10U6D3V3MX-L-GP

C836
SC10U6D3V3MX-L-GP

J29 AG21
1

VCC50 VCCIO47
C J32 AJ14 C
VCC51 VCCIO48
J34 AJ15
VCC52 VCCIO49
J35
2

VCC53
DY J37
VCC54
J38
VCC55
J40
VCC56
J42
VCC57
K26 W16
VCC58 VCCIO50
K27 W17
VCC59 VCCIO51
K29
VCC60
K32
VCC61
K34
VCC62 SA_1031
K35
VCC63
K37
VCC64
K39
VCC66
K42 BC22
VCC67 VCCIO_SEL
L25
VCC68
L28
VCC69
L33
VCC70
L36
VCC71 SA_1031 1D05V_VTT
L40
VCC72 1D05V_VTT
N26
VCC73
QUIET
RAILS

N30 AM25
VCC74 VCCPQE1 1D05V_VTT
N34 AN22

1
VCC75 VCCPQE2 C877
N38

2
VCC76 SC1U6D3V2KX-L-1-GP

2
R808

2
R804 75R2F-2-GP
130R2F-L-GP

1
Place near processor

1
A44 H_CPU_SVIDALRT# 1 R803 2
VIDALERT# H_CPU_SVIDCLK VR_SVID_ALERT# 42
B43 43R2J-GP
VIDSCLK H_CPU_SVIDCLK 42
SVID

C44 H_CPU_SVIDDAT
VIDSOUT H_CPU_SVIDDAT 42

1 R801 2 VCC_CORE
B 100R2F-L1-GP-U B

F43
SENSE LINES

VCC_SENSE VCCSENSE 43
G43 Place near processor
VSS_SENSE VSSSENSE 43
1 R805 2 1D05V_VTT

1
10R2F-L-GP
DY R802
AN16 100R2F-L1-GP-U
VCCIO_SENSE VCCIO_SENSE 45
AN17
VSS_SENSE_VCCIO VSSIO_SENSE 45
2
1

R807
10R2F-L-GP
IVY-BRIDGE-GP-NF 71.00IVY.A0U DY
2

A A
Wistron Confidential document, Anyone can not Duplicate,
Modify, Forward or any other purpose application without get
Wistron permission

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
CPU (VCC_CORE)
Document Number Rev
A2
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 8 of 102
5 4 3 2 1
5 4 3 2 1

Iccmax:18A(GT1)
SSID = CPU ICC_TDC:12A(GT1)
CPU2G POWER 7 OF 9 Routing Guideline:
Power from DDR_VREF_S3 and +V_SM_VREF_CNT
should have 10 mils trace width.
SM_VREF AY43 +V_SM_VREF_CNT 37
AA46

VREF
VAXG1
AB47 VAXG2
AB50 VAXG3 SA_DIMM_VREFDQ BE7 M_VREF_DQ_DIMM0_C 37
AB51 VAXG4 SB_DIMM_VREFDQ BG7 M_VREF_DQ_DIMM1_C 37
AB52 VAXG5
D AB53 VAXG6 SA_1031 D
AB55 VAXG7
VCC_GFXCORE AB56 VAXG8
AB58 VAXG9
AB59 VAXG10
AC61 VAXG11

C942
SC1U10V2KX-1GP

C943
SC1U10V2KX-1GP

C949
SC1U10V2KX-1GP

C950
SC1U10V2KX-1GP
AD47 VAXG12
AD48 VAXG13

1
AD50 VAXG14
AD51 AJ28 1D35V_S0
VAXG15 VDDQ1

- 1.5V RAILS
AD52 AJ33

2
VAXG16 VDDQ2
AD53 AJ36
AD55
VAXG17
VAXG18
VDDQ3
VDDQ4 AJ40 Iccmax:5A
AD56 VAXG19 VDDQ5 AL30

C934
SC10U6D3V3MX-L-GP

C933
SC10U6D3V3MX-L-GP

C932
SC10U6D3V3MX-L-GP

C931
SC10U6D3V3MX-L-GP

C959
SC10U6D3V3MX-L-GP

C958
SC10U6D3V3MX-L-GP
AD58 VAXG20 VDDQ6 AL34

1
AD59 VAXG21 VDDQ7 AL38
AE46 VAXG22 VDDQ8 AL42
N45 AM33

2
VAXG23 VDDQ9
P47 VAXG24 VDDQ10 AM36
P48 VAXG25 VDDQ11 AM40
C901
SC10U6D3V3MX-L-GP

C902
SC10U6D3V3MX-L-GP

C903
SC10U6D3V3MX-L-GP

C904
SC10U6D3V3MX-L-GP

C905
SC10U6D3V3MX-L-GP

C906
SC10U6D3V3MX-L-GP

C907
SC10U6D3V3MX-L-GP

C908
SC10U6D3V3MX-L-GP
P50 VAXG26 VDDQ12 AN30
1

1
P51 VAXG27 VDDQ13 AN34
P52 VAXG28 VDDQ14 AN38
P53 AR26

DDR3
2

2
VAXG29 VDDQ15
P55 AR28

GRAPHICS
VAXG30 VDDQ16
P56 VAXG31 VDDQ17 AR30
P61 VAXG32 VDDQ18 AR32
T48 VAXG33 VDDQ19 AR34
T58 VAXG34 VDDQ20 AR36
C T59 AR40 C
VAXG35 VDDQ21

C935
SC1U10V2KX-1GP

C936
SC1U10V2KX-1GP

C937
SC1U10V2KX-1GP

C938
SC1U10V2KX-1GP

C939
SC1U10V2KX-1GP

C952
SC1U10V2KX-1GP
T61 VAXG36 VDDQ22 AV41
U46 VAXG37 VDDQ23 AW26

1
V47 VAXG38 VDDQ24 BA40
V48 VAXG39 VDDQ25 BB28
V50 BG33

2
VAXG40 VDDQ26
V51 VAXG41
V52 VAXG42
V53 VAXG43
V55 VAXG44
V56 VAXG45
V58 VAXG46
V59 VAXG47
W50 VAXG48
W51 VAXG49
W52 VAXG50
W53 VAXG51
W55 VAXG52 SA_1031
W56 VAXG53
W61 VAXG54
VCC_GFXCORE Y48 VAXG55
Y61 VAXG56
1

SA_1031 1D35V_S0
R906 VCCSA_VID0 VCCSA_VID0 48
100R2F-L1-GP-U VCCSA_VID1 VCCSA_VID1 48

2
QUIET RAILS
AM28
SENSE
LINES
2

VCC_AXG_SENSE VCCDQ1 R904 R910


44 VCC_AXG_SENSE F45 VAXG_SENSE VCCDQ2 AN26
B VSS_AXG_SENSE B
44 VSS_AXG_SENSE G45 VSSAXG_SENSE 10KR2J-L-GP 10KR2J-L-GP
1 2
1

C948

1
R907 Angel-SA SC1U6D3V2KX-L-1-GP
100R2F-L1-GP-U 1D8V_S0
ICC_MAX:1.2A
1.8V RAIL

DY
2

R908 1 2 VCCPLL BB3 VCCSA


0R3J-L1-GP VCCPLL1
BC1 VCCPLL2 VID0 VID1 ULV
C928
SC10U6D3V3MX-L-GP

C929
SC1U10V2KX-1GP

BC4 VCCPLL3
1

1D35V_S0 SA_1031
L L 0.9V
R909
2

1 2 BC43 0D85V_S0
0R0603-PAD VDDQ_SENSE
VSS_SENSE_VDDQ BA43 L H 0.85V
SENSE LINES

1
L17 VCCSA1
L21 R912 H L 0.775V
VCCSA2 100R2F-L1-GP-U
N16 VCCSA3
N20 VCCSA4
0D85V_S0 N22 H H 0.75V
ICC_MAX:4A
SA RAIL

2
VCCSA5
P17 VCCSA6
P20 U10 VCCSA_SENSE VCCSA_SENSE
VCCSA7 VCCSA_SENSE
R16 VCCSA8
C927
SC1U10V2KX-1GP

C951
SC1U10V2KX-1GP

C944
SC1U10V2KX-1GP

C960
SC1U10V2KX-1GP

C921
SC10U6D3V3MX-L-GP

C923
SC10U6D3V3MX-L-GP

R18 Wistron Confidential document, Anyone can not Duplicate,


VCCSA9
1

R21 Modify, Forward or any other purpose application without get


VCCSA10 Wistron permission
U15
VCCSA VID

VCCSA11
V16
2

VCCSA12 VCCSA_VID0
A V17 VCCSA13 VCCSA_VID0 D48 <Variant Name> A
lines

V18 D49 VCCSA_VID1


VCCSA14 VCCSA_VID1
V21 VCCSA15
W20 VCCSA16 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

IVY-BRIDGE-GP-NF 71.00IVY.A0U Title


CPU (VCC_GFXCORE)
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 9 of 102
5 4 3 2 1
5 4 3 2 1

SSID = CPU CPU2H 8 OF 9

CPU2I 9 OF 9

A13 VSS1 VSS91 AM38


A17 VSS2 VSS92 AM4
A21 VSS3 VSS93 AM42 BG17 VSS181 VSS250 M4
A25 VSS4 VSS94 AM45 BG21 VSS182 VSS251 M58
A28 VSS5 VSS95 AM48 BG24 VSS183 VSS252 M6
A33 VSS6 VSS96 AM58 BG28 VSS184 VSS253 N1
D A37 VSS7 VSS97 AN1 BG37 VSS185 VSS254 N17 D
A40 VSS8 VSS98 AN21 BG41 VSS186 VSS255 N21
A45 VSS9 VSS99 AN25 BG45 VSS187 VSS256 N25
A49 VSS10 VSS100 AN28 BG49 VSS188 VSS257 N28
A53 VSS11 VSS101 AN33 BG53 VSS189 VSS258 N33
A9 VSS12 VSS102 AN36 BG9 VSS190 VSS259 N36
AA1 VSS13 VSS103 AN40 C29 VSS191 VSS260 N40
AA13 VSS14 VSS104 AN43 C35 VSS192 VSS261 N43
AA50 VSS15 VSS105 AN47 C40 VSS193 VSS262 N47
AA51 VSS16 VSS106 AN50 D10 VSS194 VSS263 N48
AA52 VSS17 VSS107 AN54 D14 VSS195 VSS264 N51
AA53 VSS18 VSS108 AP10 D18 VSS196 VSS265 N52
AA55 VSS19 VSS109 AP51 D22 VSS197 VSS266 N56
AA56 VSS20 VSS110 AP55 D26 VSS198 VSS267 N61
AA8 VSS21 VSS111 AP7 D29 VSS199 VSS268 P14
AB16 VSS22 VSS112 AR13 D35 VSS200 VSS269 P16
AB18 VSS23 VSS113 AR17 D4 VSS201 VSS270 P18
AB21 VSS24 VSS114 AR21 D40 VSS202 VSS271 P21
AB48 AR41 D43 P58
AB61
AC10
VSS25
VSS26
VSS27
VSS115
VSS116
VSS117
AR48
AR61
D46
D50
VSS203
VSS204
VSS205
VSS VSS272
VSS273
VSS274
P59
P9
AC14 VSS28 VSS118 AR7 D54 VSS206 VSS275 R17
AC46 VSS29 VSS119 AT14 D58 VSS207 VSS276 R20
AC6 VSS30 VSS120 AT19 D6 VSS208 VSS277 R4
AD17 VSS31 VSS121 AT36 E25 VSS209 VSS278 R46
AD20 VSS32 VSS122 AT4 E29 VSS210 VSS279 T1
AD4 AT45 E3 T47
AD61
AE13
VSS33
VSS34
VSS35
VSS VSS123
VSS124
VSS125
AT52
AT58
E35
E40
VSS211
VSS212
VSS213
VSS280
VSS281
VSS282
T50
T51
C AE8 AU1 F13 T52 C
VSS36 VSS126 VSS214 VSS283
AF1 VSS37 VSS127 AU11 F15 VSS215 VSS284 T53
AF17 VSS38 VSS128 AU28 F19 VSS216 VSS285 T55
AF21 VSS39 VSS129 AU32 F29 VSS217 VSS286 T56
AF47 VSS40 VSS130 AU51 F35 VSS218 VSS287 U13
AF48 VSS41 VSS131 AU7 F40 VSS219 VSS288 U8
AF50 VSS42 VSS132 AV17 F55 VSS220 VSS289 V20
AF51 VSS43 VSS133 AV21 G51 VSS221 VSS290 V61
AF52 VSS44 VSS134 AV22 G6 VSS222 VSS291 W13
AF53 VSS45 VSS135 AV34 G61 VSS223 VSS292 W15
AF55 VSS46 VSS136 AV40 H10 VSS224 VSS293 W18
AF56 VSS47 VSS137 AV48 H14 VSS225 VSS294 W21
AF58 VSS48 VSS138 AV55 H17 VSS226 VSS295 W46
AF59 VSS49 VSS139 AW13 H21 VSS227 VSS296 W8
AG10 VSS50 VSS140 AW43 H4 VSS228 VSS297 Y4
AG14 VSS51 VSS141 AW61 H53 VSS229 VSS298 Y47
AG18 VSS52 VSS142 AW7 H58 VSS230 VSS299 Y58
AG47 VSS53 VSS143 AY14 J1 VSS231 VSS300 Y59
AG52 VSS54 VSS144 AY19 J49 VSS232
AG61 VSS55 VSS145 AY30 J55 VSS233
AG7 VSS56 VSS146 AY36 K11 VSS234
AH4 VSS57 VSS147 AY4 K21 VSS235
AH58 VSS58 VSS148 AY41 K51 VSS236

NCTF TEST PIN:


A5,A57,BC61,BG5
AJ13 AY45 K8 A5

BG57,C3,E1,E61
VSS59 VSS149 VSS237 VSS_NCTF_1#A5
AJ16 VSS60 VSS150 AY49 L16 VSS238 VSS_NCTF_2#A57 A57
AJ20 VSS61 VSS151 AY55 L20 VSS239 VSS_NCTF_3#BC61 BC61
AJ22 VSS62 VSS152 AY58 L22 VSS240 VSS_NCTF_8#BG5 BG5
AJ26 VSS63 VSS153 AY9 L26 VSS241 VSS_NCTF_9#BG57 BG57
AJ30 VSS64 VSS154 BA1 L30 VSS242 VSS_NCTF_10#C3 C3
B B
AJ34 VSS65 VSS155 BA11 L34 VSS243 VSS_NCTF_13#E1 E1
AJ38 VSS66 VSS156 BA17 L38 VSS244 VSS_NCTF_14#E61 E61

NCTF
AJ42 VSS67 VSS157 BA21 L43 VSS245
AJ45 VSS68 VSS158 BA26 L48 VSS246
AJ48 VSS69 VSS159 BA32 L61 VSS247 VSS_NCTF_4 BD3
AJ7 VSS70 VSS160 BA48 M11 VSS248 VSS_NCTF_5 BD59
AK1 VSS71 VSS161 BA51 M15 VSS249 VSS_NCTF_6 BE4
AK52 VSS72 VSS162 BB53 VSS_NCTF_7 BE58
AL10 VSS73 VSS163 BC13 VSS_NCTF_11 C58
AL13 VSS74 VSS164 BC5 VSS_NCTF_12 D59
AL17 VSS75 VSS165 BC57
AL21 VSS76 VSS166 BD12
AL25 VSS77 VSS167 BD16
AL28 BD19 IVY-BRIDGE-GP-NF
VSS78 VSS168
AL33 VSS79 VSS169 BD23
AL36 VSS80 VSS170 BD27
AL40 VSS81 VSS171 BD32
AL43 VSS82 VSS172 BD36
AL47 VSS83 VSS173 BD40
AL61 VSS84 VSS174 BD44
AM13 VSS85 VSS175 BD48
AM20 VSS86 VSS176 BD52
AM22 VSS87 VSS177 BD56
AM26 VSS88 VSS178 BD8
AM30 BE5 Wistron Confidential document, Anyone can not Duplicate,
VSS89 VSS179 Modify, Forward or any other purpose application without get
AM34 VSS90 VSS180 BG13
Wistron permission

A <Variant Name> A

IVY-BRIDGE-GP-NF
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (VSS)
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 10 of 102
5 4 3 2 1
5 4 3 2 1

D D

C C

Blanking
B B

Wistron Confidential document, Anyone can not Duplicate,


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<Variant Name>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

XDP
Size Document Number Rev
A4
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 11 of 102
5 4 3 2 1
5 4 3 2 1

D D

C C

Blanking
B B

Wistron Confidential document, Anyone can not Duplicate,


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<Variant Name>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 12 of 102
5 4 3 2 1
5 4 3 2 1

D D

C C

Blanking
B B

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<Variant Name>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 13 of 102
5 4 3 2 1
5 4 3 2 1

SSID = MEMORY
1D35V_S3 1D35V_S3 1D35V_S3 1D35V_S3
RAM1 Angel_SA RAM2 Angel_SA RAM3 Angel_SA RAM4 Angel_SA
6 M_A_A[15:0] K8 E3 M_A_DQ14 K8 E3 M_A_DQ25 K8 E3 M_A_DQ45 K8 E3 M_A_DQ63
VDD DQ0 M_A_DQ8 VDD DQ0 M_A_DQ28 VDD DQ0 M_A_DQ40 VDD DQ0 M_A_DQ60
K2 F7 K2 F7 K2 F7 K2 F7
VDD DQ1 M_A_DQ11 VDD DQ1 M_A_DQ26 VDD DQ1 M_A_DQ43 VDD DQ1 M_A_DQ62
N1 F2 N1 F2 N1 F2 N1 F2
VDD DQ2 M_A_DQ9 VDD DQ2 M_A_DQ29 VDD DQ2 M_A_DQ41 VDD DQ2 M_A_DQ61
6 M_A_DQ[63:0] R9 F8 R9 F8 R9 F8 R9 F8
VDD DQ3 M_A_DQ15 VDD DQ3 M_A_DQ31 VDD DQ3 M_A_DQ46 VDD DQ3 M_A_DQ58
B2 H3 B2 H3 B2 H3 B2 H3
VDD DQ4 M_A_DQ12 VDD DQ4 M_A_DQ30 VDD DQ4 M_A_DQ44 VDD DQ4 M_A_DQ57
D9 H8 D9 H8 D9 H8 D9 H8
VDD DQ5 M_A_DQ10 VDD DQ5 M_A_DQ27 VDD DQ5 M_A_DQ47 VDD DQ5 M_A_DQ59
G7 G2 G7 G2 G7 G2 G7 G2
VDD DQ6 M_A_DQ13 VDD DQ6 M_A_DQ24 VDD DQ6 M_A_DQ42 VDD DQ6 M_A_DQ56
6 M_A_DQS#[7:0] R1 H7 R1 H7 R1 H7 R1 H7
VDD DQ7 VDD DQ7 VDD DQ7 VDD DQ7
N9 N9 N9 N9
VDD M_A_DQ5 VDD M_A_DQ22 VDD M_A_DQ36 VDD M_A_DQ53
6 M_A_DQS[7:0] DQ8 D7 DQ8 D7 DQ8 D7 DQ8 D7
A8 C3 M_A_DQ6 A8 C3 M_A_DQ19 A8 C3 M_A_DQ39 A8 C3 M_A_DQ54
D VDDQ DQ9 M_A_DQ1 VDDQ DQ9 M_A_DQ20 VDDQ DQ9 M_A_DQ37 VDDQ DQ9 M_A_DQ55 D
A1 VDDQ DQ10 C8 A1 VDDQ DQ10 C8 A1 VDDQ DQ10 C8 A1 VDDQ DQ10 C8
C1 C2 M_A_DQ3 C1 C2 M_A_DQ18 C1 C2 M_A_DQ38 C1 C2 M_A_DQ51
VDDQ DQ11 M_A_DQ4 VDDQ DQ11 M_A_DQ16 VDDQ DQ11 M_A_DQ32 VDDQ DQ11 M_A_DQ48
C9 VDDQ DQ12 A7 C9 VDDQ DQ12 A7 C9 VDDQ DQ12 A7 C9 VDDQ DQ12 A7
D2 A2 M_A_DQ7 D2 A2 M_A_DQ23 D2 A2 M_A_DQ34 D2 A2 M_A_DQ50
VDDQ DQ13 M_A_DQ0 VDDQ DQ13 M_A_DQ17 VDDQ DQ13 M_A_DQ33 VDDQ DQ13 M_A_DQ52
E9 VDDQ DQ14 B8 E9 VDDQ DQ14 B8 E9 VDDQ DQ14 B8 E9 VDDQ DQ14 B8
F1 A3 M_A_DQ2 F1 A3 M_A_DQ21 F1 A3 M_A_DQ35 F1 A3 M_A_DQ49
VDDQ DQ15 VDDQ DQ15 VDDQ DQ15 VDDQ DQ15
H9 VDDQ H9 VDDQ H9 VDDQ H9 VDDQ
H2 C7 M_A_DQS0 H2 C7 M_A_DQS2 H2 C7 M_A_DQS4 H2 C7 M_A_DQS6
VDDQ UDQS M_A_DQS#0 VDDQ UDQS M_A_DQS#2 VDDQ UDQS M_A_DQS#4 VDDQ UDQS M_A_DQS#6
UDQS# B7 UDQS# B7 UDQS# B7 UDQS# B7
DDR_WR_VREF_CHA H1 VREFDQ DDR_WR_VREF_CHA H1 VREFDQ DDR_WR_VREF_CHA H1 VREFDQ DDR_WR_VREF_CHA H1 VREFDQ
DDR_VREF_S3 M8 F3 M_A_DQS1 DDR_VREF_S3 M8 F3 M_A_DQS3 DDR_VREF_S3 M8 F3 M_A_DQS5 DDR_VREF_S3 M8 F3 M_A_DQS7
VRAM_CH_A_ZQ_1A VREFCA LDQS M_A_DQS#1 VRAM_CH_A_ZQ_2A VREFCA LDQS M_A_DQS#3 VRAM_CH_A_ZQ_3A VREFCA LDQS M_A_DQS#5 VRAM_CH_A_ZQ_4A VREFCA LDQS M_A_DQS#7
L8 ZQ LDQS# G3 L8 ZQ LDQS# G3 L8 ZQ LDQS# G3 L8 ZQ LDQS# G3

ODT K1 M_A_DIM0_ODT0 6 ODT K1 M_A_DIM0_ODT0 6 ODT K1 M_A_DIM0_ODT0 6 ODT K1 M_A_DIM0_ODT0 6


1

1
M_A_A0 N3 M_A_A0 N3 M_A_A0 N3 M_A_A0 N3
R1401 M_A_A1 A0 R1404 M_A_A1 A0 R1406 M_A_A1 A0 R1410 M_A_A1 A0
P7 A1 P7 A1 P7 A1 P7 A1
240R2F-1-GP M_A_A2 P3 L2 240R2F-1-GP M_A_A2 P3 L2 240R2F-1-GP M_A_A2 P3 L2 240R2F-1-GP M_A_A2 P3 L2
A2 CS# M_A_DIM0_CS#0 6 A2 CS# M_A_DIM0_CS#0 6 A2 CS# M_A_DIM0_CS#0 6 A2 CS# M_A_DIM0_CS#0 6
M_A_A3 N2 T2 DDR3_DRAMRST# 15,37 M_A_A3 N2 T2 DDR3_DRAMRST# 15,37 M_A_A3 N2 T2 DDR3_DRAMRST# 15,37 M_A_A3 N2 T2 DDR3_DRAMRST# 15,37
M_A_A4 A3 RESET# M_A_A4 A3 RESET# M_A_A4 A3 RESET# M_A_A4 A3 RESET#
P8 P8 P8 P8
2

2
M_A_A5 A4 M_A_A5 A4 M_A_A5 A4 M_A_A5 A4
P2 A5 P2 A5 P2 A5 P2 A5
M_A_A6 R8 M7 M_A_A15 M_A_A6 R8 M7 M_A_A15 M_A_A6 R8 M7 M_A_A15 M_A_A6 R8 M7 M_A_A15
M_A_A7 A6 NC#M7 VRAM_CH_A_ZQ_1B M_A_A7 A6 NC#M7 VRAM_CH_A_ZQ_2B M_A_A7 A6 NC#M7 VRAM_CH_A_ZQ_3B M_A_A7 A6 NC#M7 VRAM_CH_A_ZQ_4B
R2 A7 NC#L9 L9 R2 A7 NC#L9 L9 R2 A7 NC#L9 L9 R2 A7 NC#L9 L9
M_A_A8 T8 L1 M_A_A8 T8 L1 M_A_A8 T8 L1 M_A_A8 T8 L1
M_A_A9 A8 NC#L1 M_A_A9 A8 NC#L1 M_A_A9 A8 NC#L1 M_A_A9 A8 NC#L1
R3 A9 NC#J9 J9 R3 A9 NC#J9 J9 R3 A9 NC#J9 J9 R3 A9 NC#J9 J9
M_A_A10 L7 J1 M_A_A10 L7 J1 M_A_A10 L7 J1 M_A_A10 L7 J1
M_A_A11 A10/AP NC#J1 M_A_A11 A10/AP NC#J1 M_A_A11 A10/AP NC#J1 M_A_A11 A10/AP NC#J1
R7 A11 R7 A11 R7 A11 R7 A11

1
M_A_A12 N7 M_A_A12 N7 M_A_A12 N7 M_A_A12 N7
A12/BC# A12/BC# A12/BC# A12/BC#

1
M_A_A13 T3 J8 R1402 M_A_A13 T3 J8 M_A_A13 T3 J8 M_A_A13 T3 J8
A13 VSS A13 VSS A13 VSS A13 VSS

1
M_A_A14 T7 M1 240R2F-1-GP M_A_A14 T7 M1 R1403 M_A_A14 T7 M1 R1405 M_A_A14 T7 M1 R1408
A14 VSS A14 VSS 240R2F-1-GP A14 VSS 240R2F-1-GP A14 VSS 240R2F-1-GP
VSS M9 DY VSS M9 VSS M9 VSS M9
J2 J2 DY J2 DY J2 DY

2
VSS VSS VSS VSS
6 M_A_BS0 M2 P9 6 M_A_BS0 M2 P9 6 M_A_BS0 M2 P9 6 M_A_BS0 M2 P9

2
BA0 VSS BA0 VSS BA0 VSS BA0 VSS
6 M_A_BS1 N8 G8 6 M_A_BS1 N8 G8 6 M_A_BS1 N8 G8 6 M_A_BS1 N8 G8

2
BA1 VSS BA1 VSS BA1 VSS BA1 VSS
6 M_A_BS2 M3 BA2 VSS B3 6 M_A_BS2 M3 BA2 VSS B3 6 M_A_BS2 M3 BA2 VSS B3 6 M_A_BS2 M3 BA2 VSS B3
VSS T1 VSS T1 VSS T1 VSS T1
VSS A9 VSS A9 VSS A9 VSS A9
6 M_A_DIM0_CLK_DDR0 J7 CK VSS T9 6 M_A_DIM0_CLK_DDR0 J7 CK VSS T9 6 M_A_DIM0_CLK_DDR0 J7 CK VSS T9 6 M_A_DIM0_CLK_DDR0 J7 CK VSS T9
6 M_A_DIM0_CLK_DDR#0 K7 CK# VSS E1 6 M_A_DIM0_CLK_DDR#0 K7 CK# VSS E1 6 M_A_DIM0_CLK_DDR#0 K7 CK# VSS E1 6 M_A_DIM0_CLK_DDR#0 K7 CK# VSS E1
VSS P1 VSS P1 VSS P1 VSS P1
6 M_A_DIM0_CKE0 K9 CKE 6 M_A_DIM0_CKE0 K9 CKE 6 M_A_DIM0_CKE0 K9 CKE 6 M_A_DIM0_CKE0 K9 CKE
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
D3 UDM VSSQ E8 D3 UDM VSSQ E8 D3 UDM VSSQ E8 D3 UDM VSSQ E8
C E7 LDM VSSQ E2 E7 LDM VSSQ E2 E7 LDM VSSQ E2 E7 LDM VSSQ E2 C
VSSQ D8 VSSQ D8 VSSQ D8 VSSQ D8
VSSQ D1 VSSQ D1 VSSQ D1 VSSQ D1
6 M_A_WE# L3 WE# VSSQ B9 6 M_A_WE# L3 WE# VSSQ B9 6 M_A_WE# L3 WE# VSSQ B9 6 M_A_WE# L3 WE# VSSQ B9
6 M_A_CAS# K3 CAS# VSSQ B1 6 M_A_CAS# K3 CAS# VSSQ B1 6 M_A_CAS# K3 CAS# VSSQ B1 6 M_A_CAS# K3 CAS# VSSQ B1
6 M_A_RAS# J3 RAS# VSSQ G9 6 M_A_RAS# J3 RAS# VSSQ G9 6 M_A_RAS# J3 RAS# VSSQ G9 6 M_A_RAS# J3 RAS# VSSQ G9

MT41J256M16RE-107-D-GP MT41J256M16RE-107-D-GP MT41J256M16RE-107-D-GP MT41J256M16RE-107-D-GP


72.41256.D0U 72.41256.D0U 72.41256.D0U 72.41256.D0U

E1600:KN.00409.002 E1600:KN.00409.002 E1600:KN.00409.002 E1600:KN.00409.002


H1600:KN.0040G.007 H1600:KN.0040G.007 H1600:KN.0040G.007 H1600:KN.0040G.007

1D35V_S3 DDR_VREF_S3
SA_1031 DDR_WR_VREF_CHA 0D675V_S0 SA_1031
1x10u+4x0.1u per/SDRAM

DDR_WR_VREF_CHA 37
C1403
SC10U6D3V3MX-L-GP

C1404
SC10U6D3V3MX-L-GP

C1405
SC10U6D3V3MX-L-GP

C1406
SC10U6D3V3MX-L-GP

C1412
SCD1U10V2KX-L1-GP

C1414
SCD1U10V2KX-L1-GP

C1411
SCD1U10V2KX-L1-GP

C1413
SCD1U10V2KX-L1-GP

C1426
SCD1U10V2KX-L1-GP

C1419
SC1U6D3V2KX-L-1-GP

C1421
SC1U6D3V2KX-L-1-GP

C1429
SC1U6D3V2KX-L-1-GP

C1431
SC1U6D3V2KX-L-1-GP

C1436
SC10U6D3V3MX-L-GP

C1437
SC10U6D3V3MX-L-GP

C1438
SCD1U10V2KX-L1-GP
1

1
C1415
SCD1U10V2KX-L1-GP

C1428
SCD1U10V2KX-L1-GP

C1427
SCD1U10V2KX-L1-GP

C1433
SCD1U10V2KX-L1-GP
1

2
2

C1416
SCD1U10V2KX-L1-GP

C1417
SCD1U10V2KX-L1-GP

C1420
SCD1U10V2KX-L1-GP

C1418
SCD1U10V2KX-L1-GP

C1423
SCD1U10V2KX-L1-GP

C1422
SCD1U10V2KX-L1-GP

C1425
SCD1U10V2KX-L1-GP

C1424
SCD1U10V2KX-L1-GP

C1447
SCD1U10V2KX-L1-GP

C1448
SCD1U10V2KX-L1-GP

C1409
SCD1U10V2KX-L1-GP

C1410
SCD1U10V2KX-L1-GP

C1407
SCD1U10V2KX-L1-GP

C1408
SCD1U10V2KX-L1-GP

C1434
SCD1U10V2KX-L1-GP

C1435
SCD1U10V2KX-L1-GP
1

1
2

2
B B

0D675V_S0

0D675V_S0 1 R1418 2 M_A_A0


36R2F-1-GP

1 R1407 2 M_A_DIM0_CKE0 1 R1419 2 M_A_A1 3D3V_S0


36R2F-1-GP 36R2F-1-GP
U1401
1 R1409 2 M_A_DIM0_ODT0 1 R1420 2 M_A_A2 M_A_DIM0_CLK_DDR0
36R2F-1-GP 36R2F-1-GP 1 8
A0 VCC
2 A1 WP 7
1 R1411 2 M_A_DIM0_CS#0 1 R1421 2 M_A_A3 3 A2 DY SCL 6 PCH_SMBCLK 15,20,52,69,97

1
36R2F-1-GP 36R2F-1-GP 4 5
GND SDA PCH_SMBDATA 15,20,52,69,97
R1435
1 R1412 2 M_A_RAS# 1 R1422 2 M_A_A4 30D1R2F-L-GP
36R2F-1-GP 36R2F-1-GP AT24C02C-XHM-T-GP
72.24C02.B0Q

2
1
1 R1413 2 M_A_CAS# 1 R1423 2 M_A_A5 C1430
36R2F-1-GP 36R2F-1-GP SC1D6P16V2BN-GP
M_A_DIM0_CLK_DDR_R 1 2

2
1 R1414 2 M_A_WE# 1 R1424 2 M_A_A6 C1432
36R2F-1-GP 36R2F-1-GP SCD1U10V2KX-L1-GP

1
1 R1415 2 M_A_BS0 1 R1425 2 M_A_A7 R1436
36R2F-1-GP 36R2F-1-GP 30D1R2F-L-GP

1 R1416 2 M_A_BS1 1 R1426 2 M_A_A8

2
36R2F-1-GP 36R2F-1-GP M_A_DIM0_CLK_DDR#0

1 R1417 2 M_A_BS2 1 R1427 2 M_A_A9


36R2F-1-GP 36R2F-1-GP

A 1 R1428 2 M_A_A10 A
36R2F-1-GP

1 R1429 2 M_A_A11
36R2F-1-GP

1 R1430 2 M_A_A12
36R2F-1-GP
<Variant Name>
1 R1431 2 M_A_A13
36R2F-1-GP
Wistron Corporation
1 R1432 2 M_A_A14 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
36R2F-1-GP Taipei Hsien 221, Taiwan, R.O.C.

1 R1433 2 M_A_A15 Title


36R2F-1-GP
DDR3-SODIMM1
Size Document Number Rev
Custom
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 14 of 102
5 4 3 2 1

Wistron Confidential document, Anyone can not Duplicate, Modify,


Forward or any other purpose application without get Wistron
permission
5 4 3 2 1

DIM2
6 M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
97 A1 NP2 NP2
M_B_A2 96
M_B_A3 A2
95 A3 RAS# 110 M_B_RAS# 6
M_B_A4 92 113
A4 WE# M_B_WE# 6
M_B_A5 91 115
A5 CAS# M_B_CAS# 6
M_B_A6 90
M_B_A7 A6
86 A7 CS0# 114 M_B_DIM0_CS#0 6
M_B_A8 89 121
A8 CS1# M_B_DIM0_CS#1 6
M_B_A9 85
M_B_A10 A9
107 73 M_B_DIM0_CKE0 6
M_B_A11 A10/AP CKE0
84 74 M_B_DIM0_CKE1 6
M_B_A12 A11 CKE1
83
D M_B_A13 A12 D
119 101 M_B_DIM0_CLK_DDR0 6
M_B_A14 A13 CK0
80 103 M_B_DIM0_CLK_DDR#0 6
M_B_A15 A14 CK0#
78
A15
79 102 M_B_DIM0_CLK_DDR1 6
6 M_B_BS2 A16/BA2 CK1
104 M_B_DIM0_CLK_DDR#1 6
CK1#
109
6 M_B_BS0 BA0
108 11
6 M_B_BS1 BA1 DM0
6 M_B_DQ[63:0] 28
M_B_DQ0 DM1
5 46
M_B_DQ1 DQ0 DM2 3D3V_S0
7 63
M_B_DQ2 DQ1 DM3
15 136
M_B_DQ3 DQ2 DM4
17 DQ3 DM5 153
M_B_DQ4 4 170
DQ4 DM6

1
2
M_B_DQ5 6 187
M_B_DQ6 DQ5 DM7 RN1501
16 DQ6
M_B_DQ7 18 200 SRN10KJ-L-GP
M_B_DQ8 DQ7 SDA PCH_SMBDATA 14,20,52,69,97
21 DQ8 SCL 202 PCH_SMBCLK 14,20,52,69,97
M_B_DQ9 23
M_B_DQ10 DQ9 TS#_DIMM0_1 3D3V_S0
33 198

4
3
M_B_DQ11 DQ10 EVENT#
35 DQ11
M_B_DQ12 22 199
M_B_DQ13 DQ12 VDDSPD SA1_DIM1
24 DQ13
M_B_DQ14 34 197 TS#_DIMM0_1
DQ14 SA0

C1504
SCD1U10V2KX-L1-GP
M_B_DQ15 36 201 SA1_DIM1
DQ15 SA1

1
M_B_DQ16 39
M_B_DQ17 DQ16
41 DQ17 NC#1 77
M_B_DQ18 51 122

2
M_B_DQ19 DQ18 NC#2 1D35V_S3
53 DQ19 NC#/TEST 125
M_B_DQ20 40
M_B_DQ21 DQ20
42 DQ21 VDD1 75
M_B_DQ22 50 76
M_B_DQ23 DQ22 VDD2
52 DQ23 VDD3 81
C M_B_DQ24 C
57 DQ24 VDD4 82
M_B_DQ25 59 87
M_B_DQ26 DQ25 VDD5
67 DQ26 VDD6 88
M_B_DQ27 69 93
DDR_WR_VREF_CHB M_B_DQ28 DQ27 VDD7
SA_1031 56 DQ28 VDD8 94
M_B_DQ29 58 99
M_B_DQ30 DQ29 VDD9
68 DQ30 VDD10 100
M_B_DQ31 70 105
DDR_WR_VREF_CHB 37 M_B_DQ32 DQ31 VDD11
129 106
M_B_DQ33 DQ32 VDD12
131 111
M_B_DQ34 DQ33 VDD13 1D35V_S3
141 112
DQ34 VDD14
1

C1519 M_B_DQ35 143 117


SCD1U10V2KX-L1-GP M_B_DQ36 DQ35 VDD15
130 118
M_B_DQ37 DQ36 VDD16
132 123
2

M_B_DQ38 DQ37 VDD17


140 124
M_B_DQ39 DQ38 VDD18
142
DQ39

C1506
SC10U6D3V3MX-L-GP

C1507
SC10U6D3V3MX-L-GP

C1508
SC10U6D3V3MX-L-GP

C1509
SC10U6D3V3MX-L-GP

C1510
SC10U6D3V3MX-L-GP

C1511
SC10U6D3V3MX-L-GP
M_B_DQ40 147 2
M_B_DQ41 DQ40 VSS
149 3
DQ41 VSS

1
M_B_DQ42 157 8
M_B_DQ43 DQ42 VSS
159
DQ43 VSS
9 DY DY DY DY
M_B_DQ44 146 13

2
M_B_DQ45 DQ44 VSS
148 14
0D675V_S0 M_B_DQ46 DQ45 VSS
158 19
M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS
175 31
M_B_DQ51 DQ50 VSS
177 32
DQ51 VSS
C1501
SC1U6D3V2KX-L-1-GP

C1502
SC1U6D3V2KX-L-1-GP

M_B_DQ52 164 37
DQ52 VSS
1

M_B_DQ53 166 38
M_B_DQ54 DQ53 VSS
174 43
M_B_DQ55 DQ54 VSS
176 44
2

DQ55 VSS

C1512
SC1U6D3V2KX-L-1-GP

C1513
SCD1U10V2KX-L1-GP

C1514
SC1U6D3V2KX-L-1-GP

C1515
SC1U6D3V2KX-L-1-GP

C1516
SC10U6D3V3MX-L-GP

C1517
SC10U6D3V3MX-L-GP
B M_B_DQ56 B
181 48
DQ56 VSS

1
M_B_DQ57 183 49
M_B_DQ58 DQ57 VSS
191
DQ58 VSS
54 DY
M_B_DQ59 193 55

2
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
6 M_B_DQS#[7:0] 71
M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
6 M_B_DQS[7:0] 145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
M_B_DQS2 DQS1 VSS
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
6 M_B_DIM0_ODT0 ODT0 VSS
120 178
6 M_B_DIM0_ODT1 ODT1 VSS Wistron Confidential document, Anyone can not Duplicate,
179
VSS Modify, Forward or any other purpose application without get
DDR_VREF_S3 126 184
VREF_CA VSS Wistron permission
DDR_WR_VREF_CHB 1 VREF_DQ VSS 185
A A
VSS 189
30 RESET# VSS 190 <Variant Name>
14,37 DDR3_DRAMRST#
VSS 195
VSS 196
0D675V_S0 203
204
VTT1
VTT2
VSS
VSS
205
206 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DDR3-204P-123-GP Title

DDR3-SODIMM2
2ND = 62.10024.G11 Size Document Number Rev
Custom
3RD = 62.10024.S11
4th = 62.10017.X31 Angel-CY 1
Date: Monday, April 22, 2013 Sheet 15 of 102
5 4 3 2 1
1st = 62.10024.M51
5 4 3 2 1

D D

C C

Blanking
B B

Wistron Confidential document, Anyone can not Duplicate,


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Wistron permission

<Variant Name>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2
Size Document Number Rev
A4
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 16 of 102
5 4 3 2 1
5 4 3 2 1

3D3V_S0

Angel-SA PCH1D 4 OF 10
27 PANEL_BLEN J47 L_BKLTEN SDVO_TVCLKINN AP43
1 4 LCDVDD_EN 49 LCDVDD_EN M45 AP45 RN1701
PANEL_BLEN L_VDD_EN SDVO_TVCLKINP CTR_DP_CLK
2 3 1 4
49 PCH_BKLT_CTL P45 AM42 2 3 CTR_DP_DATA
RN1702 L_BKLTCTL SDVO_STALLN
D
SDVO_STALLP AM40 D
SRN100KJ-6-GP T40 SRN2K2J-5-GP
L_DDC_CLK
K47 L_DDC_DATA SDVO_INTN AP39
SDVO_INTP AP40
T45 L_CTRL_CLK
P39 L_CTRL_DATA
AF37 LVD_IBG SDVO_CTRLCLK P38
AF36 LVD_VBG SDVO_CTRLDATA M39

AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
DDPB_HPD AT40
AK39 LVDSA_CLK#

LVDS
AK40 LVDSA_CLK DDPB_0N AV42
DDPB_0P AV40
AN48 LVDSA_DATA#0 DDPB_1N AV45
AM47 LVDSA_DATA#1 DDPB_1P AV46

Digital Display Interface


AK47 LVDSA_DATA#2 DDPB_2N AU48
AJ48 LVDSA_DATA#3 DDPB_2P AU47
DDPB_3N AV47
AN47 LVDSA_DATA0 DDPB_3P AV49
AM49 LVDSA_DATA1
AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46 CTR_DP_CLK 52
DDPC_CTRLDATA P42 CTR_DP_DATA 52
AF40 LVDSB_CLK#
C AF39 AP47 C
LVDSB_CLK DDPC_AUXN PCH_DP_AUXN 52
DDPC_AUXP AP49 PCH_DP_AUXP 52
AH45 LVDSB_DATA#0 DDPC_HPD AT38 PCH_DP_HPD 52
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47 PCH_DP_DATA0# 52
AF45 LVDSB_DATA#3 DDPC_0P AY49 PCH_DP_DATA0 52
DDPC_1N AY43 PCH_DP_DATA1# 52
AH43 LVDSB_DATA0 DDPC_1P AY45 PCH_DP_DATA1 52
AH49 LVDSB_DATA1 DDPC_2N BA47 PCH_DP_DATA2# 52
AF47 LVDSB_DATA2 DDPC_2P BA48 PCH_DP_DATA2 52
AF43 LVDSB_DATA3 DDPC_3N BB47 PCH_DP_DATA3# 52
DDPC_3P BB49 PCH_DP_DATA3 52

N48 CRT_BLUE DDPD_CTRLCLK M43


P49 CRT_GREEN DDPD_CTRLDATA M36
T49 CRT_RED

DDPD_AUXN AT45

CRT
T39 CRT_DDC_CLK DDPD_AUXP AT43
M40 CRT_DDC_DATA DDPD_HPD BH41

DDPD_0N BB43
M47 CRT_HSYNC DDPD_0P BB45
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
DAC_IREF_R T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
B B
DDPD_3P BG42
1

R1702 PANTHER-GP-NF 71.PANTH.00U


1KR2F-L1-GP
2

Wistron Confidential document, Anyone can not Duplicate,


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A <Variant Name> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (LVDS/CRT/DDI)
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 17 of 102
5 4 3 2 1
5 4 3 2 1

SSID = PCH
PCH1E 5 OF 10
RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25 TP3
D RN1801 BJ16 AT10 D
SRN8K2J-2-GP-U TP4 RSVD5
BG16 TP5 RSVD6 BC8
INT_PIRQB# 1 10 3D3V_S0 AH38
INT_PIRQA# INT_PIRQG# TP6
2 9 AH37 TP7 RSVD7 AU2
TP_IN# 3 8 INT_PIRQD# AK43 AT4
INT_PIRQC# INT_PIRQE# TP8 RSVD8
4 7 AK45 TP9 RSVD9 AT3
3D3V_S0 5 6 INT_PIRQF# C18 AT1
TP10 RSVD10
Angel-SA Angel-SA N30 AY3
H3
AH12
TP11
TP12
RSVD11
RSVD12 AT5
AV3
USB Table
TP13 RSVD13
AM4 TP14 RSVD14 AV1
AM5 BB1
Y13
TP15 RSVD15
BA3 Pair Device
TP16 RSVD16
K24 TP17 RSVD17 BB5 0 USB3.0 Ext. port 1
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7 1 TOUCH PANEL
AB45 TP20 RSVD20 BE8

RSVD
RSVD21 BD4 2 mDP
RSVD22 BF6
3 CCD
B21 TP21 RSVD23 AV5
M20 TP22 RSVD24 AV10 4 NC
AY16 TP23
BG46 TP24 RSVD25 AT8 5 NC
RSVD26 AY5 6 X
RSVD27 BA2
62 USB30_RN1 BE28 USB3RN1 7 X
BC30 USB3RN2 RSVD28 AT12
C BE32 BF3 8 C
52 USB30_RN3 USB3RN3 RSVD29 NC
BJ32 USB3RN4
62 USB30_RP1 BC28 USB3RP1 9 USB2.0 Ext. port 1
BE30 USB3RP2
52 USB30_RP3 BF32 USB3RP3 10 Card Reader
BG32 USB3RP4 USBP0N C24 USB_PN0 62
62 USB30_TN1 AV26 USB3TN1 USBP0P A24 USB_PP0 62 11 Mini Card1 (BT)
BB26 USB3TN2 USBP1N C25 USB_PN1 49
52 USB30_TN3 AU28 USB3TN3 USBP1P B25 USB_PP1 49 12 NC
AY30 USB3TN4 USBP2N C26 USB_PN2 52
62 USB30_TP1 AU26 USB3TP1 USBP2P A26 USB_PP2 52
AY26 USB3TP2 USBP3N K28 USB_PN3 49 Angel-1
52 USB30_TP3 AV28 USB3TP3 USBP3P H28 USB_PP3 49
AW30 USB3TP4 USBP4N E28
USBP4P D28
USBP5N C28
USBP5P A28
USBP6N C29
USBP6P B29
INT_PIRQA# K40 N28
INT_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28

PCI
INT_PIRQC# H38 L30
INT_PIRQD# PIRQC# USBP8N
G38 PIRQD# USBP8P K30
USBP9N G30 USB_PN9 82,97
C46 REQ1#/GPIO50 USBP9P E30 USB_PP9 82,97

USB
C44 REQ2#/GPIO52 USBP10N C30 USB_PN10 32
E40 REQ3#/GPIO54 USBP10P A30 USB_PP10 32
USBP11N L32 USB_PN11 65
D47 GNT1#/GPIO51 USBP11P K32 USB_PP11 65
B R1809 B
27,52 SYS_COM_REQ 1 2 0R2J-L-GP SYS_COM_REQ_R E42 GNT2#/GPIO53 USBP12N G32
DY F46 GNT3#/GPIO55 USBP12P E32
USBP13N C32
USBP13P A32
INT_PIRQE# G42
INT_PIRQF# PIRQE#/GPIO2
SA_1026 G40 PIRQF#/GPIO3
INT_PIRQG# C42 C33 USB_RBIAS 1 R1811 2
PIRQG#/GPIO4 USBRBIAS# 22D6R2F-L1-GP
69,97 TP_IN# D44 PIRQH#/GPIO5
Angel-SA
USBRBIAS B33
K10 PME#
Angel-1 3D3V_S5

5,27,36,65,71,77,97 PLT_RST# C6 PLTRST# OC0#/GPIO59 A14


OC1#/GPIO40 K20

1
R1807 1 TPM 2 22R2J-2-GP B17
77 CLK_PCI_TPM OC2#/GPIO41
R1804 1 DB 2 22R2J-2-GP CLK_PCI_LPC_R H49 C16 R1820
71 CLK_PCI_LPC R1805 22R2J-2-GP CLK_PCI_FB_R CLKOUT_PCI0 OC3#/GPIO42
20 CLK_PCI_FB 1 2 H43 CLKOUT_PCI1 OC4#/GPIO43 L16 10KR2J-L-GP
R1806 1 2 22R2J-2-GP CLK_PCI_KBC_R J48 A16
27 CLK_PCI_KBC CLKOUT_PCI2 OC5#/GPIO9
K42 D14

2
CLKOUT_PCI3 OC6#/GPIO10 USB_OC
H40 CLKOUT_PCI4 OC7#/GPIO14 C14

PANTHER-GP-NF
71.PANTH.00U
Wistron Confidential document, Anyone can not Duplicate,
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Wistron permission
1

A EC1801 <Variant Name> A


SC33P50V2JN-3GP
2

DY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (PCI/USB/NVRAM)
Size Document Number Rev
A3
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 18 of 102
5 4 3 2 1
5 4 3 2 1

SSID = PCH DS3 to S0

PCH1C 3 OF 10
4 DMI_RXN[3:0] FDI_TXN[7:0] 4
DMI_RXN0 BC24 BJ14 FDI_TXN0
DMI_RXN1 DMI0RXN FDI_RXN0 FDI_TXN1
BE20 DMI1RXN FDI_RXN1 AY14
DMI_RXN2 BG18 BE14 FDI_TXN2
DMI_RXN3 DMI2RXN FDI_RXN2 FDI_TXN3
Signal Routing Guideline: BG20 DMI3RXN FDI_RXN3 BH13
4 DMI_RXP[3:0] BC12 FDI_TXN4
FDI_RXN4
DMI_ZCOMP keep W=4 mils and DMI_RXP0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_TXN5
D DMI_RXP1 FDI_TXN6 D
BC20 BG10
routing length less than 500 mils. DMI_RXP2 BJ18
DMI1RXP FDI_RXN6
BG9 FDI_TXN7
DMI_RXP3 DMI2RXP FDI_RXN7
DMI_IRCOMP keep W=4 mils and BJ20 DMI3RXP FDI_TXP[7:0] 4
4 DMI_TXN[3:0] BG14 FDI_TXP0
routing length less than 500 mils. DMI_TXN0 FDI_RXP0 FDI_TXP1
AW24 DMI0TXN FDI_RXP1 BB14
DMI_TXN1 AW20 BF14 FDI_TXP2
DMI_TXN2 DMI1TXN FDI_RXP2 FDI_TXP3
BB18 DMI2TXN FDI_RXP3 BG13
DMI_TXN3 AV18 BE12 FDI_TXP4
DMI3TXN FDI_RXP4

DMI
FDI
4 DMI_TXP[3:0] BG12 FDI_TXP5
DMI_TXP0 FDI_RXP5 FDI_TXP6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_TXP1 AY20 BH9 FDI_TXP7
DMI_TXP2 DMI1TXP FDI_RXP7
AY18 DMI2TXP
DMI_TXP3 AU18 DMI3TXP
AW16 FDI_INT 4
FDI_INT
1D05V_VTT BJ24 AV12
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4
R1901 1 2 49D9R2F-GP DMI_COMP_R BG25 BC10 FDI_FSYNC1 4
DMI_IRCOMP FDI_FSYNC1
R1902 1 2 750R2F-L-GP RBIAS_CPY BH21 AV14 FDI_LSYNC0 4
DMI2RBIAS FDI_LSYNC0
BB10 FDI_LSYNC1 4
FDI_LSYNC1

3D3V_S0 R1905 1 2 10KR2J-L-GP PCH_GPIO22 PCH_GPIO22 22 DSWVRMEN


A18 DSWODVREN

R1910
S0 to DS3

System Power Management


PM_SUSACK# C12 E22 PCH_DPWROK 1 2 PM_RSMRST#
SUSACK# DPWROK 0R0402-PAD

SYS_RESET# K3 B9
22 SYS_RESET# SYS_RESET# WAKE# PCH_PCIE_WAKE# 27,65

C C
36 SYS_PWROK P12
SYS_PWROK CLKRUN#/GPIO32
N3 PM_CLKRUN# 27,77 Angel-SA

27 S0_PWR_GOOD L22
PWROK SUS_STAT#/GPIO61
G8 Angel-SA
PM_SUS_STAT# 77

L10 N14 PCH_SUSCLK_KBC 27


APWROK SUSCLK/GPIO62

B13 D10
37 PM_DRAM_PWRGD DRAMPWROK SLP_S5#/GPIO63

PM_RSMRST# C21 H4
RSMRST# SLP_S4# PM_SLP_S4# 27,46

PM_SUSWARN# K16 F4
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 27

27,97 PM_PWRBTN# E20 G10


PWRBTN# SLP_A#

H20 G16 PM_SLP_SUS#


27 AC_PRESENT ACPRESENT/GPIO31 SLP_SUS#

20 BATLOW# BATLOW# E10 AP14


BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 5

PM_RI# A10 K14


RI# SLP_LAN#/GPIO29

PANTHER-GP-NF 71.PANTH.00U

B B

Angel-SA
DSWODVREN - On Die DSW VR Enable
Angel-SA
3D3V_S5 HIGH Enabled (DEFAULT)
3D3V_AUX_S5
Non DS3 LOW Disabled
RN1901 R1909
SRN10KJ-6-GP 1 100KR2J-4-GP
2
1 8 PM_SUSACK#
2 7 PM_RI# RTC_AUX_S5
2

3 6 PCH_PCIE_WAKE#
4 5 CLK_PCIE_WLAN_REQ# R1916
CLK_PCIE_WLAN_REQ# 20,65
10KR2J-L-GP DSWODVREN R1917 1 2 330KR2F-L-GP
Angel-SA Q1901 R1912
RN1902 4 3 PM_RSMRST# 2 1KR2J-L2-GP
1 RSMRST#_KBC 27
1

SRN10KJ-6-GP
1 8 PM_SUSWARN# 3V_5V_POK_# 5 2 3V_5V_POK_C 1 R1922 2 3V_5V_POK 41 3D3V_S0
2 7 PCH_GPIO27 PCH_GPIO27 22 0R0402-PAD
3 6 PM_SLP_SUS# 6 1 R1919
4 5 AC_PRESENT
2N7002KDW-GP PM_CLKRUN# 1 2
84.2N702.A3F 8K2R2J-3-GP
2nd = 75.00601.07C
3rd = 84.2N702.F3F

Wistron Confidential document, Anyone can not Duplicate,


1 R1904 2 S0_PWR_GOOD Modify, Forward or any other purpose application without get
A Wistron permission A
100KR2J-4-GP

1 R1908 2 PM_RSMRST# <Variant Name>


100KR2J-4-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH (DM I/FDI/PM)
Size Document Number Rev
Custom
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 19 of 102
5 4 3 2 1
5 4 3 2 1

SSID = PCH Angel-SA

PCH1B 2 OF 10
3D3V_S5
BG34
PERN1 EC_SWI#
BJ34 E12
PERP1 SMBALERT#/GPIO11 RN2003
AV32
PETN1 SMB_CLK SRN2K2J-4-GP
AU32 H14
PETP1 SMBCLK SML0_DATA 8 1
BE34 C9 SMB_DATA SML0_CLK 7 2
PERN2 SMBDATA SML1_DATA
BF34 6 3
BB32
PERP2
PETN2
WWAN SML1_CLK 5 4
AY32
PETP2

SMBUS
A12
SML0ALERT#/GPIO60 DRAMRST_CNTRL_PCH 37
BG36
PERN3 SML0_CLK RN2004
BJ36 C8
D
AV34
PERP3
PETN3
Card Reader SML0CLK SRN2K2J-5-GP
D

AU34 G12 SML0_DATA SMB_DATA 4 1


PETP3 SML0DATA SMB_CLK 3 2
65 PCIE_RXN4 BF36
PERN4
BE36
65
65
PCIE_RXP4
PCIE_TXN4
C2001 1 2 SCD1U10V2KX-L1-GP PCIE_TXN4_C AY34
PERP4
PETN4
WLAN SML1ALERT#/PCHHOT#/GPIO74
C13 PCH_GPIO74
C2002 1 2 SCD1U10V2KX-L1-GP PCIE_TXP4_C BB34 Angel-SA
65 PCIE_TXP4 PETP4
E14 SML1_CLK 27,28
SML1CLK/GPIO58

PCI-E*
BG37 PCH_GPIO74 R2023 1 2
PERN5 10KR2J-L-GP
BH37 M16
AY36
PERP5
PETN5
USB3.0 SML1DATA/GPIO75 SML1_DATA 27,28
BB36
PETP5
BJ38
PERN6 DRAMRST_CNTRL_PCH
BG38 1 R2009 2
PERP6 LAN

Controller
AU36 M7 1KR2J-L2-GP
PETN6 CL_CLK1
AV36
PETP6

Link
BG40 T11
PERN7 CL_DATA1
BJ40
AY40
PERP7
PETN7
Dock
BB40 P10
PETP7 CL_RST1#
BE38
PERN8
BC38
AW38
PERP8
PETN8
NEW CARD
AY38 3D3V_S0
PETP8
M10 PEG_CLKREQ#
PEG_A_CLKRQ#/GPIO47
Y40 RN2007
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
AB37 4 1
PCIE_CLK_REQ# CLKOUT_PEG_A_N

CLOCKS
J2 AB38 3 2
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P
Angel-SA SRN2K2J-5-GP
AB49 AV22 CLK_EXP_N 5
CLKOUT_PCIE1N CLKOUT_DMI_N
AB47 AU22 CLK_EXP_P 5
CLKOUT_PCIE1P CLKOUT_DMI_P
PCIE_CLK_REQ1# M1
3D3V_S5 22 PCIE_CLK_REQ1# PCIECLKRQ1#/GPIO18
AM12 CLK_DP_N 5
CLKOUT_DP_N SMB_DATA
C AM13 CLK_DP_P 5 6 1 PCH_SMBDATA 14,15,52,69,97
C
RN2001 CLKOUT_DP_P
AA48
SRN10KJ-6-GP CLKOUT_PCIE2N Q2001
AA47 5 2
PEG_B_CLKRQ# CLKOUT_PCIE2P CLK_BUF_EXP_N 2N7002KDW-GP
1 8 BF18
BATLOW# PCIE_CLK_REQ2# CLKIN_DMI_N CLK_BUF_EXP_P
2 7 BATLOW# 19 22 PCIE_CLK_REQ2# V10
PCIECLKRQ2#/GPIO20 CLKIN_DMI_P
BE18 84.2N702.A3F 4 3
3 6 PCIE_CLK_REQ# RN2008 2nd = 75.00601.07C
4 5 EC_SWI# SRN10KJ-L-GP
Y37 BJ30 CLK_BUF_CPYCLK_N 2 3
65 CLK_PCIE_WLAN# CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_CPYCLK_P PCH_SMBCLK 14,15,52,69,97
Y36 BG30 1 4
65 CLK_PCIE_WLAN CLKOUT_PCIE3P CLKIN_GND1_P SMB_CLK
Angel-SA WLAN 19,65 CLK_PCIE_WLAN_REQ# A8
PCIECLKRQ3#/GPIO25 CLK_BUF_DOT96_N
G24
3D3V_S0 RN2018 CLKIN_DOT_96N CLK_BUF_DOT96_P
E24
SRN10KJ-6-GP CLKIN_DOT_96P
Y43
H_A20GATE CLKOUT_PCIE4N
1 8 H_A20GATE 22,27 Y45
H_RCIN# CLKOUT_PCIE4P CLK_BUF_CKSSCD_N
2 7 H_RCIN# 22,27 AK7
PEG_CLKREQ# PCIE_CLK_REQ# CLKIN_SATA_N CLK_BUF_CKSSCD_P
3 6 L12 AK5
TOUCH_DET# PCIECLKRQ4#/GPIO26 CLKIN_SATA_P
4 5 TOUCH_DET# 22 SA_1031 UMA_DIS#;DGPU_PRSNT#
V45
CLKOUT_PCIE5N REFCLK14IN
K45 CLK_BUF_REF14
CLK_BUF_REF14 22 UMA: 1 1
PCIECLKRQ1# and PCIECLKRQ2# V46
CLKOUT_PCIE5P DIS :0 1
Support S0 power only PCIE_CLK_REQ# L14
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK
H45 CLK_PCI_FB 18 SG(PX) : 0 0
Optimus(Muxless) : 1 0
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT
PEG_B_CLKRQ# E6
PEG_B_CLKRQ#/GPIO56
Y47 XCLK_RCOMP 1 R2007 2 1D05V_VTT
XCLK_RCOMP 90D9R2F-1-GP
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
PCIE_CLK_REQ# T13
PCIECLKRQ6#/GPIO45
V38 K43 DRAM_TYPE1

FLEX CLOCKS
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
V37
CLKOUT_PCIE7P DRAM_TYPE2
F47
PCIE_CLK_REQ# CLKOUTFLEX1/GPIO65
K12
PCIECLKRQ7#/GPIO46 DRAM_TYPE3 RN2009
H47
B CLKOUTFLEX2/GPIO66 SRN10KJ-L3-GP B
AK14
CLKOUT_ITPXDP_N
AK13 K49 1 10
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 CLK_BUF_DOT96_P 2 9 CLK_BUF_EXP_N
CLK_BUF_DOT96_N 3 8 CLK_BUF_EXP_P
PANTHER-GP-NF
71.PANTH.00U 4 7 CLK_BUF_CKSSCD_N
5 6 CLK_BUF_CKSSCD_P

Angel-SA

SA_1024

3D3V_S0
XTAL25_IN 2 1

SC15P50V2JN-2-GP
Angel-SA 1 4 C2008

1
X2001
R2006 XTAL-25MHZ-181-GP
1

1
1MR2F-GP 82.30020.G71
R2016 R2022 R2014 2 3
10KR2J-L-GP 10KR2J-L-GP 10KR2J-L-GP

2
RAM_DY Hynix/Samsung Elpida60/Samsung
XTAL25_OUT 2 1
2nd = 82.30020.G61
2

2
SC15P50V2JN-2-GP
C2007
DRAM_TYPE3
DRAM_TYPE2
DRAM_TYPE1
1

R2019 R2018 R2017


10KR2J-L-GP 10KR2J-L-GP 10KR2J-L-GP
A A
2

RAM Elpida Elpida33_Hynix60


Wistron Confidential document, Anyone can not Duplicate,
Modify, Forward or any other purpose application without get
Wistron permission

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH (PCI-E/SMBUS/CLOCK/CL)
Size Document Number Rev
A2
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 20 of 102
5 4 3 2 1
5 4 3 2 1

SSID = PCH RTC_AUX_S5

RTC_X1

R2120 1 2 20KR2F-L3-GP INTVRMEN- Integrated SUS


1 R2101 2 RTC_X2 R2125 1 2 20KR2F-L3-GP
10MR2J-L-GP C2103 1.05V VRM Enable

1
SC1U10V3KX-L1-GP High - Enable internal VRs
X2101
X-32D768KHZ-34GPU
Low - Enable external VRs

2
82.30001.661
D 2nd = 82.30001.B21 D
PCH1A 1 OF 10
LPC_AD[0..3] 27,71,77
1 4
RTC_X1 A20 C38 LPC_AD0
Q2102 RTCX1 FWH0/LAD0
A38 LPC_AD1
FWH1/LAD1
1

1
C2101
SC6P50V2CN-1GP

C2102
SC6P50V2CN-1GP

LPC
27 RTCRST_ON G RTC_X2 C20 B37 LPC_AD2
RTCX2 FWH2/LAD2 LPC_AD3
2 3 FWH3/LAD3 C37
D RTC_RST# D20
2

2 RTCRST#
FWH4/LFRAME# D36 LPC_FRAME# 27,71,77

2
RTCRST_ON_C S SRTC_RST# G22 SRTCRST#

1
C2104
SC1U10V3KX-L1-GP
G2101 E36
LDRQ0#

RTC
GAP-OPEN 2 R2104 1 SM_INTRUDER# K22 K36
R2118 R2117 2N7002K-2-GP 1MR2F-GP INTRUDER# LDRQ1#/GPIO23

2
100KR2J-4-GP 2K2R2F-GP 84.2N702.J31 RTC_AUX_S5 2 1 PCH_INTVRMEN C17 V5 INT_SERIRQ 27,77

1
R2105 INTVRMEN SERIRQ
2ND = 84.2N702.031
330KR2F-L-GP

2
SATA0RXN AM3 SATA_RXN0 56
HDA_BITCLK N34 AM1
HDA_BCLK SATA0RXP SATA_RXP0 56
HDD1

SATA 6G
SATA0TXN AP7 SATA_TXN0 56
HDA_SYNC L34 AP5
RTC Reset HDA_SYNC SATA0TXP SATA_TXP0 56

29 HDA_SPKR T10 SPKR SATA1RXN AM10


SATA1RXP AM8
HDA_RST# K34 AP11
HDA_RST# SATA1TXN
SATA1TXP AP10

29 HDA_SDIN0 E34 HDA_SDIN0 SATA2RXN AD7


Flash Descriptor Security Overide SATA2RXP AD5
G34 HDA_SDIN1 SATA2TXN AH5
C Low = Default AH4 C
SATA2TXP
HDA_SDOUT High = Enable C34 HDA_SDIN2

IHDA
SATA3RXN AB8
A34 HDA_SDIN3 SATA3RXP AB10
SATA3TXN AF3
SATA3TXP AF1
27 ME_UNLOCK 1 R2107 2 HDA_SDOUT A36 HDA_SDO
1KR2J-L2-GP

SATA
PLL ODVR VOLTAGE SATA4RXN Y7
SATA4RXP Y5
Low = 1.8V (Default) C36 HDA_DOCK_EN#/GPIO33 SATA4TXN AD3
HDA_SYNC High = 1.5V SATA4TXP AD1
N32 HDA_DOCK_RST#/GPIO13
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
+3VS_+1.5VS_HDA_IO 1 R2121 2 PCH_JTAG_TCK_BUF J3 AB1
4K7R2J-L-GP JTAG_TCK SATA5TXP 1D05V_VTT
H7 JTAG_TMS SATAICOMPO Y11

JTAG
1 R2103 2 HDA_SYNC
1KR2J-L2-GP K5 Y10 SATA_COMP 1 R2112 2
JTAG_TDI SATAICOMPI 37D4R2F-GP
H1 JTAG_TDO
SATA3RCOMPO AB12

AB13 SATA3_COMP 1 R2113 2


SATA3COMPI 49D9R2F-GP
Angel_SA RN2102
SRN33J-7-GP-U T3 AH1 RBIAS_SATA3 1 R2114 2
HDA_BITCLK 60 PCH_SPI_CLK SPI_CLK SATA3RBIAS 750R2F-L-GP
29 HDA_CODEC_BITCLK 1 8
B HDA_RST# B
29 HDA_CODEC_RST# 2 7 60 PCH_SPI_CS0# Y14 SPI_CS0#
HDA_SYNC_R 3 6 HDA_SYNC
4 5 HDA_SDOUT T1
29 HDA_CODEC_SDOUT SPI_CS1#

SPI
P3 SATA_LED#
SATALED#
60 PCH_SPI_SI V4 V14 SATA_DET#0
SPI_MOSI SATA0GP/GPIO21

27,60 SPI_SO_R U3 SPI_MISO SATA1GP/GPIO19 P1


Strap pin ,Internal PU
PANTHER-GP-NF 71.PANTH.00U

5V_S0
Q2101
G 3D3V_S0

D HDA_SYNC_R
RN2103
S SRN10KJ-L-GP
29 HDA_CODEC_SYNC
INT_SERIRQ 2 3
2N7002K-2-GP SATA_DET#0 1 4
84.2N702.J31
2ND = 84.2N702.031
Wistron Confidential document, Anyone can not Duplicate,
SATA_LED# 1 R2111 2 Modify, Forward or any other purpose application without get
10KR2J-L-GP Wistron permission

A <Variant Name> A

HDA_SYNC: Wistron Corporation


This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1K external pull-up resistor is required on this signal on the board. Taipei Hsien 221, Taiwan, R.O.C.
Signal may have leakage paths via powered off devices(Audio Codec) Title
and hence contend with the external pull-up.
A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device
PCH (SPI/RTC/LPC/SATA/IHDA)
Size Document Number Rev
until after the Strap sampling is complete. A3

Monday, April 22, 2013


Angel-CY 1
Date: Sheet 21 of 102
5 4 3 2 1
5 4 3 2 1

SSID = PCH

PCH1F 6 OF 10

PCH_GPIO39 S_GPIO T7 C40 PCH_GPIO68


BMBUSY#/GPIO0 TACH4/GPIO68

1
EC_SMI# A42 B41 PCH_GPIO69
R2221 TACH1/GPIO1 TACH5/GPIO69
10KR2J-L-GP DGPU_HPD_INTR# H36 C41 PCH_GPIO70
TACH2/GPIO6 TACH6/GPIO70
D E38 A40 PCH_GPIO71 D
2
27 EC_SCI# TACH3/GPIO7 TACH7/GPIO71
ICC_EN# C10
GPIO8
LAN_DISABLE# C4
LAN_PHY_PWR_CTRL/GPIO12
PCH_GPIO15 G2 P4 H_A20GATE 20,27
GPIO15 A20GATE
AU16
SATA_ODD_PRSNT# PECI
U2
SATA4GP/GPIO16
P5 H_RCIN# 20,27
RCIN#

GPIO
PCH_GPIO17 D40 AY11
TACH0/GPIO17 PROCPWRGD H_CPUPWRGD 5,97

CPU/MISC
PCH_GPIO22 T5 AY10 PCH_THERMTRIP_R 1 R2204 2 H_THERMTRIP# 5,36
19 PCH_GPIO22 SCLOCK/GPIO22 THRMTRIP# 390R2F-2GP
PCH_GPIO24 E8 T14
GPIO24 INIT3_3V#
PCH_GPIO27 E16 AY1 NV_CLE 1D8V_S0
19 PCH_GPIO27 GPIO27 DF_TVS
P8 GPIO28

1
TS_VSS1 AH8
PSW_CLR# K1 R2207
STP_PCI#/GPIO34
TS_VSS2 AK11 2K2R2F-GP
TOUCH_DET# K4
2
20 TOUCH_DET# GPIO35
AH10

2
G2201 DMI_OVRVLTG TS_VSS3
V8
Pass Word Clear GAP-OPEN SATA2GP/GPIO36
TS_VSS4 AK10 NV_CLE 1 R2205 2 H_SNB_IVB# 5
FDI_OVRVLTG M5 1KR2J-L2-GP
SATA3GP/GPIO37
1

MFG_MODE N2 P37
SLOAD/GPIO38 NC_1
C C
PCH_GPIO39 M3 SDATAOUT0/GPIO39 FDI_OVRVLTG
3D3V_S0 RN2201 Angel_SA V13 BG2 FDI TERMINATION VOLTAGE OVERRIDE(Reserved)
SRN10KJ-6-GP SDATAOUT1/GPIO48 VSS_NCTF_15#BG2

2
8 1 PCH_GPIO17 PCH_TEMP_ALERT# V3 BG48
DGPU_HPD_INTR# SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48 R2208
7 2
6 3 EC_SCI# USB3_SUPPORT D6 BH3 10KR2J-L-GP FDI_OVRVLTG LOW - Tx, Rx terminated to same voltage
EC_SMI# GPIO57 VSS_NCTF_17#BH3
5 4 (GPIO37) (DC Coupling Model DEFAULT)
BH47

1
VSS_NCTF_18#BH47
A4 BJ4
RN2202 VSS_NCTF_1#A4 VSS_NCTF_19#BJ4

NCTF
SRN10KJ-6-GP A44 BJ44 DMI_OVRVLTG
MFG_MODE VSS_NCTF_2#A44 VSS_NCTF_20#BJ44
8 1 DMI TERMINATION VOLTAGE OVERRIDE(Reserved)
7 2 PCIE_CLK_REQ1# PCIE_CLK_REQ1# 20 A45 BJ45
VSS_NCTF_3#A45 VSS_NCTF_21#BJ45

2
6 3 SYS_RESET#
SYS_RESET# 19
5 4 PSW_CLR# A46 BJ46 R2210
VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 DMI_OVRVLTG LOW - Tx, Rx terminated to same voltage
10KR2J-L-GP
A5 BJ5 (GPIO36) (DC Coupling Model DEFAULT)
VSS_NCTF_5#A5 VSS_NCTF_23#BJ5

1
RN2203 A6 BJ6
VSS_NCTF_6#A6 VSS_NCTF_24#BJ6

A4,A44,A45,A46,A5,A6,B3,B47,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
SRN10KJ-6-GP

BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
8 1 PCH_TEMP_ALERT# B3 C2
SATA_ODD_PRSNT# VSS_NCTF_7#B3 VSS_NCTF_25#C2
7 2
6 3 S_GPIO B47 C48
PCIE_CLK_REQ2# VSS_NCTF_8#B47 VSS_NCTF_26#C48 ICC_EN#
5 4 PCIE_CLK_REQ2# 20 Integrated Clock Chip Enable(Reserved)

D49,E1,E49,F1,F49
BD1 D1
VSS_NCTF_9#BD1 VSS_NCTF_27#D1

2
NCTF TEST PIN:
BD49 D49 R2211 ICC_EN# HIGH- DISABLED [DEFAULT]
RN2205 VSS_NCTF_10#BD49 VSS_NCTF_28#D49
1KR2J-L2-GP (GPIO8)
B SRN10KJ-6-GP BE1 E1 B
PCH_GPIO68 VSS_NCTF_11#BE1 VSS_NCTF_29#E1
8 1 LOW - ENABLED

1
7 2 PCH_GPIO71 BE49 E49
PCH_GPIO70 VSS_NCTF_12#BE49 VSS_NCTF_30#E49
6 3
5 4 PCH_GPIO69 BF1 F1 DY
VSS_NCTF_13#BF1 VSS_NCTF_31#F1
BF49 F49
VSS_NCTF_14#BF49 VSS_NCTF_32#F49

PANTHER-GP-NF
71.PANTH.00U
R2214
1 2 CLK_BUF_REF14 Angel_SA
CLK_BUF_REF14 20
10KR2J-L-GP
3D3V_S0
SA_1101
1

R2222
Angel-SA 10KR2J-L-GP
DY
2

3D3V_S5 SA_1106 PCH_GPIO24


RN2204
1

SRN10KJ-L-GP
1 4 USB3_SUPPORT R2220
2 3 LAN_DISABLE# 10KR2J-L-GP Wistron Confidential document, Anyone can not Duplicate,
Modify, Forward or any other purpose application without get
Wistron permission
2

A A
1 R2201 2 PCH_GPIO15
<Variant Name>
1KR2J-L2-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH (GPIO/CPU)
Size Document Number Rev
Custom
Angel-CY 1
Date: Monday, April 22, 2013 Sheet 22 of 102
5 4 3 2 1
5 4 3 2 1

1D05V_VTT PCH1G POWER 7 OF 10


3D3V_S0
1.7A
AA23 VCCCORE1 VCCADAC U48
AC23 VCCCORE2

C2311
SC22U4V3MX-GP

C2312
SC22U4V3MX-GP

C2313
SC22U4V3MX-GP

C2314
SC22U4V3MX-GP

C2315
SC22U4V3MX-GP

C2301
SC10U6D3V3MX-L-GP

C2302
SC1U6D3V2KX-L-1-GP

C2303
SC1U6D3V2KX-L-1-GP

C2304
SC1U6D3V2KX-L-1-GP
AD21

CRT
VCCCORE3

1
D AD23 VCCCORE4 VSSADAC U47 D
AF21

VCC CORE
VCCCORE5
AF23

2
VCCCORE6
DY DY DY DY DY AG21 VCCCORE7
AG23 VCCCORE8
AG24 VCCCORE9 VCCALVDS AK36
AG26 VCCCORE10
AG27 VCCCORE11 VSSALVDS AK37
AG29 VCCCORE12
AJ23 VCCCORE13

LVDS
AJ26 VCCCORE14 VCCTX_LVDS1 AM37
AJ27 VCCCORE15
AJ29 VCCCORE16 VCCTX_LVDS2 AM38
AJ31 VCCCORE17
VCCTX_LVDS3 AP36

VCCTX_LVDS4 AP37
1D05V_VTT AN19 VCCIO28

1D05V_VTT BJ22 3D3V_S0


VCCAPLLEXP
3.711A(Total) VCC3_3_6 V33

HVCMOS
AN16 VCCIO15

1
C2319

C2306
SC1U6D3V2KX-L-1-GP

C2307
SC1U6D3V2KX-L-1-GP

C2308
SC1U6D3V2KX-L-1-GP

C2309
SC1U6D3V2KX-L-1-GP
AN17 SCD1U10V2KX-L1-GP
VCCIO16

1
V34

2
VCC3_3_7
AN21

2
C VCCIO17 C
AN26 1D5V_S0
VCCIO18
AN27 VCCIO19 VCCVRM3 AT16

AP21 1D05V_VTT
VCCIO20
AP23 VCCIO21 VCCDMI1 AT20

1
DMI
AP24 C2320
VCCIO22

VCCIO
SC1U6D3V2KX-L-1-GP
AP26 AB36

2
VCCIO23 VCCCLKDMI
AT24 L2303 1D05V_VTT
VCCIO24 IND-10UH-218-GP 70mA
+1.05VS_VCC_DMI_CCI 1 2
AN33 VCCIO25 68.10050.10Y
2nd = 68.10090.10B

1
3D3V_S0 AN34 AG16 C2321
VCCIO26 VCCDFTERM1 SC1U6D3V2KX-L-1-GP
228mA(Total)

2
BH29 VCC3_3_3 VCCDFTERM2 AG17

DFT / SPI
1

VCCDFTERM3 AJ16
C2310 167mA(Total) 1D8V_S0
SCD1U10V2KX-L1-GP 1D5V_S0 AP16 2mA
2

VCCVRM2
VCCDFTERM4 AJ17
B B

C2326
SCD1U10V2KX-L1-GP

C2322
SCD1U10V2KX-L1-GP
BG6 VCCAFDIPLL

1
1D05V_VTT AP17 10mA

2
VCCIO27
V1

FDI
VCCSPI 3D3V_S5

1D05V_VTT AU20 VCCDMI2

1
47mA(Total) C2323
SCD1U10V2KX-L1-GP
PANTHER-GP-NF
71.PANTH.00U

2
Wistron Confidential document, Anyone can not Duplicate,
Modify, Forward or any other purpose application without get
Wistron permission

A <Variant Name> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH (POWER1)
Size Document Number Rev
A3

Monday, April 22, 2013


Angel-CY 1
Date: Sheet 23 of 102
5 4 3 2 1
5 4 3 2 1

SSID = PCH PCH1J POWER 10 OF 10 1D05V_VTT

AD49 VCCACLK VCCIO29 N26 Angel-SA

1
1mA P26 C2423
VCCIO30 SC1U6D3V2KX-L-1-GP
3D3V_S5 T16 VCCDSW3_3
P28 3D3V_S5

2
VCCIO31 D2401
3D3V_S0 V12 T27 Angel-SA CH751H-40PT-GP
DCPSUSBYP VCCIO32

2
83.R0304.A8F 5V_S5
D
VCCIO33 T29 2nd = 83.R0304.D8F D
T38 3D3V_S5
VCC3_3_5
95mA

1
C2402 T23

1
SC1U10V2KX-1GP VCCSUS3_3_7
BH23 VCCAPLLDMI2

1
T24 C2424

2
VCCSUS3_3_8
1D05V_VTT AL29 VCCIO14 SCD1U10V2KX-L1-GP
V23 1 R2408 2

2
VCCSUS3_3_9

USB
10R2F-L-GP
AL24 V24 3D3V_S5
DCPSUS3 VCCSUS3_3_10

1
C2426