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978-1-4799-3328-0/14/$31.00 ©2014 IEEE 2014 Symposium on VLSI Circuits Digest of Technical Papers
Chirp Injector (CI)
Amplitude of XO / A Chirp
Start-up time (tSTART) generator CI_en
Constant Frequency f
1 Injector (CFI) CI
Ring osc. t
10-1 Chirp Inv3 Negative
Inv2 Inv2 Resistance
Enable CI_en Booster
10-2 |RN| by NRB (NRB)
NRB_en
VNOISE by CI
10-3 X1 X1 X1 X1
Time
Out Inv1 Out Inv1 Out Inv1 Out Inv1
1 A
tSTART ∝ ln R1 R1 R1 R1
RN VNOISE R2 R2 R2 R2
RN : Negative resistance C1 C2 C1 C2 C1 C2 C1 C2
Quartz Quartz Quartz Quartz
A : Steady-state amplitude crystal crystal crystal crystal
VNOISE : Internal noise (a) (b) (c) (d)
Fig. 1. Strategy to reduce tSTART of XO. Fig. 2. (a) Conventional Pierce XO. (b) XO with CFI [2]. (c) XO with CI. (d) Proposed XO with CI and NRB.
VCO
tCI
Table I Performance summary.
CI_en
V Frequency 39MHz
CMOS process 180nm
t
Chirp Chirp Supply voltage 1.5V
CI_en VCNT Core area 0.12mm2
tNRB R1 500kΩ
C3
R3 NRB_en R2 10Ω
Fig. 3. Chirp generator for CI. C 1, C 2 12pF, 12pF
2.4mm 350μm Power 181μW
|RN| Boost Start-up energy 434nJ
0
Start-up time (tSTART)
tSTART 158μs
Resistor at 1.5V, 25ºC
520μm
1.3mm
0 0 0 0
0 10 20 30 40 50 60 0 5 10 15 20 0 100 200 300
Time after CI_en [μs] Gate ratio = Gate width of Inv3 / Gate width of Inv1 tNRB [μs]
Fig. 6. Measured time dependence of chirp Fig. 7. Measured gate ratio dependence of Fig. 8. Measured tNRB dependence of tSTART
frequency. tSTART and steady-state power in XO with NRB. in XO with NRB.
7 250
[%]
Start-up time (tSTART) [ms]
CFI
5 Conv.
150 NRB_en
tSTART @ 1.5V
Conv.
4 CFI
Fig. 9 100
CI (a)
3 Out
CI 50 tSTART = 2.1ms
2
1 Proposed 0
CI + NRB Proposed CI + NRB
0 -50
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 tCI = 40μs CI_en
Supply voltage [V] Supply voltage [V] tNRB = 164μs
(a) (b) NRB_en
tSTART = 158μs
Fig. 10. Measured VDD dependence of (a) tSTART and (b) relative variations of 4 XO’s in Fig. 2 at 25ºC. (b)
3 100 Out
Start-up time (tSTART) [ms]
80 -43% -57%
Conv. Fig. 9. Measured start-up waveforms. (a) Conv. XO (Fig.
2 -58% -69%
60 2 (a)). (b) Proposed XO with CI and NRB (Fig. 2 (d)).
-88% -94%
-92% Table II Comparison with previously reported XO’s.
CFI 40 -98%
1 [3] [4] [5] [6] This
work
CI 20 Frequency MHz 26 19 32 39 39
Proposed CI + NRB CMOS process nm 65 130 NA 40 180
0 0 Supply voltage V 1.2 1.2 3.0 0.7 1.5
-40 -20 0 20 40 60 80 100 120 CFI CI CI CFI CI CI CFI CI CI
+ + + Power μW 1440 22 180 69 181
Temperature [ºC] NRB NRB NRB
Start-up time μs 3200 1200 250 259 158
Typical Low VDD High temperature (tSTART)
Fig. 11. Measured temperature dependence of (1.5V, 25ºC) (1.2V, 25ºC) (1.5V, 125ºC)
tSTART is robust to No No NA No Yes
tSTART of 4 XO’s in Fig. 2 at VDD = 1.5V. Fig. 12. Comparisons of tSTART of 4 XO’s. PVT variations.