Journal of Advanced Research in Electronics Engineering and Technology

Volume 5, Issue 1 - 2018, Pg. No. 1-7

Peer Reviewed Journal
Research Article

Single Precision Reconfigurable Floating-Point

Multiplier Using Reversible Logic
Arati B. Sudhaka1, Ramesh Chandra Panda2
1
ECE, S.G. Balekundri Institute of Technology Technology, Belgaum, Karnataka, India.
2
School of Mechanical Engineering, Lingayas University, Faridabad, India.

Abstract
To implement reversible computation, estimate its cost, and to judge its limits, it is formalized in terms of
gate-level circuits. For example, the inverter (logic gate) (NOT) gate is reversible because it can be undone.
The exclusive or (XOR) gate is irreversible because its inputs cannot be unambiguously reconstructed from
an output value. However, a reversible version of the XOR gate – the controlled NOT gate (CNOT) – can be
defined by preserving one of the inputs. The three-input variant of the CNOT gate is called the Toffoli gate.
It preserves two of its inputs a, b and replaces the third c by c. (a . b). With c=0, this gives the AND function,
and with a\cdot b=1 this gives the NOT function. Thus, the Toffoli gate is universal and can implement
any reversible Boolean function (given enough zero-initialized ancillary bits). More generally, reversible
gates have the same number of inputs and outputs. A reversible circuit connects reversible gates without
fanouts and loops. Therefore, such circuits contain equal numbers of input and output wires, each going
through an entire circuit.

Reversible logic circuits were first motivated in the 1960s by theoretical considerations of zero-energy
computation as well as practical improvement of bit-manipulation transforms in cryptography and computer
graphics. Since the 1980s, reversible circuits have attracted interest as components of quantum algorithms,
and more recently in photonic and nano-computing technologies, where some switching devices offer no
signal gain. Surveys of reversible circuits, their construction and optimization as well as recent research
challenges are available.

Keywords: Optimization, Reversible Circuits, Fredkin, Toffoli, Floating-point

Introduction to Reversible Circuits
To implement reversible computation, estimate its cost,
and to judge its limits, it is formalized in terms of gate-
level circuits. For example, the inverter (logic gate) (NOT)
gate is reversible because it can be undone. The exclusive
or (XOR) gate is irreversible because its inputs cannot
be unambiguously reconstructed from an output value.
However, a reversible version of the XOR gate – the
controlled NOT gate (CNOT) – can be defined by preserving
one of the inputs. The three-input variant of the CNOT
gate is called the Toffoli gate. It preserves two of its inputs
a, b and replaces the third c by c. (a . b). With c=0, this
gives the AND function, and with a\cdot b=1 this gives the
NOT function. Thus, the Toffoli gate is universal and can
implement any reversible Boolean function (given enough
zero-initialized ancillary bits). More generally, reversible
gates have the same numbers of inputs and outputs. A
reversible circuit connects reversible gates without fanouts
and loops. Therefore, such circuits contain equal numbers
of input and output wires, each going through an entire
circuit.

Corresponding Author: Ramesh Chandra Panda, School of Mechanical Engineering, Lingayas University, Faridabad, India.
E-mail Id: ramesh.panda@gnauniversity.edu.in
Orcid Id: https://orcid.org/0000-0002-0801-7961
How to cite this article: Sudhaka AB, Panda RC. Single Precision Reconfigurable Floating-Point Multiplier Using Reversible Logic. J
Adv Res Electro Engi Tech 2017; 5(1&2): 1-7.

Copyright (c) 2018 Journal of Advanced Research in Electronics Engineering and Technology (ISSN: 2456-1428)
Sudhaka AB et al.
J. Adv. Res. Electro. Engi. Tech. 2017; 5(1&2)
Reversible logic circuits were first motivated in the 1960s
by theoretical considerations of zero-energy computation
as well as practical improvement of bit-manipulation
transforms in cryptography and computer graphics. Since
the 1980s, reversible circuits have attracted interest as
components of quantum algorithms, and more recently
in photonic and nano-computing technologies, where
some switching devices offer no signal gain. Surveys of
reversible circuits, their construction and optimization as
well as recent research challenges are available.
Fundamentals of Reversible Logic
Landauer’s research in the early 1960s demonstrated
that irreversible hardware computation, regardless of its
realization technique, results in energy dissipation due to
the information loss. It is proved that the loss of each one
bit of information dissipates at least KTln2 joules of energy
(heat), where K=1.38×10−23m2kg−2K−1 (joules Kelvin−1) is the
Boltzmann’s constant and T is the absolute temperature
at which operation is performed. Reversible logic circuits
(or gates) are information lossless. Hence, reversible logic
circuits have theoretically zero internal power dissipation. In
1973, Bennett proved that to avoid KTln2 joules of energy
dissipation in a circuit, it must be built using reversible
logic gates.
A circuit is said to be reversible if the input vector can be
uniquely determined from the output vector and there is a
one-to-one correspondence between its input and output
assignments, i.e., not only the outputs can be uniquely
determined from the inputs but also the inputs can be
recovered from the outputs. Thus, the number of inputs
and outputs in reversible logic circuits (gates) are equal.
Such circuits (gates) allow the reproduction of the inputs
from observed outputs and we can recover the inputs
from the outputs.
Reversible circuits are circuits (gates) in which:
• The number of input bits of a given reversible circuit
is equal to the number of output bits. For example,
if a circuit with input vector is of length 5, then the
output vector length should be 5.
• There should be one-to-one mapping between input
and output vectors. No two or more than two input
vectors give the same output vector.
A Feynman
B Gate
Feynman
Gate
C in
Feynman
0 Gate
Figure 1.Full Adder Using Three Feynman Gates and One Fredkin Gate
ISSN: 2456-1428
2
• The input vector can always be reconstructed from
the output vector.
Toffoli and Fredkin discovered reversible logic in the late 70s
and early 80s. Any reversible logic gate can be characterized
by its number of inputs and outputs. A m*n gate has m
inputs and n outputs. There are several 2*2 reversible
gates and all of them are linear. A gate is said to be linear
when all its outputs are linear functions of input variables.
Implementation of Full-Adder Design Using
Reversible Gates
The most conventional way to synthesize a logic circuit
is CMOS implementation. Reversible circuits can also be
constructed using CMOS. The power consumption of logic
circuit implemented in CMOS of reversible circuit is not
guaranteed to be less than that of conventional circuit
(non-reversible). The reason behind this is that the power
saved by the reversible property of a circuit is very less
compared to the power consumption by any CMOS design.
Thus, to make use of this power saved due to reversibility,
we need to have a technology which implements logic
circuits that would consume much less power compared to
current CMOS technology. CMOS technology can be used
for functional testing and for comparing area and delay.
Three full adders can be constructed using different
combinations of basic reversible gates, i.e., Toffoli, Fredkin
and Feynman gates.
• Two Toffoli gates and two Feynman gates give two
garbage outputs.
• Three Feynman gates and one Fredkin gate give two
garbage outputs.
• Five Fredkin gates give five garbage outputs.
The full adder which has been discussed further is made
using three Feynman gates and one Fredkin gate, which
has minimum area and complexity in comparison to above
three full adders as shown in Fig. 1. It has minimum number
of garbage outputs as compared to any other reversible
full adder that produces two garbage outputs. The full
adder output produces the same output (1, 0) for the three
distinct input combinations (0, 0, 1), (0, 1, 0) and (1, 0, 0).
Therefore, to separate all the repeated values of outputs
S and Cout we need at least two garbage outputs.
G1
Fr edkin
Cout
Gat e
G2
Sum
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Floating-Point Multiplication Algorithm real numbers in binary format; the IEEE 754 standard
presents two different floating-point formats, binary
Floating-point numbers are one possible way of representing interchange format and decimal interchange format.

Figure 2.IEEE 754 Format of Representing Single Precision Floating-point Numbers

The algorithm for floating-point multiplication consists of • Add the exponents.
the following steps: • Multiply the mantissas.
• Normalize the product and round using the specified
• Check for zeros, NaN’s, inf on inputs. rounding mode. Also generate exceptions.

Figure 2.1Flow Chart Describing the Single Precision Floating-point Multiplication Algorithm

Figure 3.Simulation Results Illustrating the Multiplication Operation

Reversible Full Adder Implementation
In order to test the effect of reversible logic in IEEE standard
floating-point multiplier, we short list the following
reversible logic circuits that are proven to perform well.
The full adder is the most important part of a floating-point
multiplier and forms about 70% of the logic. Hence, it is best
to evaluate the effect of reversible logic by implementing
a reversible full adder. The following reversible full adder
implementations are considered for evaluation.
Full Adder Using DKG Gate
A 4*4 reversible DKG and TSG gate that can work singly as
a reversible full adder and as a reversible full subtractor
is shown in Fig. 4. It can be verified that input pattern
corresponding to a particular output pattern can be
uniquely determined. Its implementation as a full adder
is shown in Fig. 5. If input A=0, the proposed gate works
as a reversible full adder, and if input A=1, then it works
as a reversible full subtractor. It has been proved that a
reversible full-adder circuit requires at least two garbage
outputs to make the output combinations unique, which is
the primary condition for a reversible circuit. The proposed
reversible full adder circuit produces two garbage outputs,
so it is optimal in terms of number of garbage outputs.

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Sudhaka AB et al.
J. Adv. Res. Electro. Engi. Tech. 2017; 5(1&2) 4

Figure 4.DKG Gate

Figure 5.A Full-Adder Implemented Using DKG gate

Full-Adder Using TSG Gate gate is capable of implementing all Boolean functions
and can also work singly as a reversible full adder. Figure
The reversible TS gate is shown in Fig. 6. It can be verified 7 shows the implementation of the proposed gate as a
that input pattern corresponding to a particular output reversible full adder.
pattern can be uniquely determined. The proposed TSG

Figure 6.TSG Gate Configuration

Figure 7.TSG Configured as a Full-Adder

Full Adder Using Fredkin Gate
The Fredkin gate (also CSWAP gate) is a computational
circuit suitable for reversible computing, invented by Ed
Fredkin. It is universal, which means that any logical or
arithmetic operation can be constructed entirely of Fredkin
gates. The basic Fredkin gate is a controlled swap gate that
maps three inputs (C, I1, I2) onto three outputs (C, O1, O2).
The C input is mapped directly to the C output. If C=0,
no swap is performed; I1 maps to O1, and I2 maps to O2.
Otherwise, the two outputs are swapped so that I1 maps
to O2, and I2 maps to O1. It is easy to see that this circuit
is reversible, i.e., “undoes itself” when run backwards.
A generalized n×n Fredkin gate passes its first n-2 inputs
unchanged to the corresponding outputs, and swaps its
last two outputs if and only if the first n-2 inputs are all 1.
The Fredkin gate is the reversible three-bit gate that swaps
the last two bits if the first bit is 1.

Figure 8.Fredkin Gate

Figure 9.Fredkin Full-Adder

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Full Adder Using FTRG Gate
A New 5×5 fault-tolerant reversible Gate, FTRG, is shown in
Fig. 2. This gate is not a one-through gate. From the truth
table, it can be observed that every output is having unique
input. Input can be recovered from output or output from
input. Any arbitrary Boolean function can be implemented
by using FTRG, so it is called as universal gate. The proposed
gate is parity preserving. This can be verified by comparing
the parity of the input to the parity of the output that is A
B C D E and P Q R S T. A full-adder can be realized
using FTRG as shown in Fig. 10.

Figure 10.FTRG Configuration

Figure 11.Full Adder Using FTRG Gate

Full Adder Using PFAG Gate
PFAG is based on the Peres gate as shown in Fig. 12. PFAG
has 4-input lines and 4-output lines. This gate can be used
to realize any arbitrary Boolean function and is, therefore,
universal. The hardware complexity of this gate is less
compared to the existing ones and requires only one clock
cycle. The quantum realization cost of this gate is only 8 and
it is ready for use in current nanotechnology. Reversible logic
design differs significantly from traditional combinational
logic design approaches. A full-adder implementation
using the Peres gates, also known as Peres full-adder gate
is shown in Fig. 12.

Figure 12.Peres Gate

Figure 13.Peres Full-Adder Gate

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Figure 14.Methodology

Table 15
Conventional DKG Peres Fredkin FTRG TSG
Area (LUTS) 4357 4750 4395 4420 4403 4378
Speed (MHz) 16.6 18.77 16.47 23.46 16.584 16.668
Power (mW) 0.412 0.047 0.081 0.040 0.110 0.114

Methodology for Testing the Effects
The methodology for testing the effects of using reversible
logic in the given floating-point multiplier is best explained
through a flow chart:
Results
The area and speed (delay) information can be noted from
the synthesis report generated by the Xilinx synthesis tool.
Power analysis is done using the Xilinx XPower tool.
Clearly, of the various implementations, the floating-point
unit with reversible logic in almost all the chosen cases has
performed better in terms of power. However, there can
be variations in area and speed since reversible logic uses
more regular logic to satisfy and implement the reversible
logic principles in the design. One more point to note is
that this analysis is done on the FPGA platform that uses
LUTs and flip-flops.
Conclusion
Floating-point implementation on FPGAs has been the
interest of many researchers. Multiplier implemented
with the reversible logic can be conveniently modeled in
Verilog and tested on a FPGA. A lot of work has been done
on implementing basic multipliers but not the floating-
point multipliers with reversible computing. In this project
work, a floating-point single precision multiplier will be
designed with Verilog and implemented on the FPGA.
It can be concluded that the floating-point multiplier
shows significant improvement in terms of power and
improvements in certain cases in terms of area and speed,
when implemented using reversible logic.
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Date of Submission: 2018-1-20
Date of Acceptance: 2018-2-27
ISSN: 2456-1428