Simulation-Based Study of
III-V(InSb) HEMTs Device Physics for
High-Speed Low-Power Logic Applications
Mr.D.Godwin Raj, Dr.N.MohanKumar
1
PG Student, S.K.P Engineering College, Thiruvannamalai
godwinraj123@gmail.com
2
Professor, S.K.P Engineering College, Thiruvannamalai
Abstract: As documented by the (International
Roadmap for semiconductors (ITRS), power consumption
has been bottleneck for future silicon CMOS technology
scaling. To address this challenge, both industry and
academic are investigating alternative structures and
materials, among which III-V compound high electron
mobility transistors(HEMTs) stand out as one of the
promising device candidates for future high-speed, low-
power digital logic applications, because their light
effective masses lead to high electron mobilities and high
on-current, which should translate into high device
performance at low supply voltage.
1. INTRODUCTION
InSb, the highest bulk electron mobility reported is
78000 cm2V-1s-1 and the highest hole mobility
reported is 800 cm2V-1s-1 and bandgap of 0.17ev.
This makes fast devices based on InSb possible. As
documented by the International Roadmap for
semiconductors (ITRS), power consumption has
been bottleneck for future silicon CMOS
technology scaling. To address this challenge, both
industry and academic are investigating alternative
structures and materials, among which III-V
compound high electron mobility
transistors(HEMTs) stand out as one of the
promising device candidates for future high-speed,
low-power digital logic applications, because their
light effective masses lead to high electron
mobilities and high on-current, which should
translate into high device performance at low
supply voltage.
The rapid progress in nanofabrication technology
has shed light on the potential use of III-V HEMT
in future electronics. Consequently, understanding
device physics of SNWTs and developing TCAD
(Technology Computer Aided Design) tools for
SNWT design become increasingly important. The
principle objective of the project is to theoretically
explore device physics of InSb MOSFET by doing
computer-based numerical simulations
Indium antimonide (InSb) shows great promise as
an ultra-fast, very low power technology as it has
the highest electron mobility and saturation
velocity of any known semiconductor (Table 1).
This was earlier demonstrated in a carrier-extracted
enhancement mode MOSFET device, using an
InSb device layer on an InSb substrate with a
deposited SiO2 gate oxide. In this paper, we report
the materials growth, device fabrication and
characterisation of an InSb channel quantum well
FET, which uses a semi-insulating GaAs substrate,
a relaxed metamorphic buffer layer of AlyIn1-ySb,
a compressively strained InSb quantum well
confined between layers of AlxIn1-xSb and a
Schottky barrier metal gate.
For InSb, the highest bulk electron mobility
reported is 78000 cm2V-1s-1 and the highest hole
mobility reported is 800 cm2V-1s-1, this makes
fast devices based on InSb possible. Several
standard mobility models are used for InSb based
devices. For high accuracy of simulation, we have
to extract the model parameters from published
data.
2. INSB QW TRANSISTOR FABRICATION
Fig. 1 shows the InSb p-channel QW device
structure used in this work. The structure is grown
on (100) GaAs substrates using sentaurus TCAD.
The biaxial compressive strain in the InSb QW is
modulated between 1.0-2.0% using different Al
composition in the AlxIn1-xSb barrier layers
(0.15≤x≤0.35).

Fig. 1: Schematic of InSb p-channel compressively
strained QWFET structure on GaAs. Al composition (x)
in the barrier layers is varied from 0.15 to 0.35 to provide
compressive strain and hole confinement in the InSb
QW.
Comparing with other semiconductors, InSb has
the narrowest band gap (Eg= 0.17eV), low electron
effective mass at the bottom of conduction band,
and low hole effective mass at the top of valence
band. At the bottom of conduction band, InSb has a
very large nonparabolicity factor around 5 which
deviates from the traditional parabolic model of the
E-k relationship.
Fig. 2: Schematic of InSb QW with concentration using
Synopsys Tecplot.
However the carrier concentration has less than one
order of magnitude difference between the
traditional parabolic model and the modified model
considering of the parabolicity factor. To simplify
the simulation, in this work we use the traditional
parabolic model for carrier concentration
calculation. The density of states (DOS) at the
bottom of conduction band and at the top of
valence band is high. The intrinsic carrier density is
also very high. Comparing with other
semiconductor materials, the intrinsic carrier
concentration of InSb is about six orders of
magnitude higher than that of 36 Silicon, nine
orders of magnitude higher than that of GaAs. This
large number of minority carriers cause high
junction reverse saturation current.
3 . DC CHARACTERIZATION
However the transferred electron effect has not
been observed on InSb QW transistor yet, therefore
the transferred electron effect model is not
considered in the electron mobility models for the
InSb based FET devices in this work. Simulated
output characteristics of the same InSb NMOS
transistor without the transferred electron effect
shown in graph. Another advantage of InSb based
MOSFET is the high current driving capability.
Where the drain current of InSb NMOS is almost
three times as high as the drain current of Si
NMOS of InSb MOSFE due to the high mobility of
InSb.
Figure .3: 40 nm LG InSb QW transistor transfer
characteristics at 295 K, Type B material, LDS = 2 μm,
WG = 80 μm, Vg = 0.5 V,
However the transferred electron effect has not
been observed on InSb QW transistor yet, therefore
the model is not considered in modeling for the
InSb based FET devices.

Figure. 4: Id vs. Vd for InSb Planar MOSFET with
transferred electron effect.
Both off state leakage current and turn on current
of InSb MOSFETs is much higher than that of
silicon devices as shown in Fig.9. The high turn on
current is due to high mobility of InSb. High off
state leakage current however is because InSb has
large intrinsic carrier density (ni =1.9´1016 cm-3)
which is six order of magnitude higher than that of
silicon. Several techniques have been demonstrated
to reduce leakage current of
Figure 5.Off state leakage current/turn on current of InSb
NMOS and Si NMOS
InSb based devices, such as exclusion and
extraction electromagnetic carrier depletion low
temperature operation etc. Both leakage current of
Si and InSb devices increase as the device scales
down, but leakage current for InSb NMOS shows a
less increasing rate than silicon NMOS as the
device scales, which shows the InSb devices might
have the similar leakage current as silicon device in
sub 50nm regime. A traditional method to reduce
off state leakage current of InSb device is device
cooling as shown in Fig.5. At 200K the InSb
NMOS has more than two orders of magnitude less
leakage current.
4. CONCLUSION
In summary, we have demonstrated for the first
time InSb quantum well transistors in TCAD down
to 40 nm gate length with comparable high
frequency performance to today’s Si MOSFET’s .
The drain current and gate voltage characteristics
are ploted using TCAD sentaurus.
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