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Description ID = 36A
S
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low on-
resistance per silicon area. Additional features of
this design are a 175°C junction operating tempera-
ture, fast switching speed and improved repetitive
avalanche rating . These features combine to make
this design an extremely efficient and reliable device
for use in Automotive applications and a wide variety
TO-220AB D2Pak TO-262
IRF540Z IRF540ZS IRF540ZL
of other applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 36
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 25 A
IDM Pulsed Drain Current c 140
PD @TC = 25°C Power Dissipation 92 W
Linear Derating Factor 0.61 W/°C
VGS Gate-to-Source Voltage ± 20 V
d
EAS (Thermally limited) Single Pulse Avalanche Energy 83 mJ
EAS (Tested ) Single Pulse Avalanche Energy Tested Value h 120
IAR Avalanche Current c See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy g mJ
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting Torque, 6-32 or M3 screw i y
10 lbf in (1.1N m)y
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.64 °C/W
RθCS Case-to-Sink, Flat Greased Surface i 0.50 –––
RθJA Junction-to-Ambient i ––– 62
RθJA Junction-to-Ambient (PCB Mount) j ––– 40
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IRF540Z/S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.093 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 21 26.5 mΩ VGS = 10V, ID = 22A e
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 36 ––– ––– V VDS = 25V, ID = 22A
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 100V, VGS = 0V
––– ––– 250 VDS = 100V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 42 63 ID = 22A
Qgs Gate-to-Source Charge ––– 9.7 ––– nC VDS = 80V
Qgd Gate-to-Drain ("Miller") Charge ––– 15 ––– VGS = 10V e
td(on) Turn-On Delay Time ––– 15 ––– VDD = 50V
tr Rise Time ––– 51 ––– ID = 22A
td(off) Turn-Off Delay Time ––– 43 ––– ns RG = 12 Ω
tf Fall Time ––– 39 ––– VGS = 10V e
LD Internal Drain Inductance ––– 4.5 ––– Between lead, D
nH 6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package G
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IRF540Z/S/LPbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
ID, Drain-to-Source Current (A)
4.5V
10 10
4.5V
60µs PULSE WIDTH 60µs PULSE WIDTH
Tj = 25°C Tj = 175°C
1 1
0.1 1 10 100 0.1
0 1 10 100
100
VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)
1000 80
T J = 175°C
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
60
100
T J = 175°C
40
T J = 25°C
10
T J = 25°C
20
VDS = 25V
VDS = 10V
60µs PULSE WIDTH
380µs PULSE WIDTH
1
4.0 5.0 6.0 7.0
0
0 10 20 30 40 50
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
3000 20
VGS = 0V, f = 1 MHZ ID= 22A
C iss = C gs + C gd, C ds SHORTED
VDS= 80V
2000
Ciss
12
1500
8
1000
4
500 Coss FOR TEST CIRCUIT
Crss SEE FIGURE 13
0
0
1 10 100 0 10 20 30 40 50 60
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
1000.0 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ISD, Reverse Drain Current (A)
100.0 100
T J = 175°C
10.0 10 100µsec
1.0 1
T J = 25°C 1msec
Tc = 25°C
VGS = 0V Tj = 175°C 10msec
Single Pulse
0.1 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1 10 100 1000
VSD, Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V)
40 3.0
ID = 22A
(Normalized)
2.0
20
1.5
10
1.0
0 0.5
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
10
Thermal Response ( Z thJC )
1
D = 0.50
0.20
0.10
0.1 0.05
0.02
0.01
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
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IRF540Z/S/LPbF
180
15V
ID
60
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS 40
tp
20
0
25 50 75 100 125 150 175
I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
QG
10 V
QGS QGD 4.0
VGS(th) Gate threshold Voltage (V)
VG
3.5
ID = 250µA
Charge 3.0
2.0
L
VCC
DUT
0 1.5
1K -75 -50 -25 0 25 50 75 100 125 150 175
T J , Temperature ( °C )
Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature
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IRF540Z/S/LPbF
1000
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
Avalanche Current (A)
0.1
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
*
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
Recovery Body Diode Forward
-
+ Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Ripple ≤ 5% ISD
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
RD
VDS
VGS
D.U.T.
RG
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
VDS
90%
10%
VGS
td(on) tr t d(off) tf
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IRF540Z/S/LPbF
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IRF540Z/S/LPbF
OR
P AR T N U M B E R
IN T E R N AT IO N AL
R E C T IF IE R F 530S
L O GO
D AT E CO D E
P = D E S IG N AT E S L E AD - F R E E
AS S E M B L Y P R O D U C T (O P T IO N AL )
L OT COD E Y E AR 0 = 2 0 0 0
WE E K 02
A = AS S E M B L Y S IT E C O D E
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IRF540Z/S/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
OR
PART NUMBER
INT ERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DES IGNAT ES LEAD-FREE
AS S EMBLY PRODUCT (OPT IONAL)
LOT CODE YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S IT E CODE
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IRF540Z/S/LPbF
D2Pak Tape & Reel Infomation
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
4.10 (.161) 1.50 (.059)
3.90 (.153) 0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
30.40 (1.197)
NOTES : MAX.
1. COMFORMS TO EIA-418. 26.40 (1.039) 4
2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)
3. DIMENSION MEASURED @ HUB.
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Notes:
Repetitive rating; pulse width limited by
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
max. junction temperature. (See fig. 11). avalanche performance.
Limited by TJmax, starting TJ = 25°C, L = 0.46mH This value determined from sample failure population. 100%
RG = 25Ω, IAS = 20A, VGS =10V. Part not tested to this value in production.
recommended for use above this value. This is only applied to TO-220AB pakcage.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%. This is applied to D2Pak, when mounted on 1" square PCB (FR-
Coss eff. is a fixed capacitance that gives the 4 or G-10 Material). For recommended footprint and soldering
same charging time as Coss while VDS is rising
techniques refer to application note #AN-994.
from 0 to 80% VDSS .
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 7/04
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