DEPARTMENT OF ELECTRONICS AND COMMUNCATION

ENGINEERING

ACADEMIC YEAR: 2017 - 2018

LABORATORY RECORD

Name : ____________________________________________

Register No.: ______________________ Roll No.:______________

Branch : ____________________________________________

Semester : _____________________ Year:__________________

Subject : ______________________Subject Code:___________

1
 BONAFIDE CERTIFICATE

_______________________ LABORATORY RECORD

2017 - 2018
Certified to be the bonafide record work done by
____________________________________Reg.No______________________in
____________________________ (sub code & name) of Akshaya College of Engineering
and Technology, Coimbatore during the academic year 2017-2018.

Faculty In-charge Head of the Department

Submitted for Anna University, Practical Examination held on ------------------------- at

Akshaya College of Engineering and Technology, Coimbatore.

Internal Examiner External Examiner

Date: Date:

2
 LIST OF EXPERIMENT

Exp. DATE NAME OF THE EXPERIMENT Page. Marks Signature

no No

LIST OF ANALOG EXPERIMENTS::

1 Half Wave and Full Wave Rectifiers, Filters, Power supplies

2 Frequency Response of CE, CB, CC and CS amplifiers

3 Darlington Amplifier

4 Differential Amplifiers- Transfer characteristic, CMRR

Measurement
5 Cascode / Cascade amplifier

6 Class A and Class B Power Amplifiers

7 Determination of bandwidth of single stage and multistage

amplifiers
8 Spice Simulation of Common Emitter and Common Source
amplifiers
LIST OF DIGITAL EXPERIMENTS

9 Design and implementation of code converters using logic

gates
(i) BCD to excess-3 code and vice versa (ii) Binary to gray
and vice-versa
10 Design and implementation of 4 bit binary Adder/ Subtractor
and BCD adder using IC 7483
11 Design and implementation of Multiplexer and De-
multiplexer using logic gates
12 Design and implementation of encoder and decoder using
logic gates
13 Construction and verification of 4 bit ripple counter and Mod-
10 / Mod-12 Ripple counters
14 Design and implementation of 3-bit synchronous up/down
counter
15 Implementation of SISO, SIPO, PISO and PIPO shift registers
using Flip- flops

3
CIRCUIT DIAGRAM: HALFWAVE RECTIFIER

WITHOUT FILTER:

WITH FILTER:

4
EX.No: 1,a POWER SUPPLY CIRCUIT - HALF WAVE RECTIFIER WITH
DATE : SIMPLE CAPACITOR FILTER.

AIM:
To construct half wave rectifier with and without filter and to draw their input and
output waveforms.

APPARATUS REQUIRED:

S.No. Name Range Quantity

1. Transformer 230 V / 6-0-(-6) 1

2. Diode IN4007 1

3. Resistor 1 kΩ 1

4. Capacitor 100µF 1

5. CRO 30 MHz 1

6. Bread Board 1

FORMULA USED:

Ripple Factor (γ) = RMS value of ac component / DC value of load voltage

= VL (ac) / VL (dc)
Where VL (ac) is the peak voltage of ac input
VL (dc)is the peak voltage of dc output

5
MODEL GRAPH:

HALF WAVE RECTIFIER:

Without filter With filter

Input
signal Output signal

Amplitude Time period Amplitude Time period

(V) (sec) (V) (sec)

6
THEORY:

Half wave rectifier:

A rectifier is a circuit, which uses one or more diodes to convert A.C voltage into D.C
voltage. In this rectifier during the positive half cycle of the A.C input voltage, the diode is
forward biased and conducts for all voltages greater than the offset voltage of the semiconductor
material used. The voltage produced across the load resistor has same shape as that of the
positive input half cycle of A.C input voltage. During the negative half cycle, the diode is
reverse biased and it does not conduct. So there is no current flow or voltage drop across load
resistor. The net result is that only the positive half cycle of the input voltage appears at the
output.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Apply a.c input using transformer.

3. Measure the amplitude and time period for the input and output waveforms.

4. Calculate ripple factor.

RESULT:

7
CIRCUIT DIAGRAM:

FULLWAVE RECTIFIER WITHOUT FILTER

FULLWAVE RECTIFIER WITH FILTER

8
EX.No: 1,b POWER SUPPLY CIRCUIT - FULL WAVE RECTIFIER WITH
DATE : SIMPLE CAPACITOR FILTER.

AIM:

To construct a full wave rectifier and to measure dc voltage under load and to calculate
the ripple factor.

APPARATUS REQUIRED:

Quantity
S.No. Name Range
1
1. Transformer 230 V / 6-0-(-6)
2
2. Diode IN4007
1
3. Resistor 1 kΩ
1
4. Capacitor 100µF
1
5. CRO 30 MHz
1
6. Bread Board

FORMULA

Ripple Factor (γ) = RMS value of ac component / DC value of load voltage

= VL (ac) / VL (dc)

Where VL (ac) is the peak voltage of ac input

VL (dc)is the peak voltage of dc output

9
MODEL GRAPH:

Without filter With filter

Input
signal Output signal

Amplitude Time period Amplitude Time period

(V) (sec) (V) (sec)

10
THEORY:

The full wave rectifier conducts for both the positive and negative half cycles of the input
ac supply. In order to rectify both the half cycles of the ac input, two diodes are used in this
circuit. The diodes feed a common load RL with the help of a centre tapped transformer. The ac
voltage is applied through a suitable power transformer with proper turn’s ratio. The rectifier’s
dc output is obtained across the load.
The dc load current for the full wave rectifier is twice that of the half wave rectifier. The
lowest ripple factor is twice that of the full wave rectifier. The efficiency of full wave
rectification is twice that of half wave rectification. The ripple factor also for the full wave
rectifier is less compared to the half wave rectifier.

PROCEDURE:

1. Connections are given as per the circuit diagram without filter.

2. Note the amplitude and time period of the input signal at the secondary winding of
the transformer and rectified output.

3. Repeat the same steps with the filter and measure Vdc.

4. Calculate the ripple factor.

5. Draw the graph for voltage versus time.

RESULT:

11
Common Emitter Amplifier Circuit Diagram:

MODEL GRAPH:

12
EX.No:2.a FREQUENCY RESPONSE OF COMMON EMITTER AMPLIFIER
DATE :

AIM:
To construct a Common Emitter Amplifier circuit and to plot it’s frequency response
characteristics.
APPARATUS REQUIRED:
Signal generator : 1MHz
Power supply : 10V
CRO : 30 MHz

COMPONENTS REQUIRED:
Transistor : BC107
Biasing resistor R1, R2 : 56KΩ, 12KΩ
Bypass resistor R3 : 470Ω
Coupling resistor RC : 2.2KΩ
Bypass capacitor CE : 47µF
Coupling capacitor Cc : 2.2µF
Feedback resistor Rf : 470Ω

THEORY:

This type of biasing is otherwise called Emitter Biasing. The necessary biasing is
provided using 3 resistors: R1, R2 and R3. The resistors R1 and R2 act as a potential divider and
give a fixed voltage to the base. If the collector current increases due to change in temperature or
change in β, the emitter current IE also increases and the voltage drop across R3 increases,
reducing the voltage difference between the base and the emitter. Due to reduction in VBE, base
current IB and hence collector current IC also reduces. This reduction in VBE, base current IB and
hence collector current IC also reduces. This reduction in the collector current compensates for
the original change in IC. The stability factor S= (1+β) * ((1/ (1+β)). To have better stability,
we must keep RB/R3 as small as possible. Hence the value of R1and R2 must be small. If the
ratio RB/RE is kept fixed, S increases with β.

13
TABULATION
Vinput= V
Input signal Output Voltage Gain in
S.No. frequency Vo db
in (Hz) (volt) = (20 log (Vo/Vi))

14
PROCEDURE

1. Connect the circuit as shown in the circuit diagram.

2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression 20
log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.

RESULT:

15
Common Base Amplifier Circuit Diagram:

VCC
20V

R1

R3 10k C3
15k VO
10u R5
Q1 1k

0
C1 BC 107
C2
10u

R4
0 100u
4.7k R2
V1
3.3k

0
0

MODEL GRAPH:

16
EX.No: 2,b FREQUENCY RESPONSE OF COMMON BASE AMPLIFIER
DATE :

AIM:
To construct a Common Base Amplifier circuit and to plot it’s frequency response
characteristics.

LIST OF PARTS:
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor BC 107 1
2. Resistors 15KΩ,10KΩ,4.7KΩ,3.3KΩ,1 Each 1
KΩ
3. Capacitors 10µF,100 µF 2,1
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few

THEORY:

 Common-base transistor amplifiers are so-called because the input and output voltage
points share the base lead of the transistor in common with each other, not considering
any power supplies.The current gain of a common-base amplifier is always less than 1.

 The voltage gain is a function of input and output resistances, and also the internal
resistance of the emitter-base junction, which is subject to change with variations in DC
bias voltage. Suffice to say that the voltage gain of a common-base amplifier can be very
high.

 The ratio of a transistor's collector current to emitter current is called amplification factor
(α). The α value for any transistor is always less than unity, or in other words, less than 1.

 Some of its applications include radio frequency amplifiers. The grounded base helps
shield the input at the emitter from the collector output, preventing instability in RF
amplifiers. The common base configuration is usable at higher frequencies than common
emitter or common collector.

17
TABULATION
Vinput= V
Input signal Output Voltage Gain in
S.No. frequency Vo db
in (Hz) (volt) = (20 log (Vo/Vi))

18
PROCEDURE

1. Connect the circuit as shown in the circuit diagram.

2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.

RESULT:

19
Common Collector Amplifier Circuit Diagram:

15V

R3

200kΩ
Q1

BC 107
C1 Ii
C2
0.01uF vO
V1 R4 0.01uF

200kΩ R2 R0

10kΩ 1000kΩ

MODEL GRAPH:

20
EX. No: 2.c FREQUENCY RESPONSE OF COMMON COLLECTOR AMPLIFIER
DATE:

AIM:
To construct a Common Collector Amplifier circuit and to plot it’s frequency response
characteristics.

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. Transistor BC 107 1
2. Resistors 200KΩ,10KΩ,100KΩ 2,1,1
3. Capacitors 0.01µF 2
4. DC power supply 15 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few

OVERVIEW:

 Common-collector transistor amplifiers are so-called because the input and output
voltage points share the collector lead of the transistor in common with each other,
not considering any power supplies.
 The common-collector amplifier is also known as an emitter-follower. The output
voltage on a common-collector amplifier will be in phase with the input voltage,
making the common-collector a non-inverting amplifier circuit.
 The current gain of a common-collector amplifier is equal to β plus 1.here β is a
amplification factor of common emitter amplifier. The voltage gain is approximately
equal to 1. A popular application of the common-collector amplifier is for regulated
DC power supplies, where an unregulated (varying) source of DC voltage is clipped
at a specified level to supply regulated (steady) voltage to a load.

21
TABULATION:

Ii = mA
Input signal Output Voltage Output Current Gain
S.No. frequency Vo Io= Vo/ Ro in db
in (Hz) (volt) (mA) =20 log (I0/Ii)

22
PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.

2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage VO (p-p) and thus calculate the Io (p-p) = VO (p-p) / Ro for
various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The current gain can be calculated by using the expression 20*log (I0/Ii) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and the current gain in dB is calculated by using the expression
20 log10 (I0/Ii).
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
The bandwidth is calculated from the frequency response graph as BW=f2-f1.

RESULT:

23
Common Source Amplifier Circuit Diagram:

VCC
V1
20V

R1 R3

220kΩ 3.9kΩ
C2

6.8uF
Rs Cs J1

1.5kΩ 1uF J2N

V2 BFW10

Ro VO
R2
Vin R4 C1 5.6kΩ
68kΩ
2.2kΩ 10uF

MODEL GRAPH :

24
EX.No:2, d FREQUENCY RESPONSE OF COMMON SOURCE AMPLIFIER
DATE :

AIM:
To construct a Common Source Amplifier circuit of field effect transistor (FET) and to
plot its frequency response characteristics.

APPARATUS REQUIRED:

QUANTITY
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION
1. Transistor BFW10 1

2. Resistors 220KΩ,68KΩ,2.2KΩ, 3.9KΩ, 1 each

5.6KΩ,1.5kΩ
3. Capacitors 1µF, 10µF,6.8µF 1 each

4. DC power supply 20 V 1

5. Function Generator 0 – 10MHz 1

6. CRO Dual channel,30MHz 1

7. Probes - 2

8. Breadboard - 1

9. Connecting Wires - Few

THEORY:

The common-source (CS) amplifier may be viewed as a transconductance amplifier or as

a voltage amplifier. As a transconductance amplifier, the input voltage is seen as modulating the
current going to the load. As a voltage amplifier, input voltage modulates the amount of current
flowing through the field effect transistor( FET), changing the voltage across the output
resistance according to Ohm's law. However, the FET device's output resistance typically is not
high enough for a reasonable transconductance amplifier, nor low enough for a decent voltage
amplifier.

25
TABULATION:
Vi = V
Input signal Output Voltage Gain
S.No. frequency Vo in db
in (Hz) (volt) =(20 log (Vo/Vi))

26
PROCEDURE

1. Connect the circuit as shown in the circuit diagram.

2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.

RESULT:

27
TABULATION :

Vinput = V
Input signal Output Voltage Gain
S.No. frequency Vo in db
in (Hz) (volt) =(20 log (Vo/Vi))

28
EX.No: 3 FREQUENCY RESPONSE OF DARLINGTON AMPLIFIER
DATE :

AIM:
To construct a Darlington Amplifiercircuit and to find itsfrequency response.

LIST OF PARTS:

S.N Requirement Name Range Quantity

o
1 Transistor [Active] BC 107 2
2 Resistor [Passive] 47 KΩ, 10 KΩ 1,1,1,2
Components 4.7KΩ,1 KΩ,
3 Capacitor 47 uF,100uF 2,1
[Passive]
4 signal Generator (0-3)MHz 1
5 CRO 30MHz 1
Equipment
6 Regulated power (0-30)V 1
supply
7 Bread Board 1
-
Accessories
8 Connecting Wires Single strand as required

OVERVIEW:

In Darlington connection of transistors, emitter of the first transistor is directly connected

to the base of the second transistor.
Because of direct coupling dc output current of the first stage is (1+hfe )Ib1.If Darlington
connection for n transistor is considered, then due to direct coupling the dc output current for the
last stage is (1+hfe ) times of Ib1 .
Due to a very large amplification factor even two stage Darlington connection has large
output current. In Darlington transistor connection, the leakage current of the first transistor is
amplified by the second transistor and overall leakage current may be high, which is not desired.

29
SCHEMATIC REPRESENTATION WITH VALUES

MODEL GRAPH:

30
PROCEDURE

1. Connect the circuit as shown in the circuit diagram.

2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.

RESULT:

31
CIRCUIT DIAGRAM:
For Common mode:

For Differential
mode:

32
EXP.NO : 4 DIFFERENTIAL AMPLIFIER USING BJT
DATE :

AIM:

To construct a differential amplifier circuit and to find the difference mode gain,
common mode gain, Common Mode Rejection Ratio and also find its transfer characteristics.

REQUIREMENTS:

S.No. Requiremen Name Range Quantity

t
1 Transistor [Active] BC 107 2
Components
2 Resistor [Passive] 1 KΩ,470 Ω 2,1
4 signal Generator (0-3)MHz 2
5 CRO 30MHz 1
Equipment
6 Regulated power (0-30)V 1
supply (dual)
7 1
Bread Board
Accessories
8 Connecting Wires Single strand as required

FORMULAE USED:
1. Differential mode gain Ad = Vod/ Vid.
2. Common mode gain AC = Voc/ Vic.
Vod= (V02 ~ V01) - Output voltage in differential mode operation.
Voc= (V02 ~ V01) - Output voltage in common mode operation.
For differential mode operation, the input voltage,
Vid = (VS2 – VS1) Volts
For common mode operation, input voltage is
Vic = (VS1 + VS2) / 2 Volts
Where, V01 = output voltage at Q1.
V02= output voltage at Q2.
VS1= Input voltage to Q1.
VS2= Input voltage to Q2.
3. Common Mode Rejection Ratio (CMRR) = Ad /Ac

33
MODEL GRAPH

For differential mode operation

Amplitude

V01 output waveform

vpp
Time period

Amplitude
V02 output waveform

vpp

Time period

For common mode operation

Amplitude

V01 output waveform

vpp
Time period

Amplitude

V02 output waveform

vpp
Time period

34
THEORY
The Differential amplifier is the basic building block of Operational amplifier. The
function of a difference or differential amplifier is to amplify the difference between the two
input signals. The need for differential amplifier arises in many physical measurements in
medical electronics and in direct coupled amplifier applications.

VS1
Linear Active V0ut
Device
VS2

The above figure represents a linear active device with two input signals VS1, VS2 and one
output signal V0, each measured with respect to ground. In an ideal differential amplifier, the
output should be given by Vod = Ad (VS2 – VS1) where Ad is the gain of the differential amplifier
in differential mode.
Thus it is seen that any signal which is common to both inputs will have no effect on the
output voltage. In general the output depends not only upon the difference between the two input
signals but also upon the average level of the two input signal.The transistor Q1 and Q2 are
assumed to be identical with one another and thus perfect symmetry between both halves of the
circuits.
The difference between the input voltage is given by Vid = (VS2 – VS1), it is called
difference mode or difference mode input voltage. The average value of the input voltage is Vic
is equal to
(VS1+ VS2 )/2 and is called the common mode input voltage.
In an ideal differential amplifier, the output voltage is proportional to Vid and does not
depend on common mode voltage Vic = (VS1 + VS2) / 2. This is an ideal differential amplifier. To
measure the departure from the ideal quantity called common mode rejection ratio is used which
is defined as the ratio of differential mode gain to common mode gain.

CMRR= ρ = Differential mode gain / Common mode gain

ρ = Ad / Ac
Finally the differential amplifier may be used as an emitter coupled phase inventor. For
this application, the signal is applied to one base, where as second base is not excited. Then
output voltages taken from the collectors are equal in magnitude but 180 0out of phase.

35
TABULATION
(i) For Common mode
Input Voltages Output Voltages Common
Overall Input Voltage Output Voltages
Mode Gain
VS1 VS2 V01 V02 Vic=(VS1+VS2)/2 Volts Voc=(V02-V01)Volts
(Ac)

(ii) For Differential mode

Input Output Voltages Overall Input Output Voltages Differential
Voltages Voltage Vod= (V02–V01) mode Gain
VS1 VS2 V01 V02 Vid= (VS2-VS1)volts Volts (Ad)

36
PROCEDURE
1. Check the equipment and components to ensure their proper working condition.
2. To Calculate common mode gain,
(i) Connect the circuit as shown in figure using breadboard with very short wires.
(ii) Set the input using signal generator with the help of CRO.
(iii) Switch ON the power supply.
(iv) Measure the output voltage V01 by connecting the probe between collector - 1 and ground and
measure V02 by connecting the probe between collector - 2 and ground using the two channels
of the CRO and tabulate it on the table.
(v) Calculate the common mode gain using the given formulae.
(vi) After completion of the experiment, reduce the power to zero position and disconnect the
circuit.
3. To Calculate differential mode gain,
(i) Connect the circuit as shown in fig using breadboard with very short wires.
(ii) Set the input using signal generator with the help of CRO.
(iii) Switch ON the power supply.
(iv) Measure the output voltage V01 by connecting the probe between collector - 1 and ground and
measure V02 by connecting the probe between collector - 2 and ground using the two channels
of the CRO and tabulate it on the table .
(v) Calculate the differential mode gain using the given formulae.
(vi) After completion of the experiment, reduce the power to zero position and disconnect the
circuit.
4. Calculate common mode rejection ratio (CMRR) using the difference mode gain and & common
mode gain.
RESULT:

37
Cascode Amplifier Circuit Diagram:

15V

R5 R1
0
6.8kΩ 1.8kΩ
C3

Q1 5uF VO

C1 BC 107
R6
10uF
0 R4 1kΩ

5.6k Q2
C4
Ω
5uF
BC 107

Vinput R3
R2
4.7kΩ
1.1kΩ

C2

20uF

MODEL GRAPH :

38
EX.NO:5,a FREQUENCY RESPONSE OF CASCODE AMPLIFIER
DATE :

AIM:
To construct aCascodeAmplifier circuit and to plot its frequency response characteristics.

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. Transistor BC 107 2
2. Resistors 6.8KΩ,5.6KΩ,4.7KΩ1.1KΩ,1.8KΩ,1KΩ Each 1
3. Capacitors 10µF,5µF,20µF 1,2,1
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few

THEORY:

The cascode is a two-stage amplifier composed of a transconductance amplifier followed

by a current buffer.
Compared to a single amplifier stage, this combination may have one or more of the
following characteristics: higher input-output isolation, higher input impedance, high output
impedance, higher gain or higher bandwidth.
The cascode amplifier is constructed from two BJTs, with one operating as a common
emitter and the other as a common base. The cascode improves input-output isolation (or reverse
transmission) as there is no direct coupling from the output to input. This eliminates the Miller
effect and thus contributes to a much higher bandwidth.

39
TABULATION:

Vi = V
Input signal Output Voltage Gain
S.No. frequency Vo in db
in (Hz) (volt) =(20 log (Vo/Vi))

40
PROCEDURE

1. Connect the circuit as shown in the circuit diagram.

2. Apply an input signal using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.

RESULT:

41
Cascade Amplifier Circuit Diagram:

VCC
10V

R7
R3 0
R1 R5 2.2k
2.2k Ω
15kΩ
15kΩ Ω C10
C8
10uF
Q4 10u Q5
V0
C1

10u F
BC 107 BC 107 RO
VS
10kΩ

1kΩ
R4 R8
R6
1k
R2 k C7 4.7k C9
Ω 20uF
4.7kΩ 20uF

MODEL GRAPH:

42
EX.No:5.bFREQUENCY RESPONSE OFCASCADE AMPLIFIER
DATE :

AIM:
To construct a cascade Amplifiercircuit and to plot it’s frequency response
characteristics.

LIST OF PARTS:

QUANTITY
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION
1. Transistor BC 107 2
2. Resistors 15KΩ,2.2KΩ,4.7KΩ1KΩ,10 KΩ 2,2,2,2,1
3. Capacitors 10µF,20µF 3,2
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few

THEORY:

A cascade is type of multistage amplifier where two or more single stage amplifiers are
connected serially. Many times the primary requirement of the amplifier cannot be achieved with
single stage amplifier, because of the limitation of the transistor parameters. In such situations
more than one amplifier stages are cascaded such that input and output stages provide impedance
matching requirements with some amplification and remaining middle stages provide most of the
amplification. These types of amplifier circuits are employed in designing microphone and
loudspeaker.

43
TABULATION:

Vi = V
Input signal Output Voltage Gain
S.No. frequency Vo in db
in (Hz) (volt) =(20 log (Vo/Vi))

44
PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Determine the Q-point of the amplifier using DC analysis.

3. Determine Maximum input voltage that can be applied to amplifier using AC analysis.

4. Set the input voltage and vary the input signal frequency from 0Hz to 1MHz in incremental
steps and note down the corresponding output voltage Vo for atleast 20 different values for the
considered range.

5. The voltage gain is calculated as Av = 20log (V0/Vi)

6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking frequency on x-
axis and gain in dB on y-axis.,

7. BandWidth, BW = f2-f1
Where f1 - lower cut-off frequency
f2 - upper cut-off frequency

RESULT:

45
Class A power amplifier Circuit Diagram:

MODEL GRAPH:

46
EX.No:6.a CLASS - A AMPLIFIER
DATE :
AIM:
To design and construct a Class – A power amplifier. To observe the output waveform
and to measure the maximum power output and to determine the efficiency.

APPARATUS REQUIRED:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. Transistor BC107 1
2. Resistors 1KΩ, 4.7KΩ,61 KΩ,10KΩ Each 1
3. Capacitors 1uF, 100uF (all are electrolytic) Each 1
4. CRO (0-20MHz) 1
5. Regulated Power Supply (0-30)V 1
6. Breadboard & Connecting 1,few
Wires

FORMULA
DC power input PDC = Vcc * RC
Maximum power transfer = Po max = Vo2/RL
Efficiency, η = Pomax / PDC

THEORY:

 The power amplifier is said to be Class A amplifier if the Q point and the input signal are
selected such that the output signal is obtained for a full input signal cycle.
 For all values of input signal, the transistor remains in the active region and never enters
into cut-off or saturation region.
 When an a.c signal is applied, the collector voltage varies sinusoidally hence the
collector
 current also varies sinusoidally.
 The collector current flows for 3600 (full cycle) of the input signal. i e the angle of
the collector current flow is 3600 .

47
TABULATION :

Keep the input voltage constant, Vin =

S.No Frequency (in Hz) Output Voltage (in volts) Gain= 20 log (Vo/Vin) (in dB)

48
PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set input voltage using the signal generator.

3. Keeping the input voltage constant, vary the frequency from 10 Hz to 1M Hz in regular steps
and note down the corresponding output voltage.

4. Plot the graph; Gain (dB) vs Frequency (Hz).

RESULT:

49
Class B power amplifier Circuit Diagram:

TABULATION :

S.No OUTPUT SIGNAL

AMPLITUDE TIME PERIOD
In In (sec)
(V) Ton Toff

50
EX.No: 6.b CLASS B POWER AMPLIFIER
DATE :

AIM:
To construct a Class B complementary symmetry power amplifier and observe the
waveforms and to compute maximum output power and efficiency.

APPARATUS REQUIRED:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1 Power Supply (0 – 30) V 1
2 CRO (0 – 20) MHz 1
3 Function Generator (0 – 1) MHz 1
4 Resistor 47 KΩ,1 KΩ 1,1
5 Transistors BC 107,BC 178 1,1

CALCULATION:
POWER, PIN = 2VCCIm/π
OUTPUT POWER, POUT = VmIm/2
EFFICIENCY, η = (π /4)(Vm/ VCC) x 100

THEORY:

A power amplifier is said to be Class B amplifier if the Q-point and the input signal are
selected such that the output signal is obtained only for one half cycle for a full input cycle. The
Q-point is selected on the X-axis. Hence, the transistor remains in the active region only for the
positive half of the input signal.
There are two types of Class B power amplifiers: Push Pull amplifier and complementary
symmetry amplifier. In the complementary symmetry amplifier, one n-p-n and another p-n-p
transistor is used. The matched pair of transistor are used in the common collector configuration.
In the positive half cycle of the input signal, the n-p-n transistor is driven into active region and
starts conducting and in negative half cycle, the p-n-p transistor is driven into conduction.
However there is a period between the crossing of the half cycles of the input signals, for which
none of the transistor is active and output is zero.

51
Class B power amplifier model graph:

52
PROCEDURE:

1. Connections are given as per the circuit diagram.

2. Observe the waveforms and note the amplitude and time period of the input signal
and distorted waveforms.

3. Connections are made with transistor.

4. Observe the waveforms and note the amplitude and time period of the output signal,
measure magnitude of the output voltage (Vm) and calculate magnitude of output
current
( Im= Vm/ Rload ).

5. Draw the waveforms for the readings.

6. Calculate the maximum output power and efficiency.

Hence the nature of the output signal gets distorted and no longer remains the same as the
input. This distortion is called cross-over distortion. Due to this distortion, each transistor
conducts for less than half cycle rather than the complete half cycle. To overcome this distortion,
we can add 2 diodes to provide a fixed bias and eliminate cross-over distortion.

RESULT:

53
Single stage amplifier circuit diagram:

VCC
10V

R1 R3 0

15kΩ 2.2k
Ω C1

Q14 10uF
C1 VO
10uF BC 107
RO
Vin
10kΩ

R4

1kΩ
R2 C2

4.7kΩ 20uF

0
Tabular Column:
SINGLE STAGE AMPLIFIER
Input signal Output Voltage Gain
S.No. frequency Vo in db
in (Hz) (volt) =(20 log (Vo/Vi))

54
EX.No: 7 FREQUENCY RESPONSES OFSINGLE STAGE AND MULTI-STAGE
DATE: AMPLIFIER

AIM:
To construct a single stage and multi -stage amplifier circuit and determine it’s
bandwidth.

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. Transistor BC 107 2
2. Resistors 15KΩ,2.2KΩ,4.7KΩ1KΩ,10 KΩ 2,2,2,2,1
3. Capacitors 10µF,20µF 3,2
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few

OVERVIEW:

When we want to achieve higher amplification than a single stage amplifier can offer, it
is a common practice to cascade various stages of amplifiers, as it is shown in figure. In such a
structure the input performance of the resulted multistage amplifier is the input performance of
the first amplifier while the output performance is that of the last amplifier. The total voltage
gain of cascade connection is the product of the individual stage i.e. Av=Av1*Av2.But the
bandwidth is decreased. Hence there is a trade-off between the gain and bandwidth of the
amplifier as the number of stages is increased.

55
Multistage stage amplifier circuit diagram:

VCC
10V

R7
R3 0
R1 R5 2.2k
2.2k Ω
15kΩ
15kΩ Ω C10
C8
10uF
Q4 10uF Q5
V0
C1

10uF
BC 10 BC 107 RO
VS
10kΩ

1kΩ
R4 R8
R6
1kΩ
R2 C7 4.7kΩ C9

4.7kΩ 20uF 20uF

Tabular Column:
MULTI-STAGE AMPLIFIER

Input signal Output Voltage Gain

S.No. frequency Vo in db
in (Hz) (volt) =(20 log (Vo/Vi))

MODEL GRAPH:

56
PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.

2. Apply an input with particular frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.

RESULT:

57
SIMULATION REPORT:

Circuit Schematic:

V1
15V

R1

R2 2.2k
C2
910k
Q1 10u
C3

5u Q2N2222
V2

R6
R5
R4 C1 1k
220k
1.2k 20u

0
Simulation Graph:

58
EX.No: 8.a COMMON EMITTER AMPLIFIER
DATE :

AIM:
To simulate a Common Emitter Amplifier in ORCAD PSPICE and to obtain it’s
frequency response characteristics.

SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:

1. Select File >> New >> Project. Name your project and select the directory as the
location field. Be sure that you selected “Analog or Mixed A/D”.
2. Now, select “Create a blank project” at the appeared diagram box below.
3. An empty page in Schematic Editor will be opened.Now draw the given circuit in the
Schematic Editor.To work your circuit properly, don’t forget to add Ground to your
circuit.Set the parameters as shown in the circuit .
4. After the construction of the circuit, create a new profile using Pspice>> New
Simulation Profile from toolbar. Write a name in the New Simulation Name.
5. After clicking on the Create button, the following dialog box will appear. For frequency
response characteristics specify the type of analysis as ‘AC Sweep /Noise’. Since the
input frequency is varied , enter the start frequency as 20Hz and end frequency as
20KHz. Enter the total number of points per decade in the Points/Decade box.
6. Run your program by using toolbar as Pspice>> Run.
7. Another window will be opened and the frequency response characteristicswill be displayed.

RESULT:

59
SIMULATION REPORT:
Circuit Schematic:

V1
20V

R14 R1

220k 3.9k
C2

6.8u
R13 C3 J1

1.5k 1u J2N3819
V2

R6
R5
R4 C1 5.6k
68k
10u
2.2k

Simulation Graph :

60
EX.No: 8.b COMMON SOURCE AMPLIFIER
DATE :

AIM:
To simulate a Common Source Amplifierin ORCAD PSPICE and to obtain it’s frequency
response characteristics.

SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:

1. Select File >> New >> Project. Name your project and select the directory as the
location field. Be sure that you selected “Analog or Mixed A/D”.
2. Now, select “Create a blank project” at the appeared diagram box below.
3. An empty page in Schematic Editor will be opened.Now draw the given circuit in the
Schematic Editor.To work your circuit properly, don’t forget to add Ground to your
circuit.Set the parameters as shown in the circuit.
4. After the construction of the circuit, create a new profile using Pspice>> New
Simulation Profile from toolbar . Write a name in the New Simulation Name.
5. After clicking on the Create button, the following dialog box will appear. For frequency
response characteristics specify the type of analysis as ‘AC Sweep /Noise’. Since the
input frequency is varied , enter the start frequency as 20Hz and end frequency as
20KHz. Enter the total number of points per decade in the Points/Decade box.
6. Run your program by using toolbar as Pspice>> Run.
7. Another window will be opened and the frequency response characteristics will be
displayed.

RESULT:

61
 DIGITAL
EXPERIMENTS

62
TRUTH TABLE:

Decimal BCD Input Excess – 3 Output

Number B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1

1 0 0 0 1 0 1 0 0

2 0 0 1 0 0 1 0 1

3 0 0 1 1 0 1 1 0

4 0 1 0 0 0 1 1 1

5 0 1 0 1 1 0 0 0

6 0 1 1 0 1 0 0 1

7 0 1 1 1 1 0 1 0

8 1 0 0 0 1 0 1 1

9 1 0 0 1 1 1 0 0

63
EX.No: 9.a BCD TO EXCESS-3 CODE
DATE :

AIM:
To design and implement BCD to Excess-3 code converter

LIST OF PARTS :

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. NOT GATE IC 7404 2
2. AND GATE IC 7408 1
3. OR GATE IC 7432 2
4. XOR GATE IC 7486 2
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

Numeric codes represent numeric information that is only numbers as a series of 0’s and
1’s. Numeric codes used to represent decimal digits are called Binary Coded Decimal (BCD)
codes. A BCD code is one, in which the digits of a decimal number are encoded-one at a time
into group of four binary digits. Since there are a large number of BCD codes in order to
represent decimal digits 0, 1, 2,……9, it is necessary to use a sequence of at least four binary
digits. An Excess-3 code is a non-weighted code. It is also a self-complementing BCD code used
in decimal arithmetic units. . The Excess-3 code for the decimal number is performed in the same
manner as BCD except that decimal number 3 is added to the each decimal unit before encoding
it to binary.
The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital systems. It is some time necessary to use
the output of one system as the input to the other. The conversion circuit must be inserted
between the two systems if each uses different codes for the same information. Thus a code
converter is a circuit that makes the two systems compatible even though each uses a different
code.

64
K-Map for E3:

E3 = B3 + B2B0 + B2B1
E3 = B3 + B2 (B0 + B1)
K-Map for E2:

65
K-Map for E1:

K-Map for E0:

66
LOGICAL REPRESENTATION

67
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT :

68
TRUTH TABLE:
| Excess – 3 Input | BCD Output |

X1 X2 X3 X4 A B C D

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

K-Map for A:

A = X1 X2 + X3 X4 X1

69
EX.No: 9 i) b. EXCESS-3 TO BCD CODE
DATE :

AIM:
To design and implement Excess-3 to BCD converter using logic gates .

LIST OF PARTS :

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1 NOT GATE IC 7404 2
2 AND GATE IC 7408 2
3 OR GATE IC 7432 2
4 X-OR GATE IC 7486 2
5 IC TRAINER KIT - 1
6 PATCH CORDS - 35

THEORY:

Numeric codes represent numeric information i.e. only numbers as a series of 0’s and 1’s.
Numeric codes used to represent decimal digits are called Binary Coded Decimal (BCD) codes.
A BCD code is one, in which the digits of a decimal number are encoded-one at a time into
group of four binary digits. Since there are a large number of BCD codes in order to represent
decimal digits 0, 1, 2,……9, it is necessary to use a sequence of at least four binary digits. An
Excess-3 code is a non-weighted code. It is also a self-complementing BCD code used in
decimal arithmetic units. . The Excess-3 code for the decimal number is performed in the same
manner as BCD except that decimal number 3 is added to the each decimal unit before encoding
it to binary.
The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital systems. It is some time necessary to use
the output of one system as the input to the other. The conversion circuit must be inserted
between the two systems if each uses different codes for the same information. Thus a code
converter is a circuit that makes the two systems compatible even though each uses a different
code.

70
K-Map for B:

K-Map for C:

K-M ap for D:

71
LOGICAL REPRESENTATION

PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT :

72
TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3:

G3 = B3

73
EX.No: 9 ii) BINARY TO GRAY CODE
DATE :

AIM:
To design and implement Binary to Gray code converter

LIST OF PARTS :

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. XOR GATE IC 7486 3
2. IC TRAINER KIT - 1
3. PATCH CORDS - 35

THEORY:

Each code uses four bits to represent a decimal digit. There are four inputs and four
outputs. Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as G3, G2, G1, Go and from the truth table, the combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital systems. It is some time
necessary to use the output of one system as the input to the other. The conversion circuit must
be inserted between the two systems if each uses different codes for the same information. Thus
a code converter is a circuit that makes the two systems compatible even though each uses a
different code.

74
K-Map for G2:

K-Map for G1:

K-Map for G0:

75
LOGICAL REPRESENTATION

PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT :

76
77
EX.No: 9 ii) b. GRAY TO BINARY CODE
DATE :

AIM:
To design and implement Gray to Binary code converter

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. XOR GATE IC 7486 3
2. IC TRAINER KIT - 1
3. PATCH CORDS - 35

THEORY :

 Each code uses four bits to represent a decimal digit. There are four inputs and
four outputs. Gray code is a non-weighted code.
 The input variable are designated as G3, G2, G1, Go and the output variables are
designated as B3, B2, B1, B0 and from the truth table, the combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output
variable.
 A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit.
 The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital systems. It is
some time necessary to use the output of one system as the input to the other.
 The conversion circuit must be inserted between the two systems if each uses
different codes for the same information. Thus a code converter is a circuit that
makes the two systems compatible even though each uses a different code.

78
TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

K-Map for B3:

B3 = G3

79
K-Map for B2:

K-Map for B1:

80
K-Map for B0:

LOGICAL REPRESENTATION

81
PROCEDURE:

(iv) Give connections as per circuit diagram.

(v) Apply logical inputs as given in the truth table

(vi) Observe the logical output and verify with the truth table.

RESULT :

82
83
EX.No: 10, a 4 BIT BINARY ADDER/ SUBTRACTOR
DATE :

AIM:
To design and implement a 4 bit binary Adder/ Subtractor

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. XOR GATE IC 7486 4
2. 4-Bit Binary Full Adder IC 7483 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry from
each full adder connected to the input carry of next full adder in chain. The augends bits of ‘A’
and the addend bits of ‘B’ are designated by subscript numbers from right to left, with subscript
0 denoting the least significant bits. The carries are connected in chain through the full adder.
The input carry to the adder is C0 and it ripples through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each
data input ‘B’ and the corresponding input of full adder. The input carry C 0 must be equal to 1
when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is adder
circuit. When M=1, it becomes subtractor.

84
PIN DIAGRAM FOR IC 7483:

TRUTH TABLE:
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

85
LOGICAL REPRESENTATION

PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT :

86
PIN DIAGRAM FOR IC 7483:

TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

87
EX.No:10, b. BCD ADDER USING IC 7483
DATE :

AIM:
To design and implement a BCD adder using IC 7483.

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. AND GATE IC 7408 2
2. OR GATE IC7432 2
3. XOR GATE IC 7486 4
4. 4-Bit Binary Full Adder IC 7483 2
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

Consider the arithmetic addition of two decimal digits in BCD, together with an input

carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be

greater than 9, the 1 in the sum being an input carry. The output of two decimal digits must be

represented in BCD and should appear in the form listed in the columns. The 2 decimal digits,

together with the input carry, are first added in the top 4 bit adder to produce the binary sum.

88
K MAP

Y = S4 (S3 + S2)

LOGICAL REPRESENTATION

89
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT:

90
TRUTH TABLE:

DATA SELECT OUTPUT

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

FUNCTION TABLE:

S1 S0 Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

91
EX.No: 11, a. MULTIPLEXER USING LOGIC GATES
DATE :

AIM:
To design and implement a multiplexer using logic gates.
LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. 3 I/P AND GATE IC 7411 4
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 2
4. IC TRAINER KIT - 1
5. PATCH CORDS - 32

OVERVIEW:

Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2 n input line and
n selection lines whose bit combination determine which input is selected.

BLOCK DIAGRAM:

92
LOGICAL REPRESENTATION

93
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT :

94
TRUTH TABLE:

INPUT OUTPUT
S1 S0 X D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

FUNCTION TABLE:

S1 S0 D
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

D = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

95
EX.No: 11 b. DEMULTIPLEXER USING LOGIC GATES
DATE :

AIM:
To design and implement a Demultiplexer using logic gates.
LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. 3 I/P AND GATE IC 7411 4
2. NOT GATE IC 7404 2
3. IC TRAINER KIT - 1
4. PATCH CORDS - 32

THEORY:

The function of Demultiplexer is in contrast to the multiplexer function. It takes

information from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as a demultiplexer.
In the 1X 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

BLOCK DIAGRAM:

96
LOGICAL REPRESENTATION

97
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT :

98
TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

99
EX.No:12) a. DESIGN AND IMPLEMENT AN ENCODER
DATE :

AIM:
To design and implement an Encoder using logic gates.
LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. OR GATE IC 7432 9
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

An encoder is a digital circuit that performs the inverse operation of a decoder. An

encoder has 2n input lines and n output lines. In encoder the output lines generates the binary
code corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generate the corresponding binary code.

100
LOGICAL REPRESENTATION

101
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT:

102
TRUTH TABLE:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

103
EX.No: 12.b DESIGN AND IMPLEMENT A DECODER
DATE :

AIM:
To design and implement a Decoder using logic gates.

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. 3 I/P NAND GATE IC 7410 4
2. NOT GATE IC 7404 3
3. IC TRAINER KIT - 1
4. PATCH CORDS - 32

THEORY:

A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has fewer
bits than the output code. Each input code word produces a different output code word i.e there is
a one to one mapping in the truth table. In the block diagram of decoder circuit the encoded
information is present as n input producing 2n outputs bits.

104
LOGICAL REPRESENTATION

105
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT:

106
LOGICAL REPRESENTATION

107
EX. No: 13. a. 4 BIT RIPPLE COUNTER
DATE:
AIM:
To construct and verify a 4 Bit Ripple Counter.

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. JK FLIP FLOP IC 7476 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

A counter is a register capable of counting the number of clock pulses arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There are
two types of counter, synchronous and asynchronous. In synchronous counter a common clock is
given to all flip flop and in asynchronous counter the first flip flop is clocked by external pulse
and then each successive flip flop is clocked by the Q output of the previous stage. The clock of
the second stage is triggered by the output of the first stage. Because of inherent propagation
delay time, all flip flops are not activated at same time which results in asynchronous operation.

108
PIN DIAGRAM

TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

109
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT:

110
PIN DIAGRAM

LOGICAL REPRESENTATION MOD - 10 RIPPLE COUNTER

111
EX.No: 13.b MOD-10 / MOD-12 RIPPLE COUNTERS
DATE :
AIM:
To construct and verify a Mod-10 and Mod-12 RippleCounter.

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 32

THEORY:
A counter is a register capable of counting the number of clock pulses arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There are
two types of counter, synchronous and asynchronous. In synchronous counter a common clock is
given to all flip flop and in asynchronous counter the first flip flop is clocked by external pulse
and then each successive flip flop is clocked by the Q output of the previous stage. The clock of
the second stage is triggered by the output of the first stage. Because of inherent propagation
delay time, all flip flops are not activated at same time which results in asynchronous operation.

112
TRUTH TABLE - MOD - 10 RIPPLES COUNTER:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0
TRUTH TABLE - MOD - 12 RIPPLE COUNTER:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0

113
LOGICAL REPRESENTATION MOD –12 RIPPLE COUNTER

PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT:

114
 CHARACTERISTICS TABLE FOR J-K FLIP FLOP:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

TRUTH TABLE:

Input Present State Next State A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

115
EX. No: 14. 3-BIT SYNCHRONOUS UP COUNTER/DOWN COUNTER
DATE:
AIM:
To design and implement a 3-Bit Synchronous Up Counter/Down Counter.
LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 2
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 2
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one that is
capable of progressing in increasing order or decreasing order through a certain sequence. An
up/down counter is also called bidirectional counter. Usually up/down operation of the counter is
controlled by up/down signal. When this signal is high counter goes through up sequence and
when up/down signal is low counter follows reverse sequence.

STATE DIAGRAM:

116
K MAP

LOGICAL REPRESENTATION:

117
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT:

118
PIN DIAGRAM:

CHARACTERISTICS TABLE FOR J-K FLIP FLOP:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

119
EX.No: 15 SHIFT REGISTERS USING FLIP- FLOPS
DATE :

AIM:
To implement the following Shift Registers using Flip- Flops
 Serial in serial out
 Serial in parallel out
 Parallel in serial out
 Parallel in parallel out

LIST OF PARTS:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 3
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:

A register, capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consists of cascaded D-Flip flops with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulse which causes the shift in the output of the flip flop. The simplest possible shift register is
one that uses only flip flop. The output of a given flip flop is connected to the input of next flip
flop of the register. Each clock pulse shifts the content of register one bit position to the right.

120
SERIAL IN SERIAL OUT:
TRUTH TABLE:

Serial in Serial out

CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

LOGICAL REPRESENTATION:

121
SERIAL IN PARALLEL OUT:
TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

LOGICAL REPRESENTATION:

122
PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

LOGICAL REPRESENTATION

123
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

LOGICAL REPRESENTATION

124
125
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT :

126