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Novel strained superjunction VDMOS

Article in Superlattices and Microstructures · May 2015

DOI: 10.1016/j.spmi.2015.05.026

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 Superlattices and Microstructures 85 (2015) 461–468

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Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Novel strained superjunction VDMOS

Alok Naugarhiya ⇑, Shashank Dubey, Pravin N. Kondekar
Discipline of Electronics and Communication Engineering, PDPM-Indian Institute of Information Technology, Design & Manufacturing Jabalpur, MP, 482005 India

a r t i c l e i n f o a b s t r a c t

Article history: In this paper, we have proposed novel strained superjunction (s-SJ) vertical double diffused
Received 3 March 2015 MOS (VDMOS). Through channel engineering, we have introduced strain effects in s-SJ
Received in revised form 16 April 2015 device using thin separate p-type silicon–germanium (p-SiGe) layer over silicon p-pillar.
Accepted 22 May 2015
Further, we have designed process flow for the possible fabrication of s-SJ VDMOS. The pro-
Available online 22 May 2015
posed s-SJ devices fitted with less input capacitance (C in ) and 1.23 times higher output
current density than conventional SJ VDMOS. Therefore, 40% less gate charge (Q g ) is
Keywords:
required to turn-on the s-SJ VDMOS and Ron A is optimized in between 12% and 46%.
Strained-superjunction
Compressive stress
Ó 2015 Elsevier Ltd. All rights reserved.
Tensile stress
Gate charge
Breakdown voltage
Area specific ON-resistance
Switching frequency

1. Introduction

The superjunction (SJ) device concept is a major breakthrough in power electronics [1]. Conventional silicon-limit
(Si-limit) has been optimized by SJ devices [2,3]. Due to this, trade-offs between the breakdown voltage (BV) and area speci-
fic ON-resistance (Ron A) are improved in power devices. Nevertheless, many articles have reported various techniques for
improvement of SJ devices in terms of enhancement of BV, optimization in Ron A, reduce charge termination (CT), perfect
charge-balance (CB) [2–9]. Further, the separate high-K (HK) dielectric pillar in power devices was introduced to avoid impu-
rity inter-diffusion, reduce Ron A and improve BV [10,11]. But, some articles have reported that HK devices suffer from lower
switching speed and driving current capability due to high capacitive effect [12,13]. One of the possible solution is to
enhance the electron mobility, which extends the performance limits of the existing conventional SJ VDMOS. In literature,
it is found that SiGe incorporated in Si devices produces strain and enhanced the electron mobility [14,15]. However, a larger
Ge mole fraction of Si1ÿxGex may cause a smaller on-state resistance and more degradation of the blocking voltage. A proper
Ge mole fraction of 20% is reported [14–16].
The proposed novel strained-SJ (s-SJ) vertical double diffused MOS (VDMOS) can be used for high-speed power electronic
system such as switch mode power supply (SMPS) and various type convertors. The effect of strain on devices is increased
mobility of electron–hole in channel. To observe strain effects in s-SJ VDMOS, we have varied the thickness of strain-Si (s-Si).
Here, the outcomes revealed that due to strain effect channel mobility has also increased in s-SJ VDMOS. The channel
mobility variation is severely optimized the performance of device. The s-SJ VDMOS device performance is analyzed using:
ON-state characteristics, input capacitance (C in ) effect, gate charge Q g and transient response in comparison with SJ VDMOS.

The advantages of proposed s-SJ VDMOS over conventional SJ VDMOS [7,8] are as follows: almost 1.2–3 times higher output

⇑ Corresponding author.
E-mail addresses: aloknau@iiitdmj.ac.in (A. Naugarhiya), shashank.dubey@iiitdmj.ac.in (S. Dubey), pnkondekar@iiitdmj.ac.in (P.N. Kondekar).

http://dx.doi.org/10.1016/j.spmi.2015.05.026
0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.