INDEX

Si.No. Date Experiment Name Signature

1. To implement all logic gates.

2. To implement combination circuits-Full

Adder and Full Subtractor using Behavioral
Style of Modeling.

3. To implement Multiplexer 8x1 &

De-Multiplexer 1x8 using Behavioral Style of
Modeling.

4. To design a decoder using behavioral

modeling.

5. To implement SR Flip Flop using

Behavioral Style of Modeling.

6. To implement GRAY CODE to BINARY &

BINARY to GRAY using Behavioral Style of
Modeling

7. To verify AND GATE USING FPGA & CPLD.

8. TO VERIFY FULL ADDER AND HALF ADDER

USING FPGA.

9. TO VERIFY FULL ADDER AND HALF ADDER

USING FPGA.

10. FULL SUBTRACTOR & HALF

SUBTRACTOR using CPLD and FPGA.
 EXPERIMENT – 1

 AIM: To implement basic logic gates:

 NOT gate
 OR gate
 AND gate
 NOR gate
 NAND gate
 XOR gate
 XNOR gate

EXPERIMENT -1(a)

 Aim:
To implement logic NOT gate.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:  Truth Table:

a b
0 1
1 0

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NOT_GATE is
port ( a: in STD_LOGIC;
b: out STD_LOGIC);
end NOT_GATE;
architecture BEH_NOT of NOT_GATE is

begin
P1: process (a)
begin
if a = ‘0’ then
b <= ’1’;
 else
b <= ‘0’;
end if;
end process P1;
end BEH_NOT;

 Schematic Diagram:

 Simulation:

 Result:
Logic NOT gate is successfully implemented.
 EXPERIMENT -1(b)

 Aim:
To implement logic OR gate.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:  Truth Table

a b c
0 0 0
0 1 1
1 0 1
1 1 1

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity OR_GATE is
port ( a: in STD_LOGIC, b: in STD_LOGIC;
c: out STD_LOGIC);
end OR_GATE;
architecture BEH_OR of OR_GATE is

begin
P2: process (a, b)

begin
if a=’0’ then
if b=’0’ then
c <= ‘0’;

else
c <=’1’;

end if;
else
if b = ‘0’ then
c <= ’1’;

else
 c <= ‘1’;
end if;
end if;
end process P2;
end BEH_OR;

 Schematic Diagram:

 Simulation:

 Result:
Logic OR gate is successfully implemented.
 EXPERIMENT -1(c)

 Aim:
To implement logic AND gate.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:  Truth Table:

a b c
0 0 0
0 1 0
1 0 0
1 1 1

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AND_GATE is
port ( a: in STD_LOGIC, b: in STD_LOGIC;
c: out STD_LOGIC);
end AND_GATE;
architecture BEH_AND of AND_GATE is

begin
P3: process (a, b)

begin
if a=’0’ then
if b=’0’ then
c <= ‘0’;

else
c <=’0’;
end if;
else
if b = ‘0’ then
c <= ’0’;

else
 c <= ‘1’;
end if;
end if;
end process P3;
end BEH_AND;

 Schematic Diagram:

 Simulation:

 Result:
Logic AND gate is successfully implemented.
 EXPERIMENT -1(d)

 Aim:
To implement logic NOR gate.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:  Truth Table:

a b c
0 0 1
0 1 0
1 0 0
1 1 0

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NOR_GATE is
port ( a: in STD_LOGIC, b: in STD_LOGIC;
c: out STD_LOGIC);
end NOR_GATE;
architecture BEH_NOR of NOR_GATE is

begin
P4: process (a, b)

begin
if a=’0’ then
if b=’0’ then
c <= ‘1’;

else
c <=’0’;
end if;
else
if b = ‘0’ then
c <= ’0’;

else
 c <= ‘0’;
end if;
end if;
end process P4;
end BEH_NOR;

 Schematic Diagram:

 Simulation:

 Result:
Logic NOR gate is successfully implemented.
 EXPERIMENT -1(e)

 Aim:
To implement logic NAND gate.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:  Truth Table:

a b c
0 0 1
0 1 1
1 0 1
1 1 0

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NAND_GATE is
port ( a: in STD_LOGIC, b: in STD_LOGIC;
c: out STD_LOGIC);
end NAND_GATE;
architecture BEH_NAND of NAND_GATE is

begin
P5: process (a, b)

begin
if a=’0’ then
if b=’0’ then
c <= ‘1’;

else
c <=’0’;
end if;
else
if b = ‘0’ then
c <= ’0’;
 else
c <= ‘0’;
end if;

end if;
end process P5;
end BEH_NAND;

 Schematic Diagram:

 Simulation:

 Result:
Logic NAND gate is successfully implemented.
 EXPERIMENT -1(f)

 Aim:
To implement logic XOR gate.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:  Truth Table:

a b c
0 0 0
0 1 1
1 0 1
1 1 0

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity XOR_GATE is
port ( a: in STD_LOGIC, b: in STD_LOGIC;
c: out STD_LOGIC);
end XOR_GATE;
architecture BEH_XOR of XOR_GATE is

begin
P2: process (a, b)

begin
if a=’0’ then
if b=’0’ then
c <= ‘0’;

else
c <=’1’;
end if;

else
if b = ‘0’ then
c <= ’1’;
 else
c <= ‘0’;
end if;
end if;
end process P6;
end BEH_XOR;

 Schematic Diagram:

 Simulation:

 Result:
Logic XOR gate is successfully implemented.
 EXPERIMENT -1(g)

 Aim:
To implement logic XNOR gate.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:  Truth Table:

a b c
0 0 1
0 1 0
1 0 0
1 1 1

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity XNOR_GATE is
port ( a: in STD_LOGIC, b: in STD_LOGIC;
c: out STD_LOGIC);
end XNOR_GATE;
architecture BEH_XNOR of XNOR_GATE is

begin
P7: process (a, b)

begin
if a=’0’ then
if b=’0’ then
c <= ‘1’;

else
c <=’0’;
end if;

else
if b = ‘0’ then
 c <= ’0’;

else
c <= ‘1’;
end if;
end if;
end process P7;
end BEH_XNOR;

 Schematic Diagram:

 Simulation:

 Result:
Logic XNOR gate is successfully implemented.
 EXPERIMENT – 2

 AIM:
To implement combinational circuits
Full Adder
Full Subtractor

EXPERIMENT – 2(a)

 Aim:
To implement Full Adder using Behavioral Style of Modeling.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 Truth Table:

a b cin cout sum

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_ADDER is
port ( a: in STD_LOGIC, b: in STD_LOGIC, cin: in STD_LOGIC;
cout: out STD_LOGIC, sum: out STD_LOGIC);
 end FULL_ADDER;
architecture FA_ADDER of FULL_ADDER is

begin
P8: process (a, b, cin)
variable temp1, temp2, temp3, temp4: STD_LOGIC;

begin
temp1 := a xor b;
temp2 := a and b;
temp3 := b and cin;
temp4 := cin and a;
cout <= temp2 or temp3 or temp4;
sum <= temp1 xor cin;

end process P8;

end FA_ADDER;

 Schematic Diagram:

Full Adder
 Detailed component view

 Simulation:

 Result:
Full Adder is successfully implemented
 EXPERIMENT – 2(b)

 Aim:
To implement Full Subtractor using Behavioral Style of Modeling.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 Truth Table:

a b Bin bout diff

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_SUBTRACTOR is
port ( a: in STD_LOGIC, b: in STD_LOGIC, bin: in STD_LOGIC;
bout: out STD_LOGIC, diff: out STD_LOGIC);
end FULL_SUBTRACTOR;
architecture FA_SUBTRACTOR of FULL_SUBTRACTOR is

begin
P9: process (a, b, bin)
variable temp1, temp2, temp3, temp4, temp5: STD_LOGIC;

begin
 temp1 := not a;
temp2 := a xor b;
temp3 := temp1 and b;
temp4 := temp1 and bin;
temp5 := b and bin;
bout <= temp3 or temp4 or temp5;
diff <= temp2 xor bin;
end process P9;
end FA_ADDER;

 Schematic Diagram:

Full Subtractor

Detailed component view

 Simulation:

 Result:
Full Subtractor is successfully implemented.
 EXPERIMENT – 3.1

 Aim:
To implement Multiplexer 8x1 using Behavioral Style of Modeling.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 Truth Table:

S2 S1 S0 Z

0 0 0 7

0 0 1 6

0 1 0 5

0 1 1 4

1 0 0 3

1 0 1 2

1 1 0 1

1 1 1 0

 VHDL Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX8x1 is

port ( I : in STD_LOGIC_VECTOR(7 downto 0);

DATA_BUS : in STD_LOGIC_VECTOR(2 downto 0);

Z : out STD_LOGIC);

end MUX8x1;

architecture MUX_BEHl of MUX8x1 is

constant MUX_DLY : TIME:=10ns;

 begin

process(INP,DATA_BUS)

variable TEMP: STD_LOGIC;

begin

case DATA_BUS is

when "000" => TEMP := INP(7);

when "001" => TEMP := INP(6);

when "010" => TEMP := INP(5);

when "011" => TEMP := INP(4);

when "100" => TEMP := INP(3);

when "101" => TEMP := INP(2);

when "110" => TEMP := INP(1);

when "111" => TEMP := INP(0);

when others=> TEMP := 'U';

end case;

Z <= TEMP after MUX_DLY;

end process;

end MUX_BEH;

 Schematic Diagram:

 Simulation:
 Result:
Multiplexer 8x1 is successfully implemented.
 EXPERIMENT –3.2

 Aim:
To implement Demultiplexer 8x1 using Behavioral Style of Modeling.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 Truth Table:

Y S2 S1 S0 X7 X6 X5 X4 X3 X2 X1 X0
Y 0 0 0 0 0 0 0 0 0 0 Y
Y 0 0 1 0 0 0 0 0 0 Y 0
Y 0 1 0 0 0 0 0 0 Y 0 0
Y 0 1 1 0 0 0 0 Y 0 0 0
Y 1 0 0 0 0 0 Y 0 0 0 0
Y 1 0 1 0 0 Y 0 0 0 0 0
Y 1 1 0 0 Y 0 0 0 0 0 0
Y 1 1 1 Y 0 0 0 0 0 0 0

 VHDL Code:
library IEEE;

library IEEE.STD_LOGIC_1164.ALL;

library IEEE.STD_LOGIC_ARITH.ALL;

library IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DEMUX is

Port ( X : out STD_LOGIC_VECTOR (7 downto 0);

S : in STD_LOGIC_VECTOR (2 downto 0);

Y : in STD_LOGIC);

End DEMUX;

architecture Behavioral of DEMUX is

begin X<="00000000";

PROCESS(S) CASE S ISWHEN "000" => X(0)<=Y;

BEGIN WHEN "001" => X(1)<=Y;

WHEN "010" => X(2)<=Y;

WHEN "011" => X(3)<=Y;

WHEN "100" => X(4)<=Y;

WHEN "101" => X(5)<=Y;

WHEN "110" => X(6)<=Y;

WHEN "111" => X(7)<=Y;

WHEN OTHERS => X<="00000000";

END CASE;

END PROCESS;

end Behavioral

 Schematic Diagram:

 Simulation:

 Result:
Demultiplexer 1x8 is successfully
implemented.
 EXPERIMENT-4

 Aim: To design a decoder using behavioural modelling.


 Software Used:
Xilinx ISE 8.1

 Block Diagram:

D (0)

A (0)

D (1)

2x4
decoder D (2)

A (1)

D (3)

 VHDL Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec1 is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

E : in STD_LOGIC;

Z : out STD_LOGIC_VECTOR (0 TO 3));

end dec1;
architecture Behavioral of dec1 is

begin

process (A,B,E)

variable ABAR,BBAR: STD_LOGIC;

begin

ABAR:= not A;

BBAR:= not B;

if E='1' then

Z(3)<=not(A and B);

Z(2)<=not(A and BBAR);

Z(1)<=not(ABAR and B);

Z(0)<=not(ABAR and BBAR);

else

Z <= "1111";

end if;

end process;

end Behavioral;
 Schematic Diagram:

 Simulation:

 Result: The designing of decoder using behavioral modeling is verified.

 EXPERIMENT – 5

 Aim:
To implement SR Flip Flop using Behavioral Style of Modeling.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 Truth Table:

CLK S R Q
0 X X No change
1 0 0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Indeterminate

 VHDL Code:
library IEEE;

library IEEE.STD_LOGIC_1164.ALL;

library IEEE.STD_LOGIC_ARITH.ALL;

library IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SR is

Port ( S : in STD_LOGIC;

R : in STD_LOGIC;

CLK : in STD_LOGIC;

Q : inout STD_LOGIC;

QBAR : inout STD_LOGIC);

End SR;

architecture Behavioral of SR is

begin

PROCESS(S,R,CLK)
BEGIN

Q<='0';

QBAR<='1';

IF (CLK='1') THEN

ASSERT (S='1' NAND R='1');

REPORT "FORBIDDEN CASE";

IF(S='1' AND R='0') THEN

Q<='1';

QBAR<='0';

ELSE IF(S='0' AND R='1') THEN

Q<='0';

QBAR<='1';

ELSE IF(S='0' AND R='0') THEN

Q<=Q;

QBAR<=NOT Q;

END IF;

END IF;

END IF;

END IF;

END PROCESS;

end Behavioral;
 Schematic Diagram:

 Simulation:

 Result:
SR Flip Flop is successfully implemented.
 EXPERIMENT – 6.1

 Aim:
To implement GRAY CODE to BINARY using Behavioral Style of Modeling.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 Truth Table:
GRAY CODE I/P BINARY O/P
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

 VHDL Code:
library IEEE;

library IEEE.STD_LOGIC_1164.ALL;

library IEEE.STD_LOGIC_ARITH.ALL;

library IEEE.STD_LOGIC_UNSIGNED.ALL;

entity GRAY CODE to BINARY is

Port ( g : in STD_LOGIC_vector(0 to 3);

b : out STD_LOGIC_vector(0 to 3));

end GRAY CODE to BINARY ;

architecture Behavioral of GRAY CODE to BINARY is

begin

b(3)<=g(0);

b(2)<=g(0) xor g(1);

b(1)<=g(0) xor g(1)xor g(2);

b(0)<=g(0) xor g(1)xor g(2) xor g(3);

end Behavioral;

 Schematic Diagram:

 Simulation:

 Result:
GRAY CODE to BINARY is successfully implemented.
 EXPERIMENT – 6.2

 Aim:
To implement BINARY to GRAY CODE using Behavioral Style of Modeling.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 Truth Table:
BINARY INPUTS GRAY CODE O/P
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

 VHDL Code:
library IEEE;

library IEEE.STD_LOGIC_1164.ALL;

library IEEE.STD_LOGIC_ARITH.ALL;

library IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BINARY to GRAY CODE is

Port ( b : in STD_LOGIC_vector(0 to 3);

g : out STD_LOGIC_vector(0 to 3));

 end BINARY to GRAY CODE;

architecture Behavioral of BINARY to GRAY CODE is

begin

g(3)<= b(3);

g(2)<= b(3) xor b(2);

g(1)<= b(2) xor b(1);

g(0)<= b(1) xor b(0);

end Behavioral;

 Schematic Diagram:

 Simulation:

 Result:
BINARY to GRAY CODE is successfully implemented.
 EXPERIMENT -7.1

 Aim:
To verify AND GATE USING FPGA.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AND_GATE is
port ( a: in STD_LOGIC, b: in STD_LOGIC;
c: out STD_LOGIC);
end AND_GATE;
architecture BEH_AND of AND_GATE is

begin
P3: process (a, b)

begin
if a=’0’ then
if b=’0’ then
c <= ‘0’;

else
c <=’0’;
end if;

else
if b = ‘0’ then
c <= ’0’;
 else
c <= ‘1’;
end if;
end if;
end process P3;
end BEH_AND;

 Figure :

 Pin Assignment:

 Result:
Logic AND gate is successfully studied using FPGA .
 EXPERIMENT -7.2

 Aim:
To verify AND GATE USING CPLD.

 Software Used:
Xilinx ISE 8.1

 Block Diagram:

 VHDL Code:
library IEEE;
library IEEE.STD_LOGIC_1164.ALL;
library IEEE.STD_LOGIC_ARITH.ALL;
library IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AND_GATE is
port ( a: in STD_LOGIC, b: in STD_LOGIC;
c: out STD_LOGIC);
end AND_GATE;
architecture BEH_AND of AND_GATE is

begin
P3: process (a, b)

begin
if a=’0’ then
if b=’0’ then
c <= ‘0’;

else
c <=’0’;
end if;

else
if b = ‘0’ then
c <= ’0’;
 else
c <= ‘1’;
end if;
end if;
end process P3;
end BEH_AND;

 Figure :

 Pin Assignment:

 Result:
Logic AND gate is successfully studied using CPLD .
 EXPERIMENT NO.-8

AIM: TO VERIFY FULL ADDER AND HALF ADDER USING FPGA.

SOFTWARE USED: XILINX ISE 8.1

FULL ADDER USING FPGA-8.1

BLOCK DIAGRAM:

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION;

entity fadd is

Port (a: in STD_LOGIC;

b: in STD_LOGIC;

c: in STD_LOGIC;

sum: out STD_LOGIC;

cout: out STD_LOGIC;

 end fadd;

-- BEHAVIORAL ARCHITECTURAL BODY;

arechitecture Behavioral of fadd is

begin

process(a,b,c)

variable d,e,f,g: STD_LOGIC;

begin

d:=a xor b;

e:=a and b;

f:=b and c;

g<=a and c;

sum<=c xor d;

cout<=((e or f) or g);

end process;

end Behavioral;

FIGURE:
PIN ASSIGNMENT:

RESULT: FULL ADDER is successfully verified using FPGA.

 HALF ADDER USING FPGA:8.2

BLOCK DIAGRAM:

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION;

entity half_add is

Port (a: in STD_LOGIC;

b: in STD_LOGIC;

sum: out STD_LOGIC;

cout: out STD_LOGIC;

end half_add;

-- BEHAVIORAL ARCHITECTURAL BODY;

arechitecture Behavioral of half_add is

begin

process(a,b)
 begin

sum<=a xor b;

cout<=a and b;

end process;

end Behavioral;

FIGURE:

PIN ASSIGNMENT:

RESULT: HALF ADDER is successfully verified using FPGA.

 EXPERIMENT NO.-9

AIM: TO VERIFY FULL ADDER AND HALF ADDER USING CPLD.

SOFTWARE USED: XILINX ISE 8.1

FULL ADDER USING CPLD:-9.1

BLOCK DIAGRAM:

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION;

entity fadd is

Port (a: in STD_LOGIC;

b: in STD_LOGIC;

c: in STD_LOGIC;

sum: out STD_LOGIC;

 cout: out STD_LOGIC;

end fadd;

-- BEHAVIORAL ARCHITECTURAL BODY;

arechitecture Behavioral of fadd is

begin

process(a,b,c)

variable d,e,f,g: STD_LOGIC;

begin

d:=a xor b;

e:=a and b;

f:=b and c;

g<=a and c;

sum<=c xor d;

cout<=((e or f) or g);

end process;

end Behavioral;
FIGURE:

PIN ASSIGNMENT:

RESULT: FULL ADDER is successfully verified using CPLD.

 HALF ADDER USING CPLD:-9.2

BLOCK DIAGRAM:

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION;

entity half_add is

Port (a: in STD_LOGIC;

b: in STD_LOGIC;

sum: out STD_LOGIC;

cout: out STD_LOGIC;

end half_add;

-- BEHAVIORAL ARCHITECTURAL BODY;

arechitecture Behavioral of half_add is

begin

process(a,b)

begin

sum<=a xor b;

cout<=a and b;

end process;

end Behavioral;
FIGURE:

PIN ASSIGNMENT:

RESULT: HALF ADDER is successfully verified using CPLD.

 EXPERIMENT NO-10

AIM: To verify:

1.) FULL SUBTRACTOR using CPLD and FPGA.

2.) HALF SUBTRACTOR using CPLD and FPGA.

SOFTWARE USED: Xilinx ISE 8.1

FULL-SUBTRACTOR (CPLD):10.1.1

Block diagram:

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION;

entity full_sub is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
bin : in STD_LOGIC;
diff : out STD_LOGIC;
bout : out STD_LOGIC);
end full_sub;

-- ARCITECTURE DECLARATION;

architecture Behavioral of full_sub is

begin

process(x,y,bin)
variable xbar : std_logic;
begin

diff <= ((x xor y)xor bin);

xbar := not x;
bout <= ((xbar and y)or(y and bin)or(bin and xbar));
end process;

end Behavioral;
Figure :

Pin-Assignment:

Result: FULL-SUBTRACTOR is successfully implemented using CPLD.

 FULL-SUBTRACTOR (FPGA):10.1.2

Block diagram:

Code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION;

entity full_sub is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
bin : in STD_LOGIC;
diff : out STD_LOGIC;
bout : out STD_LOGIC);
end full_sub;

-- ARCITECTURE DECLARATION;

architecture Behavioral of full_sub is

begin

process(x,y,bin)
variable xbar : std_logic;
begin

diff <= ((x xor y)xor bin);

xbar := not x;
bout <= ((xbar and y)or(y and bin)or(bin and xbar));

end process;
end Behavioral;
Figure :

Pin-Assignment :

Result : FULL-SUBTRACTOR is successfully implemented using FPGA.

 HALF-SUBTRACTOR (CPLD):10.2.1

Block diagram:

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION;

entity half_sub is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
diff : out STD_LOGIC;
bout : out STD_LOGIC);
end half_sub;

-- ARCITECTURE DECLARATION;

architecture Behavioral of half_sub is

begin

process(x,y)
variable xbar : std_logic;
begin

diff <= (x xor y);

xbar := not x;
bout <= (xbar and y);
end process;
end Behavioral;
Figure:

Pin-Assignment:

Result: HALF-SUBTRACTOR is successfully implemented using CPLD.

 HALF-SUBTRACTOR (FPGA):10.2.2

Block diagram:

Code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION;

entity half_sub is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
diff : out STD_LOGIC;
bout : out STD_LOGIC);
end half_sub;

-- ARCITECTURE DECLARATION;

architecture Behavioral of half_sub is

begin

process(x,y)
variable xbar : std_logic;
begin

diff <= (x xor y);

xbar := not x;
bout <= (xbar and y);

end process;

end Behavioral;
Figure :

Pin-Assignment:

Result: HALF-SUBTRACTOR is successfully implemented using FPGA.