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Abstract:
A Time to digital converter is a device for recognizing events and providing a digital representation of the time they
occurred. It is a device commonly used to measure a time interval and convert it into digital (binary) output. A Time-to-digital
converter (TDC) is similar to an analog-to-digital converter (ADC), except that, instead of quantizing voltage or current, the
TDC quantizes time intervals between two rising edges. It is originally developed for nuclear experiments to locate single-shot
events, the TDC is now being used in many applications such as laser range finders, space science instruments, physical
instruments, phase meters, high energy particle detectors, and measurement devices. Our proposed work is to implement mux
based encoder for TIME TO DIGITAL CONVERTER (TDC) with bubble error correction using Xilinx software.
Keywords-- Time to digital converter (TDC), Bubble error correction circuit (BEC), Ring oscillator (RO).
I. INTRODUCTION
…..(5)
where SL Start and SL Stop are the outputs of the triggering
logic at the arrival time of the start and stop signals,
respectively, ô is the propagation delay of the delay cell,
CNTLC is the output of the loop counter, and fRO is the
oscillation frequency. Theoretically, RO-based TDCs have
unlimited dynamic range, but this cannot be accomplished in
practice due to the available number of bits of the loop counter
and limitations in the counting rate. TDCs using RO topology
usually have a time resolution limited by the propagation delay
of the inverter. For example, the TDC in [80] implemented in
the 90-nm CMOS technology had a resolution of 13.6 ps.
Figure 7 :CMOS Transmission Gate. Another disadvantage of a basic RO-based TDC is its high
CMOS Transmisson Gate has the advantage of being simple & power consumption because the RO is working in free-running
fast , complex gates are implemented with the minimum no. of mode, e.g., 24 mW in [4].
transistor ( the reduced parasitic capacitance results in fast
circuits) and better noise margin.
The decoder has a hardware cost-: Total no. of Mux to be
implemented for any N-bit Encoder is
…..(3)
Where ( N= no. of bits)
The critical path in units of tMux is:
Figure 10(b)
SIMULATION RESULT:
All the simulations have been performed using Xilinx ISE
with Verilog design methodology. Simulation result shown
in Figure 10(a), figure 10(b), figure 10(c), figure 10(d).
Figure 10(c)
Figure 10(a)
Figure 10(d)
[6] K.-C. Choi, S.-W. Lee, B.-C. Lee, and W.-Y. Choi, “A
time-to-digital converter based on a multiphase reference clock
and a binary counter with a novel sampling error corrector,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 3, pp.
143–147, Mar. 2012.
CONCLUSION: [7] W. Liu, W. Li, P. Ren, C. Lin, S. Zhang, and Y. Wang, “A
PVT tolerant 10 to 500 MHz all-digital phase-locked loop with
The proposed work present Time-to-digital coupled TDC and DCO,” IEEE J. Solid-State Circuits, vol. 45,
converters using buffers and inverters implemented in no. 2, pp. 314–321, Feb. 2010.
Xilinx 12.4 software. Analysis of Vernier type ring
oscillator TDC has performed. The output of TDC is [8] P. Lu, A. Liscidini, and P. Andreani, “A 3.6 mW, 90 nm
thermometer code which can be get affected by bubble CMOS gated-Vernier time-to-digital converter with an
error. Hence bubble error correction for thermometer code equivalent resolution of 3.2 ps,” IEEE J. Solid-State Circuits,
up to third order is effectively implemented by mux-based vol. 47, no. 7, pp. 1626–1635, Jul. 2012.
encoder circuit. Whereas existing approaches deal with
first/second-order bubble errors only, and failed with [9] Amer Samarah, Student Member, IEEE, and Anthony
higher order of bubble errors. The simulation results Chan Carusone, Senior Member, IEEE,(2013) “A Digital
illustrate that the proposed circuit requires lesser number Phase-Locked Loop With Calibrated Coarse and Stochastic
of transistors and consequently consumes less power, Fine TDC”,IEEE journal of solid-state circuits, vol. 48, no. 8
which makes the circuit superior to the existing models. .
The simulation results gives increased dynamic range in [10] Guansheng Li, Yahya, M. Tousi, Student Member, IEEE,
Vernier type ring based oscillator circuit. ArjangHassibi, Member,IEEE, and EhsanAfshari, Member,
IEEE,(2009)“Delay-Line-Based Analog-to-Digital
Converters”,IEEE transactions on circuits and systemsii:
ACKNOWLEDGEMENT express briefs, vol. 56, no. 6.
The authors are grateful to the lab facility at [11] Jianjun Yu, Student Member, IEEE, Fa Foster Dai,
Electronics and Communication Engineering Fellow, IEEE, and Richard C. Jaeger, Life Fellow, IEEE,(2010)
department of RMK Engineering college, Chennai “A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 m
which provided excellent support to finish the CMOS Technology”, IEEE journal of solid-state circuits, vol.
work successfully. 45, no. 4.
REFERENCES [12]JussiPekkaJansson,AnttiMäntyniemi,anJuhaKostamovaara,
Member, IEEE,(2006)”A CMOS Time-to-Digital Converter
With Better Than 10 ps Single-Shot Precision”, IEEE journal of
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