Lab Manual

ECLR31
Digital Design Lab

Bachelor of Technology
in
Electronics & Communication Engineering

Department of Electronics & Communication Engineering

National Institute of Technology
Kurukshetra-136119
Website: www.nitkkr.ac.in

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 Vision

To impart state-of-the-art Electronics and Communication Engineering

Education and Research responsive to global challenges.

Mission

● M1: To prepare students with strong theoretical and practical knowledge by

imparting quality education.
● M2: To produce comprehensively trained and innovative graduates in
Electronics and Communication Engineering through hands on practice and
research to encourage them for entrepreneurship.
● M3: To inculcate team work spirit and professional ethics in students.

Program Educational Objectives (PEOs)

PEO – 1: Have a lead and successful role in their professional career.

PEO – 2: Be able to analyze real life problems and design socially accepted and
economically viable solutions in Electronics and Communication Engineering
area.

PEO –3: Be capable of lifelong learning and professional development by pursuing higher
education and participation in research and development activities.

PEO –4: Have appropriate human and technical communication skills to be a good team-
member/leaders and responsible human being

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 Program Outcomes (POs)
A graduate of the Electronics and Communication Engineering Program will:
PO1: Engineering knowledge: Possess knowledge of mathematics, science, engineering
fundamentals, and Electronics and Communication Engineering specialization to
solve the problems in Electronics and Telecommunication Systems.
PO2: Problem analysis: Be able to analyze complex problems in Communication systems,
Analog &Digital Electronic Systems, & DSP based systems using first principles of
mathematics, science, and engineering sciences to reach substantiated conclusions.
PO3: Design/development of solutions: Be able to design solutions for complex
Electronics and communication engineering problems and design system components
or processes that meet the specified needs with appropriate consideration for the
public health and safety, and the cultural, societal, and environmental considerations.
PO4: Conduct investigations of complex problems: Be able to use research-based
knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid conclusions.
PO5: Modern tool usage: Be able to create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and modeling to
complex engineering activities with an understanding of the limitations.
PO6: The engineer and society: Be able to apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional Electronics and
Communication Engineering practice.
PO7: Environment and sustainability: Be able to understand the impact of Electronics
and communication engineering solutions in societal and environmental contexts, and
demonstrate the knowledge of, and need for sustainable development.
PO8: Ethics: Be able to apply ethical principles, commit to professional ethics in context to
Electronics and communication engineering practice.
PO9: Individual and team work: Be able to function effectively as an individual, as a
member or leader in diverse teams, and in multidisciplinary settings.
PO10: Communication: Be able to communicate effectively on complex Electronics and
communication engineering activities with the engineering community and with
society at large.
PO11: Life-long learning: Be able to recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context of
technological change.
PO12: Project management and finance: Have knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a
member/ leader in a team, to manage projects in multidisciplinary environments.

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 Program Specific Outcomes (PSOs)

At the end of the program, the student will:

PSO1: Clearly understand the fundamental concepts of Electronics and Communication
Engineering.
PSO2:Formulate the real life problems and develop solutions in the area of semiconductor
technology, signal processing and communication systems.
PSO3: Posses the skills to communicate effectively in both oral and written forms,
demonstrating the practice of professional ethics, and responsive to societal and
environmental needs.

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 ECLR31
Digital Design Lab

L T P

0 0 1

Course
Learning 1. To familiarize students with the working of ICs of logic gates, MUXs,
Objectives Encoder, Decoder, Flip-Flops etc.
2. To demonstrate students, the realization of MUXs/De-MUX, Encoder,
Decoder, Flip-Flops etc. with the help of basic ICs.
3. To enable students to realize one Flip-Flop with the help of other Flip-
Flops.
4. To enable the students to design counter, shift registers, adder,
subtractor etc. with the help of basic ICs.

Course At the end of the course, the student will be able to:
Outcomes CO1 Understand the use of digital ICs of different logic functions.
CO2 Design the MUXs/De-MUX, Encoder, Decoder, Flip-Flops etc. with
the help of ICs.
CO3 Design and implement one Flip-Flop with the help of other Flip-Flops
using ICs.
CO4 Design different types of counter, shift registers, adder, subtractor etc.
with the help of ICs.

List of Experiments:
1. Familiarization with digital trainer kit and associated equipment.
2. Verification of truth table of logic Gates and realization of basic logic Gates using
universal logic Gates.
3. Study of gray to binary and binary to gray conversion using basic Gates.
4. Design and study of Multiplexer and Demultiplexer using ICs.
5. Design and study of Encoder and Decoder using ICs.
6. Design and study of Full Adder and Substractor using ICs.
7. Verification of truth table of SR, JK, D and T Flip-Flops.
8. Realization of JK/SR flip-flop using SR/JK, D and T flip-flops.
9. Design and implementation of MOD-12 up and down counter.
10. Study of working of shift registers.
11. Design and study of BCD to 7-segment converter.

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 EXPERIMENT 1

Objective: To familiarize with Digital Trainer Kit and associated equipment.

Apparatus Required: Digital Trainer Kit .
Theory:
The system combines simple, easy to use, IC’s for gates, arithmetic operations flip flops,
Power supply, input and output states with a bread-board.

Features:
The Logic computer consists of the following built-in-parts:-
1. DC power supply with indicator.
a) Input voltage Fixed 5V+ 1%.
b) Output current 0.1 Amp
c) Load Regulation 50 mV
d) Line Regulation 50 mV
e) Ripple 25 mV
2. Clock Input Device Clock pulse of 1 second.
3. 10 Logic Switches; Hi/LO. Input voltage of Hi Level 4.75-5.25v
Input voltage of Lo level = 0v.
4. 10 LED output Indicator Maximum input voltage less than or equal to 5v DC.
5. Solder less Bread board Bread board having one main strip, total interconnected 640 tie
points for lCs and two half 340 tie main strip, total inter connect points in each half main
strip. One half strips used for power supply, clock input and output states second half strips
used for input states Each strip havin length 173 mm and accepting Dia 0.56mm/22-26 5W 4
Recommended.
6. Mains on/off switch and LED indicator. A common anode seven segment display is also
provided on the right side of the logic computer. The device is operative on 230 v + 10% at
50 Hz AC only.

STANDARD ACCESSORIES
The following integrated circuits & patch cords are supplied with the logic computer.

1. 7400 - Quad 2 input NAND gate

2. 7402 - Quad 2 input NOR gate.
3. 7404 -Hex invertor
4. 7408 - Quad 2 input AND gate
5. 7411 -Triple- 3 input AND gates
6. 7420 -4 input NAND gate.
7. 7427 -Triple.3 Input NOR gates.
8. 7430 - 8 - input NAND gate.
9. 7432 -Quad 2 inputs OR gate-
10. 7442 - BCD to decimal decoder.
11. 7447 - BCD to 7 segment decoder.

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12. 7472 - AND- Gates JK flip-flop.
13. 7474 - Dual D type flip flops
14. 7476 - Dual J-K flip flops (2pcs)
15. 7486 - Quad exclusive - OR gate.
16. 7490 - Decade counter.
17. 7495 - Shift register.
18. 74153 - 1to 4 line Demultiplexer.
19. 74155 - 4 to 1-line Multiplexer
20. 74193 -Synchronous counter
21. 74HC148- 8-to-3 priority encoder.
22. SC74LS138- 3-to-8 decoder.

Applications:
1. Study of OR, AND, NOT, NAND, NOR, EX-OR gates & Verification of their truth tables.
2. Verification of Boolean Identities & Demorgan’s theorem.
3. Study &Verification of truth tables of Digital Adders & Subtractors.
4. Study of flip flop and verification of their truth tables.
5. Study of Counters& Shift registers and verification of their truth tables.
6. Study of Encoders & Decoders and verification of their truth tables.
7. Study of Multiplexers, Demultiplexers and verification of their truth tables.

Panel Description:
On the left side of the bread board, one second clock pulse by pulsar switch is provided. ON
OFF switch is provided on the top at the left side of bread -board. At the top of the
breadboard 10 toggle switches as well as 10 sockets are provided for logic input. 10 sockets
for output are provided at the bottom side of the bread board with 10 LED ‘s on the right side
of the bread board One common anode seven segment display is provided with seven sockets
below seven segment display. A fixed 5v DC + 1% of 0.1 Amp. Supply is terminated on the
panel. These terminating points of the supply are further connected to the bread board slots
by using 24 SW9 wires.
The panel is provided with the bread board set. This bread board consists of two half main
strips and one full main strip (Approx. 173 mm long). The holes which are provided on the
bread board are vertically shorted.

Result: Digital trainer kit has been studied.

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 EXPERIMENT 2

Objective: To verify the truth table of logic Gates and realization of basic logic Gates using
universal logic Gates.

Apparatus required: Digital Trainer Kit, Logic gates ICs, Breadboard, connecting wires.

Theory:
Logic gates are electronic circuits which perform logical functions on one or more inputs to
produce one output. There are seven logic gates.
When all the input combinations of a logic gate are written in a series and their
corresponding outputs written along them, then this input/ output combination is called Truth
Table.

1. AND Gate (IC 7408)

AND gate produces an output as 1, when all its inputs are 1; otherwise the output is 0. This
gate can have minimum 2 inputs but output is always one. Its output is 0 when any input is 0.

IC 7408

2. OR Gate (IC 7432)

OR gate produces an output as 1, when any or all its inputs are 1; otherwise the output is 0.
This gate can have minimum 2 inputs but output is always one. Its output is 0 when all input
are 0.

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 IC 7432
3. NOT Gate (IC 7404)

NOT gate produces the complement of its input. This gate is also called an INVERTER. It
always has one input and one output. Its output is 0 when input is 1 and output is 1 when
input is 0.

IC 7404
4. NAND Gate (IC 7400)

NAND gate is actually a series of AND gate with NOT gate. If we connect the output of an
AND gate to the input of a NOT gate, this combination will work as NOT-AND or NAND
gate. Its output is 1 when any or all inputs are 0, otherwise output is 1.

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 IC 7400

5. NOR Gate (IC 7402)

NOR gate is actually a series of OR gate with NOT gate. If we connect the output of an OR
gate to the input of a NOT gate, this combination will work as NOT-OR or NOR gate. Its
output is 0 when any or all inputs are 1, otherwise output is 1.

IC 7402

6. Exclusive OR (X-OR) Gate (IC 7486)

X-OR gate produces an output as 1, when number of 1’s at its inputs is odd, otherwise output
is 0. It has two inputs and one output.

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 IC 7486

7. Exclusive NOR (X-NOR) Gate (IC 74226)

X-NOR gate produces an output as 1, when number of 1’s at its inputs is not odd, otherwise
output is 0. It has two inputs and one output.

8. Realization of basic gates using NAND Gate IC 7400.

NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate.
So its output is complement of the output of an AND gate. This gate can have minimum two
inputs, output is always one. By using only NAND gates, we can realize all logic functions:
AND, OR, NOT, X-OR, X-NOR. So this gate is also called universal gate.

8.1 NAND gates as NOT gate

A NOT produces complement of the input. It can have only one input, tie the inputs of a
NAND gate together. Now it will work as a NOT gate. Its output is
Y = (A.A)’
=> Y = (A)’

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8.2 NAND gates as AND gate

A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted,
overall output will be that of an AND gate.
Y = ((A.B)’)’
=> Y = (A.B)

8.3 NAND gates as OR gate

From DeMorgan’s theorems: (A.B)’ = A’ + B’

=> (A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.

8.4 NAND gates as X-OR gate

The output of a to input X-OR gate is shown by: Y = A’B + AB’. This can be achieved with
the logic diagram shown in the left side.

Gate No. Inputs Output

1 A, B (AB)’
2 A, (AB)’ (A (AB)’)’
3 (AB)’, B (B (AB)’)’
4 (A (AB)’)’, (B (AB)’)’ A’B + AB’
Now the ouput from gate no. 4 is the overall output of the configuration.
Y = ((A (AB)’)’ (B (AB)’)’)’
= (A(AB)’)’’ + (B(AB)’)’’
= (A(AB)’) + (B(AB)’)
= (A(A’ + B)’) + (B(A’ + B’))
= (AA’ + AB’) + (BA’ + BB’)
= ( 0 + AB’ + BA’ + 0 )
= AB’ + BA’
=> Y = AB’ + A’B

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8.5 NAND gates as X-NOR gate

X-NOR gate is actually X-OR gate followed by NOT gate. So give the output of X-OR gate
to a NOT gate, overall ouput is that of an X-NOR gate.
Y = AB+ A’B’

Procedure:
1. Connect the trainer kit to ac power supply.
2. Connect the inputs of any one logic gate to the logic sources and its output to the
logic indicator.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for each input/output combination.
5. Repeat the process for all other logic gates.
6. Realize basic logic Gates using NAND Gates as shown above. Further, Students are
advised to repeat the same process using NOR logic Gates.
7. Switch off the ac power supply.

Result:
Study and verified truth-tables of various logic gates. Realization of basic logic gates using
universal logic gates are also verified from their respective truth-tables.

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Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All LED’s should be checked.
3. All connections should be tight.
4. Always connect GROUND first and then Vcc.
5. The circuit should be off before change the connections.
6. After completing the experiment switch off the supply to apparatus.

Questions:

1. Explain about universal gates and their importance.

2. Write the IC numbers of different types of logic gates.
3. What you mean by ICs?
4. Which technology is used to fabricate those ICs?
5. How to identify the pin numbers in an IC?

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 Experiment -3

Objective: To Study, design and implement a binary to gray code and gray to binary code
converter using basic Gates.
Apparatus Required: Digital trainer kit, Ex-or gate IC 7486, connecting wire.
Theory: The reflected binary code, also known as Gray code after Frank Gray, is a binary
numeral system where two successive values differ in only one bit. The reflected binary code
was originally designed to prevent spurious output from electromechanical switches. Today
Gray codes are widely used to facilitate error correction in digital communications such as
digital terrestrial television and some cable TV systems.
Forming Gray Code:
The binary-reflected Gray code list for n bits can be generated recursively from the list for n-1
bits by reflecting the list (i.e. listing the entries in reverse order), concatenating the original
list with the reversed list prefixing the entries in the original list with a binary 0, and then
prefixing the entries in the reflected list with a binary 1. For example, generating the n = 3 list
from the n = 2 list:

Forming 1 bit to 2 bit gray code Forming 2 bit to 3-bit gray code

1-bit list: 0 1 Old 2-bit code: 00, 01, 11, 10

Reflect it: 10 New 2-bit code: 10, 11, 01, 00

Prefix old no. with 0: 00 01 Prefix old no. with 0: 000, 001, 011, 010

Prefix new no. with 1: 11 10 Prefix new no. with 1: 110, 111, 101, 100

Concatenate to get the 2-bit gray code: Concatenate both old and new no.
00, 01, 11, 10 000, 001, 011, 010, 110, 111, 101, 100

Binary to Gray Code conversion:

The logical circuit which converts binary code to equivalent gray code is known as binary to
gray code converter. The gray code is a non-weighted code. The successive gray code differs
in one-bit position only that means it is a unit distance code. It is also referred as cyclic code.
It is not suitable for arithmetic operations. It is the most popular of the unit distance codes. It
is also a reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit code
about an axis after 2 rows, and putting the MSB of 0 above the axis and the MSB of 1 below
n-1

the axis. Reflection of Gray codes is shown below

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.

Fig. 1. Conversion table of Binary to Gray code

The bits of 4 bit gray code are considered as G G G G . Now from conversion table,
4 3 2 1

From above SOPs, let us draw K-maps for G , G , G and G .

4 3 2 1

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Circuit diagram of Binary to Gray Code converter

Fig. 2. Logic circuit diagram of Binary to Gray code converter

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Grey to Binary Code Converter:

In gray to binary code converter, input is a multiplies gray code and output is its equivalent
binary code. Let us consider a 4-bit gray to binary code converter. To design a 4-bit gray to
binary code converter, we first have to draw a conversion table.

Fig. 3. Conversion table for Gray to Binary code

Now K-map solution for binary signals B4, B3, B2, B1 are given below.

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Circuit Diagram of Gray to Binary Code converter

Fig. 4. Logic circuit diagram of Gray to Binary code converter.

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Procedure:
1. Construct the circuit for binary to gray code converter.
2. Give inputs to it and match corresponding outputs.
3. Now construct the circuit for gray to binary code converter.
4. Give inputs to it and match corresponding outputs.

Result: The inputs and outputs are matched for both binary to gray and gray to binary code
converter circuits.

Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All connections should be tight.
3. Always connect GROUND first and then Vcc.
4. The circuit should be off before change the connections.
5. After completing the experiment switch off the supply to apparatus.

Questions:
1. What is weighted code?
2. What are alphanumeric codes?
3. What are the applications of Gray code?
4. What are the advantages of Gray code over binary code?

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 EXPERIMENT 4

Objective: To design and study of Multiplexer and De-multiplexer using ICs.

Apparatus Required: Digital Trainer Kit, power supply, connecting wires.

ICs: 74LS04 Hex 1-Input NOT gate
74LS08 Quad 2-Input AND gate
74LS11 Triple 3-Input AND gate
74LS32 Quad 2-Input OR gate

Theory:
Multiplexer:
Multiplexer means many into one i.e. multiplexer is a logic circuit which has many inputs
but single output . A multiplexer accepts several data inputs but allow only one of them at a
time to get through to the output . The inputs and outputs are indicated by means of broad
allow to indicate that there may be one or more inputs. Depending upon the digital code
applied at the select inputs ,one out of the N data sources (D0,D1,---------Dn-1) is selected
and transmitted the single output channel . A 4 to 1 line multiplexer has four inputs but only
single output .

To perform 4 to 1 line multiplexer experiment . We have used IC 74153 .It has 4 line inputs

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(Y0,Y1,Y2,Y3) and only one output. Go is the strobe input (active low )S0 and S1 are select
input lines ,select one out of four inputs at output for e.g. S0,S1 =00 then Y0 will be selected.

TRUTH TABLE
S1 S0 DA
TA
0 0 Y0
0 1 Y1
1 0 Y2
1 1 Y3

Conversely, a Demultiplexer (or demux) is a device taking a single input signal and
selecting one of many data-output-lines, which is connected to the single input. An electronic
demultiplexer can be considered as a single-input, multiple-output switch. A multiplexer is
often used with a complementary demultiplexer on the receiving end.

TRUTH TABLE
INPUTS OUTPUTS
D S1 S0 Y3 Y2 Y1 Y0
A
T
A
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

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Procedure:

1. Connect the circuit as shown in figure for MUX and DEMUX.

2. Apply select line input signal and observe the output as per the logic given to input
pins.
3. Switch off power supply after use.

Result: The 4:1 MUX and 1:4 De-MUX were constructed and their truth tables were
verified.

Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All connections should be tight.
3. Always connect GROUND first and then Vcc.
4. The circuit should be off before change the connections.
5. After completing the experiment switch off the supply to apparatus.

Questions:

1. Difference between Decoder and Demultiplexer.

2. Difference between Encoder and Multiplexer.
3. Implement the function F (A, B, C) =Σm (0, 1, 3, 4) using multiplexer.
4. Design an 8:1 multiplexer.
5. Design an 1 to 16 demultiplexer
7. How many select lines will a 32:1 multiplexer will have?
8. Give the applications of multiplexer.

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 Experiment- 5
Objective: To design and study of Encoder and Decoder using ICs.

Apparatus Required: Digital trainer kit, 8-to-3-bit priority encoder IC 74LS148, 3-to-8 line
decoder IC SN 74LS138.

Theory:

Encoder: Unlike a multiplexer that selects one individual data input line and then sends that
data to a single output line or switch, Digital Encoder more commonly called a Binary
Encoder takes all its data inputs one at a time and then converts them into a single encoded
output. So we can say that a binary encoder, is a multi-input combinational logic circuit that
converts the logic level “1” data at its inputs into an equivalent binary code at its output.
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the
number of data input lines. An “n-bit” binary encoder has 2n input lines and n-bit output lines
with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations.
The output lines of a digital encoder generate the binary equivalent of the input line whose
value is equal to “1” and are available to encode either a decimal or hexadecimal input
pattern to typically a binary or “B.C.D” (binary coded decimal) output code.

4-to-2 Bit Binary Encoder:

Fig. 1. Block diagram and truth table of 4 to 2 binary encoder.

One of the main disadvantages of standard digital encoders is that they can generate the
wrong output code when there is more than one input present at logic level “1”. For example,
if we make inputs D1 and D2 HIGH at logic “1” both at the same time, the resulting output is
neither at “01” or at “10” but will be at “11” which is an output binary number that is
different to the actual input present. Also, an output code of all logic “0” s can be generated
when all of its inputs are at “0” OR when input D0 is equal to one.
One simple way to overcome this problem is to “Priorities” the level of each input pin and if
there was more than one input at logic level “1” the actual output code would only
correspond to the input with the highest designated priority. Then this type of digital encoder
is known commonly as a Priority Encoder or P-encoder for short.

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Priority Encoder:
The Priority Encoder solves the problems mentioned above by allocating a priority level to
each input. The priority encoders output corresponds to the currently active input which has
the highest priority. So when an input with a higher priority is present, all other inputs with a
lower priority will be ignored. The priority encoder comes in many different forms with an
example of an 8-input priority encoder along with its truth table shown below.

8-to-3 Bit Priority Encoder:

Fig. 2. Block diagram and truth table of 8 to 3 priority encoder.

Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3-bit
priority encoder which has eight active LOW (logic “0”) inputs and provides a 3-bit code of
the highest ranked input at its output.
Priority encoders output the highest order input first for example, if input lines “D2“, “D3”
and “D5” are applied simultaneously the output code would be for input “D5” (“101”) as this
has the highest order out of the 3 inputs. Once input “D5” had been removed the next highest
output code would be for input “D3” (“011”), and so on.
Where X equals “dont care”, that is logic “0” or a logic “1”.
From this truth table, the Boolean expression for the encoder above with data inputs D0 to D7
and outputs Q0, Q1, Q2 is given as:
Output Q0

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Output Q1

Output Q2

Then the final Boolean expression for the priority encoder including the zero inputs is
defined as:

In practice these zero inputs would be ignored allowing the implementation of the final
Boolean expression for the outputs of the 8-to-3 priority encoder. We can have constructed
a simple encoder from the expression above using individual OR gates as follows.

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Digital Encoder using Logic Gates

Fig. 3. Logical circuit diagram of 8 to 3 priority encoder.

IC 74HC148 Description:

74HC148 is a 16-Pin 8-Line to 3-Line Priority Encoder IC having 2 V to 6 V Operating

Voltage range with 5.2 mA output current and low power consumption. It encodes Eight
Data Lines to 3-Line Binary. It features priority decoding of the inputs to ensure that only the
highest-order data line is encoded. Cascading circuitry (enable input EI and enable output
EO) has been provided to allow octal expansion without the need for external circuitry. Data
inputs and outputs are active at the low logic level. The 74HC148 feature priority decoding
of the inputs to ensure that only the highest-order data line is encoded. These devices encode
eight data lines to 3-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and
enable output EO) has been provided to allow octal expansion without the need for external
circuitry. Data inputs and outputs are active at the low logic level. IC 74 HC148 Pin-diagram
and functional is shown below.

Fig.4. Pin-diagram of IC 74HC148

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 Fig. 5. Functional table of IC 74HC148

Decoder:
The name “Decoder” means to translate or decode coded information from one format into
another, so a digital decoder transforms a set of digital input signals into an equivalent
decimal code at its output.
Binary Decoders are another type of digital logic device that has inputs of 2-bit, 3-bit or 4-
bit codes depending upon the number of data input lines, so a decoder that has a set of two or
more bits will be defined as having an n-bit code, and therefore it will be possible to
represent 2n possible values. Thus, a decoder generally decodes a binary value into a non-
binary one by setting exactly one of its n outputs to logic “1”.
If a binary decoder receives n inputs (usually grouped as a single Binary or Boolean number)
it activates one and only one of its 2n outputs based on that input with all other outputs
deactivated.
Then we can say that a standard combinational logic decoder is an n-to-m decoder, where
m ≤ 2n, and whose output, Q is dependent only on its present input states. In other words, a
binary decoder looks at its current inputs, determines which binary code or binary number is
present at its inputs and selects the appropriate output that corresponds to that binary input.
A Binary Decoder converts coded inputs into coded outputs, where the input and output
codes are different and decoders are available to “decode” either a Binary or BCD (8421
code) input pattern to typically a Decimal output code. Commonly available BCD-to-
Decimal decoders include the TTL 7442 or the CMOS 4028. Generally, a decoders output
code normally has more bits than its input code and practical “binary decoder” circuits
include, 2-to-4, 3-to-8 and 4-to-16 line configurations.
An example of a 2-to-4-line decoder along with its truth table is given below.

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2-to-4 Binary Decoders:

This simple example above of a 2-to-4 line binary decoder consists of an array of four AND
gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs, hence the
description of 2-to-4 binary decoder. Each output represents one of the min-terms of the 2
input variables, (each output = a min-term).
The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic
level “1” while the remaining outputs are held “LOW” at logic “0” so only one output can be
active (HIGH) at any one time. Therefore, whichever output line is “HIGH” identifies the
binary code present at the input, in other words it “de-codes” the binary input.

Some binary decoders have an additional input pin labelled “Enable” that controls the
outputs from the device. This extra input allows the decoders outputs to be turned “ON” or
“OFF” as required. These types of binary decoders are commonly used as “memory address
decoders” in microprocessor memory applications.

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IC SN 74LS138 Description:

Fig. 6. Pin diagram of IC SN 74 LS 138

SN 74LS138 is a 3-to-8 decoder / 1-to-8 demultiplexer IC. It has three data inputs A, B, C
and three selection/ Enable inputs G1, G2A(Bar), G2B(Bar). It has eight outputs Y0 to Y7.
Functional table of IC SN 74 LS 138 is given below.

Fig. 7. Functional/ Truth table of IC SC 74 LS 138

30
Procedure:
1. First mount 8-to-3 priority encoder IC 74HC148 on digital trainer kit and make input
connections by switches.
2. Now apply inputs to encoder IC and verify out puts according to truth table given in
Fig. 5
3. Next connect 3-to-8 decoder IC SC74LS138 on digital trainer kit and make
connections to inputs A, B, C and Enable inputs.
4. Now verify the output according to truth table of decoder IC as given in Fig. 7.
5. Students are advised to perform a 4-to-16-line decoder with the help of two
SC74LS138 ICs.
Result: Truth table of 8-to-3 priority encoder and 3-to-8 decoder have been verified.

Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All connections should be tight.
3. Always connect GROUND first and then Vcc.
4. The circuit should be off before change the connections.
5. After completing the experiment switch off the supply to apparatus.

Questions:
1. What are the practical applications of encoder and decoder?
2. How you will implement a 4 to 16 decoder with the help of 3 to 8 decoder?
3. What are the differences between multiplexer and encoder?
4. How decoder and demultiplexer are same?

31
 EXPERIMENT 6

Objective: To design and study of Full Adder and Subtractor using ICs.

Apparatus Required: Digital Trainer kit, power supply, connecting wires, Logic gates ICs.

Theory:

Full Adder:

A binary full adder is a multiple output combinational logic network that performs the
arithmetic sum of three input bits. It consists of three inputs, in which two are input variables
represent the two significant bits to be added, labeled as A and B, whereas the third input
terminal is the carry from the previous lower significant position and labeled as Cin. The two
outputs are a sum and a carry outputs which are labeled as Σ and Cout respectively.

Full adder can be formed by combining two half adders and an OR gate as shown in above
where output and carry-in of the first adder becomes the input to the second half adder that
produce the total sum output. The total carry out is produced by ORing the two half adder
carry outs as shown in figure. The full adder block diagram and truth table is shown below.

32
 Full Adder Truth Table

Full Subtractor:

A combinational logic circuit performs a subtraction between the two binary bits by
considering borrow of the lower significant stage is called as the full subtractor. In this,
subtraction of the two digits is performed by taking into consideration whether a 1 has
already borrowed by the previous adjacent lower minuend bit or not. It has three input
terminals in which two terminals corresponds to the two bits to be subtracted (minuend A
and subtrahend B), and a borrow bit Bi corresponds to the borrow operation. There are two
outputs, one corresponds to the difference ‘D’ output and other borrow output ‘Bo’ as shown
in figure along with truth table.

By deriving the Boolean expression for the full subtractor from above truth table, we get the
expression that tells that a full subtractor can be implemented with half subtractors with OR
gate as shown in figure below.

33
Procedure:
1. Connect the trainer kit to ac power supply.
2. Connect the inputs to the logic sources and outputs to the logic indicator of basic
gates as per the circuit diagram of full adder and subtractor.
3. Apply various input combinations and observe output as per truth tables of full adder
and subtractor.
4. Switch off the ac power supply.

Result: Working and applications of of full adder and subtractor have been studied.

Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All connections should be tight.
3. Always connect GROUND first and then Vcc.
4. The circuit should be off before change the connections.
5. After completing the experiment switch off the supply to apparatus.

Questions
1. What is the difference half-adder/subtractor and full-adder/subtractor?
2. What are the possible applications of full-adder/subtractor?
3. Design a full adder using half subtractor.
4. Design a half/full adder using NAND gate only.

34
 EXPERIMENT 7

Objective: To verify the truth table of SR, JK, D and T Flip-Flops.

Apparatus required: Digital Trainer kit, power supply, connecting wires, Logic gates ICs.

Theory: The basic one-bit digital memory circuit is known as flip-flop. It can store either 0
or 1.
Flip-flops are classifieds according to the number of inputs.
R-S Flip-Flop: The circuit is similar to SR latch except enable signal is replaced by clock
pulse.
Truth Table:

Clock Pulse S R Q(t+1)

0 x x Q(t)

1 0 0 Q(t)

1 1 0 Set

1 0 1 Reset

1 1 1 Indeterminate ?

D Flip-Flop: A D FF has a single data input. This type of FF is obtained from the SR FF by
connecting the R input through an inverter, and the S input is connected directly to data
input. The modified clocked SR flip-flop is known as D-flip-flop and is shown below.

35
From the truth table of SR flip-flop we see that the output of the SR flip-flop is in
unpredictable state when the inputs are same and high. In many practical applications, these
input conditions are not required. These input conditions can be avoided by making then
complement of each other.

Truth Table

Clock Pulse D input Q(t+1)

0 x Q(t)

1 0 0

1 1 1

J-K Flip-Flop: In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS
flip-flop circuit may be re-joined if both inputs are 1 than also the outputs are complement of
each other.

36
Truth Table

PRESET CLEAR CLOCK J K Q Q’

L L X X X H H

L H X X X H L

H L X X X L H

H H L 0 0 Q Q'

H H L 1 0 1 0

H H L 0 1 0 1

H H L 1 1 Toggle

T Flip-Flop:- T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the

J-K flip-flop. Both the JK inputs of the JK flip – flop are held at logic 1 and the clock signal
continuous to change.

Truth Table

Clock Pulse T Input Q(t+1)

0 x NC

37
1 0 NC

1 1 Toggle (Qt)'

Procedure:
1. Connect the trainer kit to ac power supply.
2. Connect the inputs to the logic sources and outputs to the logic indicator of basic
gates as per the circuit diagram..
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for different Flip-Flops.
5. Repeat the process for all other Flip-Flops.
6. Switch off the ac power supply.

Result:
Study and verified truth-tables of various flip-flops.

Precaution:
1. All the IC’s should be checked before use the apparatus.
2. All LED’s should be checked.
3. All connections should be tight.
4. Always connect GROUND first and then Vcc.
5. The circuit should be off before change the connections.
6. After completing the experiment switch off the supply to apparatus.

Questions:
1) What is a latch?
2) What is a flip flop?
3) Differentiate between a latch and a flip flop.
4) Differentiate between combinational and sequential circuits.
5) What happens to the JK flip flop if the J input is treated as an inverter is wired between J
and K inputs?
6) When a JK flip flop is in a no change condition?
7) Which is the basic sequential building block in which the output follows the data input as
long as the enable input is active?
8) How many stable states a flip flop has?

38
 Experiment-8

Objective: To Realize JK/SR flip-flop using SR/JK, D and T flip-flops.

Apparatus Required: Digital Trainer kit, JK FF IC 7476, AND gat IC 7408,NOT gate IC
7404, connecting wires.

Theory: Flip-flops are bi-stable single-bit memory devices which are one among the
numerous digital components used in sequential systems. The various kinds of flip-flops in
existence are SR flip-flop, JK flip-flop, D flip-flop, and T flip-flop. Each of them exhibit
unique characteristics and hence result in different output for the same combination of input
states. Hence, whenever we want one flip-flop to mimic the behavior of the other, we need to
resort to a flip-flop conversion technique.

Step 1:
Creating an Excitation Table: The output of a flip-flop at a given instant depends on both
its input(s) as well as its present-state, defined by the information summarized and presented
by its truth table. In other words, in the truth table of a flip-flop, the next-state output will be
the last column. That column is determined by the combination of bits in its preceding
columns, which will be the input(s) followed by its present-state.
Now, just imagine that we want to know the sequence of the input combination which
results in a definite output state. The information pertaining to this can be obtained by
back-tracing (in terms of columns) the information presented by the truth table of the flip-
flop. That is, we will have the first two columns as the present- and the next-states of the
flip-flop which will be followed by the column(s) representing the flip-flop inputs. Such a
table can be aptly referred to as an "excitation table" as it indicates the excitations to be
provided at the input pins of the flip-flop to result in the expected outcome for a known
present-state.
The concept explained can be further made clear by the following example, where we
obtain the excitation table for the SR flip-flop from its truth table:

Fig. 1. Truth table and Excitation table of SR FF

39
The first row in the truth table above shows that the present- and the next-states of the flip-
flop will be 0 and 0 if its inputs are S = 0 and R = 0.
The same output combination also appears even when the inputs are given as S = 0 and R
= 1 as evident from the third row of the truth table. This indicates that, in order to obtain
the SR flip-flop's output as 0, we must drive the input pin, S, to low (i.e. S = 0) while the
other input, R, may be pulled either low or high (i.e. R = 0 or 1), provided its present state
is 0. In other words, the input combination S = 0 and R = X (Don't Care) results in the
next-state of the flip-flop to be 0 from its current state, which is equal to 0.
Now, note that the same information is successfully conveyed by the entries (shown in the
red colour) in the first row of the excitation table.
Similarly, the present-state and next-state combination of 0 and 1 is obtained for the SR
flip-flop when its inputs are S = 1 and R = 0. This information is concisely represented by
the second row of the excitation table (shown in the blue colour).
Following on the same grounds, we find that to obtain present- and next-states of the flip-
flop as 1 and 0, we should have S = 0 and R = 1, as indicated by the entries in the black
colour corresponding to the third row of the excitation table.
Lastly, note that S can be either 1 or 0 (i.e. S = X) and R should be 0 in order to obtain the
present- and next-states of the flip-flop as 1 and 1. This is shown by the green colour
entries in the fourth row of its excitation table.
Having done this, all the information present in the truth table is transferred appropriately
into the excitation table, completing it.
By employing the same procedure, the excitation tables can be obtained for all other types
of flip-flops viz., JK flip-flop, D flip-flop, and T flip-flop as shown by Figures 2, 3 and 4,
respectively:

Fig. 2. Truth table and Excitation table of JK FF

40
 Fig. 3. Truth table and Excitation table of D FF

Fig. 4. Truth table and Excitation table of T FF

Step 2:
Creating a Conversion table: When we say, "We want a particular flip-flop", it means
that we are clear about the flip-flop outcomes for the given combination of inputs for each
case of its present-state. That is, we have the truth-table information of the desired flip-flop
in our hands. However, the expected outcome cannot be obtained directly from the given
flip-flop as its behavior for the same combination of input states and the present-state will
be different (most of the time).
Hence, one needs to determine the sequence of the input bits in the given flip-flop which
results in the same output (for a definite present-state) as that in the case of the desired flip-
flop. As mentioned before, this information is readily present in the form of the entries in
the excitation table of the given flip-flop.
Knowing this, the next step would be to merge the information presented by the excitation
table of the given flip-flop with the information present in the truth table of the desired
flip-flop. This can be done by filling the entries from the excitation table of the given flip-
flop into the appropriate rows of the truth table corresponding to the desired flip-flop by
adding additional column(s) which represent the input(s) of the given flip-flop. When done
so, we will get a new table which we can refer to as a "Conversion Table":

41
 Fig. 5. Design of conversion table
For example, the conversion process of the SR flip-flop into a JK flip-flop is initiated by
writing the truth table for the JK flip-flop as shown by the yellowish enclosure in Figure 6.
Here, it is seen that the first row has the present- and the next-states of the flip-flop as 0
and 0 (the red entries in the truth table).Now we look at the excitation table of the SR flip-
flop (shown in the right-side of Figure 6) which has a row indicating the present- and the
next-states of the SR flip-flop to be 0 and 0. As seen by the red entries in the excitation
table, this corresponds to the first row for which the inputs are S = 0 and R = X The same
information is placed into the first row of the JK flip-flop's truth table by adding two more
columns, S and R (as shown by the pink enclosure in Figure 6), to result in an SR-to-JK

Fig. 6. SR to JK FF conversion table

Similarly, the second row of the JK flip-flop has the present- and the next-states as 1 and 1
which correspond to the fourth row of the SR flip-flop's excitation table (shown as the
green entries in the respective tables). The values for the S and R inputs corresponding to
this output combination is seen to be X and 0, respectively, which are filled into the second
row of the conversion table (shown in green again).
By following the same procedure for each and every row, the entire table can be filled to
obtain a completed SR-to-JK flip-flop conversion table, as shown in the center of Figure 6.

42
Step 3:
Obtaining logical expressions: Having obtained the conversion table, the next step is to
arrive at the logical expressions for the inputs of the given flip-flop in terms of the inputs
of the desired flip-flop and the present-state.
Further, you should take care to obtain the minimal logical expression so as to facilitate the
design of the circuit with the least possible gates. This objective can be achieved by
employing any of the suitable Boolean algebraic simplification techniques like that of the
K-map technique.
According to this, for the example under consideration, we need to obtain the expressions
for the inputs S and R in terms of J, K, and Qn. This can be done by employing the K-map
simplification technique as shown in Figure 7.

Fig. 7. K-map simplification for the inputs of the SR flip-flop in terms of J, K, and Qn

Step 4:
Design logic circuit diagram: At last, by using the information provided by the logical
expression obtained, we can re-design the connections to be provided at the input pins of
the given flip-flop. This can be achieved either by just manipulating the connections and/or
by adding additional combinational circuit(s), in order to make the given flip-flop
functionally equivalent to the desired flip-flop.
In the example provided, the logical expressions obtained for S and R indicate two things:
 The input pin S of the SR flip-flop is to be fed by the output of a two-input AND gate
which is driven by J and Q̅n.
 The input pin R of the SR flip-flop is to be fed by the output of a two-input AND gate
which is driven by K and Qn.
Both of these must be satisfied in order to make an SR flip-flop behave like a JK flip-flop
as shown in Figure 8.

43
 Fig. 8. A SR flip-flop behaving like a JK flip-flop.
However, it is to be noted that similar steps will also hold good for mutual conversion
between any kind of flip-flops available.
Conversion of an SR-to-D Flip-Flop: The process is initiated by obtaining the SR-to-D
conversion table – a table which incorporates the information present in the excitation table
of the SR flip-flop into the truth table of the D flip-flop. This is shown in Figure 9.

Fig. 9. The breakdown of an SR-to-D conversion table

Next, we need to obtain the logical expressions for the S and R input pins in terms of D
and the present-state literal, Qn. We can do this using a simplification technique like that of
K-maps. In this case, the technique yields a K-map as shown in Figure 10.

Fig. 10. K-map simplification for the conversion of an SR-to-D flip-flop

44
From Figure 10, we can conclude that the given SR flip-flop can be made functionally
equivalent to a D flip-flop by driving its S and R inputs by D and D̅, respectively. Thus, the
required digital system can be designed by using a single NOT gate as shown by Figure 11.

Fig. 11. An SR flip-flop functioning as a D flip-flop

Conversion of an SR-to-T Flip-Flop:

In order to convert the given SR flip-flop into T-type, we have to first write the SR-to-T
conversion table, which is shown in Figure 12.

Fig. 12. SR-to-T conversion table

Now, we need to express the inputs S and R in terms of T and the present-state literal, Qn.
This can be accomplished by simplifying their logical expressions using the K-map
technique (Figure 13).

Fig. 13. K-map simplification for S and R inputs in terms of T and Qn

45
From Figure 13, it can be noted that the SR flip-flop can be made to function as a T flip-
flop with two actions:
1. Connect the S input to the output of a two-input AND gate which is driven by the
user-provided input, T, and the negation of the flip-flop's present-state, Q̅n
2. Connect the R input to the output of a two-input AND gate which is driven by the
user-defined input, T, and the present-state of the flip-flop, Qn
Thus the resultant digital system would be as shown in Figure 14.

Fig. 14. An SR flip-flop functioning as a T flip-flop

J K Flip-Flop to other Flip-Flops:

Now using the same procedure one can concert J K flip-flop in to S R, D, T flip-flops. The
circuit diagrams for realization of S R flip-flop, D flip-flop, T flip-flop using J K flip-flop
are given below.

Fig. 15. J-K flip-flop working as S-R flip-flop.

46
 Fig. 16. J-K flip-flop working as D flip-flop.

Fig. 17. J-K flip-flop working as T flip-flop.

Procedure:
1. Take a J-K FF IC 7476 and design the circuit according to Fig.15 and verify truth
table of S-R FF by applying proper inputs.
2. Now connect circuit according to Fig. 16 and verify the truth table of D FF.
3. Now construct Circuit according to Fig. 17 and verify truth table of T FF.
4. Student are advised to do the same exercise to convert S-R FF to J-K, D, T FFs.

Result: Realization of J-K/S-R, D, T FFs are done using S-R/J-K FF.

Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All connections should be tight.
3. Always connect GROUND first and then Vcc.
4. The circuit should be off before change the connections.
5. After completing the experiment switch off the supply to apparatus.

47
Questions:
1. What are the applications of JK FF?
2. What are the practical applications of SR FF?
3. What are the applications of D FF?
4. What are the applications of T FF?

48
 EXPERIMENT 9

Objective: To design and implement MOD-12 up and down counter.

Apparatus Required: Digital Trainer kit, power supply, connecting wires, Logic gates ICs
7473, 7404.

Theory:

MOD-12 up counter:

The modulus of a counter is the number of discrete states a counter can take up. A counter
with n no. of flip flops will have 2n number of possible states. So counters with modulus, for
example, 2, 4, 8, 16, can be built up using 1, 2, 3, 4 flip flops. It is quite often desirable to
construct a counter having a modulus of 5, 9 or 12 etc. To design counters of modulus-12
(say), one has to use a modulus 16 counter and to arrange the circuit in such a way that it
skips some of its natural states restricting it to12. The simplest way of doing this is the direct
clearing method, where a gate circuit is used to clear all the flip flops as the desired count is
reached. Thus, for a modulus N counter, the number n of flip-flops should be such that n is
the smallest number for which 2n >N and then to skip the surplus states with some
rearrangements of the circuit. The circuit diagram for a Mod-12 counter is shown below. It is
obvious that a mod-12 counter will require 4 flip-flops which when connected as a counter,
will provide 16 states. This counter counts 0, 1, 2, .., 15 and then it resets to 0. For a mod-12
counter, one may skip state 12 and return to state 0 from state 11 and the cycle should
continue this way. For this an additional combinational logic circuit, i.e. i.e. a 2-input NAND
gate is required, whose output is connected to clear terminal of all the flip flops. This will
feed a reset pulse to the counter during state 12 (1100) and immediately after state 11 (1011).
The flip-flops are reset and the counter starts counting again.

Characteristic Table

49
Procedure:
1. Connect the trainer kit to ac power supply.
2. Connect the inputs to the logic sources and outputs to the logic indicator of basic
gates as per the circuit diagram of MOD 12 up counter.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for different types of MOD 12 up counter.
5. Repeat the same process for MOD-12 down counter.
6. Switch off the ac power supply.

Result: Working and applications of MOD-12 up and down counter has been studied.

Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All connections should be tight.
3. Always connect GROUND first and then Vcc.
4. The circuit should be off before change the connections.
5. After completing the experiment switch off the supply to apparatus.

50
Questions
1. What is the difference between decade counter and 4 bit counter?
2. What is meant by a modulus of a counter?
3.What is a sequential circuit?
4.Differentiate between synchronous and asynchronous counter?
5.How many number of flip-flops are required for decade counter?
6.What is meant by excitation table?
7.If the modulus of a counter is 9 how many flip-flops are required?

51
 EXPERIMENT 10

Objective: To study the working of shift registers.

Apparatus Required: Digital Trainer kit, power supply, connecting wires, Logic gates ICs
7473, 7404.

Theory:
A shift register is a device that inputs data loaded serially into a basic memory unit (flip-flop
of latch) and then shifts this information to an adjacent storage element, leaving the original
memory unit open for additional input data. There are a large number of shift register types
and configurations. Shift registers can be made from TTL standard flip-flops or can be
packaged for specific operation. Shift registers produce a discrete delay of a digital signal or
waveform. A waveform synchronized to a clock, a repeating square wave, is delayed by “n”
discrete clock times, where “n” is the number of shift register stages. Thus, a four stage shift
register delays “data in” by four clocks to “data out”. The stages in a shift register are delay
stages, typically type “D” Flip-Flops or type “JK” Flip-flops.
Shift registers are classified by structure according to the following types:
● Serial-in/serial-out
● Parallel-in/serial-out
● Serial-in/parallel-out
● Universal parallel-in/parallel-out
● Ring counter

Serial-in/Serial-out

52
Above we show a block diagram of a serial-in/serial-out shift register, which is 4-stages long.
Data at the input will be delayed by four clock periods from the input to the output of the
shift register.
Data at “data in”, will be present at the Stage A output after the first clock pulse. After the
second pulse stage A data is transferred to stage B output, and “data in” is transferred to stage
A output. After the third clock, stage C is replaced by stage B; stage B is replaced by stage
A; and stage A is replaced by “data in”. After the fourth clock, the data originally present at
“data in” is at stage D, “output”. The “first in” data is “first out” as it is shifted from “data in”
to “data out”.

Parallel-in/Serial-out

53
Data is loaded into all stages at once of a parallel-in/serial-out shift register. The data is then
shifted out via “data out” by clock pulses. Since a 4- stage shift register is shown above, four
clock pulses are required to shift out all of the data. In the diagram above, stage D data will
be present at the “data out” up until the first clock pulse; stage C data will be present at “data
out” between the first clock and the second clock pulse; stage B data will be present between
the second clock and the third clock; and stage A data will be present between the third and
the fourth clock. After the fourth clock pulse and thereafter, successive bits of “data in”
should appear at “data out” of the shift register after a delay of four clock pulses. If four
switches were connected to DA through DD, the status could be read into a microprocessor
using only one data pin and a clock pin. Since adding more switches would require no
additional pins, this approach looks attractive for many inputs.
Serial-in/Parallel-out

54
Above, four data bits will be shifted in from “data in” by four clock pulses and be available
at QA through QD for driving external circuitry such as LEDs, lamps, relay drivers, and horns.
After the first clock, the data at “data in” appears at QA. After the second clock, the old QA
data appears at QB; QA receives next data from “data in”. After the third clock, QB data is at
QC. After the fourth clock, QC data is at QD. This stage contains the data first present at “data
in”. The shift register should now contain four data bits.

Parallel-in/Parallel-out

55
A parallel-in/parallel-out shift register combines the function of the parallel-in, serial-out
shift register with the function of the serial-in, parallel-out shift register to yield the universal
shift register. The “do anything” shifter comes at a price– the increased number of I/O
(Input/Output) pins may reduce the number of stages which can be packaged. Data presented
at DA through DD is parallel loaded into the registers. This data at QA through QD may be
shifted by the number of pulses presented at the clock input. The shifted data is available at
QA through QD. The “mode” input, which may be more than one input, controls parallel
loading of data from DA through DD, shifting of data, and the direction of shifting. There are
shift registers which will shift data either left or right.
Procedure:
1. Connect the trainer kit to ac power supply.
2. Connect the inputs to the logic sources and outputs to the logic indicator of basic
gates as per the circuit diagram.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for different types of shift registers..
5. Switch off the ac power supply.

Applications:
1. Serial data transmission, over a distance of meters to kilometers, uses shift registers
to convert parallel data to serial form. Serial data communications replace many slow
parallel data wires with a single serial high speed circuit.
2. Serial data over shorter distances of tens of centimeters, uses shift registers to get
data into and out of microprocessors. Numerous peripherals, including analog to
digital converters, digital to analog converters, display drivers, and memory, use shift
registers to reduce the amount of wiring in circuit boards.
3. Some specialized counter circuits actually use shift registers to generate repeating
waveforms

56
Result:
Working of shift register has been studied.

Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All connections should be tight.
3. Always connect GROUND first and then Vcc.
4. The circuit should be off before change the connections.
5. After completing the experiment switch off the supply to apparatus.

Questions:
1. What is a shift register?
2. Write some applications of shift register.
3. Explain the 4-bit serial in and serial out shift register.
4. What is serial in parallel out shift register?
5. State various applications of shift registers.

57
 EXPERIMENT 11

Objective: To design and implement BCD to 7-segment converter.

Apparatus Required: Digital Breadboard, 7 segment display, connecting wires, resistors,
power supply, IC-7447/7448.
Theory:

A BCD to 7 segment decoder circuit 7447 is a special form of decoder circuit that accept the
standard 8421 BCD input code and generate a special 7–bit output code that is used to
operate a 7 segment readout. The output transition in 7447 can stand up to 15V. It can link
enough current to drive common anode type LED-7 segment displays. In addition to BCD
inputs and 7 outputs for driving segments the IC have one lamp test input, a blanking
input/ripple blanking output and a ripple blanking input.

There are two important types of 7-segment LED digital display.

1. The Common Cathode Display (CCD) – In the common cathode display, all the
cathode connections of the LED’s are joined together to logic “0” or ground. The
individual segments are illuminated by application of a “HIGH”, logic “1” signal
to the individual Anode terminals.
2. The Common Anode Display (CAD) – In the common anode display, all the anode
connections of the LED’s are joined together to logic “1” and the individual
segments are illuminated by connecting the individual Cathode terminals to a
“LOW”, logic “0” signal.

Common Cathode and Common Anode Format

Electrical connection of the individual diodes for a common cathode display and a common
anode display and by illuminating each light emitting diode individually, they can be made to
display a variety of numbers or characters.

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7-Segment Display Format

So in order to display the number 3 for example, segments a, b, c, d and g would need to be
illuminated. If we wanted to display a different number or letter then a different set of
segments would need to be illuminated. Then for a 7-segment display, we can produce a truth
table giving the segments that need to be illuminated in order to produce the required
character as shown below.

A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or
74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment.

BCD to 7-Segment Decoder

The use of packed BCD allows two BCD digits to be stored within a single byte (8-bits) of
data, allowing a single data byte to hold a BCD number in the range of 00 to 99.

An example of the 4-bit BCD input ( 0100 ) representing the number 4 is given below.

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Display Decoder Example

Truth table for common Anode type BCD to seven segment decoder

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Procedure:

1. Connect the circuit as shown in figure.

2. Switch on the instrument using on/off toggle switch provided on front panel.
3. Connect lamp test (LT) of IC 7447 to ground. All LED segments should light up.
4. Make lamp test input high. Apply clock pulses one by one and see that the numbers
displayed by the LED repeat sequentially from 0 through 9.
5. Apply clock pulses till number ‘zero’ is displayed. Now connect input marked RBI to
ground. The display should disappear.
6. Switch-off the power supply.

Precautions:

1. All the IC’s should be checked before use the apparatus.

2. All connections should be tight.
3. Always connect GROUND first and then Vcc.
4. The circuit should be off before change the connections.
5. After completing the experiment switch off the supply to apparatus.

Results: The truth table of BCD to 7 segment is verified.

Questions:
1. Explain the pin configuration of 7 segment display, IC-7447, 7448.
2. Draw the decoder circuit of IC-7447 using basic gates.
3. Draw the decoder circuit of IC-7448 using basic gates.
4. Explain the difference between decoder and encoder.
5. Give the application of above experiment in real life.

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