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Not recommended for new designs.

No replacement is available

Data Sheet PD No. 60255 revA

IRS21851SPbF
SINGLE HIGH SIDE DRIVER IC
Features
Product Summary
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout for VBS and V CC VOFFSET 600 V max.
• 3.3 V and 5 V input logic compatible
• Tolerant to negative transient voltage IO+/- 4A/ 4A
• Matched propagation delays for all channels
• RoHS compliant VOUT 10 V - 20 V
Description ton/off (typ.) 160 ns & 160 ns
The IRS21851 is a high voltage, high speed power
MOSFET and IGBT single high-side driver with propa-
gation delay matched output channels. Proprietary Package
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The floating logic
input is compatible with standard CMOS or LSTTL
output, down to 3.3 V logic and can be operated up to
600 V above the ground. The output driver features a
high pulse current buffer stage designed for mini-
mum driver cross-conduction. The floating channel
can be used to drive an N-channel power MOSFET 8-Lead SOIC
or IGBT in the high- side configuration, which oper- IRS21851
ates up to 600 V.

Typical Connection

up to 600V

VCC VCC VB
IN IN HO
VS TO
LOAD

COM

(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.

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Not recommended for new designs. No replacement is available

IRS21851SPbF

Absolute Maximum Ratings


Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.

Symbol Definition Min. Max. Units


VC C Low-side supply voltage -0.3 20 (Note 1)
V IN Logic input voltage (HIN) COM -0.3 VCC + 0.3
VB High-side floating well supply voltage -0.3 620 (Note 1)
V
VS High-side floating well supply return voltage V B - 20 VB + 0.3
VHO Floating gate drive output voltage VS - 0.3 VB + 0.3
dVs /dt Allowable VS offset supply transient relative to COM — 50 V/ns
PD Package power dissipation @ TA ≤ +25 °C — 1.25 W
RthJA Thermal resistance, junction to ambient — 100 °C/W
TJ Junction temperature -55 150
TS Storage temperature -55 150 °C
TL Lead temperature (soldering, 10 seconds) — 300

Note 1: All supplies are fully tested at 25 V. An internal 20 V clamp exists for each supply.

Recommended Operating Conditions


For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to COM. The offset rating are tested with supplies of (VCC-COM)=(VB-VS)=15 V.

Symbol Definition Min. Max. Units


VC C Low-side supply voltage 10 20
V IN HIN input voltage COM VC C
VB High-side floating well supply voltage V S + 10 VS + 20 V
VS High-side floating well supply offset voltage Note 2 600
VHO Floating gate drive output voltage VS VB
TA Ambient temperature -40 125 °C

Note 2: Logic operational for VS of -5 V to 600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design
Tip DT97-3 for more details).

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Not recommended for new designs. No replacement is available

IRS21851SPbF

Dynamic Electrical Characteristics


(VCC-COM)=(VB-VS)=15 V, TA = 25 oC. CL = 1000 pF unless otherwise specified. All parameters are referenced to COM.

Symbol Definition Min. Typ. Max. Units Test Conditions


ton Turn-on propagation delay — 160 210 (VS -COM) = 0 V
t off Turn-off propagation delay — 160 210 (VS -COM) = 600 V
ns
tr Turn-on rise time — 15 40
tf Turn-off fall time — 15 40

Static Electrical Characteristics


(VCC-COM)=(VB-V S)=15 V. The VIN, VTH, and IIN parameters are referenced to COM. The VO and IO parameters are
referenced respective VS and are applicale to the respective output leads HO. The VCC parameters are referenced to
COM. The VBSUV parameters are referenced to VS.

Symbol Definition Min. Typ. Max. Units Test Conditions


VCCUV+ VCC supply undervoltage positive going threshold 8.0 8.9 9.8
VCCUV- VCC supply undervoltage negative going threshold 7.4 8.2 9.0
V
VBSUV+ VBS supply undervoltage positive going threshold 8.0 8.9 9.8
VBSUV- VBS supply undervoltage negative going threshold 7.4 8.2 9.0
ILK High-side floating well offset supply leakage current — — 50 VB = VS = 600 V
IQBS Quiescent VBS supply current — 80 150 µA
HIN = 0 V or 5 V
IQCC Quiescent VCC supply current — 120 240
V IH Logic “1” input voltage 2.5 — —
V
V IL Logic “0” input voltage — — 0.8
VOH, HO HO high level output voltage, VBIAS - VO — 20 60
mV IO = 2 mA
VOL, HO HO low level output voltage, VO — 10 30
IIN+ Logic “1” input bias current — 10 20 VHIN = 5 V
µA
IIN- Logic “0” input bias current — 0 5 VHIN = 0 V
VO = 0 V, VIN = 0 V
IO+, HO Output high short circuit pulsed current HO — 4 —
PW ≤ 10 µs
A
VO = 15 V, VIN = 15 V
IO-, HO Output low short circuit pulsed current HO — 4 —
PW ≤ 10 µs

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IRS21851SPbF

Functional Block Diagram

VCC
VCCUV
5V DETECT
COM VREG HIGHSIDE CHANNLE1

VB

FILTER,
HIN PULSE LEVEL
LATCH
GEN SHIFT UP DRIVER HO
UV DETECT

VS

Lead Definitions
Symbol Description
VCC Low-side supply voltage
COM Ground
VB High-side drive floating supply
HO High-side driver outputs
VS High voltage floating supply return
HIN Logic inputs for high-side gate driver output (in phase)

Lead Assignments

1 VCC VB 8

2 HIN HO 7
IRS21851S

3 VS 6

4 COM 5

8- Lead SOIC

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IRS21851PbF

50%
50%
IN
t on
t off
tr tf

90%
90%
OUT
10% 10%

Figure 1. Switching Time Waveforms

HIN

HO

Figure 2. Input/Output Timing Diagram

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IRS21851SPbF

300 300
T ur n- O n Propagation Delay (ns )

T ur n- O n Propagation Delay (ns )


250 250 Max

200 200
Typ
Max
150 150
Typ
100 100

50 50

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 3A. Tu rn-On Propag ation Delay vs . Figure 3B. Turn-On Propagation Delay vs.
Temperature Supply Voltage

300 250
T ur n- O ff Propagation Delay (ns )
Turn- Off Propagation Delay (ns)

Max
250 200
Typ
200
Max 150
150
Typ
100
100
50
50

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 4A. Tu rn-Off Propag ation Delay vs . Figure 4B. Turn-Off Propagation Delay vs.
Temperature Supply Voltage

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IRS21851SPbF

45 60
40 Max
50 Max
Tur n- O n Ris e Time ( ns )

Tur n- O n Ris e Time ( ns )


35
30 40
25
30
20
15 Typ 20 Typ
10
10
5
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 5A. Turn-On Rise Time vs. Figure 5B. Turn-On Rise Time vs. Supply
Temperature Voltage

45 60
40 Max
50 Max
Turn- Off Fall Time ( ns)

Turn- Off Fall Time ( ns)

35
30 40
25
30
20
15 Typ 20 Typ
10
10
5
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 6A. Turn-Off Fall Time vs. Figure 6B. Turn-Off Fall Tim e vs. Supply
Temperature Voltage

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IRS21851SPbF

3 3

Logic "1" Input Voltage (V)


Logic "1" Input Voltage (V)

2.5 Max 2.5 Max

2 2

1.5 1.5

1 1

0.5 0.5

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 7A. L ogic "1" Input Voltage vs. Figure 7B. Logic "1" Input Voltage vs. Supply
Temperature Voltage

0.9 0.9
0.8 Min 0.8 Min
Logic "0" Input Voltage (V)
Logic "0" Input Voltage (V)

0.7 0.7
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 8A. L ogic "0" Input Voltage vs. Figure 8B. Logic "0" Input Voltage vs. Supply
Temperature Voltage

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IRS21851SPbF

90 70
80
60 Max

High Lev el O utput (m V)


High Level Output (mV)

70
50
60
50 40
Max
40 30
30
20 Typ
20
Typ 10
10
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 9A. High Level Output vs. Figure 9B. High Level Outpu t vs. Supply
Temperature (Io = 2 mA) Voltage (Io =2 mA)

40 35
35 30 Max
Low Level Output (mV)
Low L evel Output (mV)

30
Max 25
25
20
20
15
15
10 Typ
10 Typ
5 5

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 10A. Low Level Output vs. Figure 10B. Low Level Output vs. Supply
Temperature (Io=2 mA) Vo ltage (Io=2 mA)

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IRS21851SPbF
Offset Supply Leakage Current (µA)

300 60

O ffs e t Supply Leak a ge Cur rent ( µA)


250 50 Max

200 40

150 30

100 20

50 10
Max
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 11A. Offset Su pply Leakage Current Figure 11B. Offse t Supply Leak age Current vs.
vs. Temperature Supply Voltage

180 250
160
V BS Supp ly Current (µA)
V BS Supply Current (µA)

140 Max 200

120
150
100
80 Typ 100 Max
60
40 50 Typ
20
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 12A. VBS Supply Current vs. Figure 12B. V BS Supply Curre nt vs. Supply
Temperature Voltage

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IRS21851SPbF

300 350

300

V CC Supp ly Current (µA)


250
V CC Supply Current (µA)

Max 250
200
200
150 Max
150
100 Typ
100
Typ
50 50

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 13A. VCC Supply Current vs. Figure 13B. V CC Supply Curre nt vs. Supply
Temperature Voltage

6 6
Logic "0" Input Bias C ur r ent ( µA)
Logic "0" Input Bias C urrent (µA)

5 Max 5 Max

4 4

3 3

2 2

1 1

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 14A. Lo gic "0" Input Bias Current vs . Figure 14B. Log ic "0" Input Bias Current vs.
Temperature Supply Voltage

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IRS21851SPbF

6 6

Logic "0" Input Bias Current (µA)


Logic "0" Input Bias Current (µA)

5 Max 5 Max

4 4

3 3

2 2

1 1

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)
Figure 15A. Logic "0" Input Bias Current Figure 15B. Logic "0" Input Bias Current
vs. Temperature vs. Voltage

12 12
V CC UVL O Threshold (+) (V)

VCC UVLO Threshold (-) (V)

11 11

10 10
Max
9 Typ 9 Max

8 Min 8 Typ
Min
7 7

6 6
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

Figure 16. V CC Undervoltage Threshold (+) Figure 17. V CC Undervoltage Threshold (-)
vs. Temperature vs. Temperature

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Not recommended for new designs. No replacement is available

IRS21851SPbF

12 12
V BS UVL O Threshold (+) (V)

VBS UVLO Threshold (-) (V)


11 11

10 10
Max
9 Typ 9 Max

8 Min 8 Typ
Min
7 7

6 6
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

Figure 18. V BS Undervoltage Threshold (+) Figure 19. V BS Undervoltage Threshold (-)
vs. Temperature vs. Temperature

5 6
4.5 Typ
Outp ut Source Current (A)

O utp ut Sour c e Cur r e nt ( A)

4 5
3.5 4
3
2.5 3
2 Typ
2
1.5
1
1
0.5
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 20A. Output Source Current vs. Figure 20B. Outp ut Source Cur rent vs. Supply
Temperature Voltage

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IRS21851SPbF

5 6
Typ
4.5
5

O utp ut Sink Cur r ent ( A)


Output Sink Current (A)

4
3.5 4
3
2.5 3
2 Typ
2
1.5
1
1
0.5
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)

Figure 21A. Output Sink Current vs. Figure 21B. Out put Sink Curre nt vs. Supply
Temperature Voltage

Case outline
INCHES MILLIMETERS
D B DIM
MIN MAX MIN MAX
A 5 FOOTPRINT A .0532 .0688 1.35 1.75
A1 .0040 .0098 0.10 0.25
8X 0.72 [.028]
b .013 .020 0.33 0.51
8 7 6 5 c .0075 .0098 0.19 0.25
6 H D .189 .1968 4.80 5.00
E E .1497 .1574 3.80 4.00
0.25 [.010] A
1 2 3 4 6.46 [.255] e .050 BASIC 1.27 BASIC
e1 .025 BASIC 0.635 BASIC
H .2284 .2440 5.80 6.20
K .0099 .0196 0.25 0.50
L .016 .050 0.40 1.27
6X e 3X 1.27 [.050] 8X 1.78 [.070] y 0° 8° 0° 8°

e1 K x 45°
A
C y

0.10 [.004]
A1 8X L 8X c
8X b
7
0.25 [.010] C A B
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
NOTES: 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
2. CONTROLLING DIMENSION: MILLIMETER 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
A SUBSTRATE.
01-6027
8-Lead SOIC

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Not recommended for new designs. No replacement is available

IRS21851SPbF

Tape & Reel LOAD ED TA PE FEED DIRECTION

8-lead SOIC
B A H

F C

N OT E : CO NTROLLING
D IM ENSION IN M M E

C A R R I E R T A P E D IM E N S I O N F O R 8 S O I C N
M e tr ic Im p e r ia l
Co d e M in M ax M in M ax
A 7 .9 0 8 .1 0 0. 31 1 0 .3 1 8
B 3 .9 0 4 .1 0 0. 15 3 0 .1 6 1
C 1 1 .7 0 1 2 . 30 0 .4 6 0 .4 8 4
D 5 .4 5 5 .5 5 0. 21 4 0 .2 1 8
E 6 .3 0 6 .5 0 0. 24 8 0 .2 5 5
F 5 .1 0 5 .3 0 0. 20 0 0 .2 0 8
G 1 .5 0 n/ a 0. 05 9 n/ a
H 1 .5 0 1 .6 0 0. 05 9 0 .0 6 2

B
C
A
E

R E E L D IM E N S I O N S F O R 8 S O IC N
M e tr ic Im p e r ia l
Co d e M in M ax M in M ax
A 32 9.60 3 3 0 .2 5 1 2 .9 76 1 3 .0 0 1
B 2 0 .9 5 2 1 . 45 0. 82 4 0 .8 4 4
C 1 2 .8 0 1 3 . 20 0. 50 3 0 .5 1 9
D 1 .9 5 2 .4 5 0. 76 7 0 .0 9 6
E 9 8 .0 0 1 0 2 .0 0 3. 85 8 4 .0 1 5
F n /a 1 8 . 40 n /a 0 .7 2 4
G 1 4 .5 0 1 7 . 10 0. 57 0 0 .6 7 3
H 1 2 .4 0 1 4 . 40 0. 48 8 0 .5 6 6

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Not recommended for new designs. No replacement is available

IRS21851SPbF

LEADFREE PART MARKING INFORMATION

Part number S
IRxxxxxx
Date code YWW? IR logo

Pin 1 ?XXXX
Identifier
Lot Code
? MARKING CODE (Prod mode - 4 digit SPN code)
P Lead Free Released
Non-Lead Free
Released
Assembly site code
Per SCOP 200-002

ORDER INFORMATION
8-Lead SOIC order IRS21851SPbF
8-Lead SOIC Tape & Reel IRS21851STRPbF

Rev. Date Page # Description of Change

A 6/10/80 1 “Not Recommended for new design: Please use IRS21850D”

1 ton/toff values should read 160ns not 170ns

The SOIC-8 is MSL2 qualified.


This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 6/10/2008

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