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MAX1762/MAX1791
The MAX1762/MAX1791 PWM step-down controllers ♦ High Operating Frequency (300kHz)
provide high efficiency, excellent transient response,
and high DC output accuracy needed for stepping ♦ No Current-Sense Resistor
down high-voltage batteries to generate low-voltage ♦ Accurate Current Limit
CPU core, I/O, and chipset RAM supplies in notebook
computers and PDAs. ♦ ±1% Total DC Error over Line and During
Maxim’s proprietary Quick-PWM™ pulse-width modula- Continuous Conduction
tor is a free-running constant on-time type with input ♦ Dual Mode Fixed Output
feed-forward. Its high operating frequency (300kHz) 1.8V/2.5V/adj (MAX1762)
allows small external components to be utilized in PC 3.3V/5.0V/adj (MAX1791)
board area-critical applications such as subnotebook
computers and smart phones. PWM operation occurs ♦ 0.5V to 5.5V Output Adjust Range
at heavy loads, and automatic switchover to pulse-skip- ♦ 5V to 20V Input Range
ping operation occurs at lighter loads. The external
high-side p-channel and low-side n-channel MOSFETs ♦ Automatic Light-Load Pulse Skipping Operation
require no bootstrap components. The MAX1762/ ♦ Free-Running On-Demand PWM
MAX1791 are simple, easy to compensate, and do not
have the noise sensitivity of conventional fixed-frequen- ♦ Foldback Mode™ UVLO
cy current-mode PWMs. ♦ PFET/NFET Synchronous Buck
These devices achieve high efficiency at a reduced
♦ 4.65V at 25mA Linear Regulator Output
cost by eliminating the current-sense resistor found in
traditional current-mode PWMs. Efficiency is further ♦ 5µA Shutdown Supply Current
enhanced by their ability to drive synchronous-rectifier
♦ 230µA Quiescent Supply Current
MOSFETs. The MAX1762/MAX1791 come in a 10-pin
µMAX package and offer two fixed voltages (Dual ♦ 10-Pin µMAX Package
Mode™) for each device, 1.8V/2.5V/adj (MAX1762) and
3.3V/5.0V/adj (MAX1791). Ordering Information
________________________Applications PART TEMP RANGE PIN-PACKAGE
Notebooks Handy-Terminals MAX1762EUB -40°C to +85°C 10 µMAX
Subnotebooks PDAs MAX1791EUB -40°C to +85°C 10 µMAX
Digital Cameras Smart Phones
1.8V/2.5V Logic Pin Configuration
and I/O Supplies
TOP VIEW
Typical Operating Circuit
VBATT
(5V TO 20V) VL 1 10 VP
REF 2 9 DH
VL VP MAX1762
FB 3 MAX1791 8 CS
MAX1762 OUT 4 7 DL
MAX1791
SHDN 5 6 GND
REF DH
VOUT
1.8V/3.3V
FB CS µMAX
OUT DL
Quick-PWM, Dual Mode, and Foldback Mode are a trade-
SHDN GND
marks of Maxim Integrated Products, Inc.
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
ABSOLUTE MAXIMUM RATINGS
MAX1762/MAX1791
VP, SHDN to GND ..................................................-0.3V to +22V Continuous Power Dissipation (TA = +70°C)
VP to VL ..................................................................-0.3V to +22V 10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW
OUT, VL to GND .......................................................-0.3V to +6V Operating Temperature Range ...........................-40°C to +85°C
DL, FB, REF to GND ....................................-0.3V to (VL + 0.3V) Junction Temperature ......................................................+150°C
DH to GND....................................................-0.3V to (VP + 0.3V) Storage Temperature Range .............................-65°C to +150°C
CS to GND ....................................................-2.0V to (VP + 0.3V) Lead Temperature (soldering, 10s) .................................+300°C
REF Short Circuit to GND ...........................................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVP = 15V, VL enabled, CVL = 1µF, CREF = 0.1µF, TA = 0 to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 1)
2 _______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
ELECTRICAL CHARACTERISTICS (continued)
MAX1762/MAX1791
(VVP = 15V, VL enabled, CVL = 1µF, CREF = 0.1µF, TA = 0 to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 1)
_______________________________________________________________________________________ 3
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
ELECTRICAL CHARACTERISTICS
MAX1762/MAX1791
(VVP = 15V, VL enabled, CVL = 1µF, CREF = 0.1µF, TA = -40 to +85°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VP Input Voltage Range VVP 5 20 V
VL Input Voltage Range VVL VL (overdriven) 4.75 5.25 V
OUT Output Voltage VVP = 5V to 20V, VVL = 4.75V to 5.25V,
VOUT 1.773 1.827 V
(MAX1762, 1.8V Fixed) FB = GND, continuous conduction mode
OUT Output Voltage VVP = 5V to 20V, VVL = 4.75V to 5.25V,
VOUT 2.463 2.538 V
(MAX1762, 2.5V Fixed) FB = VL, continuous conduction mode
OUT Output Voltage VVP = 5V to 20V, VVL = 4.75V to 5.25V,
VOUT 3.250 3.350 V
(MAX1791, 3.3V Fixed) FB = GND, continuous conduction mode
OUT Output Voltage VVP = 7V to 20V, VVL = 4.75V to 5.25V,
VOUT 4.925 5.075 V
(MAX1791, 5V Fixed) FB = VL, continuous conduction mode
VVP = 5V to 20V, VVL = 4.75V to 5.25V,
OUT Output Voltage (adj Mode) 1.231 1.269 V
FB = OUT, continuous conduction mode
FB Input Bias Current VFB = 1.3V -0.2 0.2 µA
VOUT = 1.25V, VVP = 6V 666 814
On-Time (Note 2) tON ns
VOUT = 5V, VVP = 6V 2550 3110
Minimum Off-Time tOFF (Note 2) 250 550 ns
FB = GND, VVL = 5V, OUT forced above the
VL Quiescent Supply Current 260 µA
regulation point
FB = GND, OUT forced above VVL = float 410
VP Quiescent Supply Current µA
the regulation point VVP = 20V VVL = 5V 200
VL Shutdown Supply Current VVL = 5V, SHDN = GND 15 µA
VP Shutdown Supply Current SHDN = GND, measured at VP, VVL = 0 or 5V 12 µA
VL Output Voltage ILOAD = 0 to 25mA, VVP = 5V to 20V 4.5 4.75 V
Reference Voltage VVL = 4.75V to 5.25V, no load 1.98 2.02 V
Reference Load Regulation IREF = 0 to 50µA 0.01 V
REF Sink Current REF in regulation 10 µA
Output Undervoltage Threshold
With respect to regulation point, no load 60 80 %
(Foldback)
Output Undervoltage Lockout From SHDN signal going high, VOUT < 0.6 x
10 42 ms
Time (Foldback) regulation point
Current-Limit Threshold VILIM -90 -110 mV
4 _______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
ELECTRICAL CHARACTERISTICS (continued)
MAX1762/MAX1791
(VVP = 15V, VL enabled, CVL = 1µF, CREF = 0.1µF, TA = -40 to +85°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VL Undervoltage Lockout Rising edge, hysteresis = 20mV, PWM
4.1 4.4 V
Threshold disabled below this level
SHDN Logic Input High
VIH 1.6 V
Threshold Voltage
SHDN Logic Input Low
VIL 0.6 V
Threshold Voltage
MAX1762 VOUT = 1.8V fixed
50 150 mV
MAX1791 VOUT = 3.3V fixed
Dual Mode Threshold Voltage
MAX1762 VOUT = 2.5V fixed
2.5 4 V
MAX1791 VOUT = 5V fixed
tON
DH
90% 90%
_______________________________________________________________________________________ 5
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
MAX1762/MAX1791
MAX1762/91 toc02
MAX1762/91 toc03
MAX1762/91 toc01
VVP = 5V VVP = 5V
90 90 90
VVP = 7V VVP = 5V
80 80 80
VVP = 7V
70 70 70
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
MAX1762/91 toc06
MAX1762/91 toc05
VVP = 5V
90 VVP = 7V 90 VVP = 5V 90
80 80 80 VVP = 7V
VVP = 18V
70 70 70
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
MAX1762/91 toc08
VVP = 12V
VOUT = 3.3V 0 VOUT = 2.5V
350
VL VOLTAGE ERROR (%)
-0.1
FREQUENCY (kHz)
VOUT = 5.0V
325
-0.2
-0.4
275
VOUT = 1.8V -0.5
LOAD = 1A
250 -0.6
5 8 11 14 17 0 5 10 15 20 25
SUPPLY VOLTAGE (V) VL CURRENT (mA)
6 _______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
Typical Operating Characteristics (continued)
MAX1762/MAX1791
(TA = +25°C, unless otherwise noted.)
MAX1762/91 toc10
MAX1762/91 toc09
5.8
250 5.6
5.4
200 VOUT = 3.3V 5.2
NO LOAD
150 5.0 NO LOAD
4.8
100 4.6
4.4
50
4.2
0 4.0
5 8 11 14 17 5 8 11 14 17
VP (V) VP (V)
VP VOUT VOUT
1V/div AC-COUPLED AC-COUPLED
100mV/div 100mV/div
7V
VOUT ILOAD
AC-COUPLED IL 2A/div
20mV/div 2A/div
VOUT VOUT
2V/div 2V/div
ILOAD
2A/div ILX ILX
1A/div 2A/div
_______________________________________________________________________________________ 7
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
Pin Description
MAX1762/MAX1791
+4.65V Linear Regulator Output. Serves as the supply input for the DL gate driver and supplies up to
1 VL 25mA to external loads. VL can be overdriven using an external 5V supply. Bypass VL to GND with
at least a 1µF ceramic capacitor.
2V Reference Voltage Output. Bypass to GND with 0.1µF ceramic capacitor. REF can deliver up to
2 REF
50µA for external loads.
Feedback Input. Connect to an external resistive divider from OUT to GND in adjustable version.
3 FB Regulates to 1.25V. FB also serves as Dual Mode select pin. Connect FB to GND for a fixed 1.8V
(MAX1762) or 3.3V (MAX1791) output, or to VL for a fixed 2.5V (MAX1762) or 5.0V (MAX1791) output.
Output Voltage Connection. OUT is used for sensing the output voltage to determine the on-time and
4 OUT
also serves as the feedback input in fixed-output modes.
Shutdown Input. Connect to a voltage less than VIL (<0.6V) to shut down the device. Connect to a
5 SHDN
voltage greater than VIH (>1.6V) for normal operation.
6 GND Analog and Power Ground
8 _______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
MAX1762/MAX1791
VVP
C2
C1 1µF 10Ω
10µF VL VP
MAX1762 1µF
MAX1791
REF DH Q1
C3 L1
0.1µF CS 7µH
FB VOUT
OUT DL Q2 C4
220µF
SHDN GND
VVP
C2
C1 1µF
10µF 10Ω
VL VP
1µF
MAX1762
MAX1791
REF DH Q1
C3 L1
0.1µF 7µH
FB CS VOUT
OUT DL Q2 C4 R1
220µF
SHDN GND
R2
Figure 2. Typical Application Circuit for Adjustable Output VOUT > 1.25V
VVP
C2
C1 1µF
10µF 10Ω
VL VP
1µF
MAX1762
MAX1791
REF DH Q1
C3
0.1µF R1
L1
FB CS 7µH VOUT
R2
C4
220µF
OUT DL Q2
SHDN GND
_______________________________________________________________________________________ 9
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
MAX1762/MAX1791
VVP
C2
C1 1µF
10µF 10Ω
VL VP
1µF
MAX1762
MAX1791
REF DH Q1
L1
C3 10µH
0.1µF FB CS VOUT
C4
150µF
OUT DL Q2
RS
SHDN GND
10 ______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
MAX1762/MAX1791
Table 2. Component Manufacturers
MANUFACTURER USA PHONE WEBSITE INFO
USA 847-956-0666
Sumida www.sumida.com
Japan 81-3-3607-5111
10Ω
VP
VP VIN
TOFF 1µF
TON DH DH CIN
ON-TIME Q
COMPUTE OUT TRIG Q1
Q 1-SHOT DRIVER
S
TON Q S
TRIG Q R Q
1-SHOT R
VP
CS
LINEAR
VL REG ILIM
CVL REF VOS
REF -100mV
-30%
ON/OFF OUT
SHDN FEEDBACK VL OUT
CONTROL
MUX FB
(FIGURE 9) DL COUT
UVP DL
VP TIMER Q2
LATCH
DRIVER
GND
2V
REF VREF
MAX1762
MAX1791
OUT
CREF
FB
VP Input and VL Logic Supply off when the device is in shutdown and drops by
An internal linear regulator supplied by VP produces approximately 500mV during a fault condition, such as
the +4.65V supply (VL) that powers the PWM controller, when the output is short circuited to ground, and recov-
logic, reference, and other blocks within the ers when SHDN is cycled or power is reset. If VL is not
MAX1762/MAX1791. This +4.65V low-dropout linear driven externally, then V VP should be at least 5V to
regulator can supply up to 25mA for external loads. ensure operation. If VVP is running from a 5V (±10%)
Bypass VL to GND with at least a 1µF ceramic capaci- supply, V VP should be externally connected to VL.
tor. VVP can range between 5V and 20V. VL is turned
______________________________________________________________________________________ 11
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
Overdriving the VL regulator with an external 5V supply adjustable 0.5µs (max) minimum off-time. Worst-case
MAX1762/MAX1791
also increases the MAX1762/MAX1791s’ efficiency. dropout performance is determined by the minimum
The MAX1762/MAX1791 include an input undervoltage on-time spec. The worst-case duty factor limit is:
lockout (UVLO) circuit that prevents the device from
switching until VL > 4.4V (max). UVLO ensures there is
( )
t ON MIN
=
2.55µs
= 84%
a sufficient drive for the external MOSFETs, prevents
the high-side MOSFET from being turned on for near
( ) ( )
t ON MIN + t OFF MAX 2.55µs+0.5µs
100% duty cycle, and keeps the output in regulation. with VBATT = 6V and VOUT = 5V. Therefore, with IR volt-
age drops in the loop included, the minimum input volt-
Voltage Reference (REF) age to achieve VOUT = 5V is about 6.1V, using the
The 2V reference (REF) is accurate to ±1% over tem- step-down transfer function equation for duty cycle (DC
perature, making REF useful as a precision system ref- = VOUT/VIN). Typical units exhibit better performance.
erence. Bypass REF to GND with a 0.1µF (min) ceramic Note that transient response is somewhat degraded
capacitor. REF can supply up to 50µA for external near dropout, and the circuit may need additional bulk
loads. However, if tight-accuracy specs for either VOUT output capacitance to support fast load changes.
or REF are essential, avoid loading REF. Loading slight-
ly reduces the main output voltage by an amount that Automatic Pulse-Skipping Switchover
tracks the reference-voltage load regulation error. This PWM control algorithm automatically switches over
to pulse-skipping operation at light loads. The
Free-Running Constant On-Time PWM MAX1762/MAX1791 truncates the low-side switch’s on-
Controller with Input Feed-Forward time when the inductor current drops to zero. The load
The PWM control architecture is a quasi-fixed-frequen- current level at which pulse-skipping/PWM crossover
cy constant on-time current-mode type with voltage occurs is equal to 1/2 the peak-to-peak ripple current,
feed-forward. This architecture relies on the output rip- which is a function of the inductor value (Figure 6):
ple voltage to provide the PWM ramp signal; thus, the
output filter capacitor’s ESR acts as a feedback resis- K × VOUT VVP - VOUT
tor. The control algorithm is very simple. The high-side ILOAD(SKIP) =
switch on-time is determined solely by a one-shot 2L VVP
whose period is inversely proportional to input voltage
and directly proportional to output voltage. There is The inductor current is never allowed to go negative. If
another one-shot that sets a minimum amount of off- the output voltage is above its regulation point and the
time (500ns max). The on-time one-shot triggers when inductor current reaches zero, the low-side driver is
all of the following conditions are met: the error com- switched off. Once the output voltage falls below its
parator is low, the low-side switch current is below the regulation point, the high-side driver is switched on.
current-limit threshold, and the minimum off-time one- This causes a dead time in between when the high-
shot has timed out. side and low-side drivers are on, skipping pulses and
resulting in the switching frequency slowing at light
On-Time One-Shot loads, thereby improving efficiency.
The on-time of the one-shot is inversely proportional to
the battery voltage as measured by the VP input, and MOSFET Gate Drivers
directly proportional to the output voltage sensed at The DH and DL drivers are optimized for driving moder-
OUT: ate-size power MOSFETs. This is consistent with the
low duty factor seen in the notebook CPU environment
t ON = K ×
(VOUT + 0.075V) where a large VBATT - VOUT differential exists. The high-
side driver (DH) is rated for 0.6A source/sink capability
VBATT and swings from VP to GND. The low-side driver (DL) is
where K is internally fixed at 3.349µs, and 0.075V is a
factor that accounts for the expected drop across the Table 3. Operating Frequency
synchronous switch. This arrangement maintains a K MIN TYP MAX
switching frequency that is nearly constant as V BATT, DEVICE
(µs) (kHz) (kHz) (kHz)
ILOAD, and VOUT are changed. Table 3 shows the oper-
MAX1762/MAX1791 3.349 268.7 298.5 328
ating frequency range for the MAX1762/MAX1791.
Note that the output voltage adjust range for continu-
ous-conduction operation is restricted by the non-
12 ______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
MAX1762/MAX1791
∆i VBATT - VOUT IPEAK
=
∆t L
IPEAK
ILOAD
INDUCTOR CURRENT
INDUCTOR CURRENT
ILOAD = IPEAK/2
ILIMIT
rated for +0.5A, -0.9A source/sink capability and sense voltage that appears at CS (Figure 8). Keep the
swings from VL to GND. impedance at this mode low to avoid errors at CS.
The internal pulldown transistor that drives DL low is POR and Soft-Start
robust, with a 1Ω typical on-resistance. This helps pre- Power-on reset (POR) occurs when VBATT rises above
vent DL from being pulled up during the fast rise time of approximately 2V, resetting the fault latch and soft-start
the inductor node, due to capacitive coupling from the counter and preparing the PWM for operation. UVLO
drain to the gate of the low-side synchronous-rectifier circuitry inhibits switching until VVP rises above 4.1V,
MOSFET. However, for high-current applications, some whereupon an internal digital soft-start timer begins to
combinations of high-and low-side FETS may cause ramp up the maximum allowed current limit. The ramp
excessive gate-drain coupling, which can lead to poor occurs in five steps: 20%, 40%, 60%, 80%, and 100%;
efficiency, EMI, and shoot-through currents. 100% current is available after approximately 1.7ms.
An adaptive dead-time circuit monitors the DL output
and prevents the high-side FET from turning on until DL Output Undervoltage Protection
is fully turned off. The dead time at the other edge (DH The output UVLO function is similar to foldback current
turning off) is determined by a fixed 35ns (typ) internal limiting but employs a timer rather than a variable cur-
delay. rent limit. The output undervoltage protection is
enabled 20ms after POR or when coming out of shut-
Low-Side Current-Limit Sensing (ILIM) down. If the output is under 70% of the nominal value,
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that uses the on-state resistance
VP
of the low-side MOSFET as a current-sensing element.
If the current-sense signal is below the current-limit
threshold (-100mV from CS to GND), the PWM is not DH
allowed to initiate a new cycle (Figure 7). The actual
peak current is greater than the current-limit threshold 1.0kΩ
by an amount equal to the inductor ripple current. CS VOUT
MAX1762
Therefore, the exact current-limit characteristic and MAX1791
1.0kΩ
maximum load capability are a function of the MOSFET
on-resistance, inductor value, and battery voltage.
DL
If greater current-limit accuracy is desired, CS must be
connected to the junction of the low-side switch source
and a current-sense resistor to GND. The current limit
will be 0.1V/RSENSE, and the accuracy will be ±10%. Figure 8. Using a Resistive Voltage-Divider to Adjust Current-
Limit Sense Voltage to 200mV
A resistive voltage-divider from the inductor’s switching
mode to ground can be used to adjust the current-limit
______________________________________________________________________________________ 13
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
then the PWM is latched off and does not restart until peak amplitude of the output transient (VSAG) is also a
MAX1762/MAX1791
VP power is cycled, or SHDN is toggled low then high. function of the maximum duty factor, which can be cal-
culated from the on-time and minimum off-time:
Design Procedure
V
Begin by establishing the input voltage range and max- (∆ILOAD(MAX) )2 × L K OUT + t OFF(MIN)
imum load current before choosing an inductor and its VVP
associated ripple-current ratio (LIR). The following four VSAG =
V -V
factors dictate the rest of the design: 2 × COUT × VOUT K VP OUT - t OFF(MIN)
VVP
1) Input voltage range. The maximum value (V VP
(MAX) ) must accommodate the maximum AC where minimum off-time = 0.5µs (max).
adapter voltage. The minimum value (VVP(MIN) )
must account for the lowest input voltage after Inductor Selection
drops due to connectors, fuses, and battery selec- The switching frequency (on-time) and operating point
tor switches. If there is a choice at all, lower input (% ripple or LIR) determine the inductor value as fol-
voltages result in better efficiency. lows:
2) Maximum load current. There are two values to
consider. The peak load current (ILOAD(MAX)) deter- VOUT (VVP - VOUT )
L=
mines the instantaneous component stress and fil- VVP × ƒ × LIR × ILOAD(MAX)
tering requirements and thus drives output
capacitor selection, inductor saturation rating, and Example: ILOAD(MAX) = 2A, VVP = 7V, VOUT = 1.6V, f =
the design of the current-limit circuit. The continu- 300kHz, 35% ripple current or LIR = 0.35:
ous load current (ILOAD) determines the thermal
stress and thus drives the selection of input capaci-
1.6V(7V -1.6V)
tors, MOSFETs, and other critical heat-contributing L= = 5.9µH
components. Modern notebook CPUs generally 7 × 300kHz × 0.35 × 2A
exhibit, ILOAD = ILOAD(MAX) x 0.8.
3) Switching frequency. The MAX1762/MAX1791 Find a low-loss inductor having the lowest possible DC
have a nominal switching frequency of 300kHz. resistance that fits in the allotted dimensions. Ferrite
4) Inductor ripple-current ratio (LIR). LIR is the ratio cores are often the best choice. The core must be large
of the peak-to-peak ripple current to the average enough not to saturate at the peak inductor current
inductor current. Size and efficiency trade-offs must (IPEAK):
be considered when setting the inductor ripple-cur- IPEAK = ILOAD(MAX) + [(LIR/2) ✕ ILOAD(MAX)]
rent ratio. Low inductor values cause large ripple
currents, resulting in the smallest size but poor effi-
ciency and high output noise. The minimum practi- Determining Current Limit
cal inductor value is one that causes the circuit to The minimum current-limit threshold must be great
operate at critical conduction (where the inductor enough to support the maximum load current when the
current just touches zero with every cycle). Inductor current limit is at the minimum tolerance value. The val-
values lower than this grant no further size-reduc- ley of the inductor current occurs at ILOAD(MAX) minus
tion benefit. half of the ripple current; therefore:
The MAX1762/MAX1791s’ pulse-skipping algorithm ini- IVALLEY > ILOAD(MAX) - [(LIR/2) ✕ ILOAD(MAX)]
tiates skip mode at the critical conduction point. So, the
inductor operating point also determines the load-cur- where IVALLEY = minimum current-limit threshold volt-
rent value at which switchover occurs. The optimum age divided by the RDS(ON) of Q2. For the MAX1762/
point is usually found between 20% and 50% ripple MAX1791, the minimum current-limit threshold is 90mV.
current. Use the worst-case maximum value for RDS(ON) from
the MOSFET Q2 data sheet, and add some margin for
The inductor ripple current also impacts transient-
the rise in RDS(ON) with temperature. A good general
response performance, especially at low VVP - VOUT
rule is to allow 0.5% additional resistance for each °C of
difference. Low inductor values allow the inductor cur-
temperature rise.
rent to slew faster, replenishing charge removed from
the output filter capacitors by a sudden load step. The
14 ______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
Examining the 2A circuit example with a maximum once enough capacitance is added to meet the over-
MAX1762/MAX1791
RDS(ON) = 52mΩ at +85°C temperature reveals the fol- shoot requirement, undershoot at the rising load edge
lowing: is no longer a problem (see the VSAG equation in the
IVALLEY = 90mV / 52mΩ = 1.73A Design Procedure section).
The amount of overshoot due to stored inductor energy
Checking the corresponding ILOAD(MAX) reveals: can be calculated as:
I 1.73A LIPEAK 2
ILOAD(MAX) = VALLEY = = 2.1A ∆V ≤
1 - 0.5 LIR 1 - 0.5 × 0.35 2CVOUT
A current-sense resistor can be connected from CS to where IPEAK is the peak inductor current.
GND to set the current limit for the device. The
MAX1762/MAX1791 use the sense resistor instead of Stability Considerations
the RDS(ON) of Q2 to limit the current. The maximum Stability is determined by the value of the ESR zero
value of the sense resistor can be calculated with the (fESR) relative to the switching frequency (f). The point
equation: of instability is given by the following equation:
ILIMIT = 90mV / RSENSE ƒ
ƒ ESR ≤
π
Output Capacitor Selection
The output filter capacitor must have low enough effec- where:
tive series resistance (ESR) to meet output ripple and 1
ƒ ESR ≤
load-transient requirements, yet have high enough ESR 2 × π × RESR × COUT
to satisfy stability requirements. In CPU VCORE convert-
ers and other applications where the output is subject For a typical 300kHz application, the ESR zero frequen-
to large load transients, the output capacitor’s size cy must be well below 95kHz, preferably below 50kHz.
depends on how much ESR is needed to prevent the Tantalum, Sanyo POSCAP, and Panasonic SP capaci-
output from dipping too low under a load transient. tors in widespread use at the time of publication have
Ignoring the sag due to finite capacitance: typical ESR zero frequencies of 20kHz. In the design
example used for inductor selection, the ESR needed
VDIP to support a specified ripple voltage is found by the
RESR ≤ equation:
ƒILOAD(MAX)
VRIPPLE(p-p)
where VDIP is the maximum tolerable transient voltage RESR =
drop. In non-CPU applications, the output capacitor’s ƒLIR × ILOAD
size depends on how much ESR is needed to maintain
an acceptable level of output voltage ripple: where LIR is the inductor ripple current ratio, and ILOAD
is the average DC load. Using a LIR = 0.35 and an
VP-P average load current of 2A, the ESR needed to support
RESR ≤ 50mVP-P ripple is 71mΩ.
LIR × ILOAD(MAX)
Do not use high-value ceramic capacitors directly
where VP-P is the peak-to-peak output voltage ripple. across the fast feedback inputs (FB to GND) without
The actual microfarad capacitance value required taking precautions to ensure stability. Large ceramic
relates to the physical size needed to achieve low ESR, capacitors can have a high-ESR zero frequency and
as well as to the chemistry of the capacitor technology. cause erratic, unstable operation. However, it is easy to
Thus, the capacitor is usually selected by ESR and volt- add enough series resistance by placing the capaci-
age rating rather than by capacitance value (this is true tors a couple of inches downstream from the junction of
of tantalum, SP, POS, and other electrolytic-type the inductor and FB pin.
capacitors).
Unstable operation manifests itself in two related but dis-
When using low-capacity filter capacitors such as tinctly different ways: double-pulsing and fast-feedback
ceramics, capacitor size is usually determined by the loop instability. Double pulsing occurs due to noise on
capacity needed to prevent V SAG and V SOAR from the output or because the ESR is so low that there is not
causing problems during load transients. Generally, enough voltage ramp in the output voltage signal. This
______________________________________________________________________________________ 15
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
“fools” the error comparator into triggering a new cycle duty cycle) equal to the switching losses (CV VP 2f).
MAX1762/MAX1791
immediately after the 500ns minimum off-time period has Make sure that the conduction losses at the minimum
expired. Double pulsing is more annoying than harmful, input voltage do not exceed the package thermal limits
resulting in nothing worse than increased output ripple. or violate the overall thermal budget. Conduction losses
However, it can indicate the possible presence of loop plus switching losses at the maximum input voltage
instability, which is caused by insufficient ESR. Loop should not exceed the package ratings or violate the
instability can result in oscillations at the output after line overall thermal budget (see MOSFET Power Dis-
or load perturbations that can cause the output voltage sipation).
to fall below the tolerance limit.
In addition to efficiency considerations, the selection of
The easiest method for checking stability is to apply a the RDS(ON) of the low-side MOSFET must account for
very fast zero-to-max load transient (refer to the the regulator’s required current limit. Choose a MOS-
MAX1762/MAX1791 EV kit manual) and carefully FET that has a low enough resistance over the operat-
observe the output voltage ripple envelope for over- ing temperature range such that the device does not
shoot and ringing. It can help to simultaneously monitor enter current limit during normal operation (see the
the inductor current with an AC current probe. Do not Determining Current Limit section). Conversely, ultra-
allow more than one cycle of ringing after the initial low RDS(ON) devices may set the current limit too high
step-response under- or overshoot. and may result in only incremental improvements in effi-
ciency. Some large n-channel FETs also have substan-
Input Capacitor Selection tial interelectrode capacitance. Verify that the
The input capacitor must meet the ripple-current require- MAX1762/ MAX1791 DL driver can hold the gate off
ment (I RMS ) imposed by the switching currents. when the high side switch turns on. Cross-conduction
Nontantalum chemistries (ceramic or OS-CON™) are pre- problems can occur when the high-side switch turns on
ferred due to their resilience to power-up surge currents: due to coupling through the n-channel’s parasitic drain-
to-gate capacitance.
VOUT (VVP - VOUT )
IRMS = ILOAD × The MAX1762/MAX1791 have adaptive dead-time cir-
VVP cuitry that prevents the high-side and low-side
MOSFETs from conducting at the same time (see MOS-
Power MOSFET Selection FET Gate Drivers). Even with this protection, it is still
DC bias and output power considerations dominate the possible for delays internal to the MOSFET to prevent
selection of the power MOSFETs used with the one MOSFET from turning off while the other is turned
MAX1762/MAX1791. Take care not to exceed the on. The maximum mismatch time that can be tolerated
device’s maximum voltage ratings. In general, both is 60ns. Select devices that have low turn-off times, and
switches are exposed to the supply voltage, so select make sure that NFET(tD(off,max)) - PFET(tD(on,min)) <
MOSFETs with VDS (max) greater than VP (max). Gate 60ns, and PFET(tD(off,max)) - NFET(tD(on,min)) < 60ns.
drives to the n-channel and p-channel MOSFETs are Failure to do so may result in efficiency-killing shoot-
not symmetrical. The n-channel device is driven from through currents.
ground to the logic supply VL, while the p-channel
device is driven from VP to ground. The maximum rat- MOSFET Power Dissipation
ing for VGS for the n-channel device is usually not an Worst-case conduction losses occur at the duty factor
issue; however, VGS (max) for the p-channel must be at extremes. For the high-side MOSFET, the worst-case
least VP (max). Since VGS (max) is usually lower than power dissipation (PD) due to resistance occurs at min-
V DS (max), gate drive constraints often dictate the imum battery voltage:
required p-channel breakdown rating. V
PD(Q1 resistance) = OUT × ILOAD2 × RDS(ON)
For moderate input-to-output differentials, the high-side V
VP(MIN)
MOSFET (Q1) can be sized smaller than the low-side
MOSFET (Q2) without compromising efficiency. The Generally, a small high-side MOSFET is desired to
high-side switch operates at a very low duty cycle reduce switching losses at high input voltage. However,
under these conditions, so most conduction losses the RDS(ON) required to stay within package power-dis-
occur in Q2. For maximum efficiency, choose a high- sipation limits often limits how small the MOSFET can
side MOSFET (Q1) that has conduction losses (I2R x be. Again, the optimum occurs when the switching (AC)
losses equal the conduction (RDS(ON)) losses. High-
OS-CON is a trademark of Sanyo.
16 ______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
side switching losses do not usually become an issue unchanged, this voltage is approximately 0.7V (a diode
MAX1762/MAX1791
until the input is greater than approximately 15V. drop) at both transition edges while both switches are
Switching losses in the high-side MOSFET can become off. In between the edges, the low-side switch con-
an insidious heat problem when maximum battery volt- ducts; the drop is IL ✕ RDS(ON). If a Schottky clamp is
age is applied, due to the squared term in the CV2f connected across the low-side switch, the initial and
switching loss equation. If the high-side MOSFET cho- final voltage drops is reduced, improving efficiency
sen for adequate R DS(ON) at low battery voltages slightly.
becomes extraordinarily hot when subjected to Choose a Schottky diode (D1) having a forward voltage
VVP(MAX), reconsider your choice of high-side MOS- low enough to prevent the Q2 MOSFET body diode
FET. from turning on during the dead time. As a general rule,
Calculating the power dissipation in Q1 due to switch- a diode having a DC current rating equal to 1/3 of the
ing losses is difficult since it must allow for difficult load current is sufficient. This diode is optional and can
quantifying factors that influence the turn-on and turn- be removed if efficiency isn’t critical.
off times. These factors include the internal gate resis- Applications Issues
tance, gate charge, threshold voltage, source induc-
tance, and PC board layout characteristics. The follow- Dropout Performance
ing switching loss calculation provides only a very The output voltage adjust range for continuous-conduc-
rough estimate and is no substitute for breadboard tion operation is restricted by the nonadjustable 500ns
evaluation, preferably including a verification using a (max) minimum off-time one-shot. When working with
thermocouple mounted on Q1: low input voltages, the duty-factor limit must be calcu-
C lated using worst-case values for on- and off-times.
RSS × VVP(MAX)2 × ƒ × ILOAD Manufacturing tolerances and internal propagation
PD (Q1 switching) =
IGATE delays introduce an error to the t ON K-factor. Also,
keep in mind that transient response performance of
where CRSS is the reverse transfer capacitance of Q1, buck regulators operating close to dropout is poor, and
and IGATE is the peak gate-drive source/sink current. bulk output capacitance must often be added.
For the low-side MOSFET, the worst-case power dissi- Dropout design example: VIN = 7V (min), VOUT = 5V, f
pation always occurs at maximum battery voltage: = 300kHz. The required duty cycle is :
VOUT V + VSW 5V + 0.1V
PD(Q2) = 1 - × ILOAD2 × RDS DCREQ = OUT = = 0.74
V VVP - VSW 7V - 0.1V
VP(MAX)
The absolute worst case for MOSFET power dissipation The worst-case on-time is:
occurs under heavy overloads that are greater than
V + 0.075 5V + 0.075
ILOAD(MAX) but are not quite high enough to exceed t ON(MIN) = OUT ×K= ×
the current limit and cause the fault latch to trip. To pro- VVP 7V
tect against this possibility, the circuit must be overde- 3.35µs × 90% = 2.18µs
signed to tolerate:
The maximum IC duty factor based on timing con-
ILOAD = ILIMIT(HIGH) + (LIR / 2 ) ✕ ILOAD(MAX) straints of the MAX1762/MAX1792 is:
______________________________________________________________________________________ 17
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
(Figure 10). Refer to the MAX1791 EV kit manual for a
MAX1762/MAX1791
18 ______________________________________________________________________________________
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
MAX1762/MAX1791
USE AGND PLANE TO: USE PGND PLANE TO:
- BYPASS VCC AND REF - BYPASS VVP
- TERMINATE EXTERNAL FB - CONNECT PGND TO THE TOPSIDE STAR GROUND
DIVIDER (IF USED)
- PIN-STRAP CONTROL
INPUTS AGND
VOUT
L1
PGND
C2
D1
P1
VL N1
VIA TO GROUND
GND
VBATT C1
CONNECT PGND TO AGND
BENEATH THE MAX1762/MAX1791 AT
ONE POINT ONLY AS SHOWN.
NOTE: EXAMPLE SHOWN IS FOR DUAL n-CHANNEL MOSFET.
______________________________________________________________________________________ 19
High-Efficiency, 10-Pin µMAX, Step-Down
Controllers for Notebooks
Package Information
MAX1762/MAX1791
10LUMAX.EPS
e 4X S
10 10 INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A - 0.043 - 1.10
A1 0.002 0.006 0.05 0.15
A2 0.030 0.037 0.75 0.95
D1 0.116 0.120 2.95 3.05
H
D2 0.114 0.118 2.89 3.00
E1 0.116 0.120 2.95 3.05
Ø0.50±0.1 E2 0.114 0.118 2.89 3.00
H 0.187 0.199 4.75 5.05
0.6±0.1
L 0.0157 0.0275 0.40 0.70
L1 0.037 REF 0.940 REF
b 0.007 0.0106 0.177 0.270
1 1 e 0.0197 BSC 0.500 BSC
0.6±0.1
c 0.0035 0.0078 0.090 0.200
BOTTOM VIEW 0.498 REF
TOP VIEW S 0.0196 REF
α 0° 6° 0° 6°
D2 E2
GAGE PLANE
A2 A c
b E1
A1
α L
D1 L1
PROPRIETARY INFORMATION
TITLE:
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
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