A B C D E

1 1

2
Compal Confidential 2

VIWZ1/VIWZ2 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13P

2012-11-10
3 3

LA-9061P
REV:2.A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3 C
Date: Monday, December 17, 2012 Sheet 1 of 63
A B C D E
 A B C D E

U4 HM76@ U4 HM70@ ZZZ

Compal confidential VIWZ1
LA9061
File Name : VIWZ1/VIWZ2 LS9061P PWR/B
PCH-HM76
SA00005FH70
PCH-HM70
SA00005MQ80
DA_PCB
DA80000TU2A
LS9062P USB/B
Page23‐32

1
nVIDIA N13P-GSR VIWZ2 1
nVIDIA N13P-GLR LS9061P PWR/B
Intel LS9062P USB/B
LS9063P ODD/B
Ivy Bridge LS9064P LED/B
VRAM 128*16 PCI-E x16 DDR3 SO-DIMM *2
DDR3*8 Socket-rPGA988B BANK 0, 1, 2, 3 Page12‐13
37.5mm*37.5mm
Dual Channel Up to 8GB
Page35 Page5‐11DDR3 1066MHz(1.5V)
HDMI
DDR3 1333MHz(1.5V)
Connector DDR3 1600MHz(1.5V)
100MHz
Page34 2.7GT/s FDI *8 DMI *4
CRT
2 Connector Intel Audio Codec 2 channel speaker Page41
2

Page33 AZALIA Realtek

LVDS LVDS Panther Point ALC259-VC2
Int. Digital MIC array
Page41
Connector eDP HM70 / HM76 (Combine with webcam)
Page41
Page45 USB 3.0 FCBGA 989 Combo Jack*1 Page43
USB2.0 25mm*25mm USB2.0 *14
USB3.0 *1(Left) Camera Conn.Page33
include USB2.0*1 PCI-E x1 *6
SATA *6 BlueTooth Conn.
Page40
Page14‐22
SPIROM
BIOS Page14
3 LPC BUS Card Reader Page44 3

Realtek
Page42 Reltek
RTL8111F(GLAN) EC RTS5178 for SDR50
SDXC/MMC
RTL8105E-VD(10/100) ENE KB9012
Page37

RJ-45 Page38 USB2.0 *2(Right)

Page 43
Connector Touch Pad Int. KBD
Page43
Page43
PCI-E(WLAN)
Mini PCIE Full size Slot *1
Mini PCIE Half size Slot *1 Thermal Sensor SSD Page36

EMC1403 Page39
WLAN Page36
SATA HDD
4 Page40 4

SATA ODD Page40

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 2 of 63
A B C D E
 A B C D E

SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
+V1.05S_VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+5VALW +1.5V +VCC_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
1 +B +VGA_CORE 1

+3VALW +VCC_GFXCORE_AXG
+1.8VS BOARD ID Table Board ID / SKU ID Table for AD channel
State +0.75VS Vcc 3.3V +/- 5%
Board ID PCB Revision
+1.05VS Ra/Rc/Re 100K +/- 5%
0 1.0 Board ID Porject Phase
Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
1 0.3 Z-series
0 0 0 V 0 V 0 V MP
2 0.2 Z-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
3 0.1 Z-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
4 Z-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
S0
5 Reserved
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
6 Reserved
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
7 Reserved
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PVT
S3 Reserved
O O O X 7 NC 2.500 V 3.300 V 3.300 V MP

S5 S4/AC
O O USB Port Table BOM Structure Table
X X
3 External BTO Item BOM Structure
S5 S4/ Battery only USB 2.0 Port
O X X X USB Port GPU:N13P-GS&GL N13P@
0 USB Port (Left Side) USB3.0 OPTIMUS part OPT@
S5 S4/AC & Battery
EHCI1 UHCI0
X X X X 1 Touch Screen integrate Graphic part UMA@
don't exist USB3.0
2
Address
2 Blue Tooth GPU:N13P-GS&GSR GS@ 2

UHCI1
EC SM Bus1 address EC SM Bus2 address 3 Camera GPU:N13P-GL&GLR GL@
4 GPU:N13P-GS Strap GS1@
Device Device Address
UHCI2
5 GPU:N13P-GL Strap GL1@
Smart Battery 0001 011X b Thermal Sensor EMC1403 1001_101xb
EHCI1
6 GPU:N13P-GSR Strap GSR@
USB Charger 1010 111X b
UHCI3
7 GPU:N13P-GLR Strap GLR@
8 USB Port (Right Side USB-BD) OPTIMUS no support GCLK OPTNOGCLK@
PCH SM Bus address UHCI4
9 USB Port (Right Side USB-BD) OPTIMUS support GCLK OPTGCLK@
Device Address 10 Mini Card(WLAN) Support Green CLK GCLK@
DDR DIMM0 1001 000Xb
EHCI2 UHCI5
11 Card Reader not Support Green CLK NOGCLK@
DDR DIMM2 1001 010Xb 12 Support Green CLK 244 GCLK244@
UHCI6
13 Support Green CLK 304 GCLK304@
NV-GPU SM Bus address Cardreader CR@
Support HP Woofer woofer@
Device Address Gastube Gastube@
Internal thermal sensor 1001 111Xb (0x9E)
EC RESET function RESET@
HDMI HDMI@
BlueTooth BT@
Connector ME@
SMBUS Control Table GPU BOM Structure Table 45 LEVEL 45@
3 3
10/100 LAN 8105@
Thermal BOM Structure N13P-GS N13P-GL N13P-GSR N13P-GLR
WLAN Sensor PCH TP GIGA LAN GIGA@
SOURCE VGA BATT KB9012 SODIMM WWAN OPT@ V V V V
Deep Sleep S3 DS3@
OPTNOGCLK@ V V V V
SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X X N13P@ V V V V
Not Support Deep Sleep S3 NODS3@
+3VALW ISCT AOAC@
GS@ V V
SMB_EC_CK2
SMB_EC_DA2
KB9012 X X X X X X V
+3VS
X GL@ V V
ISCT not support NOAOAC@
+3VALW GS1@ V
Camera CMOS@
SMBCLK
SMBDATA
PCH X X X V
+3VS
V
+3VS
X X V
+3VS
GL1@ V
For Z490 (14") 14@
+3VALW For Z590 (15") 15@
GSR@ V
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X X GLR@ V
Unpop
USB Charger
@
CHG@
SML1CLK
SML1DATA
PCH
+3VALW
V
+3VS
X V
+3VS
X X V
+3VS
X X not USBCharger
Keyboard Back Light
NOCHG@
KBL@
Touch Screen TS@
HM76 by PCH HM76@
HM70 by PCH HM70@
Cardreader RTS5178 RTS5178@
Cardreader RTS5170 RTS5170@
for 14" Touch Screen TS_14@
4
for 15" Touch Screen TS_15@ 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 3 of 63
A B C D E
 5 4 3 2 1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails (N13x GPIO) Performance Mode P0 TDP at Tj = 102 C* (GDDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 OUT - GPU VID4 Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

D D
GPIO1 OUT - GPU VID3 N13P-GL
64bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
1GB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) GDDR3

GPIO3 OUT H Panel Power Enable

Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO4 OUT H Panel Back-Light On/Off (PWM)
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG/PCI_DEVID[5] PEX_PLL_EN_TERM
GPIO5 OUT - GPU VID1 ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO6 OUT - GPU VID2
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO7 OUT N/A STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO8 I/O - Thermal Catastrophic Over Temperature
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO9 OUT - Thermal Alert STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO10 OUT - Memory VREF Control

GPIO11 OUT - GPU VID0

C C

GPIO12 IN AC Power Detect Input (10K pull low)

GPIO13 OUT - GPU VID5

GPIO14 OUT N/A

GPIO15 IN Hot plug detect for IFP link C

GPIO16 OUT N/A

GPIO17 IN N/A

GPIO18 IN Hot Plug Detect for IFPE

GPIO19 IN N/A

B
+3VS_VGA B

+VGA_CORE

tNVVDD >0
+1.5VS_VGA
tFBVDDQ >0

+1.05VS_VGA
tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

A A

Tpower-off <10ms

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
1.all GPU power rails should be turned off within 10ms
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 4 of 63
5 4 3 2 1
 5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
+V1.05S_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
D
24.9_0402_1% - typical impedance = 14.5 mohms D

JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
[16] DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
[16] DMI_CRX_PTX_N1 B25 DMI_RX#[1]
[16] DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] [23]
[16] DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N15
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14
PEG_RX#[1] M35
[16] DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N13
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
[16] DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 PEG Static Lane Reversal - CFG2 is for the 16x
[16] DMI_CRX_PTX_P2 A24 J32 PCIE_CRX_GTX_N11

DMI
DMI_RX[2] PEG_RX#[4] PCIE_CRX_GTX_N10
[16] DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
PEG_RX#[6] PCIE_CRX_GTX_N8
[16] DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N7
[16] DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PCIE_CRX_GTX_N6
[16] DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PCIE_CRX_GTX_N5 0:Lane Reversed
[16]

[16]
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 G22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
[16] DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
F20 B33 PCIE_CRX_GTX_N1
[16] DMI_CTX_PRX_P2

PCI EXPRESS* - GRAPHICS

DMI_TX[2] PEG_RX#[14] PCIE_CRX_GTX_N0
[16] DMI_CTX_PRX_P3 C21 DMI_TX[3] PEG_RX#[15] C32
PCIE_CRX_GTX_P[0..15] [23]
J33 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
PEG_RX[1] L35
K34 PCIE_CRX_GTX_P13
PEG_RX[2] PCIE_CRX_GTX_P12
[16] FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
C H19 H32 PCIE_CRX_GTX_P11 C
[16] FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PCIE_CRX_GTX_P10
[16] FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PCIE_CRX_GTX_P9
[16] FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P8
[16] FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PCIE_CRX_GTX_P7
[16] FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PCIE_CRX_GTX_P6
[16] FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PCIE_CRX_GTX_P5
[16] FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PCIE_CRX_GTX_P4
PEG_RX[11] PCIE_CRX_GTX_P3
PEG_RX[12] D34
A22 E31 PCIE_CRX_GTX_P2
[16] FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PCIE_CRX_GTX_P1
[16] FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
eDP_COMPIO and ICOMPO signals E20 B32 PCIE_CRX_GTX_P0
[16] FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
[16] FDI_CTX_PRX_P3 G18 PCIE_CTX_GRX_N[0..15] [23]
should be shorted near balls B20
FDI0_TX[3]
M29 PCIE_CTX_GRX_C_N15 C1 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N15
[16] FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
and routed with typical C19 M32 PCIE_CTX_GRX_C_N14 C2 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N14
[16] FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PCIE_CTX_GRX_C_N13 C3 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N13
impedance <25 mohms [16] FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PCIE_CTX_GRX_C_N12 C4 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N12
[16] FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PCIE_CTX_GRX_C_N11 C5 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N11
PEG_TX#[4] PCIE_CTX_GRX_C_N10 C6 N13P@1 0.22U_0402_6.3V K PCIE_CTX_GRX_N10
[16] FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 2
+V1.05S_VCCP J17 K28 PCIE_CTX_GRX_C_N9 C7 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N9
[16] FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6]
J30 PCIE_CTX_GRX_C_N8 C8 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N8
PEG_TX#[7] PCIE_CTX_GRX_C_N7 C9 OPT@ 1 0.22U_0402_6.3V K PCIE_CTX_GRX_N7
[16] FDI_INT H20 FDI_INT PEG_TX#[8] J28 2
H29 PCIE_CTX_GRX_C_N6 C10 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N6
PEG_TX#[9]
1

[16] FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N5

R7 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_C_N4 C12 OPT@ 1 0.22U_0402_6.3V K PCIE_CTX_GRX_N4
[16] FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 2
24.9_0402_1% F27 PCIE_CTX_GRX_C_N3 C13 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N3
PEG_TX#[12] PCIE_CTX_GRX_C_N2 C14 OPT@ 1 0.22U_0402_6.3V K PCIE_CTX_GRX_N2
PEG_TX#[13] D28 2
F26 PCIE_CTX_GRX_C_N1 C15 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_N1
2

PEG_TX#[14] PCIE_CTX_GRX_C_N0 C16 OPT@ 1 0.22U_0402_6.3V K PCIE_CTX_GRX_N0

PEG_TX#[15] E25 2
EDP_COMP A18
B eDP_COMPIO PCIE_CTX_GRX_P[0..15] [23] B
A17 M28 PCIE_CTX_GRX_C_P15 C17 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P15
eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_C_P14 C18 N13P@1 0.22U_0402_6.3V K PCIE_CTX_GRX_P14
B16 eDP_HPD# PEG_TX[1] M33 2
M30 PCIE_CTX_GRX_C_P13 C19 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P13
PEG_TX[2] PCIE_CTX_GRX_C_P12 C20 N13P@1 0.22U_0402_6.3V K PCIE_CTX_GRX_P12
PEG_TX[3] L31 2
C15 L28 PCIE_CTX_GRX_C_P11 C21 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P11
eDP_AUX PEG_TX[4] PCIE_CTX_GRX_C_P10 C22 N13P@1 0.22U_0402_6.3V K PCIE_CTX_GRX_P10
D15 eDP_AUX# PEG_TX[5] K30 2
K27 PCIE_CTX_GRX_C_P9 C23 N13P@1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P9
eDP

PEG_TX[6] PCIE_CTX_GRX_C_P8 C24 N13P@1 0.22U_0402_6.3V K PCIE_CTX_GRX_P8

PEG_TX[7] J29 2
C17 J27 PCIE_CTX_GRX_C_P7 C25 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P7
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_C_P6 C26 OPT@ 1 0.22U_0402_6.3V K PCIE_CTX_GRX_P6
F16 eDP_TX[1] PEG_TX[9] H28 2
C16 G28 PCIE_CTX_GRX_C_P5 C27 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P5
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_C_P4 C28 OPT@ 1 0.22U_0402_6.3V K PCIE_CTX_GRX_P4
G15 eDP_TX[3] PEG_TX[11] E28 2
F28 PCIE_CTX_GRX_C_P3 C29 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P3
PEG_TX[12] PCIE_CTX_GRX_C_P2 C30 OPT@ 1 0.22U_0402_6.3V K PCIE_CTX_GRX_P2
C18 eDP_TX#[0] PEG_TX[13] D27 2
E16 E26 PCIE_CTX_GRX_C_P1 C31 OPT@ 1 2 0.22U_0402_6.3V K PCIE_CTX_GRX_P1
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_C_P0 C32 OPT@ 1 0.22U_0402_6.3V K PCIE_CTX_GRX_P0
D16 eDP_TX#[2] PEG_TX[15] D25 2
F15 eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

A A

Security Classification Compal Secret Data

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 5 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1B
R10;R11 put on U4 side
D D
R02
A28 CLK_CPU_DMI_R R10 1 @ 2 0_0402_5%
BCLK CLK_CPU_DMI [15]
C26 A27 CLK_CPU_DMI#_R R11 1 @ 2 0_0402_5%

MISC

CLOCKS
[19] H_SNB_IVB# PROC_SELECT# BCLK# R02 CLK_CPU_DMI# [15]

AN34 SKTOCC#
A16 R12 2 1 1K_0402_5%
+V1.05S_VCCP DPLL_REF_CLK R13
DPLL_REF_CLK# A15 2 1 1K_0402_5% +V1.05S_VCCP

T48 H_CATERR# AL33 CATERR#

R9 1
62_0402_5%

THERMAL
AN33 R8 H_DRAMRST#
[19,42] H_PECI PECI SM_DRAMRST# H_DRAMRST# [7]
2

R15

DDR3
MISC
56_0402_5%
[42,48] H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
PROCHOT# SM_RCOMP[0] SM_RCOMP1
SM_RCOMP[1] A5 2 R17 1 25.5_0402_1%
A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]

[19] H_THRMTRIP# AN32 THERMTRIP# DDR3 Compensation Signals

+V1.05S_VCCP
AP29 XDP_PRDY# T97
PRDY# XDP_PREQ# T98
PREQ# AP27
XDP_TMS R20 2 1 51_0402_5%
AR26 XDP_TCK XDP_TDI R21 2 1 51_0402_5% PU/PD for JTAG signals
C R02 TCK XDP_TMS XDP_TDO R23 @ C
AR27 2 1 51_0402_5%

PWR MANAGEMENT
TMS

JTAG & BPM

R22 1 @ 2 0_0402_5% H_PM_SYNC_R AM34 AP30 XDP_TRST#
[16] H_PM_SYNC PM_SYNC TRST# XDP_TCK R24 2 1 51_0402_5%
AR28 XDP_TDI XDP_TRST# R25 2 1 51_0402_5%
TDI XDP_TDO
TDO AP26
[19] H_CPUPWRGD R26 1 @ 2 0_0402_5% H_CPUPWRGD_R AP33 UNCOREPWRGOOD
2

R29
DBR# AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS
1 R27 1 2 PM_DRAM_PWRGD_R V8
@ C549 130_0402_5% SM_DRAMPWROK
10K_0402_5%
AT28 XDP_BPM#0 T49
100P_0402_50V8J BPM#[0] XDP_BPM#1 T90
AR29
1

2 BPM#[1] XDP_BPM#2 T91

EMI Reserve BUF_CPU_RST# AR33
BPM#[2] AR30
AT30 XDP_BPM#3 T92
RESET# BPM#[3] XDP_BPM#4 T93
BPM#[4] AP32
AR31 XDP_BPM#5 T94
BPM#[5] XDP_BPM#6 T95
BPM#[6] AT31
AR32 XDP_BPM#7 T96
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
+3VALW

C33
1 Buffered reset to CPU
0.1U_0402_16V7K
+1.5V_CPU_VDDQ
2 +3VS
B B
1

[16] SYS_PWROK 1 @ 2
R880 0_0402_5% R30
U1 200_0402_5% +V1.05S_VCCP
1
C34
5

0.1U_0402_16V7K
2

1 R161 2 1
P

+3VS B 2
10K_0402_5% 4 PM_SYS_PWRGD_BUF R32
O 75_0402_5%
[16] PM_DRAM_PWRGD 2 A
G

5
74AHC1G09GW_TSSOP5 R34 U2
3

43_0402_1% 1 3V

P
R33 BUF_CPU_RST# BUFO_CPU_RST# NC
1 2 4 Y
39_0402_5% 2 PCH_PLTRST# PCH_PLTRST# [18]
A
1

G
@ SN74LVC1G07DCKR_SC70-5
1 2

3
D R35 @
[10] RUN_ON_CPU1.5VS3# 2 Q1 @ 0_0402_5%
G 2N7002K_SOT23-3
2

S
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 6 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D
[13] DDR_B_D[0..63]

[12] DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 [12] SB_CLK[0] AE2 M_CLK_DDR2 [13]
SA_CLK#[0] AA6 M_CLK_DDR#0 [12] SB_CLK#[0] AD2 M_CLK_DDR#2 [13]
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA [12] SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB [13]
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDR_B_D4 SB_DQ[3]
D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1 [12] A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3 [13]
D DDR_A_D5 DDR_B_D5 D
C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 [12] A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR#3 [13]
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA [12] SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB [13]
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
DDR_A_D16 SA_DQ[15] DDR_B_D16 SB_DQ[15]
K4 SA_DQ[16] RSVD_TP[4] AB3 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
K1 SA_DQ[18] RSVD_TP[6] W10 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D19 J1 DDR_B_D19 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDR_B_D22 SB_DQ[21]
J2 SA_DQ[22] SA_CS#[0] AK3 DDR_CS0_DIMMA# [12] K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# [13]
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# [12] SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# [13]
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 SA_DQ[24] RSVD_TP[7] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N10 SA_DQ[25] RSVD_TP[8] AH1 N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D26 N8 DDR_B_D26 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDR_B_D29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 [12] N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 [13]
DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4

DDR SYSTEM MEMORY B

SA_DQ[30] SA_ODT[1] M_ODT1 [12] SB_DQ[30] SB_ODT[1] M_ODT3 [13]

DDR SYSTEM MEMORY A

DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
AG6 SA_DQ[32] RSVD_TP[10] AH2 AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] [12] AN3 SB_DQ[36] DDR_B_DQS#[0..7] [13]
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D37 DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D41 SA_DQ[40] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AK8 SA_DQ[41] SA_DQS#[4] AL6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AK9 SA_DQ[43] SA_DQS#[6] AR12 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] [12] SB_DQ[48] DDR_B_DQS[0..7] [13]
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D53 AR8 AN6 DDR_B_DQS4
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 SA_DQ[60] DDR_A_MA[0..15] [12] AT12 SB_DQ[60] DDR_B_MA[0..15] [13]
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[3] W7 SB_MA[3] T6
V3 DDR_A_MA4 T2 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] V2 SB_MA[5] T4
W3 DDR_A_MA6 T3 DDR_B_MA6
SA_MA[6] DDR_A_MA7 SB_MA[6] DDR_B_MA7
[12] DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 [13] DDR_B_BS0 AA9 SB_BS[0] SB_MA[7] R2
B DDR_A_MA8 DDR_B_MA8 B
[12] DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 [13] DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
[12] DDR_A_BS2 SA_BS[2] SA_MA[9] [13] DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
[12] DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 [13] DDR_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
AD9 V5 DDR_A_MA14 AB8 R5 DDR_B_MA14
[12] DDR_A_RAS# SA_RAS# SA_MA[14] [13] DDR_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 DDR_A_MA15 AB9 R4 DDR_B_MA15
[12] DDR_A_WE# SA_WE# SA_MA[15] [13] DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

+1.5V

@ R36
1

0_0402_5%
1 2 R37
1K_0402_5%

R38
2

1K_0402_5%
S

[6] H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# [12,13]

2

Q2
R39 LBSS138LT1G_SOT-23-3
G
2

4.99K_0402_1%
1

A A
NODS3@
[15] DRAMRST_CNTRL_PCH 1 2
R40 0_0402_5%
R02 1 @ 2 DRAMRST_CNTRL_R
[10] DRAMRST_CNTRL
R92 0_0402_5%
1 2
[42] DRAMRST_CNTRL_EC
R65 DS3@ 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
For Deep S3 Eiffel used 0.01u
C35 SCHEMATICS,MB A9061
0.047U 16V K X7R 0402 Module design used 0.047u
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 7 of 63

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R41
1K_0402_1%

2
D D

Interl request AH26 short GND

JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

AH27 PAD T13 CFG2
AK28
VCC_DIE_SENSE
AH26 R02 R93 1 @ 2 0_0402_5%
socket pin map definition
CFG[0] VSS_DIE_SENSE
AK29 CFG[1]
CFG2 AL26 0:Lane Reversed
CFG4
AL27
AK26
CFG[2]
CFG[3]
CFG[4] RSVD28 L7
*
CFG5 AL29 AG7 CFG4
CFG6 CFG[5] RSVD29
AL30 CFG[6] RSVD30 AE7

1
CFG7 AM31 AK2
CFG[7] RSVD31
AM32 CFG[8]
AM30 W8 @ R42

CFG
CFG[9] RSVD32 1K_0402_1%
AM28 CFG[10]
+VCC_GFXCORE_AXG AM26

2
CFG[11]
AN28 CFG[12] RSVD33 AT26
+VCC_CORE AN31 AM33
CFG[13] RSVD34
AN26 CFG[14] RSVD35 AJ27
2

AM27 CFG[15]
R252 AK31 CFG[16]
49.9_0402_1% AN29 CFG[17]
2

Display Port Presence Strap

R253
1

49.9_0402_1% RSVD37 T8
C C
J16 1 : Disabled; No Physical Display Port
VCC_AXG_VAL_SENSE AJ31 RSVD38
H16 CFG4 * attached to Embedded Display Port
1

R82 1 @ VAXG_VAL_SENSE RSVD39

2 100_0402_1% VSS_AXG_VAL_SENSE AH31 VSSAXG_VAL_SENSE RSVD40 G16
VCC_VAL_SENSE AJ33
R88 1 @ VCC_VAL_SENSE
2 100_0402_1% VSS_VAL_SENSE AH33 VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Need PWR add new circuit on 1.05V(refer CRB) AJ26 AR35
RSVD5 RSVD_NCTF1
AT34

RESERVED
RSVD_NCTF2
RSVD_NCTF3 AT33
VSS_AXG_VAL_SENSE AP35 CFG6
RSVD_NCTF4
RSVD_NCTF5 AR34
CFG5
VSS_VAL_SENSE

1
F25 @ @
RSVD8 R43 R44
F24 RSVD9
2

F23 1K_0402_1% 1K_0402_1%

R255 R257 RSVD10
D24 RSVD11 RSVD_NCTF6 B34
49.9_0402_1% 49.9_0402_1% G25 A33

2
RSVD12 RSVD_NCTF7
G24 RSVD13 RSVD_NCTF8 A34
E23 B35
1

RSVD14 RSVD_NCTF9
D23 RSVD15 RSVD_NCTF10 C35
C30 RSVD16
A31 RSVD17
B30 RSVD18
B29 RSVD19
D30 RSVD20 RSVD51 AJ32
INTEL 12/28 recommand B31 RSVD21 RSVD52 AK32 PCIE Port Bifurcation Straps
A30
to add RC120, RC121, RC122, RC123 C29
RSVD22
RSVD23
Please place as close as JCPU1 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
J20 RSVD24
BCLK_ITP
BCLK_ITP#
AN35
AM35 CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
B18 RSVD25 disabled
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2
2 enabled)
RSVD27 RSVD_NCTF11
RSVD_NCTF12 AT1 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
RSVD_NCTF13 AR1

B1 CFG7
KEY

1
@ R45
1K_0402_1%

TYCO_2013620-2_IVY BRIDGE

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 8 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER +V1.05S_VCCP

+VCC_CORE

QC=94A 8.5A
DC=53A
AG35 VCC1
AG34 VCC2 VCCIO1 AH13
AG33 VCC3 VCCIO2 AH10
AG32 VCC4 VCCIO3 AG10
D D
AG31 VCC5 VCCIO4 AC10
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 VCC12 VCCIO11 J12
AF33 VCC13 VCCIO12 J11
AF32 VCC14 VCCIO13 H14
AF31 VCC15 VCCIO14 H12
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12

PEG AND DDR

VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
C C
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 +V1.05S_VCCP
VCC45
AA30 VCC46
AA29 VCC47
AA28 VCC48
AA27 VCC49
AA26 VCC50
Y35 1
CORE SUPPLY

VCC51
Y34 VCC52
Y33 C99
VCC53 0.1U_0402_16V7K
Y32 VCC54

1
2
Y31 VCC55
Y30 R46
VCC56
Y29 VCC57 75_0402_5%
Y28 VCC58
Y27 VR_SVID_CLK series-resistors close to VR

2
VCC59
Y26 VCC60
V35 VCC61
V34 AJ29 H_CPU_SVIDALRT# 1 R47 2 43_0402_5%
SVID

VCC62 VIDALERT# R02 R48 1 VR_SVID_ALRT# [55]

V33 AJ30 H_CPU_SVIDCLK @ 2 0_0402_5%
VCC63 VIDSCLK R02 R49 1 VR_SVID_CLK [55]
V32 AJ28 H_CPU_SVIDDAT @ 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT [55]
V31 VCC65
V30 VCC66
V29 R50 2 1 130_0402_5% +V1.05S_VCCP 0.1uF on power side
VCC67
V28 VCC68
B B
V27 VCC69
V26 VCC70
U35 VCC71
U34 VCC72
U33 VCC73
U32 VCC74
U31 VCC75
U30 VCC76
U29
U28
VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
VCC78
U27 VCC79
U26 VCC80
R35 +VCC_CORE
VCC81
R34 VCC82
R33 VCC83

1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51
100_0402_1%
R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils
SENSE LINES

2
VCC88 R02 R52 1
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R @ 2 0_0402_5% VCCSENSE [55]
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R R02 R53 1 @ 2 0_0402_5% VSSSENSE [55]
P35 VCC91
P34 VCC92

1
P33 VCC93
P32 VCC94 VCCIO_SENSE B10 VCCIO_SENSE [53] 1 R66 @2 R54
P31 A10 VSSIO_SENSE_L 1 R74 2VSSIO_SENSE 100_0402_1% 100_0402_1%
VCC95 VSS_SENSE_VCCIO 10_0402_1%
P30 VCC96
P29 @

2
VCC97
P28 VCC98 R74 & R79 put together +V1.05S_VCCP
P27 VCC99
P26 R79
A VCC100 A
VSSIO_SENSE_L [53] 2 1
10_0402_1%

VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 9 of 63
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ
@ J1 Q6

1
D LBSS138LT1G_SOT-23-3
1 2
1 2 DRAMRST_CNTRL

1
R02 PAD-OPEN 4x4m @ @ +VREF_DQ_DIMMA G DRAMRST_CNTRL [7]
R668 1 @ +VREF_DQ_DIMMB
2 0_0402_5% R55 C92 R670@ S

3
[46,51,54] SUSP 220_0402_5% 0.1U_0402_16V7K 1 2 0_0402_5%~D +V_DDR_REFA_R
2 +V_DDR_REFB_R
1 2 0_0402_5%~D
U3 R671@

1 2
AP4800BGM-HF_SO-8

1
+3VALW +VSB 8 1 AP4800 @ D

1
Q3 RUN_ON_CPU1.5VS3# D
7 2 2
D 6 3
Id=9.6A 2N7002K_SOT23-3 G DRAMRST_CNTRL 2 R353 R64 D

1
5 S G 1K_0402_1% 1K_0402_1%

3
1
R56 S @ @

2
@ R667 82K_0402_5% Q9

4
100K_0402_5% LBSS138LT1G_SOT-23-3

2
2
R885 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3 1 2

1
15K_0402_1% 1

1
D D +VCC_GFXCORE_AXG
1 2 2 Q7 @ 2 Q4 R57 C97
[42,46] CPU1.5V_S3_GATE
0_0402_5% @ R58 G 2N7002K_SOT23-3 G 2N7002K_SOT23-3 330K_0402_5% 0.047U_0603_25V7M

1
S S @ 2

2
1 2 R616
[25,42,46,51,53,54] SUSP#
0_0402_5% @ R59 10_0402_1%

2
RUN_ON_CPU1.5VS3# [6]
POWER VCC_AXG_SENSE [55]
RUN_ON_CPU1.5VS3

1
Check
+VCC_GFXCORE_AXG JCPU1G R89 @
Q5-orignal part
100_0402_1% AP2302GN-HF_SOT23-3
AT24 AK35 SB523020210 +1.5V

SENSE
LINES

2
VAXG1 VAXG_SENSE +1.5V_CPU_VDDQ
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE [55]
AT21 VAXG3

2
G
AT20 PMV45EN_SOT23-3
VAXG4 R626 Q5 @
AT18 VAXG5

1
AT17 VAXG6 10_0402_1% 3 1

D
AR24 VAXG7
AR23 +V_SM_VREF should R67 R62 @

2
VAXG8 1K_0402_1% 1K_0402_1%
AR21 VAXG9
AR20 have 20 mil trace width

2
VAXG10 +V_SM_VREF_CNT
C
AR18 VAXG11 SM_VREF AL1 1 R61 @2 +V_SM_VREF
C
AR17 0_0402_5%
VAXG12

1
AP24

VREF
VAXG13 1
AP23 VAXG14
AP21 C98 R78 R63 @
VAXG15 +V_DDR_REFA_R 0.1U_0402_16V7K 1K_0402_1% 1K_0402_1%
AP20 VAXG16 SA_DIMM_VREFDQ B4
AP18 D1 +V_DDR_REFB_R 2

2
VAXG17 SB_DIMM_VREFDQ
AP17 VAXG18
AN24 VAXG19
AN23 VAXG20
AN21 VAXG21
AN20 +1.5V_CPU_VDDQ
VAXG22
AN18

DDR3 -1.5V RAILS

VAXG23 +1.5V +1.5V_CPU_VDDQ
AN17 VAXG24
AM24 AF7

GRAPHICS
VAXG25 VDDQ1 C396 @
AM23 VAXG26 VDDQ2 AF4
AM21 AF1 1 1 0.1U_0402_16V7K
VAXG27 VDDQ3
AM20 VAXG28 VDDQ4 AC7 1 1 1 1 1 1 1 2

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C118

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C121

10U_0603_6.3V6M
C122
AM18 AC4 + C123 + C1324
VAXG29 VDDQ5

330U_2.5V_M
@ C129 @

220U_B2_2.5VM_R35
AM17 VAXG30 VDDQ6 AC1
AL24 Y7 0.1U_0402_16V7K
VAXG31 VDDQ7 2 2 2 2 2 2 2 2
AL23 VAXG32 VDDQ8 Y4 1 2
AL21 VAXG33 VDDQ9 Y1
AL20 U7 C96
VAXG34 VDDQ10 0.1U_0402_16V7K
AL18 VAXG35 VDDQ11 U4
AL17 VAXG36 VDDQ12 U1 1 2
AK24 VAXG37 VDDQ13 P7
AK23 P4 C95
VAXG38 VDDQ14 0.1U_0402_16V7K
AK21 VAXG39 VDDQ15 P1
AK20 VAXG40 1 2
AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
AJ23 VAXG44
AJ21 VAXG45
B AJ20 +VCCSA B
VAXG46
AJ18 VAXG47
AJ17 VAXG48 VCCSA1 M27 +VCCSA
SA RAIL

AH24 VAXG49 VCCSA2 M26 1 1 1 1 1

10U_0603_6.3V6M
C124

10U_0603_6.3V6M
C125

10U_0603_6.3V6M
C126

10U_0603_6.3V6M
C127
AH23 VAXG50 VCCSA3 L26
AH21 J26 + C128 @
VAXG51 VCCSA4 330U_D2_2.5VY_R9M
AH20 VAXG52 VCCSA5 J25
AH18 J24 2 2 2 2
VAXG53 VCCSA6 2
AH17 VAXG54 VCCSA7 H26
VCCSA8 H25
1.8V RAIL

H23 +3VS
+1.8VS R20 80mil VCCSA_SENSE +VCCSA_SENSE [52]
@ J14 1.5A 1 @ 2

2
1 1 2 +1.8VS_VCCPLL B6 R68 0_0402_5%
2 VCCPLL1 R75
A6 C22
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 [52]

22U_0805_6.3V6M
C154

22U_0805_6.3V6M
C345

10U_0603_6.3V6M
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

1 1 1 1 1 A2 C24 10K_0402_5%
JUMP_43X79 VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 [52]

1
@ @
2 2 2 2 2 H_VCCP_SEL R02 R77 1 @
VCCIO_SEL A19 2 0_0402_5%

TYCO_2013620-2_IVY BRIDGE

A A

Security Classification Compal Secret Data

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 10 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I

AT35 VSS1 VSS81 AJ22

AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24
AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
D AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15 D
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6
AR16 VSS17 VSS98 AH25 P3 VSS175 VSS248 E5
AR13 VSS18 VSS99 AH22 P2 VSS176 VSS249 E4
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR7 VSS20 VSS101 AH16 N34 VSS178 VSS251 E2
AR4 VSS21 VSS102 AH7 N33 VSS179 VSS252 E1
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP31 VSS24 VSS105 AG8 N30 VSS182 VSS255 D29
AP28 VSS25 VSS106 AG4 N29 VSS183 VSS256 D26
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34
AP16 VSS29 VSS110 AF2 M34 VSS187 VSS260 C31
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
AP10 VSS31 VSS112 AE34 L30 VSS189 VSS262 C27
AP7 VSS32 VSS113 AE33 L27 VSS190 VSS263 C25
AP4 VSS33 VSS114 AE32 L9 VSS191 VSS264 C23
C
AP1 VSS34 VSS115 AE31 L8 VSS192 VSS265 C10 C
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9
AN7 VSS43 VSS124 AC8 K29 VSS201 VSS274 B8
AN4 VSS44 VSS125 AC6 K26 VSS202 VSS275 B7
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35
AM16 VSS49 VSS130 AB34 H27 VSS207 VSS280 A32
AM13 VSS50 VSS131 AB33 H24 VSS208 VSS281 A29
AM10 VSS51 VSS132 AB32 H21 VSS209 VSS282 A26
AM7 VSS52 VSS133 AB31 H18 VSS210 VSS283 A23
AM4 VSS53 VSS134 AB30 H15 VSS211 VSS284 A20
AM3 VSS54 VSS135 AB29 H13 VSS212 VSS285 A3
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214
AL34 VSS57 VSS138 AB26 H8 VSS215
AL31 VSS58 VSS139 Y9 H7 VSS216
B AL28 VSS59 VSS140 Y8 H6 VSS217
B
AL25 VSS60 VSS141 Y6 H5 VSS218
AL22 VSS61 VSS142 Y5 H4 VSS219
AL19 VSS62 VSS143 Y3 H3 VSS220
AL16 VSS63 VSS144 Y2 H2 VSS221
AL13 VSS64 VSS145 W35 H1 VSS222
AL10 VSS65 VSS146 W34 G35 VSS223
AL7 VSS66 VSS147 W33 G32 VSS224
AL4 VSS67 VSS148 W32 G29 VSS225
AL2 VSS68 VSS149 W31 G26 VSS226
AK33 VSS69 VSS150 W30 G23 VSS227
AK30 VSS70 VSS151 W29 G20 VSS228
AK27 VSS71 VSS152 W28 G17 VSS229
AK25 VSS72 VSS153 W27 G11 VSS230
AK22 VSS73 VSS154 W26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 VSS76 VSS157 U6
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80

A A
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 11 of 63
5 4 3 2 1
 5 4 3 2 1

+1.5V

+VREF_DQ_DIMMA +1.5V +1.5V

1
3A@1.5V
[7] DDR_A_D[0..63]
R70
1K_0402_1% DDR3 SO-DIMM A [7] DDR_A_DQS[0..7]
JDIMM1
[7] DDR_A_DQS#[0..7]

2
+VREF_DQ_DIMMA 1 2
VREF_DQ VSS1 DDR_A_D4
3 VSS2 DQ4 4 [7] DDR_A_MA[0..15]

2.2U_0603_6.3V6K

0.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
1 DQ0 DQ5

C134

C133
1 1 DDR_A_D1 7 8
DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10
R71 DDR_A_DM0 11 12 DDR_A_DQS0
1K_0402_1% DM0 DQS0
13 VSS5 VSS6 14
D 2 2 DDR_A_D2 DDR_A_D6 D
15 16
2

DDR_A_D3 DQ2 DQ6 DDR_A_D7

17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# [13,7]
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
[7] DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA [7]
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
[7] DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 100
[7] M_CLK_DDR0 M_CLK_DDR0 101
VDD9 VDD10
102 M_CLK_DDR1 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
CK0 CK1 M_CLK_DDR1 [7]
[7] M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 [7]
DDR_A_MA10
105 VDD11 VDD12 106
DDR_A_BS1 +1.5V Layout Note: (10uF_0603_6.3V)*8
107 A10/AP BA1 108 DDR_A_BS1 [7]
[7] DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
DDR_A_RAS# [7]
Place near DIMM
BA0 RAS#
111 VDD13 VDD14 112 (0.1uF_402_10V)*4
[7] DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA#
WE# S0# DDR_CS0_DIMMA# [7]

1
[7] DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 [7]
117 118 R72
DDR_A_MA13 VDD15 VDD16 M_ODT1 1K_0402_1%
119 A13 ODT1 120 M_ODT1 [7]
[7] DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2 +1.5V
123 124

2
VDD17 VDD18 +VREF_CA
125 NCTEST VREF_CA 126

0.1U_0402_16V7K
127 VSS27 VSS28 128

C135

2.2U_0603_6.3V6K
DDR_A_D32 DDR_A_D36
129 DQ32 DQ36 130 1 EVT Check

1
C136
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37

10U_0603_6.3V6M
C137

10U_0603_6.3V6M
C138

10U_0603_6.3V6M
C139

10U_0603_6.3V6M
C140

10U_0603_6.3V6M
C141

10U_0603_6.3V6M
C142

10U_0603_6.3V6M
C143

10U_0603_6.3V6M
C144

0.1U_0402_16V7K
C145

0.1U_0402_16V7K
C146

0.1U_0402_16V7K
C147

0.1U_0402_16V7K
C148
133 VSS29 VSS30 134 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_DQS#4 135 136 DDR_A_DM4 R73 + C149 @
B DDR_A_DQS4 DQS#4 DM4 2 1K_0402_1% 220U_6.3V_M B
137 DQS4 VSS31 138
DDR_A_D38 2 @ @
139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2 2 2 2 2 2 2 2 2 2 2 2
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44
145 VSS34 DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52 6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 168 Place near DIMM
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 DQS#6 DM6 170 VTT(0.75V) =
DDR_A_DQS6 171 172 7/28 Update connect GND directly
DQS6 VSS43 DDR_A_D54
173 VSS44 DQ54 174 3*0805 10uf 4*0402 1uf
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 DQ50 DQ55 +0.75VS
177 DQ51 VSS45 178 VREF =
179 180 DDR_A_D60 DDR_A_DM0
DDR_A_D56 VSS46 DQ60 DDR_A_D61 DDR_A_DM1
181 DQ56 DQ61 182 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 183 184 DDR_A_DM2
DQ57 VSS47 DDR_A_DQS#7 @ @ DDR_A_DM3
185 VSS48 DQS#7 186 VDDSPD (3.3V)=

1U_0402_6.3V6K
C150

1U_0402_6.3V6K
C151

1U_0402_6.3V6K
C152

1U_0402_6.3V6K
C153
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
DM7 DQS7 DDR_A_DM5
189 VSS49 VSS50 190 1*0402 0.1uf 1*0402 2.2uf 1 1 1 1
DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DDR_A_D59 DQ58 DQ62 DDR_A_D63 DDR_A_DM7
193 DQ59 DQ63 194
1 R81 2 195 VSS51 VSS52 196
10K_0402_5% 2 2 2 2
197 SA0 EVENT# 198
199 200 SMB_DATA_S3 Layout Note:
+3VS VDDSPD SDA SMB_DATA_S3 [13,15,36,43]
2.2U_0603_6.3V6K

0.1U_0402_16V7K

A 201 202 SMB_CLK_S3 A

SA1 SCL SMB_CLK_S3 [13,15,36,43] Place near DIMM
C155

C156

1 1 203 VTT1 VTT2 204 +0.75VS

1 10K_0402_5%
R83

205 206 0.65A@0.75V

G1 G2
2 2 LCN_DAN06-K4806-0103
ME@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 12 of 63
5 4 3 2 1
 5 4 3 2 1

+1.5V
+VREF_DQ_DIMMB 3A@1.5V
[7] DDR_B_D[0..63]

1
+1.5V +1.5V
[7] DDR_B_DQS[0..7]
R84
1K_0402_1% JDIMM2
[7] DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
VREF_DQ VSS DDR_B_D4
3 4 [7] DDR_B_MA[0..15]

2
DDR_B_D0 VSS DQ4 DDR_B_D5
5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS

2.2U_0603_6.3V6K

0.1U_0402_16V7K
9 10 DDR_B_DQS#0
1 VSS DQS0#

C158
1 1 DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
13 VSS VSS 14

C157
R85 DDR_B_D2 15 16 DDR_B_D6
1K_0402_1% DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
D 2 2 D
19 20
2

DDR_B_D8 VSS VSS DDR_B_D12

21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# [12,7]
31 VSS VSS 32
For Arranale only +VREF_DQ_DIMMB DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
supply from a external 1.5V voltage divide 37 38
DDR_B_D16 VSS VSS DDR_B_D20
circuit. DDR_B_D17
39 DQ16 DQ20 40
DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

[7] DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB [7]
75 VDD VDD 76
77 78 DDR_B_MA15
C DDR_B_BS2 NC A15 DDR_B_MA14 C
[7] DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
[7] M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 [7]
[7] M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 [7]
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 [7]
[7] DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
BA0 RAS# DDR_B_RAS# [7] +1.5V
DDR_B_WE#
111 VDD VDD 112
DDR_CS2_DIMMB#
Layout Note: (10uF_0603_6.3V)*8
[7] DDR_B_WE# 113 WE# S0# 114 DDR_CS2_DIMMB# [7]
[7] DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
M_ODT2 [7]
Place near DIMM
CAS# ODT0

1
117 VDD VDD 118 (0.1uF_402_10V)*4
DDR_B_MA13 119 120 M_ODT3 R86
A13 ODT1 M_ODT3 [7]
[7] DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122 1K_0402_1%
S1# NC
123 VDD VDD 124
125 126 +VREF_CB

2
TEST VREF_CA

0.1U_0402_16V7K
127 VSS VSS 128
+1.5V

2.2U_0603_6.3V6K
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

C159

C160
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

1
133 VSS VSS 134

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_B_DQS#4 135 136 DDR_B_DM4
DQS4# DM4

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
DDR_B_DQS4 137 138 R87
DQS4 VSS 2 2

C161

C162

C163

C164

C165

C166

C167

C168

C169

C170

C171

C172
139 140 DDR_B_D38 1K_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1
DDR_B_D34 VSS DQ38 DDR_B_D39
141 142

2
B DDR_B_D35 DQ34 DQ39 B
143 DQ35 VSS 144
145 146 DDR_B_D44 @ @
DDR_B_D40 VSS DQ44 DDR_B_D45 2 2 2 2 2 2 2 2 2 2 2 2
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 VSS DQS5# 152
DDR_B_DM5 153 154 DDR_B_DQS5 VDDQ(1.5V) =
DM5 DQS5
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS VSS 162 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166

DDR_B_DQS#6
167 VSS VSS 168
DDR_B_DM6
VTT(0.75V) = Layout Note:
169 DQS6# DM6 170
DDR_B_DQS6 171 172 3*0805 10uf 4*0402 1uf Place near DIMM
DQS6 VSS DDR_B_D54
173 VSS DQ54 174
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS 178
179 180 DDR_B_D60 1*0402 0.1uf
DDR_B_D56 VSS DQ60 DDR_B_D61 +0.75VS
181 DQ56 DQ61 182 1*0402 2.2uf
DDR_B_D57 183 184 VDDSPD (3.3V)=
DQ57 VSS DDR_B_DQS#7 DDR_B_DM0
185 VSS DQS7# 186
DDR_B_DM7 187 188 DDR_B_DQS7 1*0402 0.1uf DDR_B_DM1
DM7 DQS7 @ @ DDR_B_DM2
189 VSS VSS 190 1*0402 2.2uf

1U_0402_6.3V6K
C173

1U_0402_6.3V6K
C174

1U_0402_6.3V6K
C175

1U_0402_6.3V6K
C176
DDR_B_D58 191 192 DDR_B_D62 DDR_B_DM3
DDR_B_D59 DQ58 DQ62 DDR_B_D63 DDR_B_DM4
193 DQ59 DQ63 194 1 1 1 1
195 196 DDR_B_DM5
VSS VSS
1 R95 2 197 SA0 EVENT# 198 DDR_B_DM6
10K_0402_5% 199 200 SMB_DATA_S3 DDR_B_DM7
VDDSPD SDA SMB_DATA_S3 [12,15,36,43] 2 2 2 2
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 [12,15,36,43]
2.2U_0603_6.3V6K

0.1U_0402_16V7K

R97 10K_0402_5% 203 204 +0.75VS

VTT VTT 0.65A@0.75V
C177

C178

1 1
A A
205 GND1 GND2 206 Layout Note:
207 BOSS1 BOSS2 208
Place near DIMM
2 2
LCN_DAN06-K4406-0103
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 13 of 63
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCVCC +RTCBATT
NOGCLK@
Y1
R99 1 2
1K_0402_5% 32.768KHZ_12.5PF_CM31532768DZFT
1 2 R03 1 1 R03
C180 NOGCLK@ C181

1
1 18P_0402_50V8J 18P_0402_50V8J
C179 CLRP1 NOGCLK@ NOGCLK@
1U_0402_6.3V6K SHORT PADS 2 2

2
R02
2 Remove R176
D D
close to Y1

R182 1 2 GCLK_32K
GCLK_32K [44]
0_0402_5%
CMOS GCLK@
U4A
+RTCVCC

SHORT PADS
CLRP2
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 [36,42]

1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 [36,42]

LPC
C183 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
RTCX2 FWH2 / LAD2 LPC_AD2 [36,42]
R102 1 2 330K_0402_5% PCH_INTVRMEN 1U_0402_6.3V6K C37 LPC_AD3
LPC_AD3 [36,42]

2
2 PCH_RTCRST# FWH3 / LAD3
1 2 D20 RTCRST#
R103 20K_0402_5% LPC_FRAME#
INTVRMEN 1 2 PCH_SRTCRST# G22
FWH4 / LFRAME# D36 LPC_FRAME# [36,42]
R100 20K_0402_5% SRTCRST# +3VS
H：Integrated VRM enable E36
* 1 LDRQ0#

1
SHORT PADS
CLRP3
SM_INTRUDER#

RTC
L：Integrated VRM disable K22 K36 R104 2 1 10K_0402_5%
C182 INTRUDER# LDRQ1# / GPIO23
(INTVRMEN should always be pull high.) 1U_0402_6.3V6K PCH_INTVRMEN C17 V5 SERIRQ SERIRQ [42]

2
2 INTVRMEN SERIRQ

AM3 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 [36]

+3VS HDA_BIT_CLK SATA0RXN SATA_DTX_C_IRX_P0
N34 HDA_BCLK SATA0RXP AM1 SATA_DTX_C_IRX_P0 [36]
SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_N0

SATA 6G
SATA0TXN AP7 SATA_ITX_DRX_N0 [36] SSD
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 1 C185 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 [36]
HDA_SYNC SATA0TXP CAP on Conn, side
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10 SATA_DTX_R_IRX_N1 0_0402_5%1 HM76@ 2 R311 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 [40]
[41] HDA_SPKR SPKR SATA1RXN
LOW= Disable (Default) AM8 SATA_DTX_R_IRX_P1 0_0402_5%1 HM76@ 2 R312 SATA_DTX_C_IRX_P1
* HDA_RST# K34 HDA_RST#
SATA1RXP
SATA1TXN AP11 SATA_ITX_R_DRX_N1 0.01U_0402_16V7K 2 1 C198 SATA_ITX_C_DRX_N1 0_0402_5% 2 @ 1 R5593 SATA_ITX_DRX_N1
SATA_DTX_C_IRX_P1 [40]
SATA_ITX_DRX_N1 [40] HDD
AP10 SATA_ITX_R_DRX_P1 0.01U_0402_16V7K 2 1 C199 SATA_ITX_C_DRX_P1 0_0402_5% 2 @ 1 R5594 SATA_ITX_DRX_P1 SATA_ITX_DRX_P1 [40]
SATA1TXP CAP on Conn, side
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
[41] HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 [40]
AD5 SATA_DTX_C_IRX_P2 SATA_DTX_C_IRX_P2 [40] ODD
R106 2 @ 1 1K_0402_5% HDA_SDOUT SATA2RXP SATA_ITX_C_DRX_N2
G34 HDA_SDIN1 SATA2TXN AH5 SATA_ITX_C_DRX_N2 [40]
AH4 SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 [40]
SATA2TXP
Low = Disabled (Default) C34
* HDA_SDIN2

IHDA
High = Enabled [Flash Descriptor Security Overide] SATA3RXN AB8
R02 A34 AB10
R109 HDA_SDIN3 SATA3RXP
0_0402_5% SATA3TXN AF3 HM70 Disable SATA Port 1,3
SATA3TXP AF1
ME_FLASH 1 @ 2 HDA_SDOUT A36
+3V_PCH [42] ME_FLASH HDA_SDO SATA_DTX_R_IRX_N4 0_0402_5%1 HM70@ 2 R318 SATA_DTX_C_IRX_N1

SATA
SATA4RXN Y7
Y5 SATA_DTX_R_IRX_P4 0_0402_5%1 HM70@ 2 R315 SATA_DTX_C_IRX_P1
R108 SATA4RXP
2 1 1K_0402_5% HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 HDA_DOCK_EN# / GPIO33 SATA4TXN AD3 SATA_ITX_R_DRX_N4 0.01U_0402_16V7K 2 1 C229 SATA_ITX_C_DRX_N1 HDD
AD1 SATA_ITX_R_DRX_P4 0.01U_0402_16V7K 2 1 C237 SATA_ITX_C_DRX_P1
10K_0402_5% SATA4TXP
+3V_PCH 2 R264 @1 N32 HDA_DOCK_RST# / GPIO13
This signal has a weak internal pull-down SATA5RXN Y3
On Die PLL VR is supplied by SATA5RXP Y1
1.5V when smapled high SATA5TXN AB3
2 R110 1 PCH_JTAG_TCK J3 AB1
* 1.8V when sampled low
Needs to be pulled High for Chief River platfrom
JTAG_TCK SATA5TXP
51_0402_5% PCH_JTAG_TMS H7 Y11 R111
JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA

JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
+5VS JTAG_TDI SATAICOMPI

8MB SPI ROM FOR ME

R112 PCH_JTAG_TDO H1
33_0402_5% JTAG_TDO R113 +1.05VS_SATA3
SATA3RCOMPO AB12
1 2 HDA_BIT_CLK 49.9_0402_1%

& Non-share ROM.

[41] HDA_BITCLK_AUDIO
2
G

R114 Q10 AB13 SATA3_COMP 1 2

33_0402_5% LBSS138LT1G_SOT-23-3 SATA3COMPI
[41] HDA_SYNC_AUDIO 1 2 HDA_SYNC_R 3 1 HDA_SYNC
R116 SPI_CLK_PCH_R RBIAS_SATA3
S

T3 SPI_CLK SATA3RBIAS AH1 1 2

33_0402_5% R115 +3VS
2

B HDA_RST# SPI_SB_CS0# 750_0402_1% R02 B

[41] HDA_RST_AUDIO# 1 2 Y14 SPI_CS0#
R118 R878 R291
33_0402_5% 1M_0402_5% R175 @ SPI_SB_CS1# T1 0_0402_5% U6 R02
SPI_CS1#
SPI

1 2 HDA_SDOUT 1 2 P3 SATALED# 2 R117 1 10K_0402_5% SPI_SB_CS1# 1 @ 2 CS1# 1 R199

[41] HDA_SDOUT_AUDIO SATALED# +3VS
SPI_SO_R CS# VCC 8
1 2 SPI_SO1 2 HOLD# 7
SPI_HOLD#1 0_0402_5%
1

0_0402_5% SPI_SI PCH_GPIO21 SO

V4 SPI_MOSI SATA0GP / GPIO21 V14 2 R119 1 10K_0402_5% +3VS SPI_WP#1 3 WP# SCLK 6
SPI_CLK1 1 @ 2 SPI_CLK_PCH_R
R188 4 SPI_SI1 2 SPI_SI
SPI_SO_R BBS_BIT0_R GND SI 5 1
check with vender U3 SPI_MISO SATA1GP / GPIO19 P1 2 R187 1 10K_0402_5% +3VS 33_0402_5% R196
+3V_PCH +3V_PCH +3V_PCH 33_0402_5%
Del Q10 check with codec 16M W25Q16BVSSIG SOIC 8P
PANTHER-POINT_FCBGA989
VDDIO using 3VALW
1

@ @ @ +3VS
R121 R122 R123
200_0402_5% 200_0402_5% 200_0402_5%
SPI_CLK_PCH_R R266 1 2 SPI_WP#1
3.3K_0402_5%
U6 Rersver 4M+2M Solution
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1

R221 1 2SPI_HOLD#1 +3VS

1

@ @ @ R124 3.3K_0402_5%
R125 R126 R128 33_0402_5% R127 1 2 SPI_WP# C191 0.1U_0402_16V7K
100_0402_1% 100_0402_1% 100_0402_1% @ 3.3K_0402_5% R02 1 2
R130
R124;c190 close to U4.T3 pin
2

R129 1 2SPI_HOLD# 0_0402_5% U5 R02

2

3.3K_0402_5% SPI_SB_CS0# 1 @ 2 CS# 1 8 R132

C190 SPI_SO_R CS# VCC
DPDG1.1 1 2 SPI_SO_L 2 SO HOLD# 7 SPI_HOLD# 0_0402_5%
22P_0402_50V8J SPI_WP# 3 6 SPI_CLK_PCH 1 @ 2 SPI_CLK_PCH_R
33_0402_5% WP# SCLK SPI_SI_R
@ 4 GND SI 5 1 2 SPI_SI
R131 R133
W25Q32BVSSIG_SO8 33_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 14 of 63
5 4 3 2 1
 5 4 3 2 1

U4B
Q60A
2N7002KDWH_SOT363-6
[37] PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 6 1 SMB_CLK_S3
PERN1 SMB_CLK_S3 [12,13,36,43]
LAN [37] PCIE_PRX_DTX_P1 PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPI011 2 R134 1 +3V_PCH
C192 PCIE_PTX_DRX_N1 PERP1 SMBALERT# / GPIO11
1 2 0.1U_0402_16V7K AV32 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
[37] PCIE_PTX_C_DRX_N1
[37] PCIE_PTX_C_DRX_P1
C193 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P1 AU32
PETN1
H14 PCH_SMBCLK 1 R136 2 1 2 R137 DIMM1

2
PETP1 SMBCLK
[36] PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 PERN2 SMBDATA C9 PCH_SMBDATA
+3V_PCH
1 2 1
+3VS
2 DIMM2

5
PCIE_PRX_DTX_P2 BF34 R135 R138
WLAN
[36] PCIE_PRX_DTX_P2
[36] PCIE_PTX_C_DRX_N2
C194 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BB32
PERP2
PETN2
2.2K_0402_5% 2.2K_0402_5% MINI CARD
C195 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
[36] PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 [12,13,36,43]

SMBUS
SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH [7]
BG36 2N7002KDWH_SOT363-6
PERN3 PCH_SML0CLK
BJ36 PERP3 SML0CLK C8 Q60B
D D
AV34 PETN3 2 R139 1 +3V_PCH
AU34 G12 PCH_SML0DATA 1K_0402_5%
PETP3 SML0DATA Q61A
BF36 2 R140 1 10K_0402_5% 2N7002KDWH_SOT363-6
PERN4 +3V_PCH
BE36 6 1 EC_SMB_CK2
PERP4 EC_SMB_CK2 [23,39,42]
AY34 C13 PCH_HOT#
PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# [42]
BB34 2.2K_0402_5%
PETP4
E14 SML1CLK 1 R141 2 VGA

2
SML1CLK / GPIO58

PCI-E*
BG37
BH37
PERN5
PERP5 SML1DATA / GPIO75 M16 SML1DATA
+3V_PCH
1 2
+3VS
EC

5
AY36 R142
BB36
PETN5
PETP5
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
EC_SMB_DA2 [23,39,42]
BJ38 PERN6
BG38 2N7002KDWH_SOT363-6
PERP6

Controller
AU36 PETN6 CL_CLK1 M7 Q61B
+3V_PCH
HM70 not support AV36 PETP6 +3V_PCH
PCIE port 5-8

Link
BG40 PERN7 CL_DATA1 T11

2
BJ40 PERP7
AY40 PETN7

2
BB40 P10 R143
PETP7 CL_RST1# R544 R545
10K_0402_5%
BE38 R02 2.2K_0402_5% 2.2K_0402_5%

1
PERN8 R144 0_0402_5%
BC38 PERP8
AW38 1 @ 2 CLK_REQ_VGA# [23]

1
PETN8 PCH_SML0CLK
AY38 PETP8
R02 M10 PEG_CLKREQ#_R 1 R145 2 10K_0402_5% PCH_SML0DATA
R153 @ PEG_A_CLKRQ# / GPIO47
[37] CLK_PCIE_LAN# 1 2 0_0402_5% CLK_PCIE_LAN#_R Y40 CLKOUT_PCIE0N
@
LAN R154 1 @ 2 0_0402_5% CLK_PCIE_LAN_R Y39 R02
[37] CLK_PCIE_LAN R02 CLKOUT_PCIE0P
AB37 CLK_PCIE_VGA#_R R146 1 @ 2 0_0402_5% CLK_PCIE_VGA#
C CLKOUT_PEG_A_N CLK_PCIE_VGA# [23] C
R151 @ 2 0_0402_5% CLKREQ_LAN#_R CLK_PCIE_VGA_R R148 1 @ 2 0_0402_5% CLK_PCIE_VGA

CLOCKS
[37] CLKREQ_LAN# 1 J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA [23]
R152 2 1 10K_0402_5% R02
+3V_PCH
R02
R149 1 @ 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#
[36] CLK_PCIE_WLAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# [6]
R150 1 @ 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI
[36] CLK_PCIE_WLAN1 R02 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI [6]
WLAN
[36] CLKREQ_WLAN# R156 1 @ 2 0_0402_5% CLKREQ_WLAN#_R M1
R158 PCIECLKRQ1# / GPIO18
+3VS 2 1 10K_0402_5% CLKOUT_DP_N AM12
CLKOUT_DP_P AM13
AA48 CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
R147 CLKIN_DMI_N
+3VS 2 1 10K_0402_5% PCH_GPIO20 V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 CLK_BUF_CPU_DMI R157 1 2 10K_0402_5%

Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%

CLKOUT_PCIE3N CLKIN_GND1_N CLKIN_DMI2 R160 1 10K_0402_5%
Y36 CLKOUT_PCIE3P CLKIN_GND1_P BG30 2

+3V_PCH R301 2 1 10K_0402_5% PCH_GPIO25 A8 PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M# R162 1 10K_0402_5%

CLKIN_DOT_96N G24 2
E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5%
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P
AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5%
R165 CLKIN_SATA_N
+3V_PCH 2 1 10K_0402_5% PCH_GPIO26 L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%

V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5% R02

CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P Remove R1381
R168 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
+3V_PCH PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK [18] close to Y2
B B
AB42 V47 XTAL25_IN 0_0402_5% 2 1 R1382 GCLK_PCH_25MHZ
CLKOUT_PEG_B_N XTAL25_IN GCLK_PCH_25MHZ [44]
AB40 V49 XTAL25_OUT GCLK@
CLKOUT_PEG_B_P XTAL25_OUT
R170 2 1 10K_0402_5% PCH_GPIO56 E6 R171 +1.05VS_VCCDIFFCLKN
+3V_PCH PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
XCLK_RCOMP
V40 CLKOUT_PCIE6N
V42 CLKOUT_PCIE6P
+3V_PCH R172 2 110K_0402_5% PCH_GPIO45 T13 PCIECLKRQ6# / GPIO45 27M_SSC
V38 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 K43
FLEX CLOCKS

V37 CLKOUT_PCIE7P
CLKOUTFLEX1 / GPIO65 F47
+3V_PCH R174 2 1 10K_0402_5% PCH_GPIO46 K12 PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 H47
T52 CLKOUT_ITPXDP_N AK14 XTAL25_IN
T53 CLKOUT_ITPXDP_P AK13 CLKOUT_ITPXDP_N PCH_GPIO67
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 K49 PCH_GPIO67 [19]
XTAL25_OUT 1 NOGCLK@2
BIOS Request SKU ID R169 1M_0402_5%
PANTHER-POINT_FCBGA989
3 OSC NC 4

2 NC OSC 1

Y2 NOGCLK@
1 25MHZ_10PF_7V25000014 1
C196 C197
12P_0402_50V8J 12P_0402_50V8J
NOGCLK@ NOGCLK@
2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 15 of 63
5 4 3 2 1
 5 4 3 2 1

D D

U4C

[5] DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 [5]

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
[5] DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 [5]
[5] DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 [5]
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
[5] DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 [5]
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 [5]
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5
[5] DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5 [5]
[5] DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 [5]
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
[5] DMI_CTX_PRX_P2 BJ18 DMI2RXP FDI_RXN7 BG9 FDI_CTX_PRX_N7 [5]
[5] DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20 DMI3RXP FDI_CTX_PRX_P0
FDI_RXP0 BG14 FDI_CTX_PRX_P0 [5]
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 [5]
[5] DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 [5]
[5] DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 [5]
[5] DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
U15 DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 [5]
[5] DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
MC74VHC1G08DFT2G_SC70-5 BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 [5]
FDI_RXP5
3

DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 FDI_CTX_PRX_P6 [5]

[5] DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6
1 DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
G

[55] VGATE A [5] DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 [5]

Y 4SYS_PWROK SYS_PWROK [6] [5] DMI_CRX_PTX_P2
DMI_CRX_PTX_P2 AY18 DMI2TXP
PCH_PWROK 2 DMI_CRX_PTX_P3 AU18
B [5] DMI_CRX_PTX_P3 DMI3TXP
P

AW16 FDI_INT
FDI_INT FDI_INT [5]
5

+V1.05S_VCCP BJ24 AV12 FDI_FSYNC0

DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 [5] +RTCVCC
R180 @
100K_0402_1% 1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 [5]
+3VS R177 49.9_0402_1%
*

1
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
FDI_LSYNC0 [5]
2

C R178 750_0402_1% DMI2RBIAS FDI_LSYNC0 R179 C

4mil width and place BB10 FDI_LSYNC1 DSWODVREN - On Die DSW VR Enable 330K_0402_5%
FDI_LSYNC1 FDI_LSYNC1 [5]
within 500mil of the PCH H：Enable
L：Disable

2
A18 DSWODVREN
DSWVRMEN
R20 R181 1 NODS3@2 0_0402_5% PCH_RSMRST#_R

System Power Management

1
[42] SUSACK# R304 1 @ 2 0_0402_5% SUSACK#_R C12 SUSACK# DPWROK E22 PCH_DPWROK R267 1 2 0_0402_5% DPWROK_EC DPWROK_EC [42]
DS3@ R183
For Deep S3 R02 330K_0402_5%
2 1 SYS_RST# K3 B9 WAKE# R185 1 @ 2 0_0402_5% For Deep S3 +3VS
+3VS SYS_RESET# WAKE# PCIE_WAKE# [36,37] @
10K_0402_5% R184 1 2 10K_0402_5% +3V_PCH

2
R186 @ R189 8.2K_0402_5%
SYS_PWROK P12 N3 PM_CLKRUN# 1 2
SYS_PWROK CLKRUN# / GPIO32
AEPWROK can be connect to R299 10K_0402_5%
PWROK if iAMT disable [42] PCH_PWROK PCH_PWROKR02 1 @ 2 PCH_POK L22 G8 SUS_STAT# T74 2 1
R190 0_0402_5% PWROK SUS_STAT# / GPIO61

[42] PCH_APWROK 1 @ 2 APWROK L10 N14

APWROK SUSCLK / GPIO62 SUSCLK [42]
PCH_POK R02 1 @ 2 APWROK R302 0_0402_5%
R191 0_0402_5%
PM_DRAM_PWRGD B13 D10
[6] PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# [42]

+3VS R02 1 @ 2 PCH_RSMRST#_R C21 H4

[42] EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# [42]
@ R193 0_0402_5%
+3V_PCH 2 R556 1 200_0402_5% R20
R1455 2 @ 1 0_0402_5% SUSWARN#_R K16 F4
[42] SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# [42]
R192 2 1 300_0402_5% PM_DRAM_PWRGD For Deep S3 Can be left NC
B R02 1 @ PBTN_OUT#_R SLP_A# T99 B
[42] PBTN_OUT# 2 E20 PWRBTN# SLP_A# G10 when IAMT is not
R198 0_0402_5% R20
support on the
R194 2 1 10K_0402_5% SUSWARN#_R R1447 0_0402_5%
D29 1 AC_PRESENT_R SLP_SUS#_R @
platfrom
[42,49] ACIN 2 H20 ACPRESENT / GPIO31 SLP_SUS# G16 2 1 SLP_SUS# [42,46]
R5574 2 NODS3@1 200K_0402_5% AC_PRESENT_R
CH751H-40PT_SOD323-2 For Deep S3
R197 2 1 10K_0402_5% PCH_RSMRST#_R 2 R200 1 PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC [6]
10K_0402_5%

+3V_PCH 2 R201 1 RI# A10 RI# SLP_LAN# / GPIO29 K14 PCH_GPIO291 2 +3V_PCH Can be left NC if no use
10K_0402_5% R261 @ integrated LAN.
10K_0402_5%
PANTHER-POINT_FCBGA989

For Deep S3

+3VALW

R195 1 DS3@ 2 200K_0402_5% AC_PRESENT_R

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 16 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS

U4D

1
D R523 R234 D
[33] PCH_ENBKL J47 L_BKLTEN SDVO_TVCLKINN AP43
2.2K_0402_5% 2.2K_0402_5% M45 AP45 +3VS
[33] PCH_ENVDD L_VDD_EN SDVO_TVCLKINP

[33] PCH_PWM P45 AM42

2
L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40

1
EDID_CLK EDID_CLK T40
+3VS [33] EDID_CLK L_DDC_CLK
EDID_DATA EDID_DATA K47 AP39 HDMI@ R202 R203HDMI@
[33] EDID_DATA L_DDC_DATA SDVO_INTN
AP40 2.2K_0402_5% 2.2K_0402_5%
2.2K_0402_5%1 R204 CTRL_CLK SDVO_INTP
2 T45 L_CTRL_CLK
2.2K_0402_5%1 R205 2 CTRL_DATA P39

2
L_CTRL_DATA
2.37K_0402_1%
2 R206 1 LVDS_IBG AF37 P38 HDMICLK_NB HDMICLK_NB [35]
LVD_IBG SDVO_CTRLCLK
AF36 LVD_VBG SDVO_CTRLDATA M39 HDMIDAT_NB HDMIDAT_NB [35]
LVD_VREF AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
DDPB_HPD AT40 TMDS_B_HPD# [35]
[33] LVDS_ACLK# AK39 LVDSA_CLK#

LVDS
[33] LVDS_ACLK AK40 LVDSA_CLK DDPB_0N AV42 TMDS_B_DATA2#_PCHHDMI@ C200 1 2 0.1U_0402_16V7K
HDMI_TX2-_CK [35]
DDPB_0P AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 0.1U_0402_16V7K
HDMI_TX2+_CK [35] HDMI D2
[33] LVDS_A0# AN48 LVDSA_DATA#0 DDPB_1N AV45 TMDS_B_DATA1#_PCHHDMI@ C202 1 2 0.1U_0402_16V7K
HDMI_TX1-_CK [35]
AM47 AV46 TMDS_B_DATA1_PCH HDMI@ C203 1 2 0.1U_0402_16V7K HDMI D1

Digital Display Interface

[33] LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK [35]
C [33] LVDS_A2# AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0#_PCHHDMI@ C204 1 2 0.1U_0402_16V7K
HDMI_TX0-_CK [35] HDMI C
AJ48 LVDSA_DATA#3 DDPB_2P AU47 TMDS_B_DATA0_PCH HDMI@ C205 1 2 0.1U_0402_16V7K
HDMI_TX0+_CK [35] HDMI D0
DDPB_3N AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 0.1U_0402_16V7K
HDMI_CLK-_CK [35]
[33] LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 TMDS_B_CLK_PCH HDMI@ C207 1 2 0.1U_0402_16V7K
HDMI_CLK+_CK [35] HDMI CLK
[33] LVDS_A1 AM49 LVDSA_DATA1
[33] LVDS_A2 AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46 CAP move on Conn, side
DDPC_CTRLDATA P42

[33] LVDS_BCLK# AF40 LVDSB_CLK#

[33] LVDS_BCLK AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
[33] LVDS_B0# AH45 LVDSB_DATA#0 DDPC_HPD AT38
[33] LVDS_B1# AH47 LVDSB_DATA#1
[33] LVDS_B2# AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
[33] LVDS_B0 AH43 LVDSB_DATA0 DDPC_1P AY45
[33] LVDS_B1 AH49 LVDSB_DATA1 DDPC_2N BA47
+3VS AF47 BA48
[33] LVDS_B2 LVDSB_DATA2 DDPC_2P
AF43 LVDSB_DATA3 DDPC_3N BB47
DAC_BLU BB49
[34] DAC_BLU DDPC_3P
R208 2 1 150_0402_1%
1

DAC_GRN
[34] DAC_GRN
B R559 R524 R209 2 1 150_0402_1% N48 M43 B
2.2K_0402_5% 2.2K_0402_5% DAC_RED CRT_BLUE DDPD_CTRLCLK
[34] DAC_RED P49 CRT_GREEN DDPD_CTRLDATA M36
R210 2 1 150_0402_1% T49 CRT_RED
2

DDPD_AUXN AT45

CRT
CRT_DDC_CLK CRT_DDC_CLK T39 AT43
[34] CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA CRT_DDC_DATA M40 BH41
[34] CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD

DDPD_0N BB43
[34] CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
[34] CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
CRT_IREF T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
1

DDPD_3P BG42
R211
1K_0402_1% PANTHER-POINT_FCBGA989
2

A A

Security Classification Compal Secret Data

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 17 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS

U4E
RP2 AY7
PCI_PIRQA# RSVD1
8 1 RSVD2 AV7
7 2 PCI_PIRQD# BG26 AU3
PCI_PIRQC# TP1 RSVD3
6 3 BJ26 TP2 RSVD4 BG4
5 4 PCI_PIRQB# BH25 TP3
BJ16 TP4 RSVD5 AT10
8.2K_8P4R_5% BG16 BC8
RP1 TP5 RSVD6
D AH38 TP6 D
8 1 PCH_GPIO2 AH37 AU2
DGPU_PWR_EN_R TP7 RSVD7
7 2 AK43 TP8 RSVD8 AT4
6 3 PCH_GPIO4 AK45 AT3
ODD_DA#_R TP9 RSVD9
5 4 C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3
8.2K_8P4R_5% H3 AT5
TP12 RSVD12
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1
AM5 TP15 RSVD15 BB1
R213 1 2 8.2K_0402_5% PCH_GPIO5 Y13 BA3
TP16 RSVD16
K24 TP17 RSVD17 BB5
R225 1 2 8.2K_0402_5% PCH_WL_OFF# L24 BB3
TP18 RSVD18
AB46 TP19 RSVD19 BB7
R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 AB45 BE8
TP20 RSVD20

RSVD
R557 1 @ 2 8.2K_0402_5% PCH_GPIO53
PPT EDS DOC#474146 RSVD21 BD4
BF6
RSVD22
R259 1 2 8.2K_0402_5% DGPU_PWR_EN1 B21 AV5
TP21 RSVD23
M20 TP22 RSVD24 AV10
R212 1 2 8.2K_0402_5% DGPU_HOLD_RST#_R AY16 TP23
BG46 TP24 RSVD25 AT8
R214 1 @ 2 8.2K_0402_5% DGPU_HOLD_RST#_R HM70 not support USB3 port 3,4
RSVD26 AY5
RSVD27 BA2
[45] USB30_RX_N1 USB30_RX_N1 BE28
T1833 USB30_RX_N2 USB3Rn1
BC30 USB3Rn2 RSVD28 AT12
C Boot BIOS Strap bit1 BBS1 T1829 USB30_RX_N3 BE32 BF3 C
T1825 USB30_RX_N4 USB3Rn3 RSVD29
BJ32 USB3Rn4
Boot BIOS [45] USB30_RX_P1 USB30_RX_P1 BC28 USB DEBUG=PORT1 AND PORT9
T1834 USB30_RX_P2 USB3Rp1
BE30
Bit11 Bit10 Destination T1832 USB30_RX_P3 BF32
USB3Rp2
USB3Rp3
T1826 USB30_RX_P4 BG32 C24 USB20_N0
USB3Rp4 USBP0N USB20_N0 [45]
0 1 Reserved USB30_TX_N1 AV26 A24 USB20_P0 LEFT USB (USB 3.0)
[45] USB30_TX_N1 USB3Tn1 USBP0P USB20_P0 [45]
GNT1#/ T1835 USB30_TX_N2 BB26 C25 USB20_N1
USB3Tn2 USBP1N USB20_N1 [43]
1 0 Reserved T1831 USB30_TX_N3 AU28 B25 USB20_P1 Touch Screen
GPIO51 T1827 USB30_TX_N4 AY30
USB3Tn3 USBP1P
C26 USB20_N2
USB20_P1 [43]
USB3Tn4 USBP2N USB20_N2 [40]
1 1 SPI (Default) USB30_TX_P1 AU26 A26 USB20_P2 Bluetooth
* [45] USB30_TX_P1
T1836 USB30_TX_P2 AY26
USB3Tp1
USB3Tp2
USBP2P
USBP3N K28 USB20_N3
USB20_P2
USB20_N3
[40]
[33]
0 0 LPC T1830 USB30_TX_P3 AV28 H28 USB20_P3 USB Camera
USB3Tp3 USBP3P USB20_P3 [33]
T1828 USB30_TX_P4 AW30 E28
USB3Tp4 USBP4N
USBP4P D28
USBP5N C28
USBP5P A28

DGPU_PWR_EN_R USBP6N C29 HM70 not support USB port 4,5,6,7,12,13

1 @ 2 NVDD_PWR_EN USBP6P B29
R319 0_0402_5% PCI_PIRQA# K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28

PCI
PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 [43]
PCI_PIRQD# G38 K30 USB20_P8 (CR-B/D USB)
PIRQD# USBP8P USB20_P8 [43]
G30 USB20_N9
R02 1 USBP9N USB20_N9 [43]
GPIO55 @ 2 DGPU_HOLD_RST#_R C46 E30 USB20_P9 (CR-B/D USB)
[23] DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 [43]

USB
R553 0_0402_5% DGPU_PWR_EN1 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 [36]
PCH_WL_OFF# R215 1 @ 2 1K_0402_5% R02 1 @ 2 DGPU_PWR_EN_R E40 A30 USB20_P10 WLAN
[23,25] DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 [36]
B R691 0_0402_5% L32 USB20_N11 B
USBP11N USB20_N11 [44]
PCH_GPIO51 D47 K32 USB20_P11 CARD READER
GNT1# / GPIO51 USBP11P USB20_P11 [44]
PCH_GPIO53 E42 G32
PCH_WL_OFF# GNT2# / GPIO53 USBP12N
A16 swap overide Strap/Top-Block [36] PCH_WL_OFF# F46 GNT3# / GPIO55 USBP12P E32
Swap Override jumper USBP13N C32
USBP13P A32
Low=A16 swap PCH_GPIO2 G42
R715 1 @ PIRQE# / GPIO2
override/Top-Block [40,42] ODD_DA# 2 0_0402_5% ODD_DA#_R G40 PIRQF# / GPIO3
PCI_GNT3# Swap Override enabled PCH_GPIO4 C42 C33 USBRBIAS 1 R218 2
PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# 22.6_0402_1%
High=Default D44 USB_OC0# Share with USB_OC4#
* PIRQH# / GPIO5
Within 500 mils due to same power switch +3V_PCH
USBRBIAS B33
[42] PCI_PME# K10 PME#
R5575 1 OPT@2 0_0402_5% 10K_1206_8P4R_5% RP3
[42] NVDD_PWR_EN_EC
R692 1 @ 2 0_0402_5% DGPU_PWR_EN1 PCH_PLTRST# C6 A14 USB_OC0# USB_OC5# 4 5
[54] NVDD_PWR_EN [6] PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# [45]
K20 USB_OC1# USB_OC2# 3 6
OC1# / GPIO40 USB_OC2# USB_OC7#
OC2# / GPIO41 B17 2 7
R5576 1 @ 2 0_0402_5% 22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 C16 USB_OC3# USB_OC0# 1 8
[19] PCH_GPIO35 [15] CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
22_0402_5% 1 2 R220 CLK_PCI_EC_R H43 L16 USB_OC4#
[42] CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# [43]
22_0402_5% 2 @ 1 R173 CLK_PCI_DB_R J48 A16 USB_OC5# USB_OC6# 4 5
[36] CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
K42 D14 USB_OC6# USB_OC1# 3 6
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7# USB_OC4#
H40 CLKOUT_PCI4 OC7# / GPIO14 C14 2 7
1 R222 2 USB_OC3# 1 8
0_0402_5%
PANTHER-POINT_FCBGA989 10K_1206_8P4R_5% RP4

A A
3

1 PCH_PLTRST#
G

A
[23,36,37,42] PLT_RST# 4 Y
B 2
P

Security Classification Compal Secret Data

1

1 U7 @
5

MC74VHC1G08DFT2G_SC70-5 2011/06/15 2012/07/11 Title

C208 @
Issued Date Deciphered Date
0.1U_0402_16V7K
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
+3VS Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2

R223 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom C
100K_0402_5% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 18 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS

2
10K_0402_5%

10K_0402_5%
PCH_GPIO69 Function PCH_GPIO70 Function
HM70@
R702
0 HM76 by PCH 17@ R703 0 14/15"
1 HM70 by PCH 1 17"

1
PCH_GPIO69 PCH_GPIO70

2
10K_0402_5%
R707
HM76@ R705
200K_0402_5%
D +3V_PCH D

1
Weak internal pull-high
1 R235 2 10K_0402_5% EC_SMI#

U4F +3VS

+3VS 1 R233 2 10K_0402_5% PCH_GPIO0 T7 BMBUSY# / GPIO0 TACH4 / GPIO68 C40 PCH_GPIO68 10K_0402_5%1 2 R224

1 R227 2 10K_0402_5% PCH_GPIO1 A42 TACH1 / GPIO1 TACH5 / GPIO69 B41 PCH_GPIO69
GPIO28
On-Die PLL Voltage Regulator 1 R228 2 10K_0402_5% PCH_GPIO6 H36 C41 PCH_GPIO70 +3VS +3VS
+3VS TACH2 / GPIO6 TACH6 / GPIO70
This signal has a weak internal pull up
[42] EC_SCI# EC_SCI# E38 A40 PCH_GPIO71 10K_0402_5%2 1 R704
TACH3 / GPIO7 TACH7 / GPIO71

2
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable [42] EC_SMI# EC_SMI# C10 GPIO8
R236
10K_0402_5%
R240 1 @ 2 1K_0402_5% PCH_GPIO28 +3V_PCH R229 1 @ 2 10K_0402_5% PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12

1
R230 1 2 1K_0402_5% EC_LID_OUT# G2 P4 +3VS
GPIO15 A20GATE GATEA20 [42]
[42] EC_LID_OUT#
mSATA_DET# AU16 PCH_PECI_R 1 @ 2
[36] mSATA_DET# PECI H_PECI [42,6]
+3VS R231 1 2 10K_0402_5% U2 0_0402_5% R237
R02 SATA4GP / GPIO16 KBRST# KBRST# R226
Deep S4,S5 wake event signal P5 1 2 10K_0402_5%
* [46,54] DGPU_PWROK
R297 1 @ 2 0_0402_5%
RCIN# KBRST# [42]
RTC alarm,Power BTN,GPIO27

GPIO
+3VS R232 1 @ 2 10K_0402_1% DGPU_PWROK_R D40 TACH0 / GPIO17 PROCPWRGD AY11 H_CPUPWRGD [6]

CPU/MISC
PU on power side
PCH_GPIO27 (Have internal Pull-High) +3VS R238 1 2 10K_0402_5% BT_DISABLE T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# H_THRMTRIP# [6]
SCLOCK / GPIO22 THRMTRIP# R239 390_0402_5%
C C
Deep S4,S5 wake event signal [36] BT_DISABLE
ODD_EN E8 T14
[40] ODD_EN GPIO24 INIT3_3V#
+3VALW For DS3 EC_WAKE# R262 1 @ 2 0_0402_5% PCH_GPIO27 E16 AY1
PCH_THRMTRIP#_R [23]
[42] EC_WAKE# GPIO27 DF_TVS
DS3@ INIT3_3V
R5530 2 1 10K_0402_5% +3V_PCH R241 1 2 10K_0402_5% PCH_GPIO28 P8 This signal has weak internal PU,can't pull low
GPIO28
[36,40] PCH_BT_ON# TS_VSS1 AH8
+3VS 1 R242 2 10K_0402_5% PCH_BT_ON# K1 STP_PCI# / GPIO34
R245 1 @ 2 10K_0402_5% PCH_GPIO27 AK11 +1.8VS
TS_VSS2
1 R243 2 10K_0402_5% PCH_GPIO35 K4 GPIO35
R03 AH10 DMI Termination Voltage
INTEL_BT_OFF# TS_VSS3
[18] PCH_GPIO35 [36] INTEL_BT_OFF# V8 SATA2GP / GPIO36

1
TS_VSS4 AK10 Set to Vcc when HIGH
PCH_GPIO37 M5 NV_CLE
+3VS SATA3GP / GPIO37 R216
Set to Vss when LOW
+3VS PCH_GPIO38 N2 P37 2.2K_0402_5%
SLOAD / GPIO38 NC_1

2
1

+3VS R247 1 2 10K_0402_5% PCH_GPIO39 M3 NV_CLE R217 2 1 1K_0402_5% H_SNB_IVB# [6]

R244 @ R250 @ SDATAOUT0 / GPIO39
10K_0402_5% 10K_0402_5% R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2 Weak internal CLOSE TO THE BRANCHING POINT
SDATAOUT1 / GPIO48 VSS_NCTF_15
PU,Do not pull low
+3VS R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
2

PCH_GPIO37 INTEL_BT_OFF# SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16

+3V_PCH R251 1 2 10K_0402_5% PCH_GPIO57 D6 BH3
GPIO57 VSS_NCTF_17
1

VSS_NCTF_18 BH47
R881
10K_0402_5% R547 A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
10K_0402_5%
2

A44 BJ44
2

B VSS_NCTF_2 VSS_NCTF_20 B

A45 VSS_NCTF_3 VSS_NCTF_21 BJ45

NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46
BIOS Request SKU ID
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5
+3VS A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

2

1
10K_0402_5%

10K_0402_5%

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

BD49 VSS_NCTF_10 VSS_NCTF_28 D49

R711 R246
UMA@ UMA@ BE1 E1
1

VSS_NCTF_11 VSS_NCTF_29
PCH_GPIO38 BE49 E49
VSS_NCTF_12 VSS_NCTF_30
PCH_GPIO67 PCH_GPIO67 [15] BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
2

1
10K_0402_5%

10K_0402_5%

OPT@ R708 R298 OPT@ PANTHER-POINT_FCBGA989

PCH_GPIO38 PCH_GPIO67 Function

1

A A

0 0 Optimus
1 1 UMA Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 19 of 63
5 4 3 2 1
 5 4 3 2 1

L1 Change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
+V1.05S_VCCP U4G POWER +3VS PCH Power Rail Table
@J2
@ J2 1300mA L1 1_0603_1% Refer to CPU EDS R1.5
2 1 +1.05VS_VCCCORE AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23 VCCCORE[2] 1 1 1 1 S0 Iccmax

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212
1 1 1 1 AD21 C395@ Voltage Rail Voltage Current (A)

CRT
VCCCORE[3]

10U_0603_6.3V6M
C209
PAD-OPEN 4x4m AD23 U47 C213 C214 C215 10U_0603_6.3V6M
VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_16V7K 10U_0603_6.3V6M
AF21

VCC CORE
VCCCORE[5] 2 2 2 2
AF23 VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 +3VS D
AG21 VCCCORE[7]
AG23 R02
VCCCORE[8] +VCCA_LVDS R295 2 @
AG24 VCCCORE[9] 1mA VCCALVDS AK36 1 0_0603_5% V5REF 5 0.001
AG26 VCCCORE[10]
AG27 VCCCORE[11] VSSALVDS AK37
AG29 VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
VCCCORE[13]

LVDS
AJ26 AM37 L2
VCCCORE[14] VCCTX_LVDS[1] 0.1UH_MLF1608DR10KT_10%_1608
AJ27 VCCCORE[15]
Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
+V1.05S_VCCP VCCCORE[16] VCCTX_LVDS[2]
AJ31 VCCCORE[17] 1 1 1 0.1uH inductor, 200mA
60mA VCCTX_LVDS[3] AP36 VccADAC 3.3 0.001
C216 C217 C218
R02 AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
R254 2 @ VCCTX_LVDS[4] 2 2 2
1 0_0603_5% +1.05VS_VCCDPLLEXPAN19
VCCIO[28]
VccADPLLA 1.05 0.075
R02
T47 +VCCAPLLEXP BJ22 R256 +3VS VccADPLLB 1.05 0.075
VCCAPLLEXP 0_0603_5%
This pin can be left as no connect in V33 +3VS_VCC3_3_6 2 @ 1
VCC3_3[6]

HVCMOS
AN16 VCCIO[15]
VccCore 1.05 1.3
On-Die VR enabled mode (default). 1
AN17 VCCIO[16]
V34 C219 VccDMI 1.05 0.042
VCC3_3[7]
0.1U_0402_16V7K
2
AN21 VCCIO[17]
VccIO 1.05 3.709
AN26 VCCIO[18]
AN27 3711mA AT16 +VCCAFDI_VRM VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+V1.05S_VCCP 10U AP21 +VCCP_VCCDMI R02 +V1.05S_VCCP
C VCCIO[20] R258 C
VccSPI 3.3 0.01
AP23 AT20 +VCCP_VCCDMI 2 @ 1
VCCIO[21] VCCDMI[1]
1
+V1.05S_VCCP
1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

DMI
1 1 1 1 1 AP24 0_0603_5% VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221

VCCIO
R02 C220
AP26 VCCIO[23] 20mA VCCCLKDMI AB36 +1.05VS_VCC_DMI_CCI R294 2 @ 1 0_0603_5% 1U_0402_6.3V6K
2 VccDFTERM 1.8 0.002
2 2 2 2 2 1
AT24 VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
2
AN33 VCCIO[25]
AN34 VCCIO[26] VCCDFTERM[1] AG16 VccSus3_3 3.3 0.065
+3VS
R02
R260 2 @ 1 0_0603_5% +3VS_VCCA3GBG BH29 AG17 +VCCPNAND +1.8VS VccSusHDA 3.3 / 1.5 0.01
VCC3_3[3] 190mA VCCDFTERM[2]

DFT / SPI
1
C227 R02
0.1U_0402_16V7K AJ16 R293 2 @ 1 0_0603_5% VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3]
2 +VCCAFDI_VRM AP16 VCCVRM[2] 1
AJ17 C228 VccCLKDMI 1.05 0.075
VCCDFTERM[4] 0.1U_0402_16V7K
This pin can be left as no connect in T50 +1.05VS_VCCAPLL_FDI BG6 VccAFDIPLL
On-Die VR enabled mode (default). R02 2 +3VS VccSSC 1.05 0.095
R263 0_0603_5%
2 @ 1 +1.05VS_VCCDPLL_FDI AP17 R02
+V1.05S_VCCP VCCIO[27]
V1 +3V_VCCPSPI R399 1 @ 2 0_0402_5% VccDIFFCLKN 1.05 0.055
FDI

20mA VCCSPI
+VCCP_VCCDMI AU20 VCCDMI[2] 1
VccALVDS 3.3 0.001
C230
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2 VccTX_LVDS 1.8 0.04

+VCCAFDI_VRM
+1.5VS

R02
R265 2 @ 1 0_0603_5% +VCCAFDI_VRM

Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 20 of 63
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS +V1.05S_VCCP R268 @
0_0603_5%
2 1 +VCCACLK
10U For Deep S3
R02
R303
@ +3VALW +V1.05S_VCCP
2 1+3VS_VCC_CLKF33
1 1 R02 U4J POWER

10U_0603_6.3V6M
C231

1U_0402_6.3V6K
C232
0_0603_5% R269 2 @ 1 0_0603_5% +VCCDSW3_3 R20
1 AD49 N26 +1.05VS_VCCUSBCORE R270 2 @ 1 0_0603_5%
VCCACLK VCCIO[29]
2 2 1
C234 P26
0.1U_0402_16V7K VCCIO[30] C233
T16 VCCDSW3_3 3mA
D 2 1U_0402_6.3V6K D
VCCIO[31] P28
2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
C235 @ T29
0.1U_0402_16V7K +3VS_VCC_CLKF33 VCCIO[33] R02 +3V_PCH
On-Die PLL Voltage Regulator T38 VCC3_3[5]
H：On-Die PLL voltage regulator enable R272
T101
T23 +3V_VCCPUSB 2 @ 1
+VCCAPLL_CPY_PCH 119mA VCCSUS3_3[7]
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 BH23 VCCAPLLDMI2 +3V_PCH

0.1U_0402_16V7K
C236
R02 T24 1 0_0603_5% R02
,VCCAPLLSATA R271 2 @ 1 0_0603_5% +VCCDPLL_CPY AL29
VCCSUS3_3[8] R273 +5V_PCH +3V_PCH
+V1.05S_VCCP VCCIO[14]
V23 +3V_VCCAUBG 2 @ 1
VCCSUS3_3[9]

USB
1

2
+VCCSUS1 2 0_0603_5%
AL24 DCPSUS[3] VCCSUS3_3[10] V24
1 C238 R275 D1
P24 0.1U_0402_16V7K 10_0402_5% CH751H-40PT_SOD323-2
@ C239
@C239 VCCSUS3_3[6] 2 R02 +V1.05S_VCCP
1U_0402_6.3V6K AA19 R276

1
2 VCCASW[1] +1.05VS_VCCAUPLL @ +PCH_V5REF_SUS
VCCIO[34] T26 2 1
+V1.05S_VCCP R20 80mil AA21 1010mA
VCCASW[2] 1
@ J16 0_0603_5%
1 1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
2 VCCASW[3] 1mA V5REF_SUS 0.1U_0402_16V7K
1 1 2

22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242
AA26

Clock and Miscellaneous

JUMP_43X79 VCCASW[4] +VCCA_USBSUS C243 @1
DCPSUS[4] AN23 2 1U_0402_6.3V6K
AA27 VCCASW[5]
2 2 +3V_VCCPSUS C316 @1
VCCSUS3_3[1] AN24 2 0.1U_0402_16V7K
AA29 VCCASW[6]
+5VS +3VS
AA31 VCCASW[7]
AC26 P34 +PCH_V5REF_RUN R02 +3V_PCH
VCCASW[8] 1mA V5REF

2
C R278 C
1 1 1

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
AC27 2 @ 1 R279 D2
VCCASW[9] +3V_VCCPSUS CH751H-40PT_SOD323-2
VCCSUS3_3[2] N20 1 10_0402_5%
+V1.05S_VCCP

PCI/GPIO/LPC
AC29 0_0603_5%
2 2 2 VCCASW[10] C247
N22

1
VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
AC31 VCCASW[11]
L5 @ 2 R02 +3VS
VCCSUS3_3[4] P20 1
1 2 +1.05VS_VCCA_A_DPL AD29 R281
VCCASW[12] @ C248
VCCSUS3_3[5] P22 2 1
1

10UH_LB2012T100MR_20% AD31 1 1U_0402_6.3V6K

R300 VCCASW[13] C249 0_0603_5% 2
0_0603_5% W21 AA16 +3VS_VCCPCORE 0.1U_0402_16V7K
VCCASW[14] VCC3_3[1]
@ 2 +3VS
L6 W23 W16 R02
VCCASW[15] VCC3_3[8]
2

1 2 +1.05VS_VCCA_B_DPL R282
10UH_LB2012T100MR_20% W24 T34 +3VS_VCCPPCI 2 @ 1
VCCASW[16] VCC3_3[4]
1 1 1
220U_B2_2.5VM_R35
C250

22U_0805_6.3V6M
C186

1U_0402_6.3V6K
C251

220U_B2_2.5VM_R35
C252

22U_0805_6.3V6M
C187

1U_0402_6.3V6K
C253

1 1 1 1 W26 0_0603_5%
+ + VCCASW[17] C254
@ @ R02 +3VS 0.1U_0402_16V7K
W29 VCCASW[18] R283 2
2 2 2 2 2 2 +VCC3_3_2 @
W31 VCCASW[19] VCC3_3[2] AJ2 2 1
+1.05VS_SATA3 +V1.05S_VCCP
1
W33 0_0603_5% R20
VCCASW[20] R285 2 @
VCCIO[5] AF13 1 0_0603_5%
C255 1
+VCCRTCEXT 2 0.1U_0402_16V7K
N16 DCPRTC
1 AH13 C257
C258 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_16V7K +VCCAFDI_VRM +1.05VS_SATA3 2
Y49 VCCVRM[4] VCCIO[13] AH14
2
B R02 B
VCCIO[6] AF14
+V1.05S_VCCP R274 2 @ 1 0_0603_5% +1.05VS_VCCA_A_DPL BD47 VCCADPLLA 80mA

SATA
AK1 +VCCSATAPLL T100
+1.05VS_VCCA_B_DPL VCCAPLLSATA +VCCAFDI_VRM
1 BF47 VCCADPLLB 80mA On-Die PLL Voltage Regulator
C256 H：On-Die PLL voltage regulator enable
1U_0402_6.3V6K AF11 +VCCAFDI_VRM
+1.05VS_VCCDIFFCLKN +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +V1.05S_VCCP
2
AF17 VCCIO[7] R20
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF33
R02 AF34
VCCDIFFCLKN[1]
55mA AC16 +1.05VS_VCC_SATA R288 2 @ 1 0_0603_5% ,VCCAPLLSATA
R280 2 @ VCCDIFFCLKN[2] VCCIO[2]
+V1.05S_VCCP 1 0_0603_5% +1.05VS_VCCDIFFCLKN AG34 VCCDIFFCLKN[3]
1 VCCIO[3] AC17 1
C261
C259 +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +V1.05S_VCCP
R02 DCPSST
1
+V1.05S_VCCP R284 2 @ 1 0_0603_5% C263
1 0.1U_0402_16V7K +1.05VM_VCCSUS T17 T21
DCPSUS[1] VCCASW[22]
V19 DCPSUS[2]
C262 2
MISC

1U_0402_6.3V6K +V1.05S_VCCP R02 V21

2 R286 VCCASW[23]
CPU

@ R290 2 @ 1 +V_CPU_IO BJ8

0_0603_5% V_PROC_IO 1mA
VCCASW[21] T19
+V1.05S_VCCP 2 1 +1.05VM_VCCSUS 0_0603_5% 1 1 1
+RTCVCC +3V_PCH
4.7U_0603_6.3V6K
C265

0.1U_0402_16V7K
C266

0.1U_0402_16V7K
C267

R02
1 R287
A22 P32 +VCCSUSHDA 2 @ 1
RTC

2 2 2 VCCRTC 10mA VCCSUSHDA

HDA

C264 @ @
1U_0402_6.3V6K
C268

0.1U_0402_16V7K
C269

0.1U_0402_16V7K
C270

1U_0402_6.3V6K 1 1 1 1 0_0603_5%
2 PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V7K A
@
2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/15 2012/07/11 Title
Issued Date Deciphered Date SCHEMATICS,MB A9061
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 21 of 63
5 4 3 2 1
 5 4 3 2 1

U4I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
D U4H D
B15 VSS[164] VSS[264] K7
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42 BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46 BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20 BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24 BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
B B
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2 D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 22 of 63
5 4 3 2 1
 5 4 3 2 1
R02

OVERT#
OVERT# [42]
+3VS_VGA

U65A @
PCH_THRMTRIP#_R [19]

1
PCIE_CTX_GRX_N[0..15]
[5] PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_P0 AN12 Part 1 of 7 @
PEX_RX0

3
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 AM12 P6 GPU_VID4 RV208
[5] PCIE_CTX_GRX_P[0..15] PEX_RX0_N GPIO0 GPU_VID4 [54]
PCIE_CTX_GRX_P1 AN14 M3 GPU_VID3 10K_0402_5% QV7B
PCIE_CRX_GTX_N[0..15] PEX_RX1 GPIO1 GPU_VID3 [54]
PCIE_CTX_GRX_N1 AM14 L6 2N7002KDWH_SOT363-6
[5] PCIE_CRX_GTX_N[0..15]

2
PCIE_CTX_GRX_P2 PEX_RX1_N GPIO2 VGA_GPIO3 0_0402_5%1 @ DPRSLPVR_VGA @
AP14 PEX_RX2 GPIO3 P5 2 5
PCIE_CRX_GTX_P[0..15]

0.1U_0402_16V7K
PCIE_CTX_GRX_N2 AP15 P7 RV113
[5] PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4

@ CV305
PCIE_CTX_GRX_P3 AN15 L7 GPU_VID1 QV7A 1
GPU_VID1 [54]

4
D PCIE_CTX_GRX_N3 PEX_RX3 GPIO5 GPU_VID2 2N7002KDWH_SOT363-6 D
AM15 PEX_RX3_N GPIO6 M7 GPU_VID2 [54]
PCIE_CTX_GRX_P4 AN17 N8 @
PCIE_CTX_GRX_N4 PEX_RX4 GPIO7 OVERT#
AM17 PEX_RX4_N GPIO8 M1 2
PCIE_CTX_GRX_P5 GC6_EVENT#_R 2
AP17 PEX_RX5 GPIO9 M2
PCIE_CTX_GRX_N5 AP18 L1 R02

1
PCIE_CTX_GRX_P6 PEX_RX5_N GPIO10 GPU_VID0
AN18 M5

GPIO
PEX_RX6 GPIO11 GPU_VID0 [54]

1
PCIE_CTX_GRX_N6 VGA_AC_DET_R D
AM18 PEX_RX6_N GPIO12 N3
PCIE_CTX_GRX_P7 AN20 M4 GPU_VID5 PLT_RST_VGA# 2 QV9
PEX_RX7 GPIO13 GPU_VID5 [54]
PCIE_CTX_GRX_N7 AM20 N4 G 2N7002K_SOT23-3
PCIE_CTX_GRX_P8 PEX_RX7_N GPIO14 VGA_GPIO15 100K_0402_5% 1 @
AP20 P2 2 RV17 S @

3
PCIE_CTX_GRX_N8 PEX_RX8 GPIO15 VGA_GPIO16 0_0402_5% 1 @ DPRSLPVR_VGA
AP21 PEX_RX8_N GPIO16 R8 2 RV114 DPRSLPVR_VGA [54]
PCIE_CTX_GRX_P9 AN21 M6
PCIE_CTX_GRX_N9 PEX_RX9 GPIO17
AM21 PEX_RX9_N GPIO18 R1
PCIE_CTX_GRX_P10 AN23 P3
PCIE_CTX_GRX_N10 PEX_RX10 GPIO19
AM23 PEX_RX10_N GPIO20 P4
PCIE_CTX_GRX_P11 AP23 P1
PCIE_CTX_GRX_N11 PEX_RX11 GPIO21
AP24 PEX_RX11_N
PCIE_CTX_GRX_P12 AN24 if GC6 is supported, stuff the BOM option to
PCIE_CTX_GRX_N12 PEX_RX12 pull high to 3.3vs system power, if not, stuff
AM24 PEX_RX12_N
PCIE_CTX_GRX_P13 AN26 the BOM option to pull high to NV3V3;
PCIE_CTX_GRX_N13 PEX_RX13
AM26 PEX_RX13_N For N13P-GS Reserve for GTGE leakage issue
PCIE_CTX_GRX_P14 AP26
PCIE_CTX_GRX_N14 PEX_RX14
AP27 PEX_RX14_N
PCIE_CTX_GRX_P15 AN27 AK9 +3VS +VDD33MISC +VDD33MISC
PCIE_CTX_GRX_N15 PEX_RX15 DACA_RED
AM27 PEX_RX15_N DACA_GREEN AL10
DACA_BLUE AL9

2
GC6_EVENT#_R 1 OPT@ 2

DACs
PCIE_CRX_GTX_P0 CV6 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P0 AK14 RV14 RV15 RV49 2.2K_0402_5%
+VDD33MISC PCIE_CRX_GTX_N0 CV7 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N0 PEX_TX0 VGA_EDID_CLK
1 2 AJ14 PEX_TX0_N DACA_HSYNC AM9 10K_0402_5% 10K_0402_5% 1 OPT@ 2
PCIE_CRX_GTX_P1 CV8 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P1 AH14 AN9 @ OPT@ RV3 2.2K_0402_5%
+VDD33MISC PCIE_CRX_GTX_N1 CV9 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N1 PEX_TX1 DACA_VSYNC VGA_EDID_DATA
1 2 AG14 1 OPT@ 2

1
PCIE_CRX_GTX_P2 CV10 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P2 PEX_TX1_N 10K_0402_5% RV4 2.2K_0402_5%
1 2 AK15 PEX_TX2
2

C PCIE_CRX_GTX_N2 CV11 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N2 AJ15 AG10 +DACA_VDD 2 RV107 1 VGA_AC_DET_R 2 1VGA_AC_DET VGA_CRT_DATA 1 N13P@ 2 C
PEX_TX2_N DACA_VDD VGA_AC_DET [42,54]

PCI EXPRESS
RV24 RV25 PCIE_CRX_GTX_P3 CV12 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P3 AL16 AP9 OPT@ DV3 RV10 2.2K_0402_5%
2.2K_0402_5% 2.2K_0402_5% PCIE_CRX_GTX_N3 CV13 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N3 PEX_TX3 DACA_VREF SDMK0340L-7-F_SOD323-2 VGA_CRT_CLK
1 2 AK16 PEX_TX3_N DACA_RSET AP8 1 N13P@ 2
GL@ GL@ PCIE_CRX_GTX_P4 CV15 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P4 AK17 OPT@ RV11 2.2K_0402_5%
PEX_TX4
5

GL@ PCIE_CRX_GTX_N4 CV17 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N4 AJ17 1 @ 2 I2CB_SCL 1 N13P@ 2

1

QV1B PCIE_CRX_GTX_P5 CV19 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P5 PEX_TX4_N RV130 0_0402_5% RV12 2.2K_0402_5%
1 2 AH17 PEX_TX5
VGA_SMB_CK2 4 3 PCIE_CRX_GTX_N5 CV14 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N5 AG17 I2CB_SDA 1 N13P@ 2
EC_SMB_CK2 [15,39,42] PEX_TX5_N
PCIE_CRX_GTX_P6 CV16 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P6 AK18 RV13 2.2K_0402_5%
2N7002KDWH_SOT363-6 PCIE_CRX_GTX_N6 CV18 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N6 PEX_TX6 OVERT#
1 2 AJ18 PEX_TX6_N 1 OPT@ 2
PCIE_CRX_GTX_P7 CV20 1 2 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_P7 AL19 RV1 2.2K_0402_5%
PCIE_CRX_GTX_N7 CV22 0.22U_0402_6.3V K OPT@ PCIE_CRX_C_GTX_N7 PEX_TX7 VGA_CRT_CLK
1 2 1 2 AK19 PEX_TX7_N I2CA_SCL R4
RV126 GS@0_0402_5% PCIE_CRX_GTX_P8 CV24 1 2 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_P8 AK20 R5 VGA_CRT_DATA 10/22
PCIE_CRX_GTX_N8 CV26 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_N8 PEX_TX8 I2CA_SDA
1 2 AJ20 PEX_TX8_N
2

GL@ PCIE_CRX_GTX_P9 CV21 1 2 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_P9 AH20 R7 I2CB_SCL

QV1A PCIE_CRX_GTX_N9 CV23 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_N9 PEX_TX9 I2CB_SCL I2CB_SDA
1 2 AG20 PEX_TX9_N I2CB_SDA R6
VGA_SMB_DA2 PCIE_CRX_GTX_P10 CV25 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_P10

I2C
1 6 EC_SMB_DA2 [15,39,42] 1 2 AK21 PEX_TX10
PCIE_CRX_GTX_N10 CV27 1 2 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_N10 AJ21 R2 VGA_EDID_CLK
2N7002KDWH_SOT363-6 PCIE_CRX_GTX_P11 CV29 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_P11 PEX_TX10_N I2CC_SCL VGA_EDID_DATA
1 2 AL22 PEX_TX11 I2CC_SDA R3
PCIE_CRX_GTX_N11 CV31 1 2 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_N11 AK22
PCIE_CRX_GTX_P12 CV33 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_P12 PEX_TX11_N VGA_SMB_CK2
1 2 1 2 AK23 PEX_TX12 I2CS_SCL T4
RV137 GS@0_0402_5% PCIE_CRX_GTX_N12 CV28 1 2 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_N12 AJ23 T3 VGA_SMB_DA2
PCIE_CRX_GTX_P13 CV30 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_P13 PEX_TX12_N I2CS_SDA
1 2 AH23 PEX_TX13
PCIE_CRX_GTX_N13 CV32 1 2 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_N13 AG23 +1.05VS_VGA
PCIE_CRX_GTX_P14 CV36 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_P14 PEX_TX13_N
PU AT EC SIDE, +3VS AND 4.7K 1 2 AK24 PEX_TX14 30 ohms @100MHz (ESR=0.05)
PCIE_CRX_GTX_N14 CV41 1 2 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_N14 AJ24
PCIE_CRX_GTX_P15 CV34 0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_P15 PEX_TX14_N R10
PCIE_CRX_GTX_N15 CV35
1 2
0.22U_0402_6.3V K N13P@PCIE_CRX_C_GTX_N15
AL25 PEX_TX15 60mA +PLLVDD LV7 1 OPT@
1 2 AK25 PEX_TX15_N 2 0_0402_5%
+3VS_VGA +3VS_VGA

22U_0805_6.3V6M
0.1U_0402_16V7K

OPT@ CV131

OPT@ CV40
AD8 RV112 1 @ 2 1 1 S SUPPRE_CHILISIN PBY100505T-300Y-N 0402
PLLVDD 0_0402_5%
AJ11 PEX_WAKE_N 45mA SM01000F100
SP_PLLVDD AE8
CLK_PCIE_VGA AL13 45mA
[15] CLK_PCIE_VGA PEX_REFCLK Near GPU
2

B @ CLK_PCIE_VGA# +SP_PLLVDD 2 2 B
[15] CLK_PCIE_VGA# AK13 PEX_REFCLK_N VID_PLLVDD AD7
RV105 CLK_REQ_GPU#

CLK
AK12 PEX_CLKREQ_N
10K_0402_5%
Differential signal 1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN
PEX_TSTCLK_OUT XTAL_IN
5

RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 H2 XTAL_OUT R02

1

PEX_TSTCLK_OUT_N XTAL_OUT Remove RV232

2
P

[18,36,37,42] PLT_RST# B
4 PLT_RST_VGA# AJ12 J4 XTALOUT
Y PEX_TERMP PEX_RST_N XTAL_OUTBUFF XTALSSIN close to YV1
[18] DGPU_HOLD_RST# 1 A AP29 PEX_TERMP XTAL_SSIN H1
G

1
OPT@ 1 2 GCLK_27MHZ
GCLK_27MHZ [44]
3

OPT@ UV2 RV18 RV26 RV27 RV231 0_0402_5%

2

MC74VHC1G08DFT2G_SC70-5 100K_0402_5% 10K_0402_5% 10K_0402_5% OPTGCLK@

RV22 N13P-GL-A1 MP OPT@ OPT@
2.49K_0402_1%
Under GPU
2

2
OPT@ U65 @ U65 GSR@ U65 GLR@
1

Under GPU(below 150mils)

OPT@ 150mA
RV29 10K_0402_5% N13P-GS-A2 N13P-GSR-A2 N13P-GLR-A1 OPT@
2 1 SA000051880 SA00005YR10 SA00005ZS10 +1.05VS_VGA 1 2 +SP_PLLVDD
[18,25] DGPU_PWR_EN

22U_0805_6.3V6M

CV113

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
LV1
+3VS_VGA

OPT@ CV112

CV4

CV5
BLM18PG330SN1D_0603 1 1 1 1
1 180ohms (ESR=0.2) Bead
OPTNOGCLK@

OPT@

OPT@

OPT@
CV42 1 2
2

0.1U_0402_16V7K RV23 10M_0402_5% 2 2 2 2

OPT@ 2 RV30
10K_0402_5%
2

OPT@ YV1
G

4 3 XTAL_OUT
1

A CLK_REQ_GPU# NC OSC A
[15] CLK_REQ_VGA# 1 3
XTALIN 1 2
D

OSC NC
2

QV2 OPT@ 1 27MHZ_16PF_X3G027000FG1H-HX 1

2N7002K_SOT23-3 @ RV32
@RV32 OPTNOGCLK@
10K_0402_5% OPTNOGCLK@ CV37 CV38 OPTNOGCLK@
10P_0402_50V8J 10P_0402_50V8J
2 2
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
1

RV110 @ 0_0402_5%
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 23 of 63
5 4 3 2 1
 5 4 3 2 1

U65D @

Part 4 of 7
AM6 IFPA_TXC
AN6 IFPA_TXC_N NC P8
AP3 IFPA_TXD0 NC AC6
AN3 IFPA_TXD0_N NC AJ28
AN5 IFPA_TXD1 NC AJ4
AM5 IFPA_TXD1_N NC AJ5
AL6 IFPA_TXD2 NC AL11
AK6 IFPA_TXD2_N NC C15

NC
AJ6 IFPA_TXD3 NC D19
D
AH6 IFPA_TXD3_N NC D20 D
NC D23
NC D26
AJ9 IFPB_TXC NC H31
AH9 IFPB_TXC_N NC T8
AP6 IFPB_TXD4 NC V32
AP5 IFPB_TXD4_N
AM7 IFPB_TXD5
AL7 IFPB_TXD5_N
AN8 IFPB_TXD6
AM8 IFPB_TXD6_N
AK8 IFPB_TXD7
AL8 IFPB_TXD7_N
L4 VCCSENSE_VGA VCCSENSE_VGA [54]
VDD_SENSE
AK1 IFPC_L0
AJ1 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA VSSSENSE_VGA [54]
IFPC_L1 GND_SENSE
AJ2 IFPC_L1_N
AH3 IFPC_L2 trace width: 16mils
AH4
AG5
IFPC_L2_N differential voltage sensing.
IFPC_L3
AG4 IFPC_L3_N differential signal routing.
TEST
AM1 AK11 TESTMODE
IFPD_L0 TESTMODE
AM2 IFPD_L0_N
AM3 IFPD_L1 JTAG_TCK AM10 TV2

1
AM4 IFPD_L1_N JTAG_TDI AM11 TV3
AL3 IFPD_L2 JTAG_TDO AP12 TV4
C AL4 AP11 10K_0402_5% C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
IFPD_L3 JTAG_TRST_N RV34 OPT@ 10K_0402_5% OPT@
AK5

2
IFPD_L3_N

LVDS/TMDS
AD2 IFPE_L0
AD3 IFPE_L0_N
AD1
AC1
IFPE_L1 SERIAL
IFPE_L1_N ROM_CS
AC2 IFPE_L2 ROM_CS_N H6
AC3 H4 ROM_SCLK ROM_SCLK [32]
IFPE_L2_N ROM_SCLK ROM_SI
AC4 IFPE_L3 ROM_SI H5 ROM_SI [32]
AC5 H7 ROM_SO ROM_SO [32]
IFPE_L3_N ROM_SO

AE3 IFPF_L0
AE4 IFPF_L0_N
AF4 IFPF_L1
AF5
AD4
IFPF_L1_N GENERAL RV35 10K_0402_5%
IFPF_L2
AD5 IFPF_L2_N BUFRST_N L2 2 OPT@ 1
AG1 IFPF_L3
AF1 IFPF_L3_N CEC L3 1 2 +3VS_VGA
RV230 GL@ 10K_0402_5% 3V3 on N13P-GL/ for CEC signal
MULTI_STRAP_REF0_GND J1 1 2
RV38 N13P@40.2K_0402_1%
AG3 IFPC_AUX_I2CW_SCL
AG2 IFPC_AUX_I2CW_SDA_N
J2 STRAP0 STRAP0 [32]
STRAP0 STRAP1
B STRAP1 J7 STRAP1 [32] B
AK3 J6 STRAP2 STRAP2 [32]
IFPD_AUX_I2CX_SCL STRAP2 STRAP3
AK2 IFPD_AUX_I2CX_SDA_N STRAP3 J5 STRAP3 [32]
J3 STRAP4 STRAP4 [32]
STRAP4
AB3 IFPE_AUX_I2CY_SCL
AB4 IFPE_AUX_I2CY_SDA_N
THERMDP K3
THERMDN K4
AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N

Reserve 1MB SPI ROM FOR VBIOS ROM

+3VS_VGA
CV295
N13P-GL-A1 MP
2 1
20mils

1
0.1U_0402_16V7K
@ RV229 @ @ RV225
10K_0402_5% 10K_0402_5%

2
@ RV224 0_0402_5% UV15
ROM_CS 1 2 ROM_CS_R 1 8
ROM_SO ROM_SO_R CS# VCC ROM_HOLD#
1 2 2 DO HOLD# 7
@ RV226 0_0402_5% 3 6
WP# CLK @ RV228 0_0402_5%
4 GND DIO 5
ROM_SCLK_R 1 2 ROM_SCLK
A MX25L1005AMC-12G_SO8 ROM_SI_R 1 2 ROM_SI A
@ @ RV227 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 24 of 63
5 4 3 2 1
 5 4 3 2 1

+1.5VS_VGA U65E @
Near GPU
Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
D AA27 FBVDDQ_0 PEX_IOVDD_0 AG19 D

OPT@ CV273

OPT@ CV269

OPT@ CV270

OPT@ CV271

OPT@ CV272
22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AA30 FBVDDQ_1 PEX_IOVDD_1 AG21

OPT@ CV43

OPT@ CV44

OPT@ CV45

OPT@ CV46

OPT@ CV47

OPT@ CV48

OPT@ CV49

OPT@ CV50

OPT@ CV51

OPT@ CV52
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 2 2 2 2 AB27 FBVDDQ_2 PEX_IOVDD_2 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_3 PEX_IOVDD_3 AG24
AC27 FBVDDQ_4 PEX_IOVDD_4 AH21
AD27 FBVDDQ_5 PEX_IOVDD_5 AH25
2 1 1 1 1 AE27 2 2 2 2 2 2 1 1 1 1
FBVDDQ_6
AF27 FBVDDQ_7
+1.5VS_VGA 0.1uF X7R 0402 * 8 AG27 AG13
FBVDDQ_8 PEX_IOVDDQ_0
4.7uF X7R 0402 * 2 B13 FBVDDQ_9 PEX_IOVDDQ_1 AG15 Under GPU(below 150mils) +1.05VS_VGA
B16 FBVDDQ_10 PEX_IOVDDQ_2 AG16 For N13P-GS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
Under GPU(below 150mils) B19 FBVDDQ_11 PEX_IOVDDQ_3 AG18

OPT@ CV54

OPT@ CV53

OPT@ CV56

OPT@ CV55
1uF X7R 0402 * 2 E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25 1 1 1 1
E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
E19 AH18 DGPU_PWR_EN#
FBVDDQ_14 PEX_IOVDDQ_6
OPT@ CV267

OPT@ CV268

OPT@ CV277

OPT@ CV278

OPT@CV279
CV279

OPT@CV280
CV280

OPT@CV292
CV292

OPT@CV287
CV287

OPT@CV294
CV294

OPT@CV284
CV284

OPT@CV285
CV285

OPT@CV286
CV286
1U_0402_6.3V6K

1U_0402_6.3V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 H10 FBVDDQ_15 PEX_IOVDDQ_7 AH26

H11 AH27 2 2 2 2 +VDD33MISC +3VS_VGA
FBVDDQ_16 PEX_IOVDDQ_8

2
G
H12 AJ27 DMG2301U-7_SOT23-3 QV8
FBVDDQ_17 PEX_IOVDDQ_9
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
H13 FBVDDQ_18 PEX_IOVDDQ_10 AK27
2 2 2 2 2 2 2 2 2 2 2 2 +VDD33MISC
H14 AL27 3 1

POWER
FBVDDQ_19 PEX_IOVDDQ_11

0.1U_0402_16V7K

0.1U_0402_16V7K

D
H15 FBVDDQ_20 PEX_IOVDDQ_12 AM28

GS@ CV72

GS@ CV105
H16 AN28 For N13P-GS Under GPU(below 150mils) 1 1 GS@
FBVDDQ_21 PEX_IOVDDQ_13
H18 FBVDDQ_22
H19 +3VS_VGA GL@
FBVDDQ_23
H20 FBVDDQ_24 1 2
+PEX_PLLHVDD RV138 1 GS@ 2 0_0402_5% 2 2

0.1U_0402_16V7K
RV140 0_0402_5%

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H21 FBVDDQ_25 PEX_PLL_HVDD AH12
+3VS

OPT@ CV70

OPT@ CV74

OPT@ CV73
H22 FBVDDQ_26 1 1 1
H23 FBVDDQ_27
H24 FBVDDQ_28 1 2
H8 AG12 +PEX_SVDD3V3 RV154 @ 0_0402_5%
FBVDDQ_29 PEX_SVDD_3V3 2 2 2
H9
rise 1.5v system source voltage to 1.55-1.57V L27
FBVDDQ_30
FBVDDQ_31
M27 FBVDDQ_32
N27 AG26 +PEX_PLLVDD
FBVDDQ_33 PEX_PLLVDD
C
P27 FBVDDQ_34 C
R27 +VDD33MISC
FBVDDQ_35
T27 FBVDDQ_36
T30 J8 +3VS_VGA
FBVDDQ_37 VDD33_0
T33 FBVDDQ_38 VDD33_1 K8 Place near balls Place near GPU R20
V27 FBVDDQ_39 VDD33_2 L8
W27 M8 +VDD33 RV5 2 @ 1 0_0603_5%
FBVDDQ_40 VDD33_3 LV2

0.1U_0402_16V7K

0.1U_0402_16V7K

4.7U_0603_6.3V6K
W30 FBVDDQ_41
+1.5VS_VGA

OPT@ CV109

OPT@ CV111

OPT@ CV293

OPT@ CV75
1U_0402_6.3V6K
W33 FBVDDQ_42 1 1 1 1
Y27 N13P@
FBVDDQ_43
IFPAB_PLLVDD AH8 +IFPAB_PLLVDD1 RV48 2 10K_0402_5%
AJ8 RV40@1 2 1K_0402_1%
10_0402_5% 2 @ IFPAB_RSET 2 2 2 2
1 RV141 FB_VDDQ_SENSE N13P@ GS@
AG8 +IFPAB_IOVDD 1 RV65 2 10K_0402_5% 0_0603_5%
IFPA_IOVDD
IFPB_IOVDD AG9
10_0402_5% 2 @ 1 RV142 FB_VSS_SENSE F1 FB_VDDQ_SENSE N13P@ CV5 Place Under GPU +1.05VS_VGA
IFPC_PLLVDD AF7 +IFPC_PLLVDD 1 RV42 2 10K_0402_5%
+1.5VS_VGA F2 AF8 RV43@2 1 1K_0402_1% Reserve for NV DG LV2 GL@
FB_GND_SENSE IFPC_RSET N13P@ +PEX_PLLVDD 120mA 2 1

CV66
AF6 +IFPC_IOVDD 1 RV44 2 10K_0402_5% +VDD33

0.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
IFPC_IOVDD

OPT@ CV65

CV3
1 OPT@

0.1U_0402_16V7K

0.1U_0402_16V7K
2 J27 1 1 1 BLM18PG121SN1D_0603
FB_CAL_PD_VDDQ

CV303

CV304
RV6 40.2_0402_1% N13P@ 120ohms @100MHz (ESR=0.18)
CALIBRATION PIN DDR3 AG7 +IFPD_PLLVDD 1 RV45 2 10K_0402_5%
1 1
IFPD_PLLVDD

OPT@

OPT@

OPT@
1 OPT@ 2 H27 FB_CAL_PU_GND IFPD_RSET AN2 RV46@1 2 1K_0402_1%
2 2 2

OPT@
RV8 42.2_0402_1% N13P@
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD 1 RV47 2 10K_0402_5% 2 2
IFPD_IOVDD
1 OPT@ 2 H25 FB_CAL_TERM_GND
RV9 51.1_0402_1% N13P@
FB_CAL_x_PU_GND 42.2Ohm AB8 +IFPEF_PLLVDD1 RV72 2 10K_0402_5% CV3 ,CV66 Place near balls
IFPEF_PLVDD RV50@1
IFPEF_RSET AD6 2 1K_0402_1%
FB_CAL_xTERM_GND 51.1Ohm Place near balls AC7 N13P@ Inc 2pcs 0.1u
IFPE_IOVDD +IFPE_IOVDD1 RV73
AC8 2 10K_0402_5%
IFPF_IOVDD following DG
B B

N13P-GL-A1 MP
+3VS to +3VS_VGA

+3VS +3VS_VGA
J10

@
1 1 2 2

JUMP_43X79
+5VALW
QV5 CV57
LP2301ALT1G_SOT23 10U_0603_6.3V6M

D
R1109 @ 3 1 2 1
0_0402_5% R1103

1
2 1 100K_0402_5% OPT@ OPT@
[10,42,46,51,53,54] SUSP#
OPT@

G
2

2
RV205 @ RV206
R02 DGPU_PWR_EN# 1 2 470_0603_5%
R1452 10K_0402_5%

1 2
1
0_0402_5% D OPT@ 1 CV241
2 @ 1 2 Q128 0.1U_0402_16V7K D RV207 @
[18,23] DGPU_PWR_EN
G 2N7002K_SOT23-3 2 2 1DGPU_PWR_EN#
S OPT@ OPT@ QV6 @ G

3
2 S 10K_0402_5%

3
1
2N7002K_SOT23-3

R1105

@ CV242
100K_0402_5%

0.1U_0402_16V7K
1
OPT@

2
A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 25 of 63
5 4 3 2 1
 5 4 3 2 1

U65F @

Part 6 of 7
A2 GND_0 GND_100 D2
AA17 GND_1 GND_101 D31
AA18 GND_2 GND_102 D33
AA20 E10 U65G @ +VGA_CORE
GND_3 GND_103 +VGA_CORE
AA22 GND_4 GND_104 E22
AB12 GND_5 GND_105 E25
AB14 E5 Part 7 of 7 V17
GND_6 GND_106 VDD_56
AB16 GND_7 GND_107 E7 AA12 VDD_0 VDD_57 V18
AB19 GND_8 GND_108 F28 AA14 VDD_1 VDD_58 V20
AB2 GND_9 GND_109 F7 AA16 VDD_2 VDD_59 V22
D
AB21 GND_10 GND_110 G10 AA19 VDD_3 VDD_60 W12 D
A33 GND_11 GND_111 G13 AA21 VDD_4 VDD_61 W14
AB23 GND_12 GND_112 G16 AA23 VDD_5 VDD_62 W16
AB28 GND_13 GND_113 G19 AB13 VDD_6 VDD_63 W19
AB30 GND_14 GND_114 G2 AB15 VDD_7 VDD_64 W21
AB32 GND_15 GND_115 G22 AB17 VDD_8 VDD_65 W23
AB5 GND_16 GND_116 G25 AB18 VDD_9 VDD_66 Y13
AB7 GND_17 GND_117 G28 AB20 VDD_10 VDD_67 Y15
AC13 GND_18 GND_118 G3 AB22 VDD_11 VDD_68 Y17
AC15 GND_19 GND_119 G30 AC12 VDD_12 VDD_69 Y18
AC17 GND_20 GND_120 G32 AC14 VDD_13 VDD_70 Y20
AC18 GND_21 GND_121 G33 AC16 VDD_14 VDD_71 Y22
AA13 GND_22 GND_122 G5 AC19 VDD_15
AC20 GND_23 GND_123 G7 AC21 VDD_16
AC22 GND_24 GND_124 K2 AC23 VDD_17 XVDD_1 U1
AE2 GND_25 GND_125 K28 M12 VDD_18 XVDD_2 U2
AE28 GND_26 GND_126 K30 M14 VDD_19 XVDD_3 U3

POWER
AE30 GND_27 GND_127 K32 M16 VDD_20 XVDD_4 U4
AE32 GND_28 GND_128 K33 M19 VDD_21 XVDD_5 U5
AE33 GND_29 GND_129 K5 M21 VDD_22 XVDD_6 U6
AE5 GND_30 GND_130 K7 M23 VDD_23 XVDD_7 U7
AE7 GND_31 GND_131 M13 N13 VDD_24 XVDD_8 U8
AH10 GND_32 GND_132 M15 N15 VDD_25
AA15 GND_33 GND_133 M17 N17 VDD_26
AH13 GND_34 GND_134 M18 N18 VDD_27 XVDD_9 V1
AH16 GND_35 GND_135 M20 N20 VDD_28 XVDD_10 V2
AH19 GND_36 GND_136 M22 N22 VDD_29 XVDD_11 V3
AH2 GND_37 GND_137 N12 P12 VDD_30 XVDD_12 V4
AH22 GND_38 GND_138 N14 P14 VDD_31 XVDD_13 V5
AH24 GND_39 GND_139 N16 P16 VDD_32 XVDD_14 V6
C AH28 GND_40 GND_140 N19 P19 VDD_33 XVDD_15 V7 C
AH29 GND_41 GND_141 N2 P21 VDD_34 XVDD_16 V8
AH30 GND_42 GND_142 N21 P23 VDD_35
GND
AH32 GND_43 GND_143 N23 R13 VDD_36
AH33 GND_44 GND_144 N28 R15 VDD_37 XVDD_17 W2
AH5 GND_45 GND_145 N30 R17 VDD_38 XVDD_18 W3
AH7 GND_46 GND_146 N32 R18 VDD_39 XVDD_19 W4
AJ7 GND_47 GND_147 N33 R20 VDD_40 XVDD_20 W5
AK10 GND_48 GND_148 N5 R22 VDD_41 XVDD_21 W7
AK7 GND_49 GND_149 N7 T12 VDD_42 XVDD_22 W8
AL12 GND_50 GND_150 P13 T14 VDD_43
AL14 GND_51 GND_151 P15 T16 VDD_44
AL15 GND_52 GND_152 P17 T19 VDD_45 XVDD_23 Y1
AL17 GND_53 GND_153 P18 T21 VDD_46 XVDD_24 Y2
AL18 GND_54 GND_154 P20 T23 VDD_47 XVDD_25 Y3
AL2 GND_55 GND_155 P22 U13 VDD_48 XVDD_26 Y4
AL20 GND_56 GND_156 R12 U15 VDD_49 XVDD_27 Y5
AL21 GND_57 GND_157 R14 U17 VDD_50 XVDD_28 Y6
AL23 GND_58 GND_158 R16 U18 VDD_51 XVDD_29 Y7
AL24 GND_59 GND_159 R19 U20 VDD_52 XVDD_30 Y8
AL26 GND_60 GND_160 R21 U22 VDD_53
AL28 GND_61 GND_161 R23 V13 VDD_54
AL30 GND_62 GND_162 T13 V15 VDD_55 XVDD_31 AA1
AL32 GND_63 GND_163 T15 XVDD_32 AA2
AL33 GND_64 GND_164 T17 XVDD_33 AA3
AL5 GND_65 GND_165 T18 XVDD_34 AA4
AM13 GND_66 GND_166 T2 XVDD_35 AA5
AM16 GND_67 GND_167 T20 XVDD_36 AA6
AM19 GND_68 GND_168 T22 XVDD_37 AA7
B
AM22 GND_69 GND_169 AG11 XVDD_38 AA8 B
AM25 GND_70 GND_170 T28
AN1 GND_71 GND_171 T32
AN10 GND_72 GND_172 T5
AN13 GND_73 GND_173 T7
AN16 U12 N13P-GL-A1 MP
GND_74 GND_174
AN19 GND_75 GND_175 U14
AN22 GND_76 GND_176 U16
AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
B22 GND_86 GND_186 W13
B25 GND_87 GND_187 W15
B28 GND_88 GND_188 W17
B31 GND_89 GND_189 W18
B34 GND_90 GND_190 W20
B4 GND_91 GND_191 W22
B7 GND_92 GND_192 W28
C10 GND_93 GND_193 Y12
C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
C22 GND_96 GND_196 Y19
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
A C7 GND_99 GND_199 AH11 A

GND_OPT C16
GND_OPT W32

N13P-GL-A1 MP Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 26 of 63
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] FBA_MA[15..0] [28,29] FBC_D[0..63] FBC_MA[15..0] [30,31]

[28,29] FBA_D[0..63] [30,31] FBC_D[0..63]
FBA_BA[2..0] [28,29] FBC_BA[2..0] [30,31]

U65C @
U65B @
Part 3 of 7
Part 2 of 7 FBC_D0 G9 D13 FBC_CS0#_L
FBB_D0 FBB_CMD0 FBC_CS0#_L [30]
FBA_D0 L28 U30 FBA_CS0#_L FBC_D1 E9 E14
FBA_D0 FBA_CMD0 FBA_CS0#_L [28] FBB_D1 FBB_CMD1
FBA_D1 M29 T31 FBC_D2 G8 F14 FBC_ODT_L
FBA_D1 FBA_CMD1 FBB_D2 FBB_CMD2 FBC_ODT_L [30]
FBA_D2 L29 U29 FBA_ODT_L FBC_D3 F9 A12 FBC_CKE_L
FBA_D2 FBA_CMD2 FBA_ODT_L [28] FBB_D3 FBB_CMD3 FBC_CKE_L [30]
FBA_D3 M28 R34 FBA_CKE_L FBC_D4 F11 B12 FBC_MA14
FBA_D3 FBA_CMD3 FBA_CKE_L [28] FBB_D4 FBB_CMD4
FBA_D4 N31 R33 FBA_MA14 FBC_D5 G11 C14 FBC_RST#
D FBA_D4 FBA_CMD4 FBB_D5 FBB_CMD5 FBC_RST# [30,31] D
FBA_D5 P29 U32 FBA_RST# FBC_D6 F12 B14 FBC_MA9
FBA_D5 FBA_CMD5 FBA_RST# [28,29] FBB_D6 FBB_CMD6
FBA_D6 R29 U33 FBA_MA9 FBC_D7 G12 G15 FBC_MA7
FBA_D7 FBA_D6 FBA_CMD6 FBA_MA7 FBC_D8 FBB_D7 FBB_CMD7 FBC_MA2
P28 FBA_D7 FBA_CMD7 U28 G6 FBB_D8 FBB_CMD8 F15
FBA_D8 J28 V28 FBA_MA2 FBC_D9 F5 E15 FBC_MA0
FBA_D9 FBA_D8 FBA_CMD8 FBA_MA0 FBC_D10 FBB_D9 FBB_CMD9 FBC_MA4
H29 FBA_D9 FBA_CMD9 V29 E6 FBB_D10 FBB_CMD10 D15
FBA_D10 J29 V30 FBA_MA4 FBC_D11 F6 A14 FBC_MA1
FBA_D11 FBA_D10 FBA_CMD10 FBA_MA1 FBC_D12 FBB_D11 FBB_CMD11 FBC_BA0
H28 FBA_D11 FBA_CMD11 U34 F4 FBB_D12 FBB_CMD12 D14
FBA_D12 G29 U31 FBA_BA0 FBC_D13 G4 A15 FBC_WE#
FBA_D12 FBA_CMD12 FBB_D13 FBB_CMD13 FBC_WE# [30,31]
FBA_D13 E31 V34 FBA_WE# FBC_D14 E2 B15 FBC_MA15
FBA_D13 FBA_CMD13 FBA_WE# [28,29] FBB_D14 FBB_CMD14
FBA_D14 E32 V33 FBA_MA15 FBC_D15 F3 C17 FBC_CAS#
FBA_D14 FBA_CMD14 FBB_D15 FBB_CMD15 FBC_CAS# [30,31]
FBA_D15 F30 Y32 FBA_CAS# FBC_D16 C2 D18 FBC_CS0#_H
FBA_D15 FBA_CMD15 FBA_CAS# [28,29] FBB_D16 FBB_CMD16 FBC_CS0#_H [31]
FBA_D16 C34 AA31 FBA_CS0#_H FBC_D17 D4 E18
FBA_D16 FBA_CMD16 FBA_CS0#_H [29] FBB_D17 FBB_CMD17
FBA_D17 D32 AA29 FBC_D18 D3 F18 FBC_ODT_H
FBA_D17 FBA_CMD17 FBB_D18 FBB_CMD18 FBC_ODT_H [31]
FBA_D18 B33 AA28 FBA_ODT_H FBC_D19 C1 A20 FBC_CKE_H
FBA_D18 FBA_CMD18 FBA_ODT_H [29] FBB_D19 FBB_CMD19 FBC_CKE_H [31]
FBA_D19 C33 AC34 FBA_CKE_H FBC_D20 B3 B20 FBC_MA13
FBA_D19 FBA_CMD19 FBA_CKE_H [29] FBB_D20 FBB_CMD20
FBA_D20 F33 AC33 FBA_MA13 FBC_D21 C4 C18 FBC_MA8
FBA_D21 FBA_D20 FBA_CMD20 FBA_MA8 FBC_D22 FBB_D21 FBB_CMD21 FBC_MA6
F32 FBA_D21 FBA_CMD21 AA32 B5 FBB_D22 FBB_CMD22 B18
FBA_D22 H33 AA33 FBA_MA6 FBC_D23 C5 G18 FBC_MA11
FBA_D23 H32
FBA_D22
FBA_D23
FBA_CMD22
FBA_CMD23 Y28 FBA_MA11 FBC_D24 A11
FBB_D23
FBB_D24
FBB_CMD23
FBB_CMD24 G17 FBC_MA5 Mode D - Mirror Mode Mapping
MEMORY INTERFACE

FBA_D24 P34 Y29 FBA_MA5 FBC_D25 C11 F17 FBC_MA3

MEMORY INTERFACE B
FBA_D25 FBA_D24 FBA_CMD24 FBA_MA3 FBC_D26 FBB_D25 FBB_CMD25 FBC_BA2
P32 FBA_D25 FBA_CMD25 W31 D11 FBB_D26 FBB_CMD26 D16
FBA_D26 P31 Y30 FBA_BA2 FBC_D27 B11 A18 FBC_BA1
FBA_D27 FBA_D26 FBA_CMD26 FBA_BA1 FBC_D28 FBB_D27 FBB_CMD27 FBC_MA12
P33 FBA_D27 FBA_CMD27 AA34 D8 FBB_D28 FBB_CMD28 D17 DATA Bus
FBA_D28 L31 Y31 FBA_MA12 FBC_D29 A8 A17 FBC_MA10
FBA_D29 FBA_D28 FBA_CMD28 FBA_MA10 FBC_D30 FBB_D29 FBB_CMD29 FBC_RAS# Address
L34 FBA_D29 FBA_CMD29 Y34 C8 FBB_D30 FBB_CMD30 B17 FBC_RAS# [30,31] 0..31 32..63
FBA_D30 L32 Y33 FBA_RAS# FBC_D31 B8 E17
FBA_D30 FBA_CMD30 FBA_RAS# [28,29] FBB_D31 FBB_CMD31
FBA_D31 L33 V31 FBC_D32 F24 FBx_CMD0 CS0#_L
FBA_D32 FBA_D31 FBA_CMD31 FBC_D33 FBB_D32
AG28 FBA_D32 G23 FBB_D33
FBA_D33 AF29 FBC_D34 E24 FBx_CMD1
FBA_D34 FBA_D33 FBC_D35 FBB_D34
AG29 FBA_D34 G24 FBB_D35 FBB_CMD_RFU0 C12
FBA_D35 AF28 R32 FBC_D36 D21 C20 FBx_CMD2 ODT_L
FBA_D36 FBA_D35 FBA_CMD_RFU0 FBC_D37 FBB_D36 FBB_CMD_RFU1
AD30 FBA_D36 FBA_CMD_RFU1 AC32 E21 FBB_D37
C FBA_D37 AD29 +1.5VS_VGA FBC_D38 G21 +1.5VS_VGA FBx_CMD3 CKE_L C
FBA_D38 FBA_D37 FBC_D39 FBB_D38
AC29 FBA_D38 F21 FBB_D39
FBA_D39 AD28 FBC_D40 G27 G14 RV60 1 @ 2 60.4_0402_1% FBx_CMD4 A14 A14
FBA_D39 FBB_D40 FBB_DEBUG0
A

FBA_D40 AJ29 R28 RV58 1 @ 2 60.4_0402_1% FBC_D41 D27 G20 RV61 1 @ 2 60.4_0402_1%
FBA_D41 FBA_D40 FBA_DEBUG0 RV59 @ FBB_D41 FBB_DEBUG1
AK29 FBA_D41 FBA_DEBUG1 AC28 1 2 60.4_0402_1% FBC_D42 G26 FBB_D42 can be unstuff by default FBx_CMD5 RST RST
FBA_D42 AJ30 can be unstuff by default FBC_D43 E27
FBA_D43 FBA_D42 FBC_D44 FBB_D43
AK28 FBA_D43 E29 FBB_D44 FBx_CMD6 A9 A9
FBA_D44 AM29 FBC_D45 F29 D12 FBC_CLK0
FBA_D44 FBB_D45 FBB_CLK0 FBC_CLK0 [30]
FBA_D45 AM31 R30 FBA_CLK0 FBC_D46 E30 E12 FBC_CLK0# FBx_CMD7 A7 A7
FBA_D45 FBA_CLK0 FBA_CLK0 [28] FBB_D46 FBB_CLK0_N FBC_CLK0# [30]
FBA_D46 AN29 R31 FBA_CLK0# FBC_D47 D30 E20 FBC_CLK1
FBA_D46 FBA_CLK0_N FBA_CLK0# [28] FBB_D47 FBB_CLK1 FBC_CLK1 [31]
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D48 A32 F20 FBC_CLK1# FBx_CMD8 A2 A2
FBA_D47 FBA_CLK1 FBA_CLK1 [29] FBB_D48 FBB_CLK1_N FBC_CLK1# [31]
FBA_D48 AN31 AC31 FBA_CLK1# FBC_D49 C31
FBA_D48 FBA_CLK1_N FBA_CLK1# [29] FBB_D49
FBA_D49 AN32 FBC_D50 C32 FBx_CMD9 A0 A0
FBA_D50 FBA_D49 FBC_D51 FBB_D50
AP30 FBA_D50 B32 FBB_D51
FBA_D51 AP32 FBC_D52 D29 F8 FBx_CMD10 A4 A4
FBA_D52 FBA_D51 FBC_D53 FBB_D52 FBB_WCK01
AM33 FBA_D52 FBA_WCK01 K31 A29 FBB_D53 FBB_WCK01_N E8
FBA_D53 AL31 L30 FBC_D54 C29 A5 FBx_CMD11 A1 A1
FBA_D54 FBA_D53 FBA_WCK01_N FBC_D55 FBB_D54 FBB_WCK23
AK33 FBA_D54 FBA_WCK23 H34 B29 FBB_D55 FBB_WCK23_N A6
FBA_D55 AK32 J34 FBC_D56 B21 D24 FBx_CMD12 BA0 BA0
FBA_D56 FBA_D55 FBA_WCK23_N FBC_D57 FBB_D56 FBB_WCK45
AD34 FBA_D56 FBA_WCK45 AG30 C23 FBB_D57 FBB_WCK45_N D25
FBA_D57 AD32 AG31 FBC_D58 A21 B27 FBx_CMD13 WE# WE#
FBA_D58 FBA_D57 FBA_WCK45_N FBC_D59 FBB_D58 FBB_WCK67
AC30 FBA_D58 FBA_WCK67 AJ34 C21 FBB_D59 FBB_WCK67_N C27
FBA_D59 AD33 AK34 FBC_D60 B24 FBx_CMD14 A15 A15
FBA_D60 FBA_D59 FBA_WCK67_N FBC_D61 FBB_D60
AF31 FBA_D60 C24 FBB_D61
FBA_D61 AG34 +1.05VS_VGA +FB_PLLAVDD FBC_D62 B26 FBx_CMD15 CAS# CAS#
FBA_D62 FBA_D61 FBC_D63 FBB_D62
AG32 FBA_D62
Place close to BGA C26 FBB_D63 FBB_WCKB01 D6
FBA_D63 AG33 J30 200mA D7 FBx_CMD16 CS0#_H
FBA_D63 FBA_WCKB01 FBMA-L11-160808300LMA25T_2P FBC_DQM0 FBB_WCKB01_N
FBA_WCKB01_N J31 E11 FBB_DQM0 FBB_WCKB23 C6
FBA_DQM0 P30 J32 1 OPT@ 2 +FB_PLLAVDD FBC_DQM1 E3 B6 FBx_CMD17
FBA_DQM1 FBA_DQM0 FBA_WCKB23 LV3 FBC_DQM2 FBB_DQM1 FBB_WCKB23_N
F31 FBA_DQM1 FBA_WCKB23_N J33 A3 FBB_DQM2 FBB_WCKB45 F26
FBA_DQM2 F34 AH31 FBC_DQM3 C9 E26 FBx_CMD18 ODT_H
FBA_DQM3 FBA_DQM2 FBA_WCKB45 FBC_DQM4 FBB_DQM3 FBB_WCKB45_N
M32 FBA_DQM3 FBA_WCKB45_N AJ31 F23 FBB_DQM4 FBB_WCKB67 A26
B FBA_DQM4 FBC_DQM5 B
AD31 FBA_DQM4 FBA_WCKB67 AJ32 F27 FBB_DQM5 FBB_WCKB67_N A27 FBx_CMD19 CKE_H
FBA_DQM5 AL29 AJ33 FBC_DQM6 C30
FBA_DQM6 FBA_DQM5 FBA_WCKB67_N FBC_DQM7 FBB_DQM6
AM32 FBA_DQM6 A24 FBB_DQM7 FBx_CMD20 A13 A13
FBA_DQM7 AF34 FBA_DQM7 RV66 10K_0402_5% FBC_DQS0 D10 FBB_DQS_WP0 FBx_CMD21 A8 A8
FBA_DQS0 M31 E1 FB_CLAMP 2 GS@ 1 FBC_DQS1 D5
FBA_DQS1 FBA_DQS_WP0 FB_CLAMP FBC_DQS2 FBB_DQS_WP1
G31 FBA_DQS_WP1 +FB_PLLAVDD C3 FBB_DQS_WP2 FBx_CMD22 A6 A6
FBA_DQS2 E33 FBC_DQS3 B9
FBA_DQS3 FBA_DQS_WP2 CV106 OPT@ 0.1U_0402_16V7K FBC_DQS4 FBB_DQS_WP3
M33 FBA_DQS_WP3 E23 FBB_DQS_WP4 FBB_PLL_AVDD H17 +FB_PLLAVDD FBx_CMD23 A11 A11

0.1U_0402_16V7K
FBA_DQS4 AE31 K27 1 2 FBC_DQS5 E28
FBA_DQS_WP4 FB_DLL_AVDD FBB_DQS_WP5

OPT@ CV108
FBA_DQS5 AK30 FBC_DQS6 B30 1 FBx_CMD24 A5 A5
FBA_DQS6 FBA_DQS_WP5 FBC_DQS7 FBB_DQS_WP6
AN33 FBA_DQS_WP6
Place close to ball A23 FBB_DQS_WP7
FBA_DQS7 AF33 FBx_CMD25 A3 A3
FBA_DQS_WP7 FBC_DQS#0
FBA_PLL_AVDD U27 +FB_PLLAVDD D9 FBB_DQS_RN0 2
22U_0805_6.3V6M
0.1U_0402_16V7K

FBA_DQS#0 M30 FBC_DQS#1 E4 FBx_CMD26 BA2 BA2

FBA_DQS_RN0 FBB_DQS_RN1
OPT@ CV107

OPT@ CV110

OPT@ CV39
1U_0402_6.3V6K

FBA_DQS#1 H30 1 1 1 FBC_DQS#2 B2

FBA_DQS#2 FBA_DQS_RN1 FBC_DQS#3 FBB_DQS_RN2
E34 FBA_DQS_RN2 A9 FBB_DQS_RN3 FBx_CMD27 BA1 BA1
FBA_DQS#3 M34 H26 FBC_DQS#4 D22
FBA_DQS#4 FBA_DQS_RN3 FB_VREF FBC_DQS#5 FBB_DQS_RN4
AF30 FBA_DQS_RN4 D28 FBB_DQS_RN5
Place close to ball FBx_CMD28 A12 A12
FBA_DQS#5 2 2 2 FBC_DQS#6
AK31 FBA_DQS_RN5 A30 FBB_DQS_RN6
FBA_DQS#6 AM34 FBC_DQS#7 B23 FBx_CMD29 A10 A10
FBA_DQS#7 FBA_DQS_RN6 FBB_DQS_RN7
AF32 FBA_DQS_RN7
FBx_CMD30 RAS# RAS#
Place close to ball Place close to BGA
N13P-GL-A1 MP
N13P-GL-A1 MP

[30,31] FBC_DQM[7..0]
[28,29] FBA_DQM[7..0] [30,31] FBC_DQS[7..0]
A [28,29] FBA_DQS[7..0] [30,31] FBC_DQS#[7..0] A
[28,29] FBA_DQS#[7..0] 30ohms (ESR=0.01) Bead
P/N;SM010007W00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 27 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits FBA_MA[15..0] [27,29]

FBA_D[0..63] [27,29]

FBA_BA[2..0] [27,29]
UV3 S1@ UV4 S1@

+1.5VS_VGA FBA_DQM[7..0] [27,29]

+FBA_VREF0 M8 E3 FBA_D4 +FBA_VREF0 M8 E3 FBA_D19
VREFCA DQL0 FBA_D1 VREFCA DQL0 FBA_D20
D H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBA_DQS[7..0] [27,29] D
F2 FBA_D7 F2 FBA_D17
DQL2 DQL2
1

FBA_MA0 N3 F8 FBA_D0 FBA_MA0 N3 F8 FBA_D21 Group2 (IN1)

A0 DQL3 A0 DQL3 FBA_DQS#[7..0] [27,29]
RV79 FBA_MA1 P7 H3 FBA_D6 Group0 (IN3) FBA_MA1 P7 H3 FBA_D16
1.1K_0402_1% FBA_MA2 A1 DQL4 FBA_D3 FBA_MA2 A1 DQL4 FBA_D23
P3 A2 DQL5 H8 P3 A2 DQL5 H8
OPT@ FBA_MA3 N2 G2 FBA_D5 FBA_MA3 N2 G2 FBA_D18
FBA_MA4 P8
A3 DQL6
H7 FBA_D2 FBA_MA4 P8
A3 DQL6
H7 FBA_D22 CMD mapping mod Mode D
2

+FBA_VREF0 FBA_MA5 A4 DQL7 FBA_MA5 A4 DQL7

P2 A5 P2 A5
FBA_MA6 R8 FBA_MA6 R8
A6 A6
1

1 FBA_MA7 R2 D7 FBA_D29 FBA_MA7 R2 D7 FBA_D10 DATA Bus

RV68 CV118 FBA_MA8 A7 DQU0 FBA_D25 FBA_MA8 A7 DQU0 FBA_D15
T8 A8 DQU1 C3 T8 A8 DQU1 C3
1.1K_0402_1% 0.01U_0402_16V7K FBA_MA9 R3 C8 FBA_D28 FBA_MA9 R3 C8 FBA_D8 Address 0..31 32..63
OPT@ OPT@ FBA_MA10 A9 DQU2 FBA_D26 FBA_MA10 A9 DQU2 FBA_D13
2
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 Group1 (TOP)
FBA_MA11 R7 A7 FBA_D31 Group3 (BOT) FBA_MA11 R7 A7 FBA_D9 FBx_CMD0 CS0#_L
2

FBA_MA12 A11 DQU4 FBA_D24 FBA_MA12 A11 DQU4 FBA_D12

N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBA_MA13 T3 B8 FBA_D30 FBA_MA13 T3 B8 FBA_D11 FBx_CMD1
FBA_MA14 A13 DQU6 FBA_D27 FBA_MA14 A13 DQU6 FBA_D14
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBA_MA15 M7 FBA_MA15 M7 FBx_CMD2 ODT_L
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD3 CKE_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD4 A14 A14
FBA_CLK0 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 FBx_CMD5 RST RST
VDD K8 VDD K8
2

VDD N1 VDD N1 FBx_CMD6 A9 A9

RV80 FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
[27] FBA_CLK0 CK VDD CK VDD
C 160_0402_1% FBA_CLK0# K7 R1 FBA_CLK0# K7 R1 FBx_CMD7 A7 A7 C
[27] FBA_CLK0# CK VDD CK VDD
OPT@ FBA_CKE_L K9 R9 FBA_CKE_L K9 R9
[27] FBA_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD8 A2 A2
1

FBA_CLK0# FBA_ODT_L K1 A1 FBA_ODT_L K1 A1 FBx_CMD9 A0 A0

[27] FBA_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_L L2 A8 FBA_CS0#_L L2 A8
[27] FBA_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD10 A4 A4
[27,29] FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBA_ODT_L
[27,29] FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD11 A1 A1
[27,29] FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 FBA_CKE_L FBx_CMD12 BA0 BA0
FBA_DQS0 VDDQ FBA_DQS2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
FBA_DQS3 C7 H9 FBA_DQS1 C7 H9 FBx_CMD13 WE# WE#
DQSU VDDQ DQSU VDDQ

2
RV67 RV76 FBx_CMD14 A15 A15
FBA_DQM0 E7 A9 FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5%
FBA_DQM3 DML VSS FBA_DQM1 DML VSS OPT@ OPT@
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD15 CAS# CAS#
E1 E1

1
VSS VSS
VSS G8 VSS G8 FBx_CMD16 CS0#_H
FBA_DQS#0 G3 J2 FBA_DQS#2 G3 J2
FBA_DQS#3 B7 DQSL VSS FBA_DQS#1 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8 FBx_CMD17
VSS M1 VSS M1
VSS M9 VSS M9 FBx_CMD18 ODT_H
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9 FBx_CMD19 CKE_H
[27,29] FBA_RST# RESET VSS RESET VSS
T1 T1 UV3 UV3 UV3 UV3 UV3
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD20 A13 A13
B B
FBx_CMD21 A8 A8
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
1

RV78 RV77 L1 B9 RV69 L1 B9 FBx_CMD22 A6 A6

10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 Hynix Samsung Hynix Samsung Micron
OPT@ OPT@ L9 D8 OPT@ L9 D8 H1@ @ H2@ S2@ M2@ FBx_CMD23 A11 A11
NCZQ1 VSSQ NCZQ1 VSSQ SA000041S30 SA000047Q10 SA00003YOI0 SA00005SH30 SA00005SM30
E2 E2
2

VSSQ 2 VSSQ
E8 E8 FBx_CMD24 A5 A5
2

VSSQ VSSQ UV4 UV4 UV4 UV4 UV4

VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD25 A3 A3
VSSQ G9 VSSQ G9
FBx_CMD26 BA2 BA2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD27 BA1 BA1
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 Hynix Samsung Hynix Samsung Micron
H1@ @ H2@ S2@ M2@ FBx_CMD28 A12 A12
SA000041S30 SA000047Q10 SA00003YOI0 SA00005SH30 SA00005SM30
FBx_CMD29 A10 A10
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE
FBx_CMD30 RAS# RAS#
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
OPT@ CV119

OPT@ CV120

OPT@ CV121

OPT@ CV123

OPT@ CV162

@ CV161

OPT@ CV159

OPT@ CV134

OPT@ CV129

OPT@ CV160

OPT@ CV133

OPT@ CV132

OPT@ CV164

@ CV136

OPT@ CV163

OPT@ CV137

OPT@ CV135

@ CV157

@ CV155

@ CV138

OPT@ CV142

@ CV143

@ CV144

OPT@ CV158
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 28 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 FBA_D[0..63] [27,28]

bits UV5 S1@ UV6 S1@

FBA_MA[15..0] [27,28]
+1.5VS_VGA
FBA_BA[2..0] [27,28]
+FBA_VREF1 M8 E3 FBA_D36 +FBA_VREF1 M8 E3 FBA_D63
VREFCA DQL0 FBA_D34 VREFCA DQL0 FBA_D58
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBA_DQM[7..0] [27,28]
1 DQL2 F2 FBA_D37
DQL2 F2 FBA_D60
RV70 FBA_MA0 N3 F8 FBA_D35 FBA_MA0 N3 F8 FBA_D59
A0 DQL3 A0 DQL3 FBA_DQS[7..0] [27,28]
D 1.1K_0402_1% FBA_MA1 P7 H3 FBA_D39 Group4 (IN1) FBA_MA1 P7 H3 FBA_D61 Group7 (IN3) D
OPT@ FBA_MA2 A1 DQL4 FBA_D32 FBA_MA2 A1 DQL4 FBA_D56
P3 A2 DQL5 H8 P3 A2 DQL5 H8 FBA_DQS#[7..0] [27,28]
FBA_MA3 N2 G2 FBA_D38 FBA_MA3 N2 G2 FBA_D62
2

+FBA_VREF1 FBA_MA4 A3 DQL6 FBA_D33 FBA_MA4 A3 DQL6 FBA_D57

P8 A4 DQL7 H7 P8 A4 DQL7 H7
FBA_MA5 P2 FBA_MA5 P2
A5 A5
1

FBA_MA6 R8 FBA_MA6 R8
RV82
1
CV178 FBA_MA7 R2
A6
A7 DQU0 D7 FBA_D45 FBA_MA7 R2
A6
A7 DQU0 D7 FBA_D55 CMD mapping mod Mode D
1.1K_0402_1% 0.01U_0402_16V7K FBA_MA8 T8 C3 FBA_D42 FBA_MA8 T8 C3 FBA_D51
OPT@ OPT@ FBA_MA9 A8 DQU1 FBA_D46 FBA_MA9 A8 DQU1 FBA_D54
2
R3 A9 DQU2 C8 R3 A9 DQU2 C8 DATA Bus
FBA_MA10 L7 C2 FBA_D41 Group5 (TOP) FBA_MA10 L7 C2 FBA_D49
2

FBA_MA11 A10/AP DQU3 FBA_D47 FBA_MA11 A10/AP DQU3 FBA_D52

R7 A11 DQU4 A7 R7 A11 DQU4 A7 Group6 (BOT) Address 0..31 32..63
FBA_MA12 N7 A2 FBA_D43 FBA_MA12 N7 A2 FBA_D50
FBA_MA13 A12 DQU5 FBA_D44 FBA_MA13 A12 DQU5 FBA_D53
T3 A13 DQU6 B8 T3 A13 DQU6 B8 FBx_CMD0 CS0#_L
FBA_MA14 T7 A3 FBA_D40 FBA_MA14 T7 A3 FBA_D48
FBA_MA15 A14 DQU7 FBA_MA15 A14 DQU7
M7 A15/BA3 +1.5VS_VGA
M7 A15/BA3 +1.5VS_VGA
FBx_CMD1
FBx_CMD2 ODT_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD3 CKE_L
FBA_CLK1 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 FBx_CMD4 A14 A14
VDD K8 VDD K8
2

VDD N1 VDD N1 FBx_CMD5 RST RST

RV83 FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
[27] FBA_CLK1 CK VDD CK VDD
160_0402_1% FBA_CLK1# K7 R1 FBA_CLK1# K7 R1 FBx_CMD6 A9 A9
[27] FBA_CLK1# CK VDD CK VDD
OPT@ FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
[27] FBA_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD7 A7 A7
1

C C
FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD8 A2 A2
[27] FBA_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_H L2 A8 FBA_CS0#_H L2 A8
[27] FBA_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD9 A0 A0
[27,28] FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9
[27,28] FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD10 A4 A4
[27,28] FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD11 A1 A1
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 DQSL VDDQ FBA_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD12 BA0 BA0
FBx_CMD13 WE# WE#
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 DML VSS FBA_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD14 A15 A15
VSS E1 VSS E1
VSS G8 VSS G8 FBx_CMD15 CAS# CAS#
FBA_DQS#4 G3 J2 UV5 UV5 UV5 UV5 UV5 FBA_DQS#7 G3 J2
FBA_DQS#5 B7 DQSL VSS FBA_DQS#6 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8 FBx_CMD16 CS0#_H
VSS M1 VSS M1
FBA_CKE_H M9 M9 FBx_CMD17
VSS VSS
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9 FBx_CMD18 ODT_H
[27,28] FBA_RST# RESET VSS RESET VSS
FBA_ODT_H T1 Hynix Samsung Hynix Samsung Micron T1
VSS H1@ @ H2@ S2@ M2@ VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD19 CKE_H
SA000041S30 SA000047Q10 SA00003YOI0 SA00005SH30 SA00005SM30
FBx_CMD20 A13 A13
1

1
RV84 RV87 J1 B1 UV6 UV6 UV6 UV6 UV6 J1 B1
10K_0402_5% 10K_0402_5% RV86 NC/ODT1 VSSQ RV85 NC/ODT1 VSSQ
B L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 FBx_CMD21 A8 A8 B
OPT@ OPT@ 243_0402_1% J9 D1 243_0402_1% J9 D1
OPT@ NC/CE1 VSSQ OPT@ NC/CE1 VSSQ
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 FBx_CMD22 A6 A6
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 FBx_CMD23 A11 A11
VSSQ F9 Hynix Samsung Hynix Samsung Micron VSSQ F9
G1 H1@ @ H2@ S2@ M2@ G1 FBx_CMD24 A5 A5
VSSQ SA000041S30 SA000047Q10 SA00003YOI0 SA00005SH30 SA00005SM30 VSSQ
VSSQ G9 VSSQ G9
FBx_CMD25 A3 A3
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD26 BA2 BA2
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
+1.5VS_VGA UV5 SIDE +1.5VS_VGA UV6 SIDE
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
OPT@ CV145

OPT@ CV174

OPT@ CV296

OPT@ CV301

OPT@ CV291

OPT@ CV302

OPT@ CV299

OPT@ CV290

OPT@ CV300

OPT@ CV297

OPT@ CV298

OPT@ CV165

OPT@ CV177

@ CV170

OPT@ CV166

OPT@ CV172

@ CV179

@ CV173

@ CV169

@ CV180

OPT@ CV167

OPT@ CV171

@ CV168

@ CV175
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 29 of 63
5 4 3 2 1
 5 4 3 2 1

FBC_D[0..63] [27,31]
Memory Partition C - Lower 32 bits FBC_MA[15..0] [27,31]

FBC_BA[2..0] [27,31]

FBC_DQM[7..0] [27,31]
+1.5VS_VGA UV7 S1@ UV8 S1@
FBC_DQS[7..0] [27,31]
+FBB_VREF0 M8 E3 FBC_D4 +FBB_VREF0 M8 E3 FBC_D16
1 VREFCA DQL0 VREFCA DQL0 FBC_DQS#[7..0] [27,31]
D H1 F7 FBC_D3 H1 F7 FBC_D21 D
RV111 VREFDQ DQL1 FBC_D7 VREFDQ DQL1 FBC_D18
DQL2 F2 DQL2 F2
1.1K_0402_1% FBC_MA0 N3 F8 FBC_D0 Group0 (IN3)FBC_MA0 N3 F8 FBC_D17
OPT@ FBC_MA1 A0 DQL3 FBC_D5 FBC_MA1 A0 DQL3 FBC_D20
P7 A1 DQL4 H3 P7 A1 DQL4 H3 Group2 (IN1) CMD mapping mod Mode D
FBC_MA2 P3 H8 FBC_D1 FBC_MA2 P3 H8 FBC_D23
2

+FBB_VREF0 FBC_MA3 A2 DQL5 FBC_D6 FBC_MA3 A2 DQL5 FBC_D19

N2 A3 DQL6 G2 N2 A3 DQL6 G2
FBC_MA4 P8 H7 FBC_D2 FBC_MA4 P8 H7 FBC_D22
A4 DQL7 A4 DQL7
1

1 FBC_MA5 P2 FBC_MA5 P2 DATA Bus

RV115 CV202 FBC_MA6 A5 FBC_MA6 A5
R8 A6 R8 A6
1.1K_0402_1% 0.01U_0402_16V7K FBC_MA7 R2 D7 FBC_D28 FBC_MA7 R2 D7 FBC_D8 Address 0..31 32..63
OPT@ OPT@ FBC_MA8 A7 DQU0 FBC_D27 FBC_MA8 A7 DQU0 FBC_D15
T8 A8 DQU1 C3 T8 A8 DQU1 C3
2 FBC_MA9 FBC_D31 FBC_MA9 FBC_D11
R3 C8 R3 C8 FBx_CMD0 CS0#_L
2

FBC_MA10 A9 DQU2 FBC_D25 FBC_MA10 A9 DQU2 FBC_D12

L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
FBC_MA11 R7 A7 FBC_D29 Group3 (BOT)FBC_MA11 R7 A7 FBC_D9 Group1 (TOP) FBx_CMD1
FBC_MA12 A11 DQU4 FBC_D24 FBC_MA12 A11 DQU4 FBC_D13
N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBC_MA13 T3 B8 FBC_D30 FBC_MA13 T3 B8 FBC_D10 FBx_CMD2 ODT_L
FBC_MA14 A13 DQU6 FBC_D26 FBC_MA14 A13 DQU6 FBC_D14
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBC_MA15 M7 FBC_MA15 M7 FBx_CMD3 CKE_L
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD4 A14 A14
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD5 RST RST
FBC_CLK0 FBC_BA2 M3 G7 FBC_BA2 M3 G7
BA2 VDD BA2 VDD UV7 UV7 UV7 UV7 UV7
VDD K2 VDD K2 FBx_CMD6 A9 A9
VDD K8 VDD K8
2

310mA VDD N1 VDD N1 FBx_CMD7 A7 A7

RV89 FBC_CLK0 J7 N9 FBC_CLK0 J7 N9
[27] FBC_CLK0 CK VDD CK VDD
C 160_0402_1% FBC_CLK0# K7 R1 FBC_CLK0# K7 R1 FBx_CMD8 A2 A2 C
[27] FBC_CLK0# CK VDD CK VDD
OPT@ FBC_CKE_L K9 R9 FBC_CKE_L K9 R9
[27] FBC_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
Hynix Samsung Hynix Samsung Micron FBx_CMD9 A0 A0
1

H1@ @ H2@ S2@ M2@

FBC_CLK0# FBC_ODT_L K1 A1 FBC_ODT_L K1 A1 SA000041S30 SA000047Q10 SA00003YOI0 SA00005SH30 SA00005SM30 FBx_CMD10 A4 A4
[27] FBC_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CS0#_L L2 A8 FBC_CS0#_L L2 A8
[27] FBC_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1 UV8 UV8 UV8 UV8 UV8 FBx_CMD11 A1 A1
[27,31] FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
[27,31] FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2 FBx_CMD12 BA0 BA0
[27,31] FBC_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD13 WE# WE#
FBC_DQS0 F3 H2 FBC_DQS2 F3 H2
FBC_DQS3 DQSL VDDQ FBC_DQS1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 Hynix Samsung Hynix Samsung Micron FBx_CMD14 A15 A15
H1@ @ H2@ S2@ M2@
SA000041S30 SA000047Q10 SA00003YOI0 SA00005SH30 SA00005SM30 FBx_CMD15 CAS# CAS#
FBC_DQM0 E7 A9 FBC_DQM2 E7 A9
FBC_DQM3 DML VSS FBC_DQM1 DML VSS FBC_ODT_L
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD16 CS0#_H
VSS E1 VSS E1
VSS G8 VSS G8 FBx_CMD17
FBC_DQS#0 G3 J2 FBC_DQS#2 G3 J2 FBC_CKE_L
FBC_DQS#3 B7 DQSL VSS FBC_DQS#1 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8 FBx_CMD18 ODT_H
VSS M1 VSS M1
VSS M9 VSS M9 FBx_CMD19 CKE_H

1
P1 P1 RV117 RV116
FBC_RST# VSS FBC_RST# VSS 10K_0402_5% 10K_0402_5%
[27,31] FBC_RST# T2 RESET VSS P9 T2 RESET VSS P9 FBx_CMD20 A13 A13
T1 T1 OPT@ OPT@
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD21 A8 A8
B B

2
FBx_CMD22 A6 A6
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
1

RV91 RV90 L1 B9 RV88 L1 B9 FBx_CMD23 A11 A11

10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
OPT@ OPT@ L9 D8 OPT@ L9 D8 FBx_CMD24 A5 A5
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

VSSQ 2 VSSQ
E8 E8 FBx_CMD25 A3 A3
2

VSSQ VSSQ
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD26 BA2 BA2
VSSQ G9 VSSQ G9
FBx_CMD27 BA1 BA1
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD28 A12 A12
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VS_VGA UV7 SIDE +1.5VS_VGA UV8 SIDE
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
@ CV191

@ CV183

OPT@ CV199

OPT@ CV189

OPT@ CV205

@ CV188

@ CV190

OPT@ CV206

@ CV181

OPT@ CV182

@ CV185

@ CV194

OPT@ CV192

OPT@ CV203

OPT@ CV195

OPT@ CV184

OPT@ CV197

OPT@ CV186

OPT@ CV187

OPT@ CV198

OPT@ CV200

OPT@ CV201

OPT@ CV204

OPT@ CV193
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 30 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

FBC_D[0..63] [27,30]

FBC_MA[15..0] [27,30]

FBC_BA[2..0] [27,30]
UV9 S1@

+1.5VS_VGA FBC_DQM[7..0] [27,30]

+FBB_VREF1 M8 E3 FBC_D39
VREFCA DQL0 FBC_D33 UV10 S1@
D H1 VREFDQ DQL1 F7 FBC_DQS[7..0] [27,30] D
F2 FBC_D38
DQL2
1

FBC_MA0 N3 F8 FBC_D32 +FBB_VREF1 M8 E3 FBC_D60

A0 DQL3 VREFCA DQL0 FBC_DQS#[7..0] [27,30]
RV120 FBC_MA1 P7 H3 FBC_D36 Group4 (IN1) H1 F7 FBC_D57
FBC_MA2 A1 DQL4 FBC_D35 VREFDQ DQL1 FBC_D63
P3 A2 DQL5 H8 DQL2 F2
1.1K_0402_1% FBC_MA3 N2 G2 FBC_D37 FBC_MA0 N3 F8 FBC_D58
OPT@ FBC_MA4 A3 DQL6 FBC_D34 FBC_MA1 A0 DQL3 FBC_D61
P8 H7 P7 H3 Group7 (IN3) CMD mapping mod Mode D
2

+FBB_VREF1 FBC_MA5 A4 DQL7 FBC_MA2 A1 DQL4 FBC_D56

P2 A5 P3 A2 DQL5 H8
FBC_MA6 R8 FBC_MA3 N2 G2 FBC_D62
A6 A3 DQL6
1

1 FBC_MA7 R2 D7 FBC_D47 FBC_MA4 P8 H7 FBC_D59 DATA Bus

RV127 CV229 FBC_MA8 A7 DQU0 FBC_D43 FBC_MA5 A4 DQL7
T8 A8 DQU1 C3 P2 A5
1.1K_0402_1% 0.01U_0402_16V7K FBC_MA9 R3 C8 FBC_D46 FBC_MA6 R8 Address 0..31 32..63
OPT@ OPT@ FBC_MA10 A9 DQU2 FBC_D42 FBC_MA7 A6 FBC_D54
L7 A10/AP DQU3 C2 R2 A7 DQU0 D7
2 FBC_MA11 FBC_D40 FBC_MA8 FBC_D51
R7 A7 Group5 (TOP) T8 C3 FBx_CMD0 CS0#_L
2

FBC_MA12 A11 DQU4 FBC_D45 FBC_MA9 A8 DQU1 FBC_D55

N7 A12 DQU5 A2 R3 A9 DQU2 C8
FBC_MA13 T3 B8 FBC_D44 FBC_MA10 L7 C2 FBC_D49 FBx_CMD1
FBC_MA14 A13 DQU6 FBC_D41 FBC_MA11 A10/AP DQU3 FBC_D52
T7 A14 DQU7 A3 R7 A11 DQU4 A7 Group6 (BOT)
FBC_MA15 M7 FBC_MA12 N7 A2 FBC_D50 FBx_CMD2 ODT_L
A15/BA3 +1.5VS_VGA FBC_MA13 A12 DQU5 FBC_D53
T3 A13 DQU6 B8
FBC_MA14 T7 A3 FBC_D48 FBx_CMD3 CKE_L
FBC_BA0 FBC_MA15 A14 DQU7
M2 BA0 VDD B2 M7 A15/BA3
FBC_BA1 N8 D9 +1.5VS_VGA FBx_CMD4 A14 A14
FBC_BA2 BA1 VDD
M3 BA2 VDD G7
FBC_CLK1 K2 FBC_BA0 M2 B2 FBx_CMD5 RST RST
VDD FBC_BA1 BA0 VDD
VDD K8 N8 BA1 VDD D9
N1 FBC_BA2 M3 G7 FBx_CMD6 A9 A9
VDD BA2 VDD
2

FBC_CLK1 J7 N9 K2
[27] FBC_CLK1 CK VDD VDD
C RV129 FBC_CLK1# K7 R1 K8 FBx_CMD7 A7 A7 C
[27] FBC_CLK1# CK VDD VDD
160_0402_1% FBC_CKE_H K9 R9 N1
[27] FBC_CKE_H CKE/CKE0 VDD VDD
OPT@ FBC_CLK1 J7 N9 FBx_CMD8 A2 A2
FBC_CLK1# K7 CK VDD
R1
1

FBC_ODT_H FBC_CKE_H K9 CK VDD

[27] FBC_ODT_H K1 ODT/ODT0 VDDQ A1 CKE/CKE0 VDD R9 FBx_CMD9 A0 A0
FBC_CLK1# FBC_CS0#_H L2 A8
[27] FBC_CS0#_H CS/CS0 VDDQ
FBC_RAS# J3 C1 FBx_CMD10 A4 A4
[27,30] FBC_RAS# RAS VDDQ
FBC_CAS# K3 C9 FBC_ODT_H K1 A1
[27,30] FBC_CAS# CAS VDDQ ODT/ODT0 VDDQ
FBC_WE# L3 D2 FBC_CS0#_H L2 A8 FBx_CMD11 A1 A1
[27,30] FBC_WE# WE VDDQ CS/CS0 VDDQ
E9 UV9 UV9 UV9 UV9 UV9 FBC_RAS# J3 C1
VDDQ FBC_CAS# RAS VDDQ
VDDQ F1 K3 CAS VDDQ C9 FBx_CMD12 BA0 BA0
FBC_DQS4 F3 H2 FBC_WE# L3 D2
FBC_DQS5 DQSL VDDQ WE VDDQ
C7 DQSU VDDQ H9 VDDQ E9 FBx_CMD13 WE# WE#
VDDQ F1
FBC_DQS7 F3 H2 FBx_CMD14 A15 A15
FBC_DQM4 FBC_DQS6 DQSL VDDQ
E7 DML VSS A9 Hynix Samsung Hynix Samsung Micron C7 DQSU VDDQ H9
FBC_DQM5 D3 B3 H1@ @ H2@ S2@ M2@ FBx_CMD15 CAS# CAS#
DMU VSS SA000041S30 SA000047Q10 SA00003YOI0 SA00005SH30 SA00005SM30
VSS E1
G8 FBC_DQM7 E7 A9 FBx_CMD16 CS0#_H
FBC_DQS#4 G3 VSS UV10 UV10 UV10 UV10 UV10 FBC_DQM6 DML VSS
DQSL VSS J2 D3 DMU VSS B3
FBC_DQS#5 B7 J8 E1 FBx_CMD17
FBC_ODT_H DQSU VSS VSS
VSS M1 VSS G8
M9 FBC_DQS#7 G3 J2 FBx_CMD18 ODT_H
VSS FBC_DQS#6 B7 DQSL VSS
VSS P1 DQSU VSS J8
FBC_CKE_H FBC_RST# T2 P9 M1 FBx_CMD19 CKE_H
[27,30] FBC_RST# RESET VSS VSS
VSS T1 Hynix Samsung Hynix Samsung Micron VSS M9
L8 T9 H1@ @ H2@ S2@ M2@ P1 FBx_CMD20 A13 A13
ZQ/ZQ0 VSS VSS
1

B RV118 RV119 SA000041S30 SA000047Q10 SA00003YOI0 SA00005SH30 SA00005SM30 FBC_RST# T2 P9 B

10K_0402_5% 10K_0402_5% RESET VSS
VSS T1 FBx_CMD21 A8 A8
1

OPT@ OPT@ J1 B1 L8 T9
RV123 NC/ODT1 VSSQ ZQ/ZQ0 VSS
L1 NC/CS1 VSSQ B9 FBx_CMD22 A6 A6
243_0402_1% J9 D1
2

NC/CE1 VSSQ

1
OPT@ L9 D8 J1 B1 FBx_CMD23 A11 A11
NCZQ1 VSSQ RV128 NC/ODT1 VSSQ
E2 L1 B9
2

VSSQ NC/CS1 VSSQ

VSSQ E8 243_0402_1% J9 NC/CE1 VSSQ D1 FBx_CMD24 A5 A5
F9 OPT@ L9 D8
VSSQ NCZQ1 VSSQ
G1 E2 FBx_CMD25 A3 A3

2
VSSQ VSSQ
VSSQ G9 VSSQ E8
VSSQ F9 FBx_CMD26 BA2 BA2
96-BALL G1
SDRAM DDR3 VSSQ
VSSQ G9 FBx_CMD27 BA1 BA1
K4W1G1646E-HC12_FBGA96
96-BALL FBx_CMD28 A12 A12
SDRAM DDR3
K4W1G1646E-HC12_FBGA96 FBx_CMD29 A10 A10
+1.5VS_VGA UV9 SIDE +1.5VS_VGA UV10 SIDE
FBx_CMD30 RAS# RAS#
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
OPT@ CV209

@ CV227

OPT@ CV213

OPT@ CV233

OPT@ CV226

OPT@ CV207

@ CV230

OPT@ CV220

OPT@ CV221

@ CV228

OPT@ CV225

OPT@ CV210

@ CV208

OPT@ CV223

@ CV211

@ CV222

OPT@ CV212

@ CV231

OPT@ CV224

OPT@ CV214

OPT@ CV215

OPT@ CV217

OPT@ CV218

OPT@ CV232
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 31 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS_VGA Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG/PCI_DEVID[5] PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]

2
RV92 GL1@ RV93 @ RV94 GL1@ RV121 @ RV122 @ ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 20K_0402_1% 20K_0402_1%
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]

1
STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
[24] STRAP0 STRAP0
[24] STRAP1 STRAP1 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
[24] STRAP2 STRAP2
STRAP3 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
[24] STRAP3
[24] STRAP4 STRAP4
STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
2 CHANGE_GEN3

2
D RV95 @ RV96 GL1@ RV97 @ RV124 @ RV125 @ D
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 4.99K_0402_1% 10K_0402_1% Pull-up to
Resistor Values +3VS_VGA Pull-down to Gnd Vendor VRAM Sturcture
1

1
5K 1000 0000 Samsung 2G S2@
10K 1001 0001 Hynix 2G H2@
15K 1010 0010 Samsung 1G S1@
+3VS_VGA 20K 1011 0011 Hynix 1G H1@
25K 1100 0100
30K 1101 0101
35K 1110 0110
2

2
RV98 45K 1111 0111
4.99K_0402_1% RV99 GS1@ RV100 GS1@
@ 10K_0402_1% 4.99K_0402_1%
1

SUB_VENDOR 3GIO_PADCFG XCLK_417

1

[24] ROM_SI ROM_SI

[24] ROM_SO ROM_SO
[24] ROM_SCLK ROM_SCLK 0 No VBIOS ROM 3GIO_PADCFG[3:0] 0 277MHz (Default)
2

ZZZ1 ZZZ2 1 BIOS ROM is present (Default) 0110 Notebook Default 1 Reserved
RV101 RV102 GL1@ RV103 GL1@
X76 20K_0402_1% 10K_0402_1% 15K_0402_1%
S1@
FB_0_BAR_SIZE SLOT_CLK_CFG
1

Samsung Hynix 0 Reserved 0 GPU and MCH don't share a common reference clock
S1GP@ H1GP@
X7643238L01 X7643238L02
1 Reserved 1 GPU and MCH share a common reference clock (Default)
RV101 S2@ RV101 H2@ RV101 H1@ ZZZ3 ZZZ5

2 256MB (Default) SMBUS_ALT_ADDR VGA_DEVICE

ZZZ4
3 Reserved 0 0x9E (Default) 0 3D Device (Class Code 302h)
C
45.3K_0402_1% 30.1K_0402_1% 15K_0402_1% Samsung Samsung C
SD034453280 SD034301280 SD034150280 S2GP_GLR@ S2GP_GSR@
X7643238L03 X7643238L05 1 0x9C (Multi-GPU usage) 1 VGA Device (Default)
USER Straps
RV101 S2_GSR@ RV101 S2_GLR@ RV101 M2_GSR@ RV101 M2_GLR@ Hynix ZZZ6 ZZZ7
H2GP_GLR@ User[3:0]
X7643238L04

1000-1100 Customer defined

24.9K_0402_1% 10K_0402_1% 10K_0402_1% 24.9K_0402_1% Micron Micron
SD034249280 SD034100280 SD034100280 SD034249280 M2GP_GLR@ M2GP_GSR@
X7643238L06 X7643238L07 PEX_PLL_EN_TERM
For N13P-GS strap table X76 0 Disable (Default)

GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK 1 Enable
128M* 16* 8 Samsung (2Gb) R R R R R R R R
N13P-GS 900 MHz 2GB K4W2G1646C-HC11 PU 45K PD 5K PD 15K PD 5K PD 45K PD 45K PU 10K PU 5K
128M* 16* 8 Hynix (2Gb) R R R R R R R R PCIE_MAX_SPEED
N13P-GS 900 MHz 2GB H5TQ2G63DFR-11C PU 45K PD 5K PD 15K PD 5K PD 45K PD 30.1K PU 10K PU 5K
64M* 16* 8 Samsung (1Gb) R R R R R R R R 0 Limit to PCIE Gen1
N13P-GS 900 MHz 1GB K4W1G1646G-BC11 PU 45K PD 5K PD 15K PD 5K PD 45K PD 20K PU 10K PU 5K
64M* 16* 8 Hynix (1Gb) R R R R R R R R
N13P-GS 900 MHz 1GB H5TQ1G63DFR-11C PU 45K PU 5K PD 15K PD 5K PD 45K PD 15K PU 10K PU 5K 1 PCIE Gen 2/3 Capable
strap0 strap1 strap2 strap3 strap4
RV92 GS1@ RV96 GS1@ RV97 GS1@ RV124 GS1@ RV125 GS1@

45.3K_0402_1% 4.99K_0402_1%15K_0402_1% 4.99K_0402_1% 45.3K_0402_1%

SD034453280 SD034499180 SD034150280 SD034499180 SD034453280

For N13P-GSR strap table X76

GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK

128M* 16* 8 Samsung (2Gb) R R R R R R R R

N13P-GS 900 MHz 2GB K4W2G1646C-HC11 PU 45K PD 5K PU 10K PD 5K PD 45K PD 45K PU 10K PU 5K
128M* 16* 8 Hynix (2Gb) R R R R R R R R
B N13P-GS 900 MHz 2GB H5TQ2G63DFR-11C PU 45K PD 5K PU 10K PD 5K PD 45K PD 30.1K PU 10K PU 5K B
64M* 16* 8 Samsung (1Gb) R R R R R R R R
N13P-GS 900 MHz 1GB K4W1G1646G-BC11 PU 45K PD 5K PU 10K PD 5K PD 45K PD 20K PU 10K PU 5K
64M* 16* 8 Hynix (1Gb) R R R R R R R R
N13P-GS 900 MHz 1GB H5TQ1G63DFR-11C PU 45K PU 5K PU 10K PD 5K PD 45K PD 15K PU 10K PU 5K

strap0 strap1 strap2 strap3 strap4 ROM_SO ROM_SCLK

RV92 GSR@ RV96 GSR@ RV94 GSR@ RV124 GSR@ RV125 GSR@ RV99 GSR@ RV100 GSR@

45.3K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 45.3K_0402_1% 10K_0402_1% 4.99K_0402_1%

SD034453280 SD034499180 SD034100280 SD034499180 SD034453280 SD034100280 SD034499180

For N13P-GL strap table X76

GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK

128M* 16* 8 Samsung (2Gb) R R R R R R

N13P-GL 900 MHz 2GB K4W2G1646C-HC11 PU 45K PD 45K PU 10K n/a n/a PD 45K PD 10K PD 15K
128M* 16* 8 Hynix (2Gb) R R R R R R
N13P-GL 900 MHz 2GB H5TQ2G63DFR-11C PU 45K PD 45K PU 10K n/a n/a PD 30.1K PD 10K PD 15K
64M* 16* 8 Samsung (1Gb) R R R R R R
N13P-GL 900 MHz 1GB K4W1G1646G-BC11 PU 45K PD 45K PU 10K n/a n/a PD 20K PD 10K PD 15K
64M* 16* 8 Hynix (1Gb) R R R R R R
N13P-GL 900 MHz 1GB H5TQ1G63DFR-11C PU 45K PD 45K PU 10K n/a n/a PD 15K PD 10K PD 15K

For N13P-GLR strap table X76

GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK

128M* 16* 8 Samsung (2Gb) R R R R R R

N13P-GL 900 MHz 2GB K4W2G1646C-HC11 PU 45K PD 45K PD 20K n/a n/a PD 45K PD 10K PD 15K
128M* 16* 8 Hynix (2Gb) R R R R R R
N13P-GL 900 MHz 2GB H5TQ2G63DFR-11C PU 45K PD 45K PD 20K n/a n/a PD 30.1K PD 10K PD 15K
64M* 16* 8 Samsung (1Gb) R R R R R R
N13P-GL 900 MHz 1GB K4W1G1646G-BC11 PU 45K PD 45K PD 20K n/a n/a PD 20K PD 10K PD 15K
64M* 16* 8 Hynix (1Gb) R R R R R R
N13P-GL 900 MHz 1GB H5TQ1G63DFR-11C PU 45K PD 45K PD 20K n/a n/a PD 15K PD 10K PD 15K
A A

strap0 strap1 strap2 strap3 strap4 ROM_SO ROM_SCLK

RV92 GLR@ RV96 GLR@ RV97 GLR@ RV102 GLR@ RV103 GLR@

45.3K_0402_1% 45.3K_0402_1% 20K_0402_1% 10K_0402_1% 15K_0402_1%

SD034453280 SD034453280 SD034200280 SD034100280 SD034150280

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 32 of 63
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+LCDVDD +5VALW +3VS
+3VS
W=60mils
(20 MIL)
1 CMOS@ +3VS_CMOS
Q83

1
R400 R401 C513
150_0603_1% 100K_0402_5% 4.7U_0603_6.3V6K PMV65XP_SOT23-3~D R02 (20 MIL)
+3VALW R296
D D
2

D
3 1 2 @ 1 10U
R403 1 1

2
1

3
D 220K_0402_5%
S
CMOS@ 0_0603_5%
G 1
Q80 C518 C519 @

G
2 1 2 2

2
Q79 G PMV65XP_SOT23-3~D C542 @ 0.1U_0402_16V7K 10U_0603_6.3V6M
2N7002K_SOT23-3 R435 CMOS@ 0.1U_0402_16V7K 2 2
S 1
D
W=60mils

1
1
C515 150K_0402_5% 2
0.1U_0402_16V7K 4.7V

OUT
[42] CMOS_ON#
2 +LCDVDD +LCDVDD_CONN
L29 1
[17] PCH_ENVDD 2 R296 for CMOS shake issue reserve
IN C520 CMOS@
1 2

GND
0.1U_0402_16V7K
Q81 DTC124EK FBMA-L11-201209-221LMA30T_0805 2
1
DTC124EKAT146_SC59-3 1 1

3
C516 C517
@ R408 4.7U_0603_6.3V6K 0.1U_0402_16V7K
100K_0402_5%
2 2
2

+3VS VGA LCD/PANEL BD. Conn.

R02
R717 +LEDVDD B+
0_0402_5% 1 R02
C 1 @ 2 R433 @ R813 0_0805_5% C
1 2
4.7K_0402_5% 1 1
C539
2

BKOFF# 1 2 DISPOFF# 680P_0402_50V7K C541

[42] BKOFF# 4.7U_0805_25V6-K
@
D4 @ 2 2
1

CH751H-40PT_SOD323-2 R02
R716 JLVDS1 ME@
10K_0402_5% 1 1
2 2 G1 41
3 42
2

R03 3 G2
4 4 G3 43
5 5 G4 44
R02 R447 1 @ 2 0_0402_5% 6 45
R538 1 @ 6 G5
[17] PCH_ENBKL 2 0_0402_5% ENBKL [42]
DISPOFF# 7 7 G6 46
R430 1 @ 2 0_0402_5% INVT_PWM 8
[17] PCH_PWM 8
9 9
R20 [17] LVDS_BCLK 10
R431 1 @ 10
[42] EC_INVT_PWM 2 0_0402_5% [17] LVDS_BCLK# 11 11
2

[17] LVDS_B2 12 12
R438 [17] LVDS_B2# 13
100K_0402_1% 13
[17] LVDS_B1 14 14
[17] LVDS_B1# 15 15
[17] LVDS_B0 16
1

16
[17] LVDS_B0# 17 17
18 18
B [17] LVDS_ACLK 19 19 B
[17] LVDS_ACLK# 20 20
[17] LVDS_A2 21 21
[17] LVDS_A2# 22 22
[17] LVDS_A1 23 23
[17] LVDS_A1# 24 24
[17] LVDS_A0 25 25
[17] LVDS_A0# 26 26
[17] EDID_DATA 27 27
[17] EDID_CLK 28 28
+3VS 29 29
+LCDVDD_CONN 30 30
(60 MIL) 31 31
32 32
1 +3VS 33 33
DMIC_DATA 34
[41] DMIC_DATA 34
680P_0402_50V7K DMIC_CLK 35
[41] DMIC_CLK 35
C540 @ 36
2 36
37 37
[18] USB20_P3 USB20_P3 38
USB20_N3 38
[18] USB20_N3 39 39
CMOS +3VS_CMOS 40 40
ACES_50203-04001-001

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 33 of 63
5 4 3 2 1
 A B C D E

+5VS +5VS +5VS

3 3 3

1 BLUE 1 GREEN 1 RED

2 2 2
@ @ @
D5 D6 D7
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

1 1

+5VS
D10
+CRT_VCC
CRT Connector
F1
2 1 1 2 +CRT_VCC_F
1
RB491D_SC59-3
FCM1608CF-121T03 0603 1.1A_6V_SMD1812P110TF C521
1 2 RED 0.1U_0402_16V7K
[17] DAC_RED
L30 W=40mils 2
FCM1608CF-121T03 0603
1 2 GREEN
[17] DAC_GRN
L31
FCM1608CF-121T03 0603
1 2 BLUE
[17] DAC_BLU

C522

C523

C524

C525

C526

C527
10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
L32 JCRT1
1

1
1 1 1 1 1 1 6
PAD T66 NC11 11
R445 R443 R446 RED 1
150_0402_1% 150_0402_1% 150_0402_1% 7
2 2 2 2 2 2 CRT_DDC_DAT_CONN 12
2

2
GREEN 2
8
CLOSE TO CONN JVGA_HS 13
BLUE 3
9
JVGA_VS 14
4
2 10 G 16 2
+CRT_VCC CRT_DDC_CLK_CONN 15 G 17
R448
5
1 2 1
1 C528 ME@

2
0_0402_5%

0_0402_5%

0_0402_5%
C-H_13-12201557CP
1K_0402_5%

0_0402_5%
R437
C529 100P_0402_50V8J
2

R436

R434

R432
0.1U_0402_16V7K @ @ @ @
2
5

1
FCM1608CF-121T03 0603
P

OE#

2 4 CRT_HSYNC_1 1 2 JVGA_HS
[17] CRT_HSYNC A Y L33
G

U23
SN74AHCT1G125DCKR_SC70-5 1 EMI Request
3

@
D8
C530 @
10P_0402_50V8J JVGA_VS 3 6 JVGA_HS
+CRT_VCC 2 I/O2 I/O4
R451
1 2
1 2 GND VDD 5 +5VS
C531 1K_0402_5%
0.1U_0402_16V7K
2 CRT_DDC_CLK_CONN CRT_DDC_DAT_CONN
1 I/O1 I/O3 4
5

FCM1608CF-121T03 0603
P

OE#

CRT_VSYNC_1 JVGA_VS AZC099-04S.R7G_SOT23-6

[17] CRT_VSYNC 2 A Y 4 1 2
3 L34 3
G

U24 1
SN74AHCT1G125DCKR_SC70-5
3

@ C532
10P_0402_50V8J
2

+CRT_VCC
+3VS
1

Pull high at chipset/VGA side R456 R457

5

2.2K_0402_5% 2.2K_0402_5%
2

[17] CRT_DDC_DATA 4 3 CRT_DDC_DAT_CONN

2N7002DW-T/R7_SOT363-6
2

Q62B

[17] CRT_DDC_CLK 1 6 CRT_DDC_CLK_CONN

1 1
2N7002DW-T/R7_SOT363-6 @ @
4 4
Q62A C533 C534
100P_0402_50V8J 68P_0402_50V8K
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 34 of 63
A B C D E
 5 4 3 2 1

+5VS
W=40mils +5VS_HDMI
+5VS PMEG2010ET_SOT23-3 F2 HDMI@
+3VS D13 HDMI@ 1.1A_8V_SMD1812P110TF
2 1+HDMI_5V 1 2 +5VS_HDMI

2
1

2
R482 @ C543
D R485 0_0805_5% HDMI@ D
1M_0402_5% Q93 D14 @ 0.1U_0402_16V7K 2
HDMI@ HDMI@ BAT54S-7-F_SOT23-3

1
2
G
2N7002K_SOT23-3

1
TMDS_B_HPD# 3 1
[17] TMDS_B_HPD#

2
2
HDMI@ R483 R484 HDMI@
R488 2.2K_0402_5% 2.2K_0402_5%
20K_0402_5%

1
HDMI@
JHDMI1

1
HDMI_DET 19 HP_DET
+5VS_HDMI 18 +5V
17 DDC/CEC_GND
HDMIDAT_R 16
HDMICLK_R SDA
15 SCL
14 Reserved
13 CEC
[17] HDMI_CLK-_CK HDMI_CLK-_CK R464 1 @ 2 0_0402_5% HDMI_CLK-_CONN 12 20
CK- GND
[17] HDMI_CLK+_CK 11 CK_shield GND 21
HDMI_CLK+_CKR465 1 @ 2 0_0402_5% HDMI_CLK+_CONN 10
C CK+ C
[17] HDMI_TX0-_CK HDMI_TX0-_CK R466 1 @ 2 0_0402_5% HDMI_TX0-_CONN 9 D0-
[17] HDMI_TX0+_CK 8 D0_shield
HDMI_TX0+_CK R467 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7
+3VS HDMI_TX1-_CK R468 1 @ D0+
[17] HDMI_TX1-_CK 2 0_0402_5% HDMI_TX1-_CONN 6 D1-
[17] HDMI_TX1+_CK 5 D1_shield
HDMI_TX1+_CK R469 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4
HDMI_TX2-_CK R470 1 @ D1+
[17] HDMI_TX2-_CK 2 0_0402_5% HDMI_TX2-_CONN 3 D2-
2

R02 2
[17] HDMI_TX2+_CK D2_shield
R783 HDMI_TX2+_CK R471 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1 D2+
0_0402_5%
@ ACON_HMR2H-AK120C
Pull up R for PCH OR VGA SIDE ME@
1

Q63A
HDMI@
2

2N7002KDWH_SOT363-6
L35 HDMI@
1 6 HDMICLK_R HDMI_CLK-_CK 1 2 HDMI_CLK-_CONN 680 +-5% 8P4R
[17] HDMICLK_NB 1 2 C982 1 2 0.1U_0402_16V7K @ HDMI_CLK-_CONN 5 4
5

HDMI_CLK+_CONN 6 3
HDMI_CLK+_CK 4 HDMI_CLK+_CONN
3 HDMI_TX1-_CONN 7 2
HDMIDAT_R 4 3 C983 1
B [17] HDMIDAT_NB 4 3 2 0.1U_0402_16V7K @ HDMI_TX1+_CONN 8 1 SD309680080 B
WCM-2012HS-900T_4P
Q63B RP5 HDMI@ S ROW RES 1/16W 680 +-5% 8P4R
HDMI@ L36 HDMI@
2N7002KDWH_SOT363-6 HDMI_TX0-_CK 1 2 HDMI_TX0-_CONN 680 +-5% 8P4R
1 2 C984 1 2 0.1U_0402_16V7K @ HDMI_TX0-_CONN 5 4
HDMI_TX0+_CONN 6 3
HDMI_TX0+_CK 4 HDMI_TX0+_CONN
3 HDMI_TX2-_CONN 7 2
4 3 C985 1
HDMIDAT_R 2 0.1U_0402_16V7K @ HDMI_TX2+_CONN 8 1
WCM-2012HS-900T_4P +3VS
RP6 HDMI@

1
HDMICLK_R L37 HDMI@ D
HDMI_TX1-_CK 1 2 HDMI_TX1-_CONN 2
1 2 C986 1 2 0.1U_0402_16V7K @ G
S Q95

3
3

HDMI_TX1+_CK 4 HDMI_TX1+_CONN HDMI@

D11 @ 4 3 3 C987
1 2 0.1U_0402_16V7K @ 2N7002K_SOT23-3
YSLC05CH_SOT23-3 WCM-2012HS-900T_4P

L38 HDMI@
HDMI_TX2-_CK 1 2 HDMI_TX2-_CONN
1 2 C988 1 2 0.1U_0402_16V7K @

HDMI_TX2+_CK 4 HDMI_TX2+_CONN
3 3 C989
1

4
A 1 2 0.1U_0402_16V7K @ A
WCM-2012HS-900T_4P

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
SCHEMATICS,MB A9061
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 35 of 63
5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN/WiMAX(Half)

R5550
+3VS_WLAN +3VALW +1.5VS 0_0402_5%
USB20_N10_WLAN 1 @ 2 USB20_N10

1 1 1 1
+3VS_WLAN C548 @ C547 USB20_P10_WLAN 1 @ 2 USB20_P10
1
Mini-Express
@
Card(WLAN/WiMAX) +1.5VS
4.7U_0603_6.3V6K 0.1U_0402_16V7K C544 @
0.1U_0402_16V7K
C545 @
0.1U_0402_16V7K 0_0402_5%
1

R1505 1 EC_WL_WAKE#_R 2 2 2 2
[42,44] EC_WL_WAKE# 2 0_0402_5% R5551

JWLN1
[16,37] PCIE_WAKE# PCIE_WAKE# R514 1 @ 2 0_0402_5% 1 2 for Intel AOAC function Reserved
BT_ACTIVE 1 R497 1 2
[40] BT_ACTIVE 2 @ 0_0402_5% 3 3 4 4
1 @ 2 BT_DISABLE_F_R R5580 1 @ 2 0_0402_5% BT_DISABLE_R 5 6 +3VALW
[19,40] PCH_BT_ON# 5 6
R892 0_0402_5% [15] CLKREQ_WLAN# 7 8 LPC_FRAME#_R
@ 7 8 LPC_AD3_R
[19] BT_DISABLE 1 2 9 9 10 10
11 12 LPC_AD2_R
Low - Disable [15] CLK_PCIE_WLAN1# 11 12 C1318
R897 0_0402_5% 13 14 LPC_AD1_R @
R02 [15] CLK_PCIE_WLAN1 13 14
15 16 LPC_AD0_R 7 8 1 2
PCI_RST#_R 15 16 R02 NC VCC 0.1U_0402_16V7K
17 17 18 18
1 @ 2 INTEL_BT_OFF#_R CLK_PCI_DB 19 19 20 20 R498 1 @ 2 0_0402_5% PCH_WL_OFF# [18]
USB20_N10_WLAN 5 D- HSD- 6 USB20_N10 [18]
R893 1K_0402_1% 21 22
21 22 PLT_RST# [18,23,37,42]
23 24 R499 1 2 @ 0_0402_5% +3VALW USB20_P10_WLAN 3 2
[15] PCIE_PRX_DTX_N2 23 24 D+ HSD+ USB20_P10 [18]
25 26 R500 1 @ 2 0_0402_5% +3VS_WLAN
[15] PCIE_PRX_DTX_P2 25 26 R02
[19] INTEL_BT_OFF# 1 2 27 27 28 28 4 GND OE# 1 WLAN_USB_ON# [42]
R894 1K_0402_1% 29 30 1 R501 2 @ 0_0402_5% SMB_CLK_S3 [12,13,15,43]
R03 29 30
[15] PCIE_PTX_C_DRX_N2 31 31 32 32 1 R502 2 @ 0_0402_5% SMB_DATA_S3 [12,13,15,43] U75

1
33 34 @
[15] PCIE_PTX_C_DRX_P2 33 34
35 36 USB20_N10_WLAN TS3USB31RSER_QFN8_1P5X1P5 R5552 @
+3VS_WLAN 35 36 USB20_P10_WLAN
37 37 38 38 0_0402_5%
39 39 40 40
41 42

2
41 42
43 43 44 44
100_0402_1% 45 46
R505 45 46
47 47 48 48
[42] EC_TX 1 2 49 49 50 50
[42] EC_RX 1 2 51 51 52 52
R506
R03 100_0402_1% 53 54
INTEL_BT_OFF#_R GND1 GND2 +3VS 80mil +3VS_WLAN
for Intel AOAC function
BELLW_80003-3041
ME@
R308 2 1 0_0805_5%
2 R02 NOAOAC@ 2

2
For EC to detect
R507
debug card insert. 100K_0402_5%
+3VALW
1

Q105 AO3413_SOT23-3

D
3 1 1
AOAC@
AOAC@ C536
0.1U_0402_16V7K

G
2
2
Reserve for SW mini-pcie debug card. [42] AOAC_ON#
1
R439 AOAC@
Series resistors closed to KBC side. 150K_0402_5% C537
AOAC@ 0.1U_0402_16V7K
LPC_FRAME#_R R508 @ 0_0402_5% LPC_FRAME# 2
1 2 LPC_FRAME# [14,42]
LPC_AD3_R R509 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 [14,42]
LPC_AD2_R R510 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 [14,42]
LPC_AD1_R R511 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 [14,42]
LPC_AD0_R R512 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 [14,42]
PCI_RST#_R R513 1 @ 2 0_0402_5% PLT_RST#
CLK_PCI_DB CLK_PCI_DB [18]

Mini-Express Card(SSD) SSD Active:4.5W(1.5A)

3 3
+3VS_SSD +3VS +3VS_SSD
J5
0.1U_0402_16V7K 10U_0603_6.3V6M
1 1 2 2
1 1 1 1
@
C566 C567 C568 C569 JUMP_43X79
@
2 2 2 2 JSSD1
1 1 2 2
0.01U_0402_16V7K 10U_0603_6.3V6M 3 4
3 4
11/07 Change type to 0603 5 5 6 6
7 7 8 8
9 9 10 10
11 11 12 12
13 13 14 14
15 15 16 16
17 17 18 18
19 19 20 20
0.01U_0402_16V7K 21 22
SATA_DTX_C_IRX_P0 2 21 22
[14] SATA_DTX_C_IRX_P0 1 C572 SATA_DTX_IRX_P0 23 23 24 24
SATA_DTX_C_IRX_N0 2 1 C573 SATA_DTX_IRX_N0 25 26
[14] SATA_DTX_C_IRX_N0 25 26
27 27 28 28
0.01U_0402_16V7K 29 30
SATA_ITX_DRX_N0 29 30
[14] SATA_ITX_DRX_N0 31 31 32 32
[14] SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 33 34
33 34
35 35 36 36
37 37 38 38
+3VS_SSD 39 40
39 40
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
49 49 50 50
[19] mSATA_DET#
R558 1 @ 2 0_0402_5% mSATA_DET#_R 51 51 52 52

4 For SSD use: 53 GND1 GND2 54 4

1

BELLW_80003-3041
R5554 ME@
220_0402_5% @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 36 of 63
A B C D E
 5 4 3 2 1

+3VALW +3V_LAN

J15
1 1 2 2

JUMP_43X79

@
D +3V_LAN D

W=60mils +LAN_VDD10
L74 W=60mils 1.5A
U47 8105@ +LAN_REGOUT 1 2 1 2
2.2UH_NLC252018T-2R2J-N_5% 0.1U_0402_16V7K C1189
1 2

2
0.1U_0402_16V7K C1190
C1184 C1182 1 2
4.7U_0603_6.3V6K 0.1U_0402_16V7K 0.1U_0402_16V7K C1191

1
RTL8105E-VL-CGT 1 2
SA00003PO40 GIGA@ 0.1U_0402_16V7K C1192
1 2
The C1183, C1186 close to U47 Pin 22, 23 GIGA@ 0.1U_0402_16V7K C1193
U47 These components close to U47 : Pin 36 1 2
( Should be place within 200 mils ) GIGA@ 0.1U_0402_16V7K C1194
[15] PCIE_PRX_DTX_P1 C1183 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 22 31
HSOP LED3/EEDO
C1186 1 PCIE_PRX_C_DTX_N1 LED1/EESK 37 These caps close to U47 : Pin 12,27,39,42,47,48
[15] PCIE_PRX_DTX_N1 2 0.1U_0402_16V7K 23 HSON LED0 40
@
17 30 R1506 2 1 10K_0402_5% +LAN_VDD10 R02 +LAN_EVDD10
[15] PCIE_PTX_C_DRX_P1 HSIP EECS
18 32 R1507 2 1 10K_0402_5% L75
[15] PCIE_PTX_C_DRX_N1 HSIN EEDI @ 2 @ 1

2
16 1 MDI0+ 0_0603_5%
[15] CLKREQ_LAN# CLKREQB MDIP0 MDI0+ [38]
2 MDI0- C1187 C1188
MDIN0 MDI0- [38] +LAN_VDD10
25 4 MDI1+ 1U_0402_6.3V4Z 0.1U_0402_16V7K
[18,23,36,42] PLT_RST# MDI1+ [38]

1
PERSTB MDIP1 MDI1-
MDIN1 5 MDI1- [38]
19 7 MDI2+ 1 2
[15] CLK_PCIE_LAN REFCLK_P NC/MDIP2 MDI2+ [38]
20 8 MDI2- 0.1U_0402_16V7K C1197
[15] CLK_PCIE_LAN# REFCLK_N NC/MDIN2 MDI2- [38]
C 10 MDI3+ 1 2 C
NC/MDIP3 MDI3+ [38]
NOGCLK@ 11 MDI3- 0.1U_0402_16V7K C1198
NC/MDIN3 MDI3- [38]
LAN_XTALI R1373 1 2 0_0402_5% LAN_XTALI_R 43 1 2
R03 GCLK@ CKXTAL1 0.1U_0402_16V7K C1199
GCLK_LAN_25MHZ R5585 1 2 0_0402_5% LAN_XTALO 44 13 +LAN_VDD10 +3V_LAN Rising time (10%~90%)要>1mS and <100mS 1 2
[44] GCLK_LAN_25MHZ CKXTAL2 DVDD10
29 GIGA@ 0.1U_0402_16V7K C1200
R02 DVDD10
DVDD10 41 1 2
R1508 1 @ 2 0_0402_5% PCIE_WAKE#_R 28 +3V_LAN R02 +LAN_VDDREG GIGA@ 0.1U_0402_16V7K C1201
[42] LAN_WAKE# LANWAKEB
R1509 1 @ 2 0_0402_5% L76 1 2
[16,36] PCIE_WAKE#
ISOLATEB 26 27 +3V_LAN 2 @ 1 GIGA@ 0.1U_0402_16V7K C1202
ISOLATEB DVDD33
DVDD33 39 1 2

2
0_0603_5% GIGA@ 0.1U_0402_16V7K C1203
14 12 +3V_LAN C1195 C1196
@ NC/SMBCLK AVDD33
2 R1510 1 10K_0402_5% 15 42 4.7U_0603_6.3V6K 0.1U_0402_16V7K

1
@ NC/SMBDATA AVDD33
+3V_LAN 1 R1511 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47
AVDD33 48 These caps close to U47 : Pin 3,6,9,13,29,41,45
ENSWREG 33 ENSWREG
EVDD10 21 +LAN_EVDD10
+LAN_VDDREG 34 VDDREG
35 VDDREG AVDD10 3 +LAN_VDD10
AVDD10 6
AVDD10 9
1 2 46 45 +3VS +3V_LAN
R1513 2.49K_0402_1% RSET AVDD10

2
24 36 +LAN_REGOUT
GND REGOUT

1
49 R1515
PGND R1514 0_0402_5%
1K_0402_5% @
R1512 1 @ 2 10K_0402_5% CLKREQ_LAN# RTL8111F-CGT_QFN48_6x6
+3V_LAN

1
B B
GIGA@

2
ISOLATEB ENSWREG
R1518 1 @ 2 10K_0402_5% PCIE_WAKE#_R

R1517
R1516 0_0402_5%
15K_0402_5% @

LAN_XTALI

Y4 LAN_XTALO
4 NC OSC 3

1 OSC NC 2
R03 1 25MHZ_10PF_7V25000014 1 R03
C1204 NOGCLK@ C1205
12P_0402_50V8J 12P_0402_50V8J
NOGCLK@ NOGCLK@
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 37 of 63
5 4 3 2 1
 5 4 3 2 1

Reserve gas tube for EMI go rural solution

T71

MDI3+ 1 16 MDO3+ @
[37] MDI3+ TD+ TX+
MDI3- 2 15 MDO3- DL3
[37] MDI3- TD- TX-
@ 3 14 MCT3 2 1 GT1812-420CSMD_1812-2
D D34 CT CT CHASSIS1_GND D
4 NC NC 13
AZC099-04S.R7G_SOT23-6 5 12 DL2
MDI2+ MDI3+ NC NC MCT2 GT1812-420CSMD_1812-2
1 I/O1 I/O3 4 6 CT CT 11 2 1
MDI2+ 7 10 MDO2+ CHASSIS1_GND
[37] MDI2+ RD+ RX+
MDI2- 8 9 MDO2- @
[37] MDI2- RD- RX-
2 GND VDD 5 +3V_LAN
MHPC_NS681610H
GIGA@
Place Close to T1,T2
MDI3- 3 6 MDI2-
I/O2 I/O4
T72

Place Close to T71 MDI0+ 1 16 MDO0+ @

[37] MDI0+ TD+ TX+
MDI0- 2 15 MDO0- DL5
[37] MDI0- TD- TX-
3 14 MCT0 2 1 GT1812-420CSMD_1812-2
CT CT CHASSIS1_GND
4 NC NC 13
5 12 DL4
NC NC MCT1 GT1812-420CSMD_1812-2
1 6 CT CT 11 2 1
MDI1+ 7 10 MDO1+ CHASSIS1_GND
[37] MDI1+ RD+ RX+
@ MDI1- 8 9 MDO1- @
[37] MDI1- RD- RX-
D35 C1207
AZC099-04S.R7G_SOT23-6 2 0.01U_0402_16V7K
C C
MDI1+ 1 4 MDI0+ MHPC_NS681610H
I/O1 I/O3

MCT3 R60 1 GIGA@ 2 75_0603_5%

2 GND VDD 5 +3V_LAN
MCT2 R289 1 GIGA@ 2 75_0603_5%

MDI0- 3 6 MDI1-
I/O2 I/O4 MCT0 R305 1 2 75_0603_5%

MCT1 R306 1 2 75_0603_5%

Place Close to T72
R03
JRJ45 ME@

1
12 R03
GND R307
11 0_0603_5%
D34/D35 GND

1
10

2
GND
1'S PN:SC300001G00 MDO0+ 1 PR1+
9
Gastube@ DL6
1
GND
B
2'S PN:SC300002E00 MDO0- 2 PR1-
BS4200N-C-LV_SMB-F2 C906
10P_0603_50V8-J
B

2
MDO1+ 3 PR2+ CHASSIS1_GND 2
MDO2+ 4 PR3+
MDO2- 5 PR3-
MDO1- 6 CHASSIS1_GND
PR2-
MDO3+ 7 PR4+ R03
MDO3- 8 PR4-
CHASSIS1_GNDC1325 1 2 .1U_0603_25V7K
SANTA_130460-3
DC231112261 C1326 1 2 .1U_0603_25V7K

C1327 1 2 .1U_0603_25V7K

CHASSIS1_GND
Reserve for EMI go rural solution
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 38 of 63
5 4 3 2 1
 5 4 3 2 1

SMSC thermal sensor

placed near by VRAM Close to DDR
+3VS REMOTE1+
D D
Close U27 1

1
C

1
REMOTE1+ @ C586 2 Q97
+3VS R540 100P_0402_50V8J B MMST3904-7-F_SOT323-3
1 2
10K_0402_5% E

3
C587 @ REMOTE1-
2200P_0402_50V7K U27

2
2 REMOTE1-

1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 [15,23,42]
REMOTE1+ EC_SMB_DA2
REMOTE2+ 2
2 DP1 SMDATA 9 EC_SMB_DA2 [15,23,42]
REMOTE2+
Under WWAN
1 REMOTE1- 3 8 1
DN1 ALERT#

1
C590 C
C588 @ 0.1U_0402_16V7K REMOTE2+ 4 7 @ C589 2 Q98
2200P_0402_50V7K 1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 REMOTE2- REMOTE2- 2 E
5 6

3
DN2 GND REMOTE2-

EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
C Address 1001_101xb Trace width/space:10/10 mil
C

Trace length:<8"
R02 R02
CPU VGA_L VGA_R new new new
H1 H2 H3 H18 new
HOLEA HOLEA HOLEA H4 H5 HOLEA H20 H21
HOLEA HOLEA HOLEA HOLEA H22
HOLEA FD1 FD2 FD3 FD4

1
1

1
H_3P8 H_3P8 H_3P8 H_3P9N CHASSIS1_GND CHASSIS1_GND
H_3P3 H_3P3
H_3P3 H_4P6 H_3P3
A B

B FAN1 Conn M/B 橢圓孔 B

R02
new
new M/B 圓孔
H6 H7 H8 H9 H10 H11 H12 H13 H14 H19 L
+5VS HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H15 H23 H17
R02 HOLEA HOLEA HOLEA
R581 JFAN1
2 @ 1 1
1

1
1
[42] EC_TACH 2

1
0_0603_5% [42] EC_FAN_PWM 2
3 3
4 4 H_2P8 H_3P0 H_2P3 H_2P8 H_2P8 H_2P8 H_2P8 H_2P3 H_2P8 H_2P8
2 5 H_3P0X4P0N H_3P0X4P0N
G5 H_3P0N
6 G6
C591
10U_0603_6.3V6M ACES_85205-04001 D
1 ME@
2P8 * 7 pcd E
10U

A A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
SCHEMATICS,MB A9061
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 39 of 63
5 4 3 2 1
 A B C D E F G H

BT MODULE CONN SATA HDD Conn.

JHDD1

1 GND
[14] SATA_ITX_DRX_P1 SATA_ITX_DRX_P1 2
SATA_ITX_DRX_N1 A+
[14] SATA_ITX_DRX_N1 3 A-
4 GND
SATA_DTX_C_IRX_N1 C596 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5
[14] SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C597 1 B-
[14] SATA_DTX_C_IRX_P1 2 0.01U_0402_16V7K SATA_DTX_IRX_P1 6 B+
7 GND

R632 BT@ C709 BT@ 8

100K_0402_5% 0.1U_0402_16V7K V33
+3VS 9 V33
[19,36] PCH_BT_ON# 1 2 1 2 10 V33
1 11 GND 1
+3VS_BT 12 GND
13 GND
+3VS R550 0_0805_5% 14
R02 +5V_HDD V5
+5VS 15 V5
R583 30mils 16 V5

D
3 1 2 @ 1 17 GND
1 18 DAS/DSS
0_0603_5% 0.1U_0402_16V7K 19
Q104 C712 GND

G
20

2
PMV65XP_SOT23-3~D @ V12
21 V12 GND 24
BT@ 2 +5V_HDD +3VS 22 V12 GND 23
JBT1
1 1
2 1 1 1 1 1 SUYIN_127043HR022M25KZR
USB20_P2 2 @
[18] USB20_P2 3 3 ME@
[18] USB20_N2 USB20_N2 4 C598 C599 C600 @ C602 C603 DC010007P00
4 1000P_0402_50V7K 0.1U_0402_16V7K 1U_0402_6.3V6K 10U_0603_6.3V6M 0.1U_0402_16V7K
BTON_LED:NC 5 5 G1 7
2 2 2 2 2
[36] BT_ACTIVE BT_ACTIVE 6 8
6 G2
ACES_87213-0600G
ME@

ODD Power Control

@ J9
1 1 2 2
+5V_ODD FOR 15"
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
S

3 1 JODD2
1 [14] SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 15@ C605 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P2_15 1 1
1

2 Q99 @ [14] SATA_ITX_C_DRX_N2 SATA_ITX_C_DRX_N2 15@ C606 1 2 0.01U_0402_16V7K SATA_ITX_DRX_N2_15 2 2

R552 @ PMV65XP_SOT23-3~D C604 2
G

3
2

R568 @ 10K_0402_5% 0.1U_0402_16V7K SATA_DTX_C_IRX_N2 15@ C618 1 3

[14] SATA_DTX_C_IRX_N2 2 0.01U_0402_16V7K SATA_DTX_IRX_N2_15 4 4
10K_0402_5% R675 @ 2 SATA_DTX_C_IRX_P2 15@ C617 1
[14] SATA_DTX_C_IRX_P2 2 0.01U_0402_16V7K SATA_DTX_IRX_P2_15 5 5
100K_0402_5% 1 6
2

R710 1 @ 6
1 2 2 0_0402_5% ODD_DETECT# 7 7
C608 +5V_ODD 8 8
1

1 10U_0603_6.3V6M R02 R554 0_0402_5% 9

2 ODD_DA# @ R_ODD_DA# 9
1 2 10
OUT

C607 @ [18,42] ODD_DA# 10

0.01U_0402_16V7K 11 GND
2 R555 2
[19] ODD_EN 2 IN +3VS 1 12 GND
10K_0402_5%
GND

ACES_51524-01001-003
Q100 @ ME@
DTC124EKAT146_SC59-3
3

JODD3
SATA_ITX_DRX_P2_15 1
SATA_ITX_DRX_N2_15 1
2 2
3 3
SATA_DTX_IRX_N2_15 4
SATA_DTX_IRX_P2_15 4
5 5
6 6
ODD_DETECT# 7
+5V_ODD 7
8 8
9 9
R_ODD_DA# 10 10
+5VS 11 11
12 12
+5VALW 13 13
[42,43] LED_KB_PWM_R 14 14
15 15
16 16
3 17 GND 3
18 GND
ACES_51524-0160N-001
ME@

Co-lay
FOR 14"
SATA ODD Conn.
JODD1 ME@
1 GND
SATA_ITX_C_DRX_P2 14@ C616 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P2_14 2
SATA_ITX_C_DRX_N2 14@ C615 1 RX+
2 0.01U_0402_16V7K SATA_ITX_DRX_N2_14 3 RX-
4 GND
SATA_DTX_C_IRX_N2 14@ C614 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2_14 5
SATA_DTX_C_IRX_P2 14@ C613 1 TX-
2 0.01U_0402_16V7K SATA_DTX_IRX_P2_14 6 TX+
7 GND
ODD_DETECT# 8
+5V_ODD DP
9 +5V
10 +5V
R_ODD_DA# 11 MD
12 GND GND1 14
13 GND GND2 15

SUYIN_127382FB013M266ZR
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 40 of 63
A B C D E F G H
 5 4 3 2 1

600ohms @100MHz 1A +3VS +3VDD_CODEC +IOVDD_CODEC +3VDD_CODEC

P/N: SM01000BU00
R20
+5VS +5VDDA_CODEC +5VDDA_CODEC R1529 0_0805_5% R1530
L77 1 @ 2 1 2

10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K
1U_0402_6.3V6K
1 2 1 1 1 SUPPRE_ KC FBMA-10-100505-101T 0402

1
C1226

C1227

C1228

C1229
FBMA-L11160808601LMA10T_2P

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 2 @ @

2
2 2 2

C1231

C1232
C1230

C1233
2 2 2 1
Place near Pin1 Place near Pin9
600ohms @100MHz 2A
P/N: SM01000EE00 +5VS_PVDD
D R02 D
Place near Pin25 Place near Pin38
R1531 0_0805_5%
+5VS 1 2 +5VS_PVDD

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
2 1 1 +3VDD_CODEC

C1235

C1236
C1234
1 2 2 +IOVDD_CODEC Vendor recommend. 2.2K
+MIC1_VREFO_L

39

46

25

38

9
Power down (PD#) power stage for save power U50

2
PVDD1

PVDD2

AVDD1

AVDD2

DVDD1

DVDD-IO
0V: Power down power stage R1537
3.3V: Power up power stage 2.2K_0402_5%

MIC_JD 1 @ 2 MIC_JD_R 47 24 Vendor recommend. 2.2u

1
R1533 0_0402_5% DAPD/COMB_JACK LINE1-R(PORT-C-R)
EC_MUTE# 1 @ 2 EC_MUTE#_R 4 23
[42] EC_MUTE# PD# LINE1-L(PORT-C-L)
R1538 0_0402_5%
HDA_SDOUT_AUDIO 5 22 MIC_EXTR_C 1 2 2 1 EXT_MIC external MIC
+3VS [14] HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R) EXT_MIC [43]
C1237 2.2U_0402_6.3V6M R1534 1K_0402_5%
HDA_BITCLK_AUDIO 6 21 MIC_EXTL_C 1 2
[14] HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L) C1238 2.2U_0402_6.3V6M
2

HDA_SDIN0 2 1 SDATA_IN 8 17 Placement near Audio Codec

R1535
[14] HDA_SDIN0
R1536 22_0402_5% SDATA-IN MIC2-R(PORT-F-R)
Head Phone Woofer

1
4.7K_0402_5% 16 R5567
MIC2-L(PORT-F-L) R5571 SENSEB
@ 2 1
10 15 22K_0402_5% woofer@
[14] HDA_SYNC_AUDIO
1

SYNC LINE2-R(PORT-E-R) Reference Schematic 22Kohm 39.2K_0402_1%

HDA_RST_AUDIO# 11 14
[14] HDA_RST_AUDIO#

2
RESET# LINE2-L(PORT-E-L)

1
PC_BEEP R02 D +5VS_PVDD
12 PCBEEP woofer@ Q11 2Woofer_JD
40 SPK_L2+ 2N7002K_SOT23-3 G
JDREF SPK-OUT-L+
2 1 19 S

3
JDREF

1
C 20K_0402_1% R1541 41 SPK_L1- Internal Speaker R4946 C
SPK-OUT-L-

2
20 SENSEA 2 1SENSEA_R R4948
MONO-OUT(PORT-H) SPK_R1- R4947 U73 woofer@ 100K_0402_5%
SPK-OUT-R- 44
SENSEA 13 39.2K_0402_1% 200K_0402_5% EXT_MIC_RC1 woofer@
Sense A SPK_R2+ woofer@ IN+
45 5

2
SENSEB SPK-OUT-R+ VCC+
18 2

1
Sense-B GND

1
R02 D Woofer_JD
OUT 4
MIC Sense CBN 35 33 HPOUT_R 2 1 Q12 2 PLUG_IN [43] 3
CBN HPOUT-R(PORT-A-R) HP_OUTR [43] IN-
75_0402_5% R1544 Headphone 2N7002K_SOT23-3 G

1
R939 place near pin13 2 1 CBP 36 32 HPOUT_L 2 1 HP_OUTL [43] S LMV331IDCKRG4_SC70-5

3
C1239 2.2U_0402_6.3V6M CBP HPOUT-L(PORT-A-L) 75_0402_5% R1545 R4950
Capless HP Sense 2 1 34 48 300K_0402_5%
C1240 2.2U_0402_6.3V6M CPVEE SPDIF-OUT woofer@
R940 place near pin34 2 1 28 R20

2
C1241 4.7U_0603_6.3V6K LDO-CAP DMIC_CLK_R R937 2 @
GPIO1/DMIC-CLK 3 1 0_0402_5% DMIC_CLK [33]
29 2 DMIC_DATA_R R1548 2 @ 1 0_0402_5% DMIC_DATA [33]
MIC2-VREFO GPIO0/DMIC-DATA
30 MIC1-VREFO-R
+MIC1_VREFO_L 31 MIC1-VREFO-L

42 PVSS1 VREF 27 Place close to pin 27

1U_0402_6.3V6K

0.1U_0402_16V7K
43 PVSS2 AVSS1 26 1

1
C1242

C1243
7 DVSS AVSS2 37

2
49 2
Thermal PAD

ALC259Q-VC2-GR_QFN48_6X6

R1549
B
1 2 B
0_0402_5%
R1550 HDA_RST_AUDIO#
Pin Assignment Location Function 1 2
0_0402_5% HDA_SYNC_AUDIO
EMI
R1551
SPK-OUT (Pin40/41/44/45) Internal Int Speaker 1 2 HDA_SDOUT_AUDIO
@ 0_0402_5%
wide 25MIL Capless HP-OUT (Pin32/33) External Headphone out
1 2 HDA_BITCLK_AUDIO

R1552 27_0402_5%
SPK L+L-R+R- trace width MIC1(Pin21/22) External Mic in
1 1 1 1

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
Speaker 4 ohm ==>40 mils

C1244

C1245

C1246
C1247
@ 33P_0402_50V8J
Speaker 8 ohm ==>20 mils 2 2 2 2
R02 @ @ @
JSPK1
SPK_L2+ R1556 1 2 0_0603_5% SPK_L2+_CONN 1
SPK_L1- R1554 1 1
2 0_0603_5% SPK_L1-_CONN 2 2 GND GNDA
SPK_R1- R1555 1 2 0_0603_5% SPK_R1-_CONN 3
SPK_R2+ R1553 1 SPK_R2+_CONN 3
2 0_0603_5% 4 4
Combo Jack detect (normal open)
220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

1 1 1 1 5 GND1
C1248

C1249

C1250

C1251

6 GND2
R1559 and C1135
2 2 2 2
ACES_88231-04001
ME@ R5582 PC Beep
R1123,C1134
Close to U50.47 Close to U73.1
R02 R02

R1123 47K_0402_5% R1559 EC Beep [42] BEEP# 1 2

MIC_JD 1 2 EXT_MIC 1 2 EXT_MIC_RC C1252 0.1U_0402_16V7K
0_0402_5%
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

woofer@ R1557 C1254

SPK_R2+_CONN SPK_L1-_CONN 2 woofer@ 2 PCH Beep [14] HDA_SPKR 1 2PC_BEEP1 1 2 1 2 PC_BEEP
EXT_MIC_RC1 2 C1253 0.1U_0402_16V7K 33_0402_5%
C1134

C1135

SPK_R1-_CONN SPK_L2+_CONN R5582 0_0402_5% 0.1U_0402_16V7K

1
A @ A
1 1 @
3

R1558
10K_0402_5%

2
@ @
D38 D39
PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
Reserve for ESD request. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 41 of 63
5 4 3 2 1
 +3VLP

1
C535
+3VALW 100P_0402_50V8J
2 Vcc 3.3V +/- 5%
L44 100K +/- 5%
FBMA-L11-160808-601LMT_2P 1 1 1 1 1 1
+3VALW R694
+EC_VCCA

0.1U_0402_16V7K
C653

0.1U_0402_16V7K
C654

0.1U_0402_16V7K
C662

0.1U_0402_16V7K
C655

1000P_0402_50V7K
C657

1000P_0402_50V7K
C658
+3VALW 1 2 +EC_VCCA Board ID R695 VAD_BID min V AD_BID typ VAD_BID max
1 1
C659
C656 2 2 2 2 2 2 0 0 0 V 0 V 0 V MP

111
125
0.1U_0402_16V7K 1000P_0402_50V7K U31 8.2K +/- 5% 0.216

22
33
96

67
1 V 0.250 V 0.289 V PVT

9
2 ECAGND 2
1 2
L45 18K +/- 5%
2 0.436 V 0.503 V 0.538 V DVT

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0
FBMA-L11-160808-601LMT_2P
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
R1443 0_0402_5%
1 21 LED_KB_PWM 2 @ 1
[19] GATEA20 GATEA20/GPIO00 GPIO0F LED_KB_PWM_R [40,43]
2 23 BEEP#
[19] KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# [41]
3 26 NOVO# +3VS
[14] SERIRQ SERIRQ GPIO12 NOVO# [43]
4 27 ACOFF +3VALW
[14,36] LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF [49]
LPC_AD3 5
[14,36] LPC_AD3 LPC_AD3

2
LPC_AD2 7 PWM Output
[14,36] LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMP
[14,36] LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP [48]
LPC_AD0 10 LPC & MISC 64 VGA_IMVP_IMON R758 2 @ 1 0_0402_5% R588 R694
[14,36] LPC_AD0 LPC_AD0 GPIO39 R02 GPU_IMON [54]
2 1 2 1 65 10K_0402_5% 100K_0402_1%
ADP_I/GPIO3A ADP_I [48,49]
@C660
@ C660 22P_0402_50V8J @ R589 10_0402_5% 12 AD Input 66 EC_TS_ON# @
[18] CLK_PCI_EC EC_TS_ON# [43]

1
R03 R612 2 CLK_PCI_EC GPIO3B BRDID EC_FAN_PWM BRDID
[43,50] KBC_HANGUP_RESET# 1 0_0402_5% [18,23,36,37] PLT_RST# 13 PCIRST#/GPIO05 GPIO42 75
1 2 EC_RST# 37 76 R03
+3VALW EC_RST# IMON/GPIO43 IMVP_IMON [55]

2
R590 47K_0402_5% EC_SCI# 20 R20
[19] EC_SCI# EC_SCII#/GPIO0E
2 38 WLAN_USB_ON#_R R5586 2 1 0_0402_5% PCH_PWR_EN2 R695
[45] PWRSHARE_EN_R GPIO1D PCH_PWR_EN2 [46]
68 EC_WL_WAKE# 0_0402_5%
R02 DAC_BRIG/GPIO3C EC_WL_WAKE# [36,44]
C661 70 WLAN_USB_ON#_R R1595 2 @ 1
EN_DFAN1/GPIO3D WLAN_USB_ON# [36]
0.1U_0402_16V7K DA Output 71 0_0402_5%
DPWROK_EC [16]

1
1 KSI0 IREF/GPIO3E +3VALW +5VALW
55 KSI0/GPIO30 CHGVADJ/GPIO3F 72 SUSWARN# [16]
KSI1 56
KSI2 KSI1/GPIO31 EC_MUTE#
57 KSI2/GPIO32 1 R593 2 10K_0402_5%
KSO[0..17] KSI3 58 83 R594 +3VS
[43] KSO[0..17] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# [41]
KSI4 59 84 USB_ON# USB_ON# 1 2
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# [43,45]
KSI5
[43] KSI[0..7] KSI6
60
61
KSI5/GPIO35
PS2 Interface
CAP_INT#/GPIO4C 85
86
EC_WAKE# [19] For DS3 10K_0402_5%
KSI6/GPIO36 EAPD/GPIO4D CHG_ON# [45]
+3VALW KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK [43] +3VALW
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA [43]
R595 1 @ 2 47K_0402_5% KSO1 KSO1 40 TP_CLK R603 1 2 4.7K_0402_5%
KSO2 KSO1/GPIO21
41 KSO2/GPIO22

1
R597 1 @ 2 47K_0402_5% KSO2 KSO3 42 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 97 CPU1.5V_S3_GATE
CPU1.5V_S3_GATE [10,46]
TP_DATA R598 1 2 4.7K_0402_5%
KSO4 43 98 VGA_AC_DET R5536
KSO4/GPIO24 WOL_EN/GPXIOA01 VGA_AC_DET [23,54]
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 99
NTC_V_R R750 2 @
ME_FLASH [14] 100K_0402_1%
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 1 0_0402_5% NTC_V [48] @
KSO7 46 SPI Device Interface

2
+3VS +3VALW KSO8 KSO7/GPIO27
47 KSO8/GPIO28
R600 KSO9 48 119 PCH_PWR_EN PCH_PWR_EN BATT_TEMP 1 2
KSO9/GPIO29 SPIDI/GPIO5B PCH_PWR_EN [46,48]
1 2 EC_SMB_CK1 KSO10 49 120 GPU_PWR_EN C663 100P_0402_50V8J
KSO10/GPIO2A SPIDO/GPIO5C GPU_PWR_EN [54]
2.2K_0402_5% KSO11 50 SPI Flash ROM 126 ACIN 1 2
KSO11/GPIO2B SPICLK/GPIO58 AOAC_ON# [36]

1
R604 KSO12 C664 100P_0402_50V8J
R601 R602 1 2 EC_SMB_DA1 KSO13
51
52
KSO12/GPIO2C SPICS#/GPIO5A 128 SUSACK# [16] For DS3 R5537 1 2
2.2K_0402_5% KSO14 KSO13/GPIO2D 100K_0402_5% R522 @ 4.7K_0402_5%
2.2K_0402_5% 2.2K_0402_5% 53 KSO14/GPIO2E
KSO15 54 73 R02
KSO15/GPIO2F ENBKL/GPIO40 ENBKL [33]
KSO16 81 74 EC_PWRSHARE_EN# [45]

2
EC_SMB_CK2 KSO17 KSO16/GPIO48 PECI_KB930/GPIO41 NVDD_PWR_EN_EC
82 KSO17/GPIO49 FSTCHG/GPIO50 89 NVDD_PWR_EN_EC [18]
EC_SMB_DA2 90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# [43]
1 1 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# [43]
@ @ EC_SMB_CK1 77 GPIO 92
[48,49] EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# [43] +3VLP
C665 C666 EC_SMB_DA1 78 93 BATT_LOW_LED#
[48,49] EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# [43]
100P_0402_50V8J 100P_0402_50V8J EC_SMB_CK2 79 SM Bus 95 SYSON
2 2 [15,23,39] EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON [46,51]
EC_SMB_DA2 80 121 @
[15,23,39] EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON [55]

1
127 PM_SLP_S4# [16] KB9012A2 work around
PM_SLP_S4#/GPIO59 R4945 R737
47K_0402_5% VR_HOT# 1 @ 2 H_PROCHOT# [48,6]
[55] VR_HOT#
[16] PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 100 EC_RSMRST# [16]
14 101 EC_LID_OUT# 0_0402_5%
[16] PM_SLP_S5# EC_LID_OUT# [19]

2
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04

1
EC_SMI# Turbo_V D
[19] EC_SMI# 15 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 102 Turbo_V [48]
H_PROCHOT#_EC R02 R757 1 @ 2 0_0402_5% H_PROCHOT#_EC
+3VS
For DS3 [33] CMOS_ON# 16
17
GPIO0A H_PROCHOT#_EC/GPXIOA06 103
104 MAINPWON_R R02 R738 1 @ 2 0_0402_5%
PROCHOT [48] 2
G
1
[16,46] SLP_SUS# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON [48,50]
18 GPO 105 BKOFF# Q37 S C493
[7] DRAMRST_CNTRL_EC BKOFF# [33]

3
ODD_DA# GPIO0C BKOFF#/GPXIOA08 PBTN_OUT# 2N7002K_SOT23-3 47P_0402_50V8J
[18,40] ODD_DA# 19 GPIO0D GPIO PBTN_OUT#/GPXIOA09 106 PBTN_OUT# [16] 2
EC_INVT_PWM 25 107 PCH_APWROK [16]
[33] EC_INVT_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10
1 2 EC_TACH EC_TACH 28 108 SA_PGOOD [52]
[39] EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
R605 10K_0402_5% EC_PME# 29
EC_TX EC_PME#/GPIO15
[36] EC_TX 30 EC_TX/GPIO16
EC_RX 31 110 ACIN
[36] EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN [16,49]
PCH_PWROK 32 112 EC_ON +3VALW
[16] PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON [50]
EC_FAN_PWM 34 114 ON/OFF [43]
[39] EC_FAN_PWM SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
36 GPI 115 LID_SW#
[43] NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# [43]

2
2 1 116 SUSP#
SUSP#/GPXIOD05 SUSP# [10,25,46,51,53,54]
@ R608 117 PCH_HOT#_R R792 2 @ 1 0_0402_5%
GPXIOD06 PCH_HOT# [15]
10K_0402_5% 118 PECI_KB9012 R793 2 @ 1 0_0402_5% R606
PECI_KB9012/GPXIOD07 OVERT# [23]
AGND/AGND

R611 EC_RTCX1 122 R20 10K_0402_5%

SUSCLK_R 123 XCLKI/GPIO5D +V18R R669 1 2 43_0402_1%
GND/GND
GND/GND
GND/GND
GND/GND

[16] SUSCLK 2 1 124 H_PECI [19,6]

1
0_0402_5% XCLKO/GPIO5E V18R
1
GND0
1

C694 R02
1

4.7U_0603_6.3V6K R609 1 @ 2 0_0402_5%

R740 C93 2 LAN_WAKE# [37]
11
24
35
94
113

69

100K_0402_5% 20P_0402_50V8
2

2 R610 1
2

KB9012QF-A3_LQFP128_14X14
ECAGND

EMC Request 0_0402_5% @

EC_RTCX1 SYSON EC_PME#

S
1 3 PCI_PME# [18]

0.1U_0402_16V7K
C492
1 2 SUSCLK_R ECAGND Q102 @
R120 @ 2N7002K_SOT23-3

G
2
10M_0402_5% 1 +3VALW

PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER 2

32.768KHZ_12.5PF_9H03200413
1

4
18P_0402_50V8J

Y5
OSC

OSC

1 1
C347 @ C367 @
@ 18P_0402_50V8J
NC

NC

2 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
check
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 42 of 63
 ON/OFF switch K/B Connector
+3VALW
15" 14"

2
R642 KSI[0..7] JKB1 ME@ JKB2 ME@
KSI[0..7] [42]
100K_0402_5% KSI1 30 32
KSO[0..17] KSI7 30 GND
KSO[0..17] [42] 29 29 GND 31 GND1 28
KSI6 28 27

1
D26 KSO9 28 KSI1 GND2
27 27 26 26
NOVO# 2 KSI4 26 KSI7 25
[42] NOVO# 26 25
1 NOVO_BTN# KSO2 C668 1 2 @ 100P_0402_50V8J KSO16 C693 1 2 @ 100P_0402_50V8J KSI5 25 KSI6 24
ON/OFF R02 R725 1 @ KSO0 25 KSO9 24
[42] ON/OFF 2 0_0402_5% 3 24 24 23 23
KSO15 C670 1 2 @ 100P_0402_50V8J KSO17 C692 1 2 @ 100P_0402_50V8J KSI2 23 KSI4 22
KSI3 23 KSI5 22
DAN202UT106_SC70-3
22 22 21 21
KSO6 C672 1 2 @ 100P_0402_50V8J KSO1 C669 1 2 @ 100P_0402_50V8J KSO5 21 KSO0 20
KSO1 21 KSI2 20
20 20 19 19
KSO8 C674 1 2 @ 100P_0402_50V8J KSO7 C671 1 2 @ 100P_0402_50V8J KSI0 19 KSI3 18
KSO2 19 KSO5 18
18 18 17 17
KSO13 C676 1 2 @ 100P_0402_50V8J KSI2 C673 1 2 @ 100P_0402_50V8J KSO4 17 KSO1 16
+3VLP KSO7 17 KSI0 16
16 16 15 15
KSO12 C678 1 2 @ 100P_0402_50V8J KSO5 C675 1 2 @ 100P_0402_50V8J KSO8 15 KSO2 14
KSO6 15 KSO4 14
14 14 13 13

2
KSO11 C680 1 2 @ 100P_0402_50V8J KSI3 C677 1 2 @ 100P_0402_50V8J +3VS KSO3 13 KSO7 12
KSO12 13 KSO8 12
12 12 11 11
R701 KSO10 C682 1 2 @ 100P_0402_50V8J KSO14 C679 1 2 @ 100P_0402_50V8J KSO13 11 KSO6 10
100K_0402_5% KSO14 11 KSO3 10
10 10 9 9

2
ON/OFFBTN# KSO3 C684 1 2 @ 100P_0402_50V8J KSI7 C681 1 2 @ 100P_0402_50V8J KSO11 9 KSO12 8

1
R207 R96 KSO10 9 KSO13 8
8 8 7 7
KSO4 C686 1 2 @ 100P_0402_50V8J KSI6 C683 1 2 @ 100P_0402_50V8J 300_0402_5% 300_0402_5% KSO15 7 KSO14 6
J11 7 6
KB1 6 KSO11 5
R02 R720 1 @ ON/OFF KSI0 KSI5 KB2 6 KSO10 5
1 2 2 0_0402_5% C688 1 2 @ 100P_0402_50V8J C685 1 2 @ 100P_0402_50V8J 5 4

1
KB_LED_PWR 4 5 KSO16 R5563 1 15@ 0_0402_5% KSO15 4
4 2 3 3
SHORT PADS KSO0 C690 1 2 @ 100P_0402_50V8J KSI4 C687 1 2 @ 100P_0402_50V8J CAPS_LED# 3 KB_LED_PWRR5564 1 14@ 2 0_0402_5% KB1 2
[42] CAPS_LED# 3 2
2 KSO17 R5565 1 15@ 2 0_0402_5% KB2 1
J13 2 1
KSO9 C689 1 2 @ 100P_0402_50V8J 1 CAPS_LED# R5566 1 14@ 2 0_0402_5%
[42] NUM_LED# 1
1 2
KSI1 C691 1 2 @ 100P_0402_50V8J TYCO_3-2041084-0 ACES_88514-02601-071
SHORT PADS

TP/B Connector PWR/B Connector USB I/O Connector

+5VALW
R03 R03 +USB_VCCB
JTP1 ME@ +3VALW JUSB3
+3VS 1 USB20_N8 3 L78 4 USB20_N8_R 1
TP_CLK 1 3 4 1
[42] TP_CLK 2 2 2 2
TP_DATA 3 JPWRB1 ME@ 3
[42] TP_DATA 3 3
C760 1 1 4 1 USB20_P8 2 1 USB20_P8_R 4
SMB_CLK_S3_R 4 1 2 1 USB20_P8 4
@ @ 5 5 2 2 [18] USB20_P8
R5587 1 @ 2 0_0402_5% USB20_P8_R 5 5
0.1U_0402_16V7K C761 C762 SMB_DATA_S3_R 6 NOVO_BTN# 3 WCM-2012-900T_4P USB20_N8 R5588 1 @ 2 0_0402_5% USB20_N8_R 6
6 3 [18] USB20_N8 6
100P_0402_50V8J

100P_0402_50V8J ON/OFFBTN# 4 7
2 2 PWR_LED# 4 USB20_N9 USB20_N9_R USB20_P9 7
7 GND 5 5 3 3
L79
4 4 [18] USB20_P9
R5589 1 @ 2 0_0402_5% USB20_P9_R 8 8
3

2
8 LID_SW# 6 USB20_N9 R5590 1 @ 2 0_0402_5% USB20_N9_R 9
GND 6 [18] USB20_N9 R02 9
1 1 @ D24 7 10
7 USB20_P9 10
C1304 @ @ ACES_88514-00601-071 8 8 2 2 1 1 USB20_P9_R 11 11
100P_0402_50V8J

C1305 9 +3VS 12
GND 12
100P_0402_50V8J

PJSOT24C 3P C/A SOT-23 10 WCM-2012-900T_4P 13

2 2 GND EXT_MIC R20 R5568 13
D58 [41] EXT_MIC 1 @ 2 0_0603_5% EXT_MIC_R 14
1

1
HP_OUTR 14
PACDN042Y3R_SOT23-3 ACES_51524-00801-001
[41] HP_OUTR
R5569 1 @ 2 0_0603_5% HP_OUTR_R 15 15
@ HP_OUTL R5570 1 @ 2 0_0603_5% HP_OUTL_R 16
[41] HP_OUTL 16
[41] PLUG_IN PLUG_IN 17 19
17 G1
18 18 G2 20

1 ACES_50505-0184N-001
LID_SW# [42]
0_0402_5% C1321
@ ME@
[12,13,15,36] SMB_CLK_S3
R723 1 @ 2 SMB_CLK_S3_R 100P_0402_50V8J
[12,13,15,36] SMB_DATA_S3
R724 1 @ 2 SMB_DATA_S3_R
0_0402_5% 2

LED (For 14")

LED1 14@ R10

PWR_LED#
R623 LED (For 15")
[42] PWR_LED# 1 2 2 1 +5VALW
560_0402_5%
14@
19-213A-T1D-CP2Q2HY-3T_WHITE
JLED1 ME@
LED2 14@ +5VALW 1 1
Right Side USB2.0 Port X 2 (USB/B)
+3VALW 2 2
[42] BATT_LOW_LED# BATT_LOW_LED# 1 2 2 R764 1 +3VALW PWR_LED# 3
470_0402_5% BATT_LOW_LED# 3
4 4
BATT_CHG_LED# 5 +5VALW +USB_VCCB
14@ 5
HT-191UD5_AMBER 6 U42
6
1 GND VOUT 8
LED5 14@ R10 7 C768 0.1U_0402_16V7K 2 7
R765 GND VIN VOUT
8 GND 2 1 3 VIN VOUT 6
[42] BATT_CHG_LED# BATT_CHG_LED# 1 2 2 1 +5VALW [42,45] USB_ON# USB_ON# 4 5 USB_OC4#
130_0402_5% ACES_88514-00601-071 EN FLG USB_OC4# [18]
14@ SY6288DCAC_MSOP8 1
19-213A-T1D-CP2Q2HY-3T_WHITE C905
@ 1000P_0402_50V7K
Low Active 2A 2

EC RESEST function KB Lighting CONN.4pin

R20 R03 ACES_88514-0401
R4961 1 @ 2 0_0402_5% ME@
+3VALW
6 GND
R4960 1 @ 2 0_0402_5% +VCC_KB_LED 5
+3VLP GND
U74 RESET@
C554 1 2 0.1U_0402_16V7K 1 6 R4958 1 @ 2 0_0402_5% +3VS 4
MRDLY VCC 4
2 5 3

0.1U_0402_16V7K
GND RESET KBC_HANGUP_RESET# [42,50] 3

C1314
RESET@ 3 CD MR 4 2 2 2
1 R03 1
R20 S IC G601A31U ADFN 6P RESET 1
R5579 1 @ 2 0_0402_5% C1311 RESET@ @ JKBL1
0.1U_0402_16V7K 1
ON/OFFBTN# 1 2 2
D59 CH751H-40PT_SOD323-2
@

SA00005VZ00 S IC G601A31U ADFN 6P RESET +5VS

+5VALW
+VCC_KB_LED
Touch Screen Q153

D
11/07 change to +5VALW 3 1
R5548
10K_0402_5% AO3413_SOT23-3
KBL@

KBL@ C1315
KBL@ KBL@

10U_0603_6.3V6M
1 2

2
R02, 10/22 Add
R5581 TS@ C1331 TS@ 1 R5549 2 C1316
10K_0402_5% 0.1U_0402_16V7K JTS1 100K_0402_5% 0.1U_0402_16V7K
1 2 1 2 1 KBL@ KBL@ 2 1
[42] EC_TS_ON# +3VS_TS 1 1
R20 2 2 C1317
[18] USB20_N1
R718 1 @ 2 0_0402_5% USB20_N1_R 3 3
+3VS_TS_R +3VS_TS R719 1 @ 2 0_0402_5% USB20_P1_R 4 0.01U_0402_16V7K
[18] USB20_P1
R10 4 2
5 5 G1 7

1
EC_TS_ON# R721 1 @ 2 0_0402_5% TS_RST# 6 8
6 G2
OUT
S

3 1 ACES_87213-0600G
ME@ 11/07 Change type to 0603
[40,42] LED_KB_PWM_R 2 IN
Q156 Touch Screen
G

0.1U_0402_16V7K

GND
2

+5VS +3VS_TS_R
C1322

PMV65XP_SOT23-3~D2
TS@ Q154
R10 DTC124EKAT146_SC59-3
3

TS@ 1 TS_15@ 2 KBL@

1 R03 R5592 0_0402_5%
+3VS +3VS_TS
R02
1 TS_14@ 2 1 @ 2
R5572 0_0402_5% R5583 0_0402_5%
+3VALW Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/15 2012/07/11 Title
1 2
Issued Date Deciphered Date SCHEMATICS,MB A9061
R5584 @ 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 43 of 63
 A B C D E

RTS5178 CardReader U9 RTS5170@

R20
+3VS R76 2 @ 1 0_0603_5% +3VS_CARD

SA00005T300 S IC RTS5170-GR QFN 24P CARD READER

U9
JCR1
+3VS_CARD +VCC_3IN1 R31 2 CR@ 1 6.19K_0402_1% RREF 1 4
RREF +VCC_3IN1 VDD
MS_BS/SP14 22
R20 21 SD_D2_R R3 1 @ 2 0_0402_5% SD_D2 1 SD_D0 7
SD_D2/SP13 DAT0

C50
R688 2 @ 1 0_0402_5% USB20_N11_C 2 20 SD_D3_R R4 1 @ 2 0_0402_5% SD_D3 SD_D1 8
[18] USB20_N11 DM MS_D1/SD_D3/SP12 DAT1
R684 2 @ 1 0_0402_5% USB20_P11_C 3 19 SD_D2 9
1 [18] USB20_P11 DP SP11 DAT2 1
C40 C36 C37 R6 18 SD_CMD_R R5 1 @ 2 0_0402_5% SD_CMD CR@ SD_D3 1
SD_CMD/SP10 DAT3

2
2

4.7U_0603_6.3V6K
1 1 1 Trace width:40mil 4
MS_D0/SP9 16
15 SD_CLK_R R8 1 CR@ 2 0_0402_5% SD_CLK SD_CD# 11
+3VS_CARD 3V3_IN MS_D2/SD_CLK/SP8 CD
CR@ CR@ CR@ @ +VCC_3IN1 5 14 SD_WP/XD_D7 10
CARD_3V3 SP7 WP
0.1U_0402_16V7K

4.7U_0603_6.3V6K

0.1U_0402_16V7K

10K_0402_5%
13 SD_CD# 1
2 2 2 SD_CD#/SP6 SD_CMD
12 2

1
MS_D3/SP5 SD_D0_R R14 1 @ SD_D0 SD_CLK CMD
7 XD_CD# SD_D0/SP4 11 2 0_0402_5% C41 @ 5 CLK
23 10 SD_D1_R R19 1 @ 2 0_0402_5% SD_D1 5P_0402_50V8C
XD_D7 SD_D1/SP3

2
2
17 GPIO0 MS_INS#/SP2 9 3 VSS1 GND 12
8 SD_WP/XD_D7 R80 @ 6 13
MS_CLK/SD_WP/SP1 0_0402_5% VSS2 GND
6 SDREG
V18 24 TAITW_PSDBTC-09GLBS1N14N0
V18 ME@

1
C42 C43 25
2 2
Thermal pad
1 SD/MMC
CR@ CR@ RTS5178-GR_QFN24_4X4
RTS5178@ C45 @
C37 R6 close to JCR1 Pin4 68P_0402_50V8K

De-coupling and Bulk

1 1 update PN to RTS5178 (SA000050K00) 2

1U_0402_6.3V6K

1U_0402_6.3V6K
0907 Vendor not agree mount C45
capacitor should place
near to RTS5179 chip and
Combo Socket

2 2

Every power trace need:

Green Clock W=20mils
U69 GCLK244@ U69 GCLK304@

For GreenCLK generate CLK:

SLG3NB244VTR_TQFN16_2X3SLG3NB300VTR_TQFN16_2X3
+CHGRTC_R
Mount: All parts in this page except
+RTCBATT
R10
Swing Level RES (Marked "*")
2
NA: PD108,
+3VLP RG10 @

+3VLP +V1.05S_VCCP +3V_GCLK +3VS_VGA +3V_GCLK

0_0402_5% Y1,R98,C180,C181,
1 Y2,R169,C196,C197,
1

3 3
0_0402_5%

CG3 GCLK@
1

GCLK@ 1 22U_0805_6.3V6M Y6,C968,C969

0_0402_5%

CG2 1
1

2
GCLK304@
0.1U_0402_16V7K

RG9

CG4
2 R02 @ 2.2U_0402_6.3V6M
2

U69
1

R02 2 GCLK@
RG11
2
RG8

@ 0_0402_5% 1 10 14
CG6 VBAT VDD_RTC_OUT
GCLK@ 1
0.1U_0402_16V7K

15 +V3.3A
2

GCLK304@

CG5
2 +3VS_GCLK
0.1U_0402_16V7K

2 1 2 VDD
GCLK@ 1 CG1 9 GCLK_32K_R RG1 1 2 0_0402_5% GCLK_32K
CG7 2
0.1U_0402_16V7K
32kHz GCLK@
GCLK_32K [14]
PCH_32.768K
0.1U_0402_16V7K

2
GCLK@ VGA_GCLK 11 VDDIO_27M 27MHz 12 GCLK_27MHZ_R RG2 1 2 22_0402_5%
GCLK304@
GCLK_27MHZ
GCLK_27MHZ [23] NV_GPU
8 VDDIO_25M_A 25MHz_A 6 GCLK_LAN_25MHZ_R RG3 1
GCLK@
2 33_0402_5% GCLK_LAN_25MHZ GCLK_LAN_25MHZ [37] LAN
PCH_GCLK 3 VDDIO_25M_B 25MHz_B 5 GCLK_PCH_25MHZ_R RG4 1
GCLK@
2 0_0402_5% GCLK_PCH_25MHZ GCLK_PCH_25MHZ [15] PCH_25M
GreenCLK_XTALI 1
Y8 GreenCLK_XTALO 16
XTAL_IN
XTAL_OUT
Close to GCLK
GND1
GND2
GND3

GND4

4 NC OSC 3

1 OSC NC 2
SLG3NB274VTR_TQFN16_2X3
Reserved for Swing Level adjustment
4
7
13

17

1 GCLK@ 1
GCLK@ CG8 25MHZ_10PF_7V25000014 GCLK@ CG9 GCLK274@
15P_0402_50V8J 15P_0402_50V8J
( Close GCLK side )
2 2
@
GCLK_27MHZ RG5 *1 2 0_0402_5%

RG13 GCLK@ CG10 GCLK@ @

4 10K_0402_5% 0.1U_0402_16V7K GCLK_LAN_25MHZ RG6 * 1 2 0_0402_5% 4
[36,42] EC_WL_WAKE# 1 2 1 2
@
GCLK_PCH_25MHZ RG7 *1 2 0_0402_5%
+3VALW +3V_GCLK
S

3 1

QG1 Security Classification Compal Secret Data Compal Electronics, Inc.

G
2

PMV65XP_SOT23-3~D 2011/06/15 2012/07/11 Title

GCLK@
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 44 of 63
A B C D E
 5 4 3 2 1

LEFT SIDE USB3.0 PORT X1

+5VALW +5V_CHGUSB
U41
C767 0.1U_0402_16V7K 1 8
GND VOUT
2 1 2 VIN VOUT 7
3 VIN VOUT 6
[42,43] USB_ON# R1169 1 NOCHG@
2 0_0402_5% 4 5 USB_OC0#
EN FLG USB_OC0# [18] +5V_CHGUSB
D D
For EMI request PWRSHARE_EN# R1168 1 @ 2 0_0402_5% SY6288DCAC_MSOP8 1 C814 220U_6.3V_M
C904

+
1 2
USB2.0 choke --> SM070000K00 [42] EC_PWRSHARE_EN# R5577 1 CHG@ 2 0_0402_5% @ 1000P_0402_50V7K

R02
Low Active 2A 2
USB3.0 Choke --> SM070001S00 1 2
C816 470P_0402_50V7K

R20
L68
USB30_RX_N1 2 1 USB30_RX_R_N1 R20 JUSB1 ME@
2 1 USB30_TX_P1 C299 1 USB30_TX_C_P1
[18] USB30_TX_P1 2 0.1U_0402_16V7K R1156 1 @ 2 0_0402_5% USB30_TX_R_P1 9 SSTX+
R20 1
USB30_RX_P1 VBUS
3 3 4 4 USB30_RX_R_P1 [18] USB30_TX_N1
USB30_TX_N1 C300 1 2 0.1U_0402_16V7K USB30_TX_C_N1 R1157 1 @ 2 0_0402_5% USB30_TX_R_N1 8 SSTX-
USB20_P0_C R1162 1 @ 2 0_0402_5% USB20_P0_R 3
WCM-2012HS-900T_4P D+
7 GND
R20 USB20_N0_C R1163 1 @ 2 0_0402_5% USB20_N0_R 2 10
USB30_RX_P1 D- GND
L70
[18] USB30_RX_P1
R1154 1 @ 2 0_0402_5% USB30_RX_R_P1 6 SSRX+ GND 11
USB30_TX_C_N1 2 USB30_TX_R_N1 R20
2 1 1 USB30_RX_N1
4 GND GND 12
[18] USB30_RX_N1
R1155 1 @ 2 0_0402_5% USB30_RX_R_N1 5 SSRX- GND 13

USB30_TX_C_P1 3 4 USB30_TX_R_P1 TAITW_PUBAU1-09FNLSCNN4H0

3 4
For ESD request
WCM-2012HS-900T_4P
D27 D28
@ @
C USB20_N0_C 3 L72 4 USB20_N0_R USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USB20_P0_R 3 6 C
3 4 I/O2 I/O4
USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1
USB20_P0_C 2 1 USB20_P0_R
2 1 USB30_TX_R_N1 7 7 4 4 USB30_TX_R_N1 2 GND VDD 5 +5VALW
WCM-2012-900T_4P
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

3 3 1 4 USB20_N0_R
I/O1 I/O3
8 AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9

Left Side Charger USB3.0 Port

R20

R20 U76
[42] PWRSHARE_EN_R
R5578 1 @ 2 0_0402_5% PWRSHARE_EN 1 CEN CB 8 R5555 1 @ 2 0_0402_5% CHG_ON# [42]
USB20_N0_C 2 7 USB20_N0 [18]
DM TDM

1
USB20_P0_C 3 6 USB20_P0 [18]
SELCDP DP TDP R5556
4 SELCDP VDD 5 +5VALW
B 9 100K_0402_5% B
Thermal Pad CHG@
2

SLG55584AVTR_TDFN8_2X2

2
CHG@ C991
0.1U_0402_16V7K
1

CHG@

+5VALW R03
+5VALW +5VALW
NOCHG@ NOCHG@
1

USB20_P0 R1167 1 2 0_0402_5% USB20_P0_C_R R1171 1 2 0_0402_5% USB20_P0_C

1

R5558 USB20_N0 R1166 1 2 0_0402_5% USB20_N0_C_R R1170 1 2 0_0402_5% USB20_N0_C

R5560 R5557 10K_0402_5% NOCHG@ NOCHG@
10K_0402_5% 10K_0402_5% @
2

CHG@ CHG@ PWRSHARE_EN#

2

Q155 D
SELCDP PWRSHARE_EN 2N7002_SOT23 2 PWRSHARE_EN CB SELCDP Function
@ G
S R02 0 X DCP autodetect with mouse /keyboard wakeup
3
1

Remove R1170
R5559 1 0 S0 charging with SDP only
R5561 10K_0402_5%
10K_0402_5% @ 1 1 S0 charging with CDP or SDP only (depending on external device )
A @ A
2

USB2.0/3.0 choke and ESD diode at sub-B.

Security Classification Compal Secret Data
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 45 of 63
5 4 3 2 1
 A B C D E

+5VALW TO +5VS +3VALW TO +3VS for Deep Sleep S3 +5VALW

2
+5VALW +5VS +3VALW +3VS
U38 R5531
U39 100K_0402_5%
AP4800BGM-HF_SO-8 AP4800BGM-HF_SO-8 R03 DS3@
8 1 8 1 DS3@

1
1 7 2 1 1 10U 1 7 2 1 1 R5591 PCH_PWR_EN#

1
6 3 6 3 [42] PCH_PWR_EN2 1 2
C720 5 C721 C722 C723 5 C724 C725 0_0402_5%
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K @ R644 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R645

1
2 2 2 470_0603_5% 2 2 2 470_0603_5% @ D

4
10U 10U @ 1 R5532 2 2 Q151
[42,48] PCH_PWR_EN

1 2

1 2
+VSB 0_0402_5% G DS3@

1
D +VSB D
S SB570020110

3
2 SUSP 2 SUSP [16,42] SLP_SUS# 1 @ 2 2N7002E-T1-E3_SOT23-3
1

1
1 1
G G 0_0402_5% R5529
R646 S @ Q107 S Q108 R5533 100K_0402_5%

3
150K_0402_5% 2N7002K_SOT23-3 R647 2N7002K_SOT23-3 @

2
470K_0402_1% @
2

2
5VS_GATE2 R649 15VS_GATE_R
1 1
1

2
D D
SUSP Q110 82K_0402_5% C726 SUSP Q111 R650 C727
2 2
G 2N7002K_SOT23-3 0.01U_0402_25V7K G 2N7002K_SOT23-3 0_0402_5% 0.01U_0402_25V7K
S 2 S @ 2 for Deep Sleep S3 +3VALW +3VALW TO +3V_PCH +3V_PCH
3

3
@

1
2 1

2MM J20

DS3@ Q152 AO3413_SOT23

D
3 1
+1.8VS +1.5V +V1.05S_VCCP +0.75VS +1.5V to +1.5VS

0.1U_0402_16V7K

20K_0402_5%~D
G
2

1
+1.5V Q8 +1.5VS
1
1

R5535
PMV65XP_SOT23-3~D

C1312
PCH_PWR_EN# R5534 2 DS3@ 1 47K_0402_5% DS3@ @

D
R655 R656 R659 R658 3 1
470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% 2
1 1 1

2
1
@ @ @ 2 1 1
CPU1.5V_S3_GATE [10,42]
1 2

1 2

1 2

1 2

@ R91 0_0402_5% C717 C718 C719

0.1U_0402_16V7K
G
2
D D D D

C1313
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R643 DS3@
2 2 2
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 470_0603_5%
G G G G @ 2

2
S Q113 S Q114 S Q116 S Q115
3

2N7002K_SOT23-3 2N7002K_SOT23-3 2N7002K_SOT23-3 2N7002K_SOT23-3

1
@ @ @ +3VALW D
2 SUSP
2 For Intel S3 Power Reduction. G 2

1
S Q109

3
2N7002K_SOT23-3
100K_0402_5% @ for Deep Sleep S3
R648 +5VALW +5VALW TO +5V_PCH +5V_PCH
@

2
2 R651 1 1.5VS_GATE
Q112 1 2 1

1
D
SUSP# 2 0_0402_5% C729 2MM J21
G 0.1U_0402_16V7K
2N7002K_SOT23-3 S 2

3
DS3@ QH1 AO3413_SOT23

D
3 1

0.1U_0402_16V7K

20K_0402_5%~D
1
G
1

RH1
CH1
DS3@ @
PCH_PWR_EN# 1 2
0_0402_5% 2

2
DS3@ R5573 1
@

0.1U_0402_16V7K
C1323
2

+RTCVCC +5VALW +5VALW

2

R652 @
220K_0402_5% R653 R654 @
100K_0402_5% 100K_0402_5%
1

SUSP SYSON#
[10,51,54] SUSP
1

Q117
+1.5V to +1.5VS_VGA Transfer
1

3 3
DTC124EKAT146_SC59-3 Q119@
OUT

DTC124EKAT146_SC59-3
OUT

SYSON 2 +1.5V +1.5VS_VGA

[42,51] SYSON IN
2
GND

[10,25,42,51,53,54] SUSP# IN
GND

Del J12
300mil(7.2A)
3
1

+5VALW
1 1
R1110 @ OPT@
100K_0402_5% C856 C851
1

10U_0603_6.3V6M AO4430: Rdson: 5.5mohm @ VGS=10V 10U_0603_6.3V6M

2

2 2 @
R1107 OPT@
100K_0402_5% U49 AO4304L_SO8
OPT@
300mil(7.2A)
8 1
2

7 2
DGPU_PWROK# 6 3
DGPU_PWROK# [54]

2
R20 5 1 1
1

R1106 0_0402_5% D C853 C854 R1101

1
2 @ 1 2 Q129 C852 10U_0603_6.3V6M 0.1U_0402_16V7K 470_0603_5%
[19,54] DGPU_PWROK

4
G 2N7002K_SOT23-3 10U_0603_6.3V6M OPT@ OPT@ @
S OPT@ OPT@ 2 2
3

1
2
2
1

R4963
+VSB 0_0402_5%
R1108 @
100K_0402_5% R1102 10K_0402_5%

1
@ 2 1
2

1
OPT@ D @
1 @ Q127 2 2 R790 1 DGPU_PWROK#
C855 2N7002K_SOT23-3 G 0_0402_5%
Q126OPT@ 0.1U_0402_25V7K S

3
2N7002K_SOT23-3 OPT@
1

R20 D 2 SUSP
2 R791 @1
DGPU_PWROK#R782 2 @ 1 0_0402_5% 2 0_0402_5%
G
S
3

4 4
SUSP 2 R789 @1
0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 46 of 63
A B C D E
 5 4 3 2 1

D D

VIN

PF101 PL101
JDCIN 7A_24VDC_429007.WRML SMB3025500YA_2P
1 APDIN 1 2 APDIN1 1 2
1
2 2
3 3
4 4

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
GND 5
GND 6

1
@
ACES_50305-00441-001

2
PC101

PC102

PC103

PC104
C
20120723 C
For all sku
1. Change PR108 to 150_0603_5% SD013150080 from 560_0603_5% SD013560080
Change PR109 to 1K_0603_5% SD013100180 from 560_0603_5% SD013560080

+3VLP
20120731
+CHGRTC_R 1. Change PR106 footprint to R0402_0ohm-NEW
+CHGRTC

1
- JRTC1 + PR108
150_0603_5%
PR109
1K_0603_5%
PD103
RB751V-40_SOD323-2
PR106
0_0402_5%
2 1 1 2 1 2 2 1 +RTCBATT @

2
@ MAXEL_ML1220T10 1 2
RTCVREF
PD104
RB751V-40_SOD323-2

RTC Battery

20120731
1. Add PR110 SD013000080 0_0603_5%
B Add PR111 SD013150080 150_0603_5% B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Xz90 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 47 of 63
5 4 3 2 1
 5 4 3 2 1

VMB2 VMB
JBATT1 PF201 PL201
12A_65V_451012MRL SMB3025500YA_2P
1 1
2 2 1 2 1 2 BATT+
3 3
4 4 EC_SMCA
5 5 EC_SMDA
6 6

1
D D
7 7

1
PC201 PC202
8 8

100_0402_1%

100_0402_1%
1000P_0402_50V7K 0.01U_0402_25V7K
9 9 ADP_I need to write Charge Options Register (0x12H)=> bit6=1

2
10 10 PR201

PR202
ACES_50299-01001-001
2

2
0: IOUT is the 20x current amplifier output <default @ POR>
ME@
1: IOUT is the 40x current amplifier output

90W(DIS) : 6.65K 100W active 90W recovery

PH201 under CPU botten side :
65W(UMA): 1.65K 70W active 65W recovery
EC_SMB_CK1 [42,49] CPU thermal protection at 93 +-3 degree C 20120314
Recovery at 56 +-3 degree C Change to +EC_VCCA from +3VLP
EC_SMB_DA1 [42,49]

1 2 +3VALW
VL
PR203
6.49K_0402_1%
+EC_VCCA
[42,49] ADP_I

21.5K_0402_1%
2

1
6.65K_0402_1%

12.7K_0402_1%
1

PR207
1 2 BATT_TEMP [42] A/D

PR205

PR206
PR204

1
10K_0402_5%
PC203 +3VS

2
@ 0.1U_0603_16V7K PU201

2
1 8 NTC_V_1 @
VCC TMSNS1

100K_0402_1%
C OTP_N_002 C
2 GND RHYST1 7 2 1

PR208
PR209
3 6 Turbo_V_1 @ 10K_0402_1%
[42,6] H_PROCHOT# OT1 TMSNS2

100K_0402_1%_TSM0B104F4251RZ
PR210
4 5 ADP_OCP_2 1 2

1
OT2 RHYST2

1
PQ201

2
D

10K_0402_1%

PH201
@ G718TM1U_SOT23-8 @ 27.4K_0402_1% PR213
PR211

PR212
2ADP_OCP_1 0_0402_5% PR235

OTP_N_003
G @ 0_0402_5% @ 0_0402_5%
S 2N7002KW_SOT323-3 90W(DIS) : 27.4K @

2
2
65W(UMA) : 5.11K 1 2

1
2
PR216
@ 47K_0402_1%

1
[42] PROCHOT

0_0402_5%
1 2 2 1 1 2 ECAGND
MAINPWON [42,50]

PR218
PR217
PR214 @ PR215 0_0402_5% 1 2
@ 0_0402_5% +3VALW
@ 0_0402_5%

2
@

Turbo_V

NTC_V
[42]

[42]
20120731
1. Change PR214,PR211,PR213 and PR235 footprint to R0402_0ohm-NEW

B B

PQ202
TP0610K-T1-GE3_SOT23-3

B+ 3 1 +VSBP

100K_0402_1%

0.22U_0603_25V7K
1

1
PR219

PC204
PC205
0.1U_0603_25V7K

2
2

2
PR220
VL 22K_0402_1%
1 2
2

PR221
@ 100K_0402_1%

PR222
1

@ 1K_0402_5% D PJ201
1 2 2 PQ203 @ JUMP_43X39
[50] SPOK
G 2N7002KW_SOT323-3 1 1
+VSBP 2 2 +VSB
1U_0402_6.3V6K

S
3
1

PC206

PR223
1K_0402_5%
[42,46] PCH_PWR_EN 1 2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Zx90 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 48 of 63
5 4 3 2 1
 5 4 3 2 1

P3
B+ Need EC write ChargeOption() bit[8]=1
P2
Setting (ACP to PHASE Rising Threshold)=1350mV(min)
PQ301 PQ302
AO4407AL_SO8 AO4423L_SO8
PR302
VIN 8 1 1 8
0.01_1206_1% CHG_B+
7
6
2
3
2
3
7
6
SH00000AA00
5 5 1 4 1 2 PQ303
PL301 AO4407AL_SO8
2 3 1UH_PCMB061H-1R0MS_7A_20% 1 8

4
2 7

@ 10U_0805_25V6K

@ 10U_0805_25V6K
3 6

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D
PQ304 5 D
47K_0402_5%

1 2
1

2
200K_0402_1%
0.1U_0603_25V7K

PC308

4
1
PR301

PC303

PC304

PC305

PC306

PC307
DTA144EUA_SC70-3 PC302 DISCHG_G

PC301

PR303
5600P_0402_25V7K

1
PR304
200K_0402_1%
2

2
2 1 2

2
ACN VIN

1SS355_SOD323-2
2ACOFF
2
1

ACP PR305

1DISCHG_G-1
47K_0402_1%
1

2
+3VALW

PD301
0.1U_0603_25V7K
P2-1 PR306

1
2 200K_0402_1%
PQ305 PQ306
PC309 PC310 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3
[49] ACPRN
1 2 2 1
3

0.1U_0603_25V7K 2 1 2
6

150K_0402_1%

PC311 PD302 PQ308

PR307

PQ307A 1SS355_SOD323-2
2 2N7002KDW-2N_SOT363-6 0.1U_0603_25V7K P2 2N7002KW_SOT323-3

1
D

0.1U_0603_25V7K
2 1 2 PACIN
1

1
PC312
VIN @ @ G

10K_0402_5%

10K_0402_5%
S

3
2

2
390K_0603_1%

2
1
P2-2

10_1206_5%
PR309

PR310

5
6
7
8
C C
PR308
2N7002KDW-2N_SOT363-6

PQ309
AO4466L_SO8
PR311
3
PQ307B

<BOM Structure>

ACOK

CMPOUT
CMPIN

ACP

ACN
1

1
PR312 [42,48] ADP_I
2

47K_0402_1% PR313 21

1
PACIN 1 TP
PACIN 2 5 1 2 6 ACDET PC315 4

59K_0603_1% PC314 20 BQ24727VCC1 2

4

PC313 VCC
ACON 1 2 7 IOUT
1 2 PL302 PR314

3
2
1
1U_0603_25V6K
1

PQ310 100P_0603_50V8 19 10UH_PCMB063T-100MS_4A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 0.1U_0603_25V7K
[42,48] EC_SMB_DA1
8 SDA
PU301 BATT+
BQ24727RGRR_QFN20_3P5X3P5 LX_CHG 1 2CHG 1 4
18 DH_CHG
HIDRV

5
6
7
8
ACOFF
[42] ACOFF 2 9 SCL SA000051W00 2 3

1
[42,48] EC_SMB_CK1

PQ311
AO4466L_SO8

4.7_1206_5%
PR316 PR317 PC316

PR318
316K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K

10U_0805_25V6K

10U_0805_25V6K
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
ILIM BTST
1

16251_SN
+3VALW PD303
3

PR319 4 @

LODRV

1
PC317

PC318
100K_0402_1% 16 2 1

GND
SRN

SRP
REGN

BM
20120615
Change PR313 to 60.4K_0603_1% SD014604280
2

2
RB751V-40_SOD323-2

680P_0603_50V7K
11

1 12

13

14

15

3
2
1
1

1
10_0603_5%
from 64.9K_0603_1% SD014649280

PC319
6.8_0603_5%

2
BQ24727VDD

PR321
PC320

PR320
1U_0603_25V6K

2
20120723 @
Change PR313 to 59K_0603_1% SD014590280
from 60.4K_0603_1% SD014604280 2
2

PC321 DL_CHG
B 0.1U_0603_25V7K B
2 1
1

1
PC322 @
0.1U_0603_25V7K PC323
2

2 0.1U_0603_25V7K

BQ24727VDD

PR322
10K_0402_1%
1

1 2 ACIN [16,42]
PR324
PR323 10K_0402_1%
47K_0402_1%
PACIN
2

1 2

ACPRN [49] PR325

2
12K_0402_1%
2

PQ312

A DTC115EUA_SC70-3 A
3

For disable pre-charge circuit.

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Zx90
Date: Monday, December 17, 2012 Sheet 49 of 63

5 4 3 2 1
 5 4 3 2 1

2VREF_8205 PJ402
+3VALWP 2 2 1 1 +3VALW
@ JUMP_43X118

1U_0603_10V6K
D D

1
PC402
PJ403
+5VALWP 2 1 +5VALW

2
2 1
@ JUMP_43X118

PR401 PR402
20120321 13K_0402_1% 30K_0402_1%
Change netname to CPU_B+ from B+ 1 2 1 2

PR403 PR404
RT8205_B+ 20K_0402_1% 19.6K_0402_1% RT8205_B+
1 2 1 2
CPU_B+ PJ401 Typ: 175mA
0.1U_0603_25V7K

2 2 1 1 +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

2200P_0402_50V7K
PC401

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.1U_0603_25V7K
@ JUMP_43X118 PR405 PR406
1

130K_0402_1% 66.5K_0402_1%
PC403

PC409
4.7U_0805_10V6K
1 2 1 2
1

1
PC404

PC405

PC406

PC407

PC408

PC411
2

8
7
6
5

5
6
7
8
2

2
PC410

ENTRIP2

REF
FB2

FB1

ENTRIP1
TONSEL
1

MDS1525URH_SO8
C PQ401 C

PQ402
25 P PAD
AO4466L_SO8

2
4 4
7 VO2 VO1 24
SPOK [48]
8 23 PR408 PC413
PR407 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
2.2_0603_5%
PL401 PC412 UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH_PCMB063T-4R7MS_5.5A_20% 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_PCMB063T-4R7MS_5.5A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
4.7_1206_5%

4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1

5
6
7
8
PR409

PR410
PQ403

SKIPSEL
[42,43,50] KBC_HANGUP_RESET#

150U_B2_6.3VM_R35M
AO4712L_SO8

VREG5
PU401

GND

VIN
@ RT8205LZQW(2)_WQFN24_4X4 @

NC
EN
1 2 1 1
2

2
4 0_0402_5%
+ +

PC416
@ PR420 4

13

14

15

16

17

18
1

1
680P_0603_50V7K

PC414 PR411

680P_0603_50V7K
PQ404
150U_B2_6.3VM_R35M 499K_0402_1%

MDS1521URH 1N SO8
2 2
PC417

PC418
1 2
2

1
2
3

2
CPU_B+

3
2
1
1
100K_0402_1%

1U_0603_10V6K
@ 20120402 @
+3VALWP VL

1
PC419
Change netname to CPU_B+ from B+

1
PR412

PC420
OCP min 6.8A

4.7U_0805_10V6K
B Typ: 175mA B

2
OVP min 3.56V ENTRIP1 ENTRIP2
2

2
RT8205_B+
6

1
PQ405B

0.1U_0603_25V7K
PQ405A 2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6 2 5 2VREF_8205

2
PC421
,43,50] KBC_HANGUP_RESET#
1

20120606
+5VALWP
PR419 and PR420 unmount OCP min 8.5A
2

@ PR419 PR415 OVP min 5.4V

0_0402_5% 100K_0402_1%
VL 2 1
[42] EC_ON
1

PR413
2.2K_0402_5%
2 1
PQ407
PR414
[42,48] MAINPWON @ 0_0402_5% 2N7002KW_SOT323-3
1

D
1 2 2
G
4.7U_0603_6.3V6M

S
3

A A
1

PC422

20120731
1. Change PR414 footprint to R0402_0ohm-NEW
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Zx90
Date: Monday, December 17, 2012 Sheet 50 of 63
5 4 3 2 1
 A B C D

@PJ501
@PJ501
1.5V_B+ 1 1 2 2 CPU_B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K
STATE S3 S5 1.5VP VTT_REFP 0.75VSP JUMP_43X118

1
PC501

PC502
S0 Hi Hi On On On 20120321

5
Change netname to CPU_B+ from B+
Off

2
S3 Lo Hi On On (Hi-Z) +1.5VP PQ501
TPCA8065-H_PPAK56-8-5
UG_1.5V 4
S4/S5 Lo Lo Off Off Off PJ502 @

1
1
JUMP_43X39 20120405 1

LX_1.5V

1
Change PL501 to H = 3 SH00000AB00

3
2
1
Note: S3 - sleep ; S5 - power off

2
PR501 PC503 PL501

2
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB103T-1R0MS_13A_20%
BST_1.5V 1 2 BST_1.5V-1 1 2 2 1
+0.75VSP +1.5VP

10U_0805_25V6K

10U_0805_25V6K

1
5

TPCA8057-H_PPAK56-8-5
20

19

18

17

16
<BOM Structure> <BOM Structure>

PQ502
PC504

PC505
PU501 PR502 @
4.7_1206_5% 1

VTT

VLDOIN

BOOT

UGATE

PHASE
21

2
PAD + PC506
1 15 LG_1.5V 4 330U_D2_2.5VY_R9M
VTTGND LGATE

1
2

680P_0603_50V7K
2 VTTSNS PGND 14

PC507
PR503

3
2
1

2
6.65K_0402_1%
3 GND CS 13 2 1
RT8207MZQW_WQFN20_3X3

4 12
+1.5VP
+VTT_REFP VTTREF VDDP @ OCP min 20A
5 11 2 1 OVP min 1.65V
+1.5VP VDDQ VDD
+5VALW

PGOOD
PR504
+3VALW
1

1U_0603_10V6K
5.1_0603_5%

TON
PC508

FB

S3

S5
2 0.033U_0402_16V7K 2
2

1
10K_0402_5%
PC509
6

10

PR505
PC510
1U_0603_10V6K

S3_1.5V

2
PR506

S5_1.5V
49.9K_0402_5% @

2
42,46,51,53,54] SUSP# 1 2 PGOOD_1.5V
20120321
PR507 PR508
0_0402_5% 887K_0402_1% Add PJ507
[42,46] SYSON 1 2 2 1 1.5V_B+

PR509 PJ507
1

PC511 @PC512
@ PC512 6.34K_0402_1% 2 1
0.1U_0402_16V6K 0.1U_0402_16V7K 2 1
2 1
@ JUMP_43X118
2

PQ503@ FB=0.75V 20120626

1

D
1

2N7002KW_SOT323-3 PJ503
2 To GND = 1.5V Change PR509 to 6.34K_0402_1% SD034634180 from 5.9K_0402_1% SD034590180 +1.5VP 2 1 +1.5V
G PR510 To VDD = 1.8V 2 1
[10,46,54] SUSP S
5.76K_0402_1% @ JUMP_43X118
3

PJ504

+0.75VSP 2 2 1 1 +0.75VS

JUMP_43X79
@
3 3

20120723
Change PU502 to SA00004CY10 S IC RT8061AZQW WDFN 10P PWM from SA00003RU00 S IC SY8033BDBC DFN 10P SINGLE BUCK

PU502 PL502
+1.8VP
4

PJ505
1.8VSP_VIN 1.8VSP_LX
1UH_PH041H-1R0MS_3.8A_20% current limit min 4A
+3VALW 2 1 10 2 1 2
PG

2 1 PVIN LX +1.8VSP
68P_0402_50V8J

@ JUMP_43X79 9 3
PVIN LX
1

1
680P_0603_50V7K 4.7_1206_5%
1

1
PC514

PC513 8 SVIN
PR511

22U_0805_6.3VAM PR512

2200P_0402_50V7K

68P_0402_50V8J

0.1U_0402_25V6
6 20K_0402_1%
2

FB
22U_0805_6.3VAM

22U_0805_6.3VAM
5
1 2

EN
1

1
PC520

PC517

PC518
@ PJ506
NC

NC
TP

PC515

PC516
FB=0.6Volt +1.8VSP 2 1 +1.8VS
2 1
[10,25,42,46,51,53,54] SUSP#
PC519

PR513
11

2
1 2 EN_1.8VSP @ JUMP_43X79
2
0.1U_0402_10V7K

0_0402_5% @
2

PC521 @

SY8033BDBC_DFN10_3X3 @ @
1

PR514 @ 1.8VSP max current=4A

1M_0402_5%
1.8VSP_FB
2
1

PR515
4
10K_0402_1% 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Zx90 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 51 of 63
A B C D
 5 4 3 2 1

D D
+3VS PR602
1K_0402_5%
2 1
VID [0] VID[1] VCCSA Vout

100K_0402_5%
PJ602
+VCC_SAP +VCCSA
0 0 0.9V H_VCCSA_VID1 [10] +VCCSAP 2 2 1 1

1
TDC 4.2A

PR601
@ JUMP_43X118
0 1 0.8V Peak Current 6A
1 0 0.725V OCP current 7.2A

2 +VCCSA_PWRGD
1 1 0.675V H_VCCSA_VID0 [10] OVP 1.06V
PR603
[42] SA_PGOOD
1K_0402_5%
output voltage adjustable network 2 1
The 1k PD on the VCCSA VIDs are empty.
20120731 These should be stuffed to ensure that

+VCCSA_VID0
+VCCSA_VID1
1U_0603_10V6K
+5VALW

+VCCSA_PWRGD
1. Change PR605 footprint to R0402_0ohm-NEW VCCSA VID is 00 prior to VCCIO stability.

2
PR605

PC602
PR604 @ 0_0402_5%
10_0402_1%

1
2 1 +VCCSA_EN 1 2 +V1.05S_VCCP_PWRGOOD [53]
PC601
2.2U_0603_10V7K
1 2
20120731
1. Change PR606 footprint to R0603_0ohm-NEW

18

17

16

15

14

13
PU601 20120411
PR606 PC603

V5DRV

V5FILT

PGOOD

VID1

VID0

EN
@ 0_0603_5% 0.22U_0603_16V7K Change PL601 footprint to PL302 footprint
C 12 +VCCSA_BT 2 1+VCCSA_BT_1 1 2 C
BST PL601
19 PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW 11 +VCCSA_PHASE 1 2 +VCCSAP
20 PGND

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_10V7K
1

2200P_0402_50V7K
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
10
2200P_0402_50V7K

SW @PR607
@PR607
0.1U_0603_25V7K

21
10U_0805_6.3V6M

10U_0805_6.3V6M

PGND

2
PC604

PC605

PC607

PC608

PC610

PC611
4.7_1206_5%

PC606

PC609
TPS51461RGER_QFN24_4X4 9
SW
PC613

1 2 2 22

1
VIN
2
PC612

PC614

PC615

SW 8

1
23 @ PC616
1

2 1 1 VIN 1000P_0603_50V7K
PJ601 7

2
+3VALW 2 2 1 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24 VIN
SW

@ JUMP_43X118 25

COMP

MODE
TP

SLEW

VOUT
VREF
1GND

6
@ PR608
2 1

33K_0402_5%
PC617 PR609
2 1 100_0402_5%
2 1
0.22U_0402_10V6K

0.01U_0402_25V7K
2
2 1 2 1 PC619 PR611
@ 0_0402_5%
PC618 PR610 1
3300P_0402_50V7K 5.1K_0402_1% 1 2 +VCCSA_SENSE [10]

B B

20120731
1. Change PR611 footprint to R0402_0ohm-NEW

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Zx90
Date: Monday, December 17, 2012 Sheet 52 of 63
5 4 3 2 1
 5 4 3 2 1

D D

20120330
Change net name to +V1.05S_VCCP from +1.05S_VCCP
PJ703
PR705 2 1
[10,25,42,46,51,54] SUSP# 60.4K_0402_1% 2 1
1 2 @ JUMP_43X118

@ 10K_0402_1%
+1.05VS_VCCPP PJ704 +V1.05S_VCCP

.1U_0402_16V7K
<bom structure>
2 2 1 1
+3VS

1
PR706

100K_0402_1%
PC707
@ JUMP_43X118

2
1

2
PR707
PR709

100K_0402_1%
C 0_0402_5% PJ707 C
[52] +V1.05S_VCCP_PWRGOOD

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 2 1.05VS_B+ 2 1
2 1
B+

0.1U_0402_25V6
2
PR708
PQ701 @ JUMP_43X118

1
PC708

PC712
TPCA8065-H_PPAK56-8-5

PC709

PC711
PR710 PC710
2.2_0603_5% 0.1U_0603_25V7K

2
BST_1.05VS_VCCP
1 2 1 2

1
10.7K_0402_1%~N

17

16

15

14

13
PU702 4

MODE

BST
PAD

PGOOD

EN
2
PR712
0.1U_0402_25V6

1 12 LX_1.05VS_VCCP PL701

3
2
1
VREF SW 1UH_PCMB104T-1R0MH_18A_20%
+1.05VS_VCCPP
1

12K_0402_1%

2 1
1
PC713

2 11 DH_1.05VS_VCCP
2

REFIN DH
2

1000P_0603_50V7K 4.7_1206_5%
PR713

5
PR715 PC714

PR714
@ 0_0402_5% 0.01UF_0402_25V7K TPS51219RTER_QFN16_3X3 1
1

DL_1.05VS_VCCP

330U_D2_2.5VY_R9M
3 GSNS <BOM Structure> DL 10
1 2 +
1

PC715
TPCA8057-H_PPAK56-8-5
@
4
2
4 VSNS V5 9 +5VALW +1.05VP
COMP

1
PGND

PQ703
OCP min 20A
TRIP

GND

B B

3
2
1
[9] VSSIO_SENSE_L OVP min 1.24V

PC716
2
PC717
PR716
5

[9] VCCIO_SENSE

1
75K_0402_1%

1 2 1 2 @
PR717
1

PC718
1 2 @ 10_0402_5% 0.01UF_0402_25V7K 1U_0603_10V6K

2
PR718

10_0402_1%
2
2

20120731
PC719
1. Change PR715 footprint to R0402_0ohm-NEW 1000P_0402_50V7K
1

PR719
1 2
10_0402_1%
2

PC720
1000P_0402_50V7K
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Zx90
Date: Monday, December 17, 2012 Sheet 53 of 63
5 4 3 2 1
 A B C D

+3VS_VGA 20120405
10K_0402_5% +V1.05S_VCCP +1.05VS_VGA Change PQ802 and PJ802 netname to +V1.05S_VCCP from +1.05VS

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
+V1.05S_VCCP PJ802
2 2 1 1 +1.05VS_VGA
+5VALW 8 1
2

2
7 2 @ JUMP_43X118

2
6 3 @

1
PC801 5 PC802 PC803 PR813
10U_0805_10V6K 470_0603_1% +VGA_B+

2
2
PR801

PR802

PR803

PR804

PR805

PR806

PR807

PR808

PR809

PR810

PR811

PR812
MDS1521URH 1N SO8 10U_0805_10V6K1U_0603_10V6K PJ801
1

2
PR814 PQ802 <BOM Structure> @ PR815 2 1 B+

1
PQ803 0_0402_5% 2 1
20K_0402_1%
PR816 2N7002KW_SOT323-3
@ 1 2 @ JUMP_43X118
DGPU_PWROK# [46,54]
GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

1
D

2200P_0402_50V7K
100K_0402_5%

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1
1 2 2 1 2 SUSP
SUSP [10,46,51,54]

1
PC804 G

1
PC805

PC807

PC808
@ @ @ @ @ @ PR818 S PR817 @

PC806
0_0402_5% 0.1U_0603_25V7K 0_0402_5%

2
1 1

20120409 [46,54] DGPU_PWROK# 1 2 PQ804

2
1
D 2N7002KW_SOT323-3
Add PR956 to GPU_PWR_EN for reserve

5
@ PD801
SUSP
[10,46,51,54] SUSP 1 2 2
G
+VGA_COREP
[42] GPU_PWR_EN PR972 RB751V-40_SOD323-21 2 PR819 @ S OCP min 56A

3
@ 0_0402_5% 0_0402_5%
1 2 PR820 N13P-GL:0.95V(VID5~0=101100) OVP min 1.525V
0_0402_5% 4
1 2VRON_VGA N13P-GS:0.9V(VID5~0=110000)
PD802
1 2 PR821 PC809 PQ801 20120511
[18] NVDD_PWR_EN RB751V-40_SOD323-2 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5 Change net name to +VGA_CORE from +VGA_COREP

3
2
1
@ BOOT2_VGA 2 1 BOOT2_2_VGA 1 2

[23]

[23]

[23]

[23]

[23]

[23]
GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0
1 PR822 2
[10,25,42,46,51,53] SUSP# @0_0402_5% 2@ PR823 1 UGATE2_VGA PL801
47K_0402_5% 0.36UH_PDME064T-R36MS1R405_24A_20%
[23] DPRSLPVR_VGA 1 2 PHASE2_VGA 1 2 +VGA_CORE

2
PR824
10K_0402_1% @ PC810 100P_0402_50V8J PR825 PQ806

10K_0402_1%
2 DPRSLPVR_VGA

3.65K_0805_1%
1 0_0402_5%

1
TPCA8057-H_PPAK56-8-5

10K_0402_1%
PR829
20120517 +3VS @ PR827

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
GPU_VID6
1 1

1
PR826
1.91K_0402_1%
1.Add PR972 SD028000080 0_0402_5% + +

PC811

PC812
1 2 CLK_ENABLE#_VGA PR828 PR830
2.Unmount PD801

PR870
LGATE2_VGA 4 1_0402_1%

2
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
3.Change PR820 to 0_0402_5% SD028000080 @4.7_1206_5%

1
PR831 2 2

SNUB2_VGA
from 150K_0402_1% SD034150380

2
PR832

PR833

PR834

PR835

PR836

PR837
1.91K_0402_1%
4.Unmount PC810

3
2
1
2

@ @ @ @ @ @ VSUM+_VGA ISEN2_VGA ISEN1_VGA VSUM-_VGA

[19,46] DGPU_PWROK

2
+3VS_VGA 1 2 PR839
100K_0402_5%
@ PR838 +3VS 1 2

1
0_0402_5% @ PC813
680P_0603_50V7K
2
PSI#_VGA PR840 +VGA_CORE Under VGA Core 2

2
147K_0402_1%
@ PR841
100K_0402_5%
2 1 +VGA_CORE Near VGA Core

1
+3VS 1 2 PC814
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

1 2 PU801
[23,42] VGA_AC_DET

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
CLK_EN#
DPRSLPVR

VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON
PSI#_VGA
RBIAS_VGA

47U_0805_4V
PR842 @

22U_0805_6.3V6M

22U_0805_6.3V6M
2 Structure>

4.7U_0805_6.3V6K
1

1
PC815

PC816

PC817

PC818

PC819

PC820

PC821

PC822
20120405 0_0402_5% 30 1
BOOT2

1
PC823

PC824

PC825

PC826
Exhange PH802 and PR843 position UGATE2 29
1 28

2
PGOOD PHASE2
2 27

<BOM
2

2
470K_0402_5%_TSM0B474J4702RE PR843 PSI# VSSP2 PR844 2
3 RBIAS LGATE2 26
1 2 1 2 4 25 VCCP_VGA 1 2 +5VS
VR_TT# VCCP 0_0402_5%
5 NTC PWM3 24
PH802 4.02K_0402_1% VW_VGA 6 23
COMP_VGA VW LGATE1
7 COMP VSSP1 22
FB_VGA

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
8 FB PHASE1 21
1 2ISEN3_VGA 9 ISEN3
1

1
UGATE1

PC829

PC830

PC831

PC832

PC833

PC834

PC835

PC836

PC837

PC838

PC839
10 PC828
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN
1000P_0402_50V7K

IMON
8.06K_0402_1%

PC827 1U_0603_10V6K
VDD
RTN

VIN
@249K_0402_1%

22P_0402_50V8J 41
2

2
AGND
2

PC840
PR845

PR846

ISL62883CHRTZ-T_TQFN40_5X5
11
12
13
14
15
16
17
18
19
20

PR847
2

499_0402_1% PC841
ISUM-_VGA

1 2FB1_VGA1 2
VDD_VGA
RTN_VGA
1

390P_0402_50V7K
PC842 PR848 PR849 @ 0_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

@0.1U_0402_10V7K

@0.1U_0402_10V7K

@0.1U_0402_10V7K
100P_0402_50V8J 1.47K_0402_1% @ PR850 IMON_VGA 1 2 +5VS @

1
PC847

PC848

PC843

PC845

PC849

PC844

PC850

PC851
1 2 1 2 0_0402_5% VSEN_VGA PR851
11K_0402_1%

@ 0_0402_5% PR854 0_0402_5%

0.047U_0402_16V7-K

1 2 +5VS
2

VIN_VGA 1 2 1 2

2
1

GPU_IMON [42]
PC846

PR853

ISEN2_VGA +VGA_B+
1 2FB2_VGA1 2 PR852 <BOM Structure>
ISEN1_VGA 1_0402_5%
2

PC852 PR855 +VGA_B+

0.22U_0402_10V6K

0.22U_0402_10V6K

3
1 2 3
1
1

150P_0402_50V8J 33K_0402_1% +5VS

1

1
PC853

PC854

PC855

PC856
1U_0603_10V6K

0.22U_0603_25V7K

PR856

2200P_0402_50V7K
68K_0402_1%
2

10U_0805_25V6K

10U_0805_25V6K
BOOT1_VGA

0.1U_0402_25V6
2

5
20120314

1
PC857
Change PR853 to 11K from 11.3K

PC858

PC859

PC860
PR857
20120314 10_0402_5%

2
UGATE1_VGA 4
Change PR848 to 1.47K from 1.15K VSUM-_VGA
VSUM+_VGA
@82.5_0402_5%

+VGA_CORE 1 2 20120511
PR860 PC861 PQ807
Change net name to +VGA_CORE from +VGA_COREP
1

PR858

20120511 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5

3
2
1
1

20120314 1 BOOT1_1_VGA
2.61K_0402_1%~N

Change net name to +VGA_CORE from +VGA_COREP 2 1 2

PR859

DNP PC864 PL802

1 2 0.36UH_PDME064T-R36MS1R405_24A_20%
2

PHASE1_VGA 1 2 +VGA_CORE
2

PR861
0.22U_0603_10V7K

0.022U_0603_25V7K
VSUM_VGA_N001
1

@ 0_0402_5%
NTC_VGA

5
PC862
1

10K_0402_1%
PC863

PC864

3.65K_0805_1%
330P_0402_50V7K
2

10K_0402_1%
PR863
PQ809
@0.01U_0402_25V7K

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
[24] VCCSENSE_VGA 1 1

1
TPCA8057-H_PPAK56-8-5
2

+ +

PR864

PC865

PC866
[24] VSSSENSE_VGA @ PR862 PR865

PR871
@330P_0402_50V7K

LGATE1_VGA 4 1_0402_1%

2
1

1
11K_0402_1%
PC868

PC869

@4.7_1206_5% @

2
1

2 2
PR867

PC867 PH801

2
PR866 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ

SNUB1_VGA
@ 0_0402_5%
2

3
2
1
1 2
2

Layout Note: VSUM+_VGA

PR868 PR869 Place near Phase1 Choke ISEN1_VGA ISEN2_VGA
10_0402_5% 1.58K_0402_1% VSUM-_VGA
4 4
1 2 1 2 VSUM-_VGA

1
@ PC870
@ 680P_0603_50V7K
20120314

2
Change PR869 to 1.58K from 1K
1

Set OCP is 56.35A PC871

0.1U_0402_16V7K
20120731
2

1. Change PR832,PR833,PR834,PR835,PR836,PR837,PR972,
PR851,PR861 and PR866 footprint to R0402_0ohm-NEW Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019K3
Date: Monday, December 17, 2012 Sheet 54 of 63
A B C D
 5 4 3 2 1

20120514 PR915,PR946=200K(setting 113 degreeC)

Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE PR915,PR946=8.25K(setting 93 degreeC)
from SL200000500 220K_0402_5%_ERTJ0EV224J
PC902

1200P_0402_50V7K
1 PR9012 FBA3 1 2 PC901 1 2

1000P_0402_50V7K
<BOM Structure>
D PUT COLSE D

75K_0402_1%
10_0402_1% 680P_0402_50V7K .1U_0402_16V7K
TO GT

1
PR903 1 PR904 2

PC903

PC904

PR905
TRBSTA# 1 PR9022 FBA1 1 2 PH901 Inductor
2P: 24K 24.9K_0402_1% PR906 PC906

1
1
1.21K_0402_1% 10.7K_0402_1%~N 220K_0402_5%_TSM0B224J4702RE CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC905 1P: 24.9K

2
PR908 PC907 PC908 2 PR9071 NTC_PH203 1K_0402_1% 1000P_0402_50V7K

2
4700P_0402_25V7K 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% 20120514 2P: 1.65K
680P_0402_50V7K PR910 10P_0402_50V8J PC909
1 PR9092 1 2 COMPA1 1 2
Change PR921 to 71.5K_0603_1% SD014715280 1P: 1K
from 63.4K_0603_1% SD014634280
1K_0402_1% 6.04K_0402_1% 2200P_0402_50V7K CSREFA
20120731 PC910 TSENSEA

2
1 PR9122 SWN1A 0.047U_0402_16V7K
1. Change PR937,PR954,PR926,PR936,PR938
footprint to R0402_0ohm-NEW 2P: 21.5K 71.5K_0603_1% PR913 6.98K_0402_1%

1
PR937 CSP1A 1 2
1P: 15.8K SWN1A [56]

2
15.8K_0402_1%
@ 0_0402_5%

CSCOMPA
1 2 PC911
[10] VCC_AXG_SENSE

2
1000P_0402_50V7K

1PR914

200K_0402_1%
1
PR954 PC912 PH904

PR915
@ 0_0402_5% 1000P_0402_50V7K
CSREFA [56]

1
1 2 100K_0402_1%_TSM0B104F4251RZ
[10] VSS_AXG_SENSE
PC914

1
CSP2A
CSP1A
1 2

TRBSTA#

DROOPA

CSSUMA

TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K

DIFFA

ILIMA
+V1.05S_VCCP @

PR918 2P: 36K

1 2
1P: 26.1K PUT COLSE
26.1K_0402_1%

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+5VS 1 PR9192 PU901 TO V_GT
C C
2_0603_5% HOT SPOT

VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
6132_PWMA
PC915
1 2 6132_VCC
.1U_0402_16V7K

.1U_0402_16V7K

1 45 PR921 PC918
2.2U_0603_10V7K VCC PWMA BSTA1
2 VDDBP BSTA 44 1 2 BSTA1_11 2
+5VS
130_0402_1%

54.9_0402_1%

PR920 3 43 2.2_0603_5% 0.22U_0603_25V7K

VRDYA HGA HG1A [56]
1

PR922 2

1 2VR_ON_CPU 4 42
[42] VR_ON EN SWA SW1A [56]
PR923

PC916 PC917 0_0402_5% VR_SVID_DAT1 5 41 PC919

SDIO LGA LG1A [56]
VR_SVID_ALRT# 6 40 BST2 1 PR9242 BST2_1 1 2 2Phase: @
2

PR927 PR925 VR_SVID_CLK ALERT# BST2 2.2_0603_5% 0.22U_0603_25V7K

7 39 HG2 [56]
SCLK HG2 1Phase: install

1
@ PR926 0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 SW2 [56] Option for
1

VBOOT NCP6132AMNR2G_QFN60_7X7 SW2

[9] VR_SVID_DAT 1 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 ROSC LG2 37 LG2 [56]
PC920 1 phase GFX PR928
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 PR9302 1 2 0_0402_5%
[9] VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 0_0402_5% 2.2U_0603_10V7K
[9] VR_SVID_CLK VRHOT# PGND
PR929 1K_0402_1%
0.01U_0402_25V7K

VGATE 12 34 LG1 [56] +5VS

2
VRDY LG1
1

13 33 CSP2A
+V1.05S_VCCP VSN SW1 SW1 [56]
PC921 14 32 PC922
+3VS VSP HG1 HG1 [56]
DIFF_CPU 15 31 BST1 1 PR9312 BST1_1 1 2

CSCOMP
2

DIFF BST1

TRBST#
2.2_0603_5% 0.22U_0603_25V7K

DROOP

CSSUM

DRVEN
CSREF
1

COMP

TSNS
CSP3
CSP2
CSP1

PWM
IOUT
ILIM
1

PR932 @

FB
75_0402_1% PR933 +5VS
10K_0402_5%

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3P: 73.2K
2

1 PR9342
[42] VR_HOT#
2

COMP_CPU
2P: 41.2K

1
PR936 FB_CPU 41.2K_0402_1% Option for 3Phase: @
TRBST#
[16] VGATE
@ 0_0402_5% 2 phase CPU PR935

DROOP

TSENSE
ILIM_CPU
1 2 VSN 3P: 22p 0_0402_5% 2Phase: install
[9] VSSSENSE 6132_PWM
1

IMON

PR938 PC923 2P: 10p

2
@ 0_0402_5% 1000P_0402_50V7K CSP3
2

1 2 VSP PC924
[9] VCCSENSE
2
PR939 12.4K_0402_1%

1 2
.1U_0402_16V7K
IMVP_IMON

B PR941 B
20120514 PC926 CSP1 CSP2 1 6.98K_0402_1%
2 TSENSE
SWN2 [56]
3P: 330p 1 PR940 2 2 1 CSP2 20120723
Change PC928 to 560P_0402_50V7K SE074561K80
1

2
1K_0402_1% CSP3
2P: 1000p unmount PR915 and PR946

1
from 680P_0402_50V7K SE074681K80 22P_0402_50V8J PC927 PR960 @
0.047U_0402_16V7K 6.98K_0402_1%
PR942 PC928 PR943 PC929 3P: 21K

2
1 2FB_CPU1 1 2 2 1COMP_CPU12 1

1
PR944 PC930 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K CSREF

200K_0402_1%
1 2FB_CPU3 1 2 560P_0402_50V7K 1500P_0402_50V7K

2 PR946 1

2
10_0402_1% 3P: 6.04K CSP1 1 PR9452
CSREF [56] SWN1 [56]
CSCOMP

0.033U_0402_16V7K 6.98K_0402_1% PH902

2P: 4.32K

2
PR947 PR948 PC932 PC931
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p0.047U_0402_16V7K PR961 @ 100K_0402_1%_TSM0B104F4251RZ
1
0.033U_0402_16V7K

6.98K_0402_1%

1
2P: 1200p
1

8.06K_0402_1% 806_0402_1% 3P: 2200p

PC933

1
2P: 3300p CSSUM CSREF
2

PC934 @
3P: 348 3P: 3.65K
1 2
2P: 1.21K 2P: 9.53K 1000P_0402_50V7K 1 PR9492 SWN1
24.9K_0402_1%

143K_0603_1% PUT COLSE

2

.1U_0402_16V7K

TO VCORE
PC935

3P: 23.7K 1 2 PC936 1 PR9512 SWN2

PR950

1000P_0402_50V7K 143K_0603_1% HOT SPOT

1

2P: 24.9K
1 PR952 2NTC_PH201 1 PR953 2 20120514
1

75K_0402_1%
PR955 PC937 165K_0402_1% Change PR949,PR951 to 143K_0603_1% SD014143380 from 130K_0603_1% SD014130380
CSCOMP 1 2 DROOP 1 2 CSREF PH903 20120514
PUT COLSE Change PC936 to 1000P_0402_50V7K SE074102K80 from 680P_0402_50V7K SE074681K80
1K_0402_1% 1000P_0402_50V7K 2 1
3P: 806 TO VCORE
Phase 1 220K_0402_5%_TSM0B224J4702RE
2P: 1K
A Inductor A

[42] IMVP_IMON

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom C38-G series Chief River Schematic C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 55 of 63
5 4 3 2 1
 5 4 3 2 1

CPU_B+ CPU_B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
B+

2200P_0402_25V7K

2200P_0402_25V7K
0.1U_0402_25V6

0.1U_0402_25V6
5

5
PL901
FBMA-L11-453215800LMA90T_2P PQ902

1
PC938

PC939

PC940

PC941

PC942

PC943

PC944

PC946
PQ901 1 1 2 CPU_B+

100U_25V_M
+

PC953
2

2
[55] HG1 4 1 [55] HG2 4

100U_25V_M
+VCC_CORE 2 + +VCC_CORE

PC954
TPCA8065-H_PPAK56-8-5 PL902 TPCA8065-H_PPAK56-8-5

3
2
1

3
2
1
D
0.36UH_PCMB104T-R36MH1R105_30A_20% 2 PL903 D
0.36UH_PCMB104T-R36MH1R105_30A_20%
[55] SW1 1 4 [55] SW2 1 4

1
2 3 2 3

5
@ PR956 PQ904 @ PR957
PQ903 4.7_1206_5% 4.7_1206_5%

2
PR958
4 V1N_CPU2 1 4 V2N_CPU 2 PR959 1 CSREF

1SNUB_CPU1

SNUB_CPU2
[55] LG1 CSREF [55] [55] LG2
10_0402_1%
10_0402_1%

TPCA8057-H_PPAK56-8-5
SWN1 [55] SWN2 [55]

3
2
1

3
2
1
TPCA8057-H_PPAK56-8-5
@ PC948
680P_0603_50V7K

1
@ PC949

2
680P_0603_50V7K

2
C C

DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A

CPU_B+
10U_0805_25V6K

10U_0805_25V6K

2200P_0402_25V7K
0.1U_0402_25V6

B B
1

1
PC957

PC958

PC959

PC960
2

2
5

PQ907

[55] HG1A 4

PL905

TPCA8065-H_PPAK56-8-5
+VCC_GFXCORE_AXG
3
2
1

0.36UH_PCMB104T-R36MH1R105_30A_20%

[55] SW1A 1 4
1

2 3
5

PQ909 @ PR967
V1N_GFX

4.7_1206_5%
2

[55] LG1A 4
SNUB_GFX1

TPCA8057-H_PPAK56-8-5 2 PR971 1
CSREFA [55]
3
2
1

<BOM Structure>
10_0402_1%
1

@ PC968
680P_0603_50V7K SWN1A [55]
2

A A

DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=21.5A Issued Date 2009/12/01 Deciphered Date 2012/07/11 Title

R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number Rev
OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C38-G series Chief River Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 56 of 63
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC1
PC2 PC3 PC4 PC5
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
+VCC_GFXCORE_AXG sites

D
7 x 22 µF (0805) D

@ @ @
Socket Top 2 x (0805) no-stuff
sites

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1

PC12

PC13

PC14

PC15

PC16

PC17

PC18

PC19
PC6 PC7 PC8 PC9 PC10 PC11
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+V1.05S_VCCP
+VCC_CORE @
+V1.05S_VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @ @

PC25

PC26

PC27

PC28

PC29

PC30

PC31

PC32

PC33

PC34

PC35
PC20 PC21 PC22 PC23 PC24
2 2 2 2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 @ 1 1 1 1 1 1
2 2 2 2 2

PC36

PC37

PC38

PC39

PC40

PC41

PC42

PC43
2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @

PC49

PC50

PC51

PC52

PC53

PC54

PC55

PC56
PC44 PC45 PC46 PC47 PC48
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2
1 1 1
+ PC57 + PC58 + PC59
C 330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M C

2 2 2
1 1 1
1 1 1 1 1
@ @ PC65 + + PC66 +
PC60 PC61 PC62 PC63 PC64 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 20120514
2 2 2 2 2 2 2 2
Unpop PC58 PC67
@ 330U_D2_2.5VY_R9M

1 1 1 1 20120514
@ @
PC68 PC69 PC70 PC71 Unpop PC66
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2

+VCC_CORE

1 PC72 1 1
330U_D2_2.5VY_R9M
+ + PC73 + PC76
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
B 2 2 2 B

1 1
+ PC74 + PC75
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
2 2

@
20120514
Unpop PC75
Change PC72,PC73,PC74,PC76 to SGA00006100 from 330U_D2_2.5VY_R9M SGA00002680
20120318
Change PC72,PC73,PC74,PC75 to 2 pin footprint

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 57 of 63
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Reason for change PG# Modify List Date Phase

1 For EC net name P48 PR206 change pull high voltage to +EC_VCCA from +3VLP 20120316 EVT
1.Change PR848 to 1.47K SD000009480 from 1.15K
D
2 Intersil advise P54 20120316 EVT D

2.Unmount PC864

3 VGA IMON setting P54 Change PR853 to 11K SD034110280 from 11.3K 20120316 EVT

4 set OCP is 56A P54 Change PR869 to 1.58K (SD00000SJ80) from 1K 20120316 EVT

5 For 1.5V current P51 Add PJ507 for 1.5V 20120321 EVT

P55 1.Change PC954 pull high to CPU_B+ from B+

6 For B+ layout
P50 2.Change 3/5VALWP B+ input netname to CPU_B+ 20120321 EVT
P51 3.Change 1.5VALWP B+ input netname to CPU_B+
P50 4.Change PR411 netname to CPU_B+ from B+

P53 1.Change +1.05S_VCCP netname to +V1.05S_VCCP

7 For HW net name 20120330 EVT
C P54 2.Change PQ802.5 netname to +V1.05S_VCCP from +1.05VS C

1.Add control PU801 pin GPU_PWR_EN and reserve PR956 0_0402_5%

8 For HW power sequence P54 20120330 EVT
2.Change PR820 to SD034150380 150K_0402_1% from 100K
3.Change PC810 to SE071101J80 100P_0402_50V8J from 0.1u

9 For Intersil advise P54 Change PR853 pull down netname to gnd 20120409 EVT

10 For IMON design P55 Change PU901 to NCP6132A from ISL95836 20120412 EVT

11 For layout design P54 1.Del PJ803 PJ804 20120511 DVT

2.Change net name to VGACORE from VGACOREP

12 For 1.05V, GFX_CORE,CPU_CORE design fine tune P57 Unpop PC58, PC66,PC75 330U_D2_2.5VY_R9M SGA00002680 20120514 DVT
B B

13 For CPU_CORE design fine tune and ON advise P57 Change PC72,PC73,PC74,PC76 to S POLY C 330U 2V M D2 ESR9M SGA00006100 20120514 DVT
from 330U_D2_2.5VY_R9M SGA00002680

14 For CPU_CORE design fine tune and ON advise P55 1.Change PC928 to 560P_0402_50V7K SE074561K80 20120514 DVT
from 680P_0402_50V7K SE074681K80
2.Change PR949,PR951 to 140K from 130K
3.Change PR912 to 71.5K_0603_1% SD014715280 from 63.4K_0603_1% SD014634280
4.Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE
from SL200000500 220K_0402_5%_ERTJ0EV224J

15 For material EOL P55 Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE 20120514 DVT
from SL200000500 220K_0402_5%_ERTJ0EV224J

A 16 For HW VGA power sequence P54 Add PR972 SD028000080 0_0402_5% 20120516 DVT A

Unmount PD801
Change PR820 to 0_0402_5% SD028000080 from 150K_0402_1% SD034150380
Unmount PC810
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/06 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Zx90
Date: Monday, December 17, 2012 Sheet 58 of 63
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 2

for PWR
Item Reason for change PG# Modify List Date Phase

17 For HW reset function P50 1.Add PR420 SD028000080 0_0402_5% for reserve 20120606 PVT
2 reserve.PR419 and PR420
D D

18 For ACDET function P49 1.Change PR313 to 60.4K_0603_1% SD014604280 from 64.9K_0603_1% SD014649280 20120615 PVT

19 For HW Grenn clock UMA sku trial tun P47 1. unmount PD103 20120625 PVT
2. Change PR108 to 150_0603_5% SD013150080 from 560_0603_5% SD013560080
Change PR109 to 1K_0603_5% SD013100180 from 560_0603_5% SD013560080

20 For ACDET function P49 1.Change PR313 to 59K_0603_1% SD014590280 from 60.4K_0603_1% SD014604280 20120705 PVT

21 For VR_HOT P55 1.unmount PR915 and PR946 20120705 PVT

22 For HW Grenn clock P47 1. mount PD103 20120723 SVT

2. Change PR108 to 150_0603_5% SD013150080 from 560_0603_5% SD013560080
Change PR109 to 1K_0603_5% SD013100180 from 560_0603_5% SD013560080
C C
23 For material issue P51 1.Change PU502 to SA00004CY10 S IC RT8061AZQW WDFN 10P PWM 20120723 SVT
from SA00003RU00 S IC SY8033BDBC DFN 10P SINGLE BUCK

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Zx90
Date: Monday, December 17, 2012 Sheet 59 of 63
5 4 3 2 1
 5 4 3 2 1

COMPAL CONFIDENTIAL
MODEL NAME: Power Sequence Block Diagram
PCB NAME: LA-7981P
D REVISION: D

DATE: 2011/07/13 10

PCH_PWROK
AC A1
MODE VIN +3V_PCH

V V
A2 A3 B5 +5V_PCH

VV
V
PU301 A5 3

V
B+ PU401
+3VALW B7 3 3
BATT BATT V 10
+5VALW
MODE
B1
B2
B+ B4 V PCH_PWROK
V SYS_PWROK 15 14 VGATE

V
EC 4
PQ2 11
PCH_RSMRST#_R PM_DRAM_PWRGD

V
V V PCH
B3 A5 B7 5 12
PBTN_OUT# H_CPUPWRGD
CPU

V V
13 SVID

V
C C
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 16
PM_SLP_S5#
A4 B6 PM_SLP_SUS# 6
DGPU_PWROK

V
V
ON/OFF

SYSON 7 SYSON#

V
+1.5V
PU501

DGPU_PWR_EN
SUSP#,SUSP 8

(DIS)

V
PU601 U38
8b
B
+VCC_SA +5VS B

(DIS)
V

V
PU702 U39
8a
+V1.05S +3VS DGPU

V
V
V

PU602 Q8
+V1.05S_VCCP +1.5VS

PU701

V
SA_PGOOD 8a +0.75VS

13 SVID
VR_ON 9 PU901
V

+VCC_CORE
A A

14 VGATE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 60 of 63
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2 for HW PIR

Item Reason for change PG# Modify List Date Phase

1 Initial 5/7 DVT

D D

P14
2 For Green CLK and Crystal co-lay better layout P15 Delete R176,R1381 and RV232 5/7 DVT
P23

3 For Change Audio Woofer MOSFET from Dual to single channel P15 Changer Part from SB00000EO10 to SB00000EN00
5/7 DVT

4 For OVERT# Glitch issue at Power on status P23 Add QV9 5/7 DVT
to modify R897 value from 0 ohm to 1K ohm
5 For BT&WLAN Combo Card P36 add BT_DISABLE_F_R on JWLN1.51 5/8 DVT
add R5580

6 For Factory request and cost down LVDS PIN Define P33 To Modify LVDS PIN Define 5/8 DVT
To Add PWRSHARE_EN_R on U31.38
7 For USB Charger mode control request P45 To Add EC_PWRSHARE_EN# on U31.74 5/8 DVT
P42 add R5577 and R5578, delete CHG_ON#
to change R4959 value from 200K ohm to
C 8 To change Reset IC G601
P42 0 ohm add R5579 0 ohm 5/8 DVT C

add R5581,C1331,R5572,R5583,R5584 and Q156

9 Reserved Touch Screen Power Control P42 add EC_TS_ON on U31.66 5/8 DVT
P43 add +3VS_TS,+3VS_TS_R

10 To change Speaker PIN define for ME routing request SPK_L2+ R1556 net in JSPK1.1
P41 SPK_L1- R1554 net in JSPK1.2 5/8 DVT
SPK_R1- R1555 net in JSPK1.3
SPK_R2+ R1553 net in JSPK1.4
R1123,C1134 close to U50.47
11 for Realtek Vendor recommand R5582,R1559 and C1135 Close to U73.1
P41 EXT_MIC_R 5/8 DVT

To Modify H21,H7,H18 PCB Footprint as below

H21 from H_3P3 to H_4P6
12 for ME request P39
H7 from H_2P8 to H_3P0
5/8 DVT
H18 from H_3P3 to H_3P9N

13
B B
for LAN Clock be better P37 change C990 value from 5PF to 0 ohm. 5/9 DVT

change JUSB3.11 from GND to +3VS

change JUSB3.12 from +3VS to AGND
14 for Audio Vendor recommand P43 5/10 DVT

15 for Crystal finetune Capacitor P43 C180,C181 from 18PF to 12PF 5/16 DVT

16 for DVT Board ID request P42 R695 from 33K to 18K 5/17 DVT

17 for PVT request P37 Change Reference from C990 to R5585 5/23 PVT

18 for Surge request P38 C1325,C1326,C1327 change package from 5/23 PVT
0402 to 0603

19 for Reset IC function P42, add R612,PR420,R4960,R4961 5/24 PVT

P50,P43 Delete R4959
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 61 of 63
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 2 for HW PIR

Item Reason for change PG# Modify List Date Phase

20 for USB2.0 Port 0 TLC fine tune P45 add R1170,R1171 5/29 PVT
D D

21 for INTEL Combo card BT off P36 add R893,R894 1Kohm ,change R897 to 0 ohm 6/5 PVT
P19 change net name from PCH_GPIO36 to
INTEL_BT_OFF#
add INTEL_BT_OFF#_R
JWLN1.51 chnage NET from BT_DISABLE_F_R to
INTEL_BT_OFF#_R

22 for LVDS prevent short EC DISPOFF# P33 R447 change value from no stuff to stuff 0ohm 6/12 PVT

add R5586 and R5591

23 for VSB and PCH Power rail control issue P42 6/21 PVT
P46

C C

24 add common choke for USB port 8, port 9 P43 add L78,L79,R5587,R5588,R5589,R5590 6/21 PVT

25 no need reserved C1330 P38 remove C1330 6/21 PVT

26 for PVT Board ID request P42 R695 from 18K to 8.2K 6/21 PVT

27 for Surge modify P38 DL6 change Part from SCV00001C00 to SCV00001D00 6/21 PVT

28 for Crystal finetune Capacitor P14 C180,C181 change value from 12P to 18P 6/25 PVT
P37 C1204,C1205 change value from 27P to 12P

29
B B
for SMT Request P23 LV7 change value from KC_FBMA-10-100505-300T_2P 07/11 SVT
to 0ohm_0402

30 for Vendor recommand P23 add RG10 0ohm 07/19 SVT

31 for Touch Screen request P43 add R5592,R721 0 ohm, 07/25 SVT

32 for Green CLK request P44 add QG1,RG13,CG10 8/1 SVT

33 for LED Brightness P44 modify R623,R765 value from 300 ohm to 560 ohm 8/1 SVT

34 for reduce component count P10 Modify footprint to jumper R69 to J14 8/1 SVT
P R277 to J16

35 for SVT Board ID request P42 R695 from 8.2K to 0 ohm 8/1 SVT

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 62 of 63
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 3 of 3 for HW PIR

Item Reason for change PG# Modify List Date Phase

36 for EMI Request P45 not stuff R1154,R1155,R1156,R1157 8/1 SVT

D
Stuff L68,L70 D

37 for Remove ODD Zero Power Function P40 Q99,Q100 R552,R675,C607 not stuff on MB

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A9061
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019K3 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 17, 2012 Sheet 63 of 63
5 4 3 2 1
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