Q.1 Consider the given circuit.

In this circuit, the race around

(A) does not occur (B) occurs when CLK = 0
(C) occurs when CLK = 1 and A = B = 1 (D) occurs when CLK = 1 and A = B = 0

Q.2 For the n-channel MOS transistor shown in the figure, the threshold voltage VTh is 0.8 V.
Neglect channel length modulation effects. When the drain voltage VD = 1.6 V, the drain current ID
was found to be 0.5 mA. If VD is adjusted to be 2 V by changing the values of R and VDD, the new
value of ID (in mA) is

(A) 0.625 (B) 0.75 (C) 1.125 (D) 1.5

Q.3 The state transition diagram for the logic circuit shown is

2-1 MUX
D Q X1
Y
CLK Q X0
Select

A
A=1 A=0 A=0 A=0

A=1 A=1
(A) (B)
Q=0 Q=1 Q=0 Q=1
A=0 A=1

A=0 A=1 A=1 A=1

A=0 A=0
(C) (D)
Q=0 Q=1 Q=0 Q=1
A=1 A=0
 Q.4 The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit
input B. The number of combinations for which the output is logic 1, is
(A) 4 (B) 6 (C) 8 (D) 10

Q.5 In CMOS technology, shallow P-well or N-well regions can be formed using
(A) low pressure chemical vapour deposition
(B) low energy sputtering
(C) low temperature dry oxidation
(D) low energy ion-implantation

Q.6 For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an
external device is shown in the figure. The instruction for correct data transfer is

(A) MVI A, F8H (B) IN F8H (C) OUT F8H (D) LDA F8F8H

Q.7 A bulb in a staircase has two switches, one switch being at the ground floor and the other one at
the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches
irrespective of the state of the other switch. The logic of switching of the bulb resembles

(A) an AND gate (B) an OR gate (C) an XOR gate (D) a NAND gate

Q.8 In a MOSFET operating in the saturation region, the channel length modulation effect causes

(A) an increase in the gate-source capacitance

(B) a decrease in the Transconductance

(C) a decrease in the unity-gain cutoff frequency

(D) a decrease in the output resistance

Q.9 The small-sig al resista e i.e., dV / dI B D i kΩ offered the -channel MOSFET M shown in
the figure below, at a bias point of V 2 V B = is (device data for M: device Transconductance
parameter ( ) ' 2 k C W / L 40 A / V N n ox , = µ = µ threshold voltage V 1 V, TN = and neglect body
effect and channel length modulation effects)

(A) 12.5 (B) 25 (C) 50 (D) 100

Q.10 The Boolean function realized by the logic circuit shown is

a F=Ʃ , , , , , . F=Ʃ , , , , , . F=Ʃ , , , , , . d F=Ʃ

(2,3,5,7,8,9.12)

Q.11 Without any additional circuitry an 8:1 MUX can be used to obtain (a) Some but not all
Boolean functions of 3 variables (b) All function of 3 variables but none of 4 variables (c) All functions
of 3 variables and some but not all of 4 variables (d) All functions of 4 variables
Q12. If the input X3, X2, X1, X0 to the ROM in the figure are 8, 4, 2, 1 BCD numbers, then the output
Y3, Y2, Y1, Y0 are

(a) gray code numbers (b) 2 4 2 1 BCD numbers (c) Excess-3 code numbers (d) None of the above

Q.13 . Which of the following Boolean expressions correctly represents the relation between P, Q, R
and M1

(a) M1 = (P OR Q) XOR R (b) M1 = (P AND Q) XOR R (c) M1 = (P NOR Q) XOR R (d) M1 = (P XOR Q) XOR
R

Q.14 . A Boolean function f of two variables X and Y is defined as follows: f(0, 0) = f(0, 1) = f(1, 1) = 1;
f(1, 0) = 0 Assuming complements of X and Y are not available, a minimum cost solution for realizing
using only 2-input NOR gates and 2-input OR gates (each having unit cost) would have a total cost of

(a) 1 unit (b) 4 unit (c) 3 unit (d) 2 unit

Q.15 D/A converters are generally

a. Weighted resistor network

b. Binary ladder network

c. Either (a) or (b)

d. Neither (a) nor (b)

Q.16 8. A 6 bit ladder D/A converter has input 101001. For 1 = 10 V and 0 = 0V, The output is

a. 4.23

b. 6.51

c. 5.52

d. 9.23

Q.17 In a 4 bit D/A converter, The offset error is the output voltage when input digital voltage is

a. 1111

b. 0000

c. Either 1111 or 0000

d. None of the above

Q.18 Which converters uses integrating op-amp a. Parallel A/D converter b. Single slope A/D
converter c. Dual slop A/D converter d. Both (b) and (c)

Q.19 Perform the following operations in 2 s complement method (use 8 bit representation) (a)
(52)10 – (23)10 (b) (23)10 – (52)10 (c) (52)10 – (-23)10 (d) (-52)10 – (-23)10 (e) (-77)10 + (-122)10

Q.20 Consider the following processors (ns stands for nanoseconds). Assume that the pipeline
registers have zero latency. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns. P2:
Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns. P3: Five-stage pipeline with stage
latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns. P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1
ns, 1 ns, 1.1 ns. Which processor has the highest peak clock frequency?

(A) P1 (B) P2 (C) P3 (D) P4

Q. Co sider the followi g i ter e pressio for F. F P,Q,R,S , , , , , , , = ∑ The

minterms 2, 7, 8 and 13 are do not care terms. The minimal sum of-products form for F is
(A) QS QS + (B) QS QS + (C) Q R S Q R S Q R S QRS + + + (B) PQS PQS PQS PQS + + +

Q.22 Consider an instruction pipeline with five stages without any branch prediction: Fetch
Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write
Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns,
respectively. There are intermediate storage buffers after each stage and the delay of each buffer is
1 ns. A program consisting of 12 instructions 1 2 3 12 I ,I ,I ,......I is executed in this pipelined
processor. Instruction 4 I is the only branch instruction and its branch target is 9 I . If the branch is
taken during the execution of this program, the time (in ns) needed to complete the program is

(A) 132 (B) 165 (C) 176 (D) 328

Q.23 A depletion MOSFET differs from a JFET in the sense that it has no
a. channel
b. gate
c. P-N junction
d. Substrate

Q.24 The extremely high input impedance of a MOSFET is primarily due to the
a. absence of its channel
b. negative gate-source voltage
c. depletion of current carriers
d. extremely small leakage current of its gate capacitor

Q.25 A D-MOSFET can operate in the

a. Depletion-mode only
b. Enhancement-mode only
c. Depletion-mode or enhancement-mode
d. Low-impedance

Q.26 If X is a ten bit number, which of the following will left extend X[9] three times? A. {(X[9], X[9],
X[9]), X} B. (X[9], X[9], X[9], X) C. {3(X[9]), X[9]} D. {3{X[9]}, X[9]}

Q.27 Which of the following is a difference between a Function and a Task?

A. A Function can call another function; a Task cannot. B. A Function cannot call a task; a Task can
call another task.. C. A Function has one or more inputs; a Task has no inputs. D. A Function
argument may be an output; a Task s argument may only be an input.

Q.28. Which of the following is not true about operators?

A. A logical or is performed by writing C = A || B; B. ! performs logical negation while ~

performs bitwise negation. C. The two types of or operators are logical and bitwise. A. The
shift right (>>) operator inserts zeros on the left end of its argument.
Q.29 In synthesis, what will happen when a signal that is needed in a sensitivity list is not included?

A. An error will be generated and the code cannot be synthesized. B. A warning message will be
generated and the code will be synthesized but the resulting netlist will not provide the desired
results. C. The synthesis tool will ignore the sensitivity list since all objects that are read as part of a
procedural assignment statement are considered to be sensitive. D. There will be no effect on the
design and pre-synthesis simulation will be consistent with post-synthesis simulation.

Q.30 Which of the following is used for Verilog-based synthesis tools?

A. Intra-statement delay statements can be synthesized, but interstatement delays cannot. B. Inter-
statement delay statements can be synthesized, but intrastatement delays cannot. C. Initial values
on wires are almost always ignored. D. Synthesized results are identical for if and case
statements

Q.31 In the following circuit, X given by

(a) = ̅ ̅+ ̅ ̅+ ̅ ̅ + (b) = ̅ + ̅ + ̅+ ̅ ̅ ̅ (c) = + + (d) = ̅ ̅+

̅ ̅+ ̅ ̅

Q.32 The minimum number of 2-to-1 multiplexers required to realize a 4-to-1 multiplexer is

(a) 1 (b) 2 (c) 3 (d) 4

Q.33 The circuit shown in the figure converts

(a) BCD to binary code (b) Binary to excess-3 code (c) Excess-3 to Gray code (d) Gray to Binary code

Q.34 Minimum number of 2 input NAND gates required to implement the function, = ( ̅ + ̅)( +
) is

(a) 3 (b) 4 (c) 5 (d) 6

Q.35 9. The minimum number of NAND gates required to implement the Boolean function + ̅+
̅ is equal to

(a) Zero (b) 1 (c) 4 (d) 7

Q.36 . For the output F to be 1 is the logic circuit shown, the input combination should be

(a) = 1, = 1, = 1 (b) = 1, = 0, = 0 (c) = 0, = 1, = 0 (d) = 0, = 0, =1

Q.37 . -24 is 2 s complement form is

(a) 11101000 (b) 01001000 (c) 01111111 (d) 00111111

Q.38 Consider the following two situations about the internal conditions in an n – channel MOSFET
operating in the active region. S1: The inversion charge decreases from source to drain S2 : The
channel potential increases from source to drain Which of the following is correct?

(a) Only S2 is true (b)Both S1 and S2 are false (c) Both S1 and S2 are true but S2 is not a reason for S1
(d)Both S1 and S2 are true and S2 is reason for S1

Q.39 An n – channel depletion MOSFET has following two points on its 𝐼 − 𝑆 curve (i) 𝑆 = 0 𝑡
𝐼 = 12 𝑑 (ii) 𝑆 = − 𝑡 𝐼 = 0 Which of the following Q point will give the highest
transconductance gain for small signals?

(a) 𝑆=− (b)𝑆 = − (c) 𝑆=0 (d) 𝑆=3

Q.40 MOSFET can be used as a

(a) Current controlled capacitor (b)Voltage controlled capacitor (c) Current controlled inductor
(d)Voltage controlled inductor

Q41. Three capacitors C1, C2 and C3 whose values are 10μF, 5μF, and 2μF respectively, have breakdown
voltages of 10V, 5V, and 2V respectively. For the interconnection shown below, the maximum safe
voltage in Volts that can be applied across the combination, and the corresponding total charge
in μC stored in the effective capacitance across the terminals are respectively,

(A) 2.8 and 36 (B) 7 and 119

(C) 2.8 and 32 (D) 7 and 80

Q42. The circuit shown below is driven by a sinusoidal input Vi= Vp cos (t /RC ) . The steady state
output vo is
(A) (Vp / 3) cos (t / RC )

(B) (Vp / 3) sin(t / RC )

(C) (Vp / 2) cos (t / RC )

(D) (Vp / 2) sin (t / RC )

Q43.For the circuit shown below if the voltage V across the current source of 5A is 25V, then what is
the value of 'R'

A) 1 ohm

B) 2 ohm

C) 3 ohm

D) 4 ohm

Q44. For the tank circuit shown below period of oscillation is

A π

B π

C π

D π

Q45. For the circuit shown below the steady state voltage 'V' across the current source is

A) 20V

B) 25V

C) 27V

D) none of these

Q46. For the phasor diagram of the circuit as shown the unknown element 'z' is
A) R

B) C

C) L

D) combination of R and C

Q47.If both the circuits shown below are equivalent then the value of RC in seconds is

A) 2.5

B) 3

C) 3.5

D) 4

Q48. Equivalent resistance seen between the terminals A and B

A) 1.8 ohm

B) 2.4 ohm

C) 3.6 ohm

D) 4.8 ohm
O49. A periodic sawtooth wave is passed through a 1H inductor as shown below. What is the value
of

VL(t) at t=3 msec

A) 1 V

B) 2 V

C) 3 V

D) 4 V

Q50.If the maximum energy stored in the capacitor below is finite then the possible current source
charging it is

A) impulse

B) ramp

C) unit step

D) parabolic

Q 51. In the circuit shown below, s is a constant voltage source and 𝐼L is a constant current load.
The value of 𝐼L that maximizes the power absorbed by the constant current load is
A) s/4R

B) s/2R

C) s/R

D ∞

Q52. If ir=( 4exp(-3t) + 3exp(-4t) )A and iL(0-)=1A then what is angle

A π/

B π/

C π/

D) π/

Q53.

A) 10

B) 20

C) 30
D) 40

Q54.

A) 3

B) 4

C) 5

D) 3.5

Q55.

A). 3

B) .45

C) .9

D) 3
Q56.

A)0 V

B) 2.5 V

C) 5.5 V

D) 5 V

Q 57.

A)1

B) 2

C) 3

D)4

Q 58.
A)0.5

B) 1

C) 1.5

D)2

Q59.

A)4

B) 5

C) 6

D)7

Q60.

A)49.5

B) 48

C) 46.5

D)47
Q61.

A)45

B) 60

C) 125

D)225

Q62.

A)

B)

C)

D)
Q63.

A)0

B) 1.5

C) 2

D)4

Q64. In a series RLC circuit the resonant frequency f0 is the frequency at which the current is
maximum.For the maximum voltage across L the frequency is

A)=f0

B) >f0

C) <f0

D)cannot be determined

Q65.

A).5

B) .6

C) .65

D).7

Q66
A)1

B) 2

C) 4

D)6

Q67.

A)integrator

B) positive zero crossing detector

C) sample and hold circuit

D)half wave precision rectifier

Q68.
Q69
 A)25

B) 40

C) 50

D)55

Q 70.

A)6

B) 7

C) 8

D)9

Q.71. A second-order system has the transfer function:

 C(s)/R(s) = 4/(s2 + 4s + 4).

With r(t) as the unit-step function, the response c(t) of the system is:-

Q.72. In the circuit shown below the current voltage relationship when D1 and D2 are identical is given
by (Assume Ge diodes)
Q.73. In the circuit shown below, the switch was connected to position 1 at t<0 and at t=0, it is changed
to position 2. Assume that the diode has zero voltage drop and a storage time ts. For 0<t<ts, VR is given
by (all in volts)

(a) VR = -5
(b) VR = +5
(c) 0<=VR<5
(d) -5<VR<0

Q.74. In MOSFET devices the n-channel type is better than the p-channel type in the following respects:

(a) it has better noise immunity

(b) it is faster

(c) It is TTL compatible

(d) it has better drive capability

Q.75. The circuit shown in the figure is:

(a) a non inverting amplifier

(b) an inverting amplifier

(c) an oscillator

(d) a Schmitt trigger

Q.76. The output voltage Vo of the circuit shown in the figure is:

(a) -4 V (b) 6 V

(c) 5 V (d) -5.5 V

Q.77. The CMRR of the differential amplifier of the figure shown is:

(a) infinity
(b) 0
(c) 1000
 (d) 1800

Q.78. The Op-Amp of figure shown below has a very poor open loop voltage gain of 45 but is
otherwise ideal. The gain of the amplifier is:

(a) 5
(b) 20
(c) 4
(d) 4.5

Q.79. The I-V characteristics of the zener diode D1 and D2 are shown in Figure I. These diodes are
used in the circuit in Figure II. If the supply voltage is varied from 0 to 100 V, then breakdown occurs
in
 (a) D1 only
(b) D2 only
(c) Both D1 and D2
(d) None of D1 and D2

Q.80. MOSFET can be used as a

(a) current controlled capacitor

(b) voltage controlled capacitor

(c) current controlled inductor

(d) voltage controlled inductor

Q.81. For an n-channel enhancement type MOSFET, if the source is connected at a higher potential
than that of the bulk (i.e. VSB>0), the threshold voltage VT of the MOSFET will

a) remain unchanged
b) decrease
c) change polarity
d) increase

Q.82. In the following circuit employing pass transistor logic, all NMOS transistors are identical with a
threshold voltage of 1 V. Ignoring the body effect the output voltages at P, Q and R are:

(a) 4 V, 3 V, 2 V
(b) 5 V, 5 V, 5 V
(c) 4 V, 4 V, 4 V
(d) 5 V, 4 V, 3 V
 Q.83. For the circuit shown in the following figure, transistors M1 and M2 are identical NMOS
transistors. Assume that M2 is in saturation and output is unloaded. The current Ix is related to Ibias
as:

a) Ix = Ibias + Is
b) Ix = Ibias
c) Ix = Ibias – Is
d) Ix = Ibias – (VDD – Vout/RE)

Q.84. The Op-A p show i the figure elow is ideal. R = √ L/C).The phase angle between Vo and Vi at
 = / √ LC).

(a) /2
(b) 
(c) 3/2
(d) 2
Q.85. The circuit that uses an ideal Op Amp for small positive values of Vin with a diode in the feedback
path and input connected to resistor:

(a) A half wave rectifier

(b) A differentiator
(c) A logarithmic amplifier
(d) An exponential amplifier

Q.86. In the circuit of the figure, Vo is :

(a) -1 V
(b) 2V
(c) +1 V
(d) + 15 V

Q.87. Assume that the op amp of the figure is ideal. If Vi is a triangular wave, then Vo will be:
(a) square wave
(b) triangular wave
(c) parabolic wave
(d) sine wave

Q.88. Figure shows the circuit of a gate in the resistor logic family. The circuit represents a:

(a) NAND
(b) AND
(c) NOR
(d) OR

Q. 89. Both transistors T1 and T2 shown in the figure have a threshold voltage of 1 Volt. The device
parameters K1 and K2 of T1 and T2 are respectively 36 A/V2 and 9A/V2. The output Vo is:
(a) 1V
(b) 2V
(c) 3V
(d) 4V

Q.90. In the circuit, the Silicon npn transistor Q has a very high value of . The required value of R2 in
kilo to produce Ic = 1 mA:

(a) 20
(b) 30
(c) 40
(d) 50
Q. 91. In the circuit shown below the op-amps are ideal. Then Vout in volts is:

(a) 4
(b) 6
(c) 8
(d) 10

Q. 92. What type of filter is shown and what is the cut-off frequency?

(a) high pass, 1000 rad/sec

(b) low pass, 1000 rad/sec
(c) high pass 10000 rad/sec
(d) low pass 10000 rad/sec
Q. 93. The inverting Op amp has open loop gain of 100. Closed loop gain is:

(a) -8
(b) -9
(c) -10
(d) -11

Q. 94. An NMOS transistor is biased in the linear region with small VDS and is used as a resistance. Which
one of the following statements is NOT correct?

(a) If the device width W is increased, the resistance decreases.

(b) If the threshold voltage is reduced, the resistance decreases.
(c) If the device length L is increased, the resistance increases.
(d) If VGS is increased, the resistance increases.

Q. 95. The drain current of a MOSFET in saturation is given by ID = K(VGS – VT)2 where K is a constant. The
magnitude of the trans-conductance gm is

(a) K(VGS – VT)2/VDS (b) 2K(VGS – VT)

(c) ID/(VGS- VDS ) (d) K(VGS- VT)2/VGS

Q. 96. In the figure, all transistors are identical and have a high value of beta. The voltage VDC is:

(a) 5V
(b) 10 V
(c) 1V
(d) None of these

Q. 97. The circuit in the figure is

(a) low-pass filter

(b) high-pass filter
(c) band-pass filter
(d) band-reject filter

Q. 98. In the op-amp circuit given, the load current iL is:

(a) –Vs/R2
(b) Vs/R2
(c) -Vs/RL
(d) Vs/R1

Q. 99. The wave shape of Vo in figure is:

Q. 100. In the circuit given, assume transistor is in the active region. It as a large  and its base emitter
voltage is 0.7 V. The value of Ic is:

(a) Indeterminate since RC is not given

(b) 1 mA
(c) 5 mA
(d) 10 mA

Q. 101. The circuit shown here is:

(a) low pass filter with f3db = 1/(R1 + R2)C rad/s

(b) high pass filter with f3db = 1/R1C rad/s
(c) low pass filter with f3db = 1/R1C rad/s
(d) high pass filter with f3db = 1/(R1 + R2)C rad/s

Q. 102. The output voltage of the regulated power supply shown in the figure:

(a) 3V
(b) 6V
(c) 9V
(d) 12 V

Q. 103. In the CMOS circuit shown, electron and hole mobilites are equal and M1 and M2 are equally
sized. Device M1 is in the linear region if:
(a) Vin < 1.875 V
(b) 1.875 V < Vin < 3.125 V
(c) Vin > 3.125 V
(d) 0 < Vin <5 V

Q. 104. Logic function implemented by circuit:

(a) Y = AB + C
(b) Y = (A + B) C
(c) Y = (A + B)C
(d) AB + C

Q. 105. The output Y of the circuit is:

(a) A+B+C
(b) A + B.C + AC
(c) A+B+C
(d) A.B.C

If any doubts mail at vaanshikmahindroo@gmail.com

 ANSWERS

2) c 30) c

5) d 31) a

6) d 32) c

7) c 33) d

8) d 34) b

9) b 35) a

10) d 36) d

11) d 37) a

12) b 38) d

13) d 39) d

14) d 40) b

15) b 41) c

16) b 42) a

17) b 43) b

18) c 44) c

19) a 45) b

20) c 46) c

21) b 47) d

22) b 48) d

23) c 49) a

24) d 50) a

25) c 51) b

26) d 52) d

27) b 53) b

28) c 54) b

29) c 55) c
56) d 84) c

57) b 85) c

58) c 86) d

59) c 87) a

60) b 88) d

61) d 89) c

62) c 90) c

63) a 91) c

64) b 92) a

65) d 93) b

66) b 94) d

67) b 95) b

68) c 96) a

69) c 97) a

70) c 98) a

71) b 99) a

72) b 100) d

73) a 101) b

74) b 102) c

75) d 103) a

76) d 104) d

77) c 105) a

78) d 81) d

79) a 82) c

80) b 83) b