Design and Analysis of Low Noise Amplifier at 28 GHz in

Standard 45nm CMOS Technology with Optimal Noise

Figure and Gain
at
Cadence System Design, Noida

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Submitted By:
Swarnima Rajput
(13502917, DECE)

Under the supervision of

Dr. Vikram Karwal

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

JAYPEE INSTITUE OF INFORMATION TECHNOLOGY

(Declared Deemed to be University U/S 3 of UGC Act)

A-10, SECTOR-62, NOIDA, INDIA

May 2018
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Wirelessacommunication has been experiencing tremendous growthain technology. In this

industry, number of frequency bands required to be supported, and the demand for low cost
Radio Frequency IntegratedaCircuit (RFIC) designs has increased immensely. Lot of ongoing
researche is based on front-endadesign of RF transceiver. The design of receiver path has
become a challenging aspect, because of increased interferences occurred around the
communication path. The receiving end of any communication system has an important
element which is the Low Noise Amplifier (LNA). LNA is the first basic block on the receiver
end. As the operatingafrequency is higher in RFIC design, receiver path also experiencesathe
internal noises in the system. The performance of transceiveradepends on each of the individual
blocks such as low noise amplifier, oscillator etc. In RF transceiver, RF signal is amplified by
one or more LNA stages, and then passed to a mixer. The mixer is basically used to mix the
RF signal with a local oscillator output at a fixed offset to be tuned to develop a down-
converted, intermediate frequency (IF) signal that can then be further amplified. The most
important considerations that measure the performance of LNA areagain and noise figure. Due
to the large number of LNAs in aasingle receiver, minimization of noise figure and power
consumption are two major congestions in LNA design. With the demand for higher data rates,
attempts were made to develop wireless data standards using concepts similar to those used in
the successful wireless telecommunication standards. To achieve high data rates, the radio
frequency was increased, resulting in the 28 GHz carrier frequency for 5G standards. The main
objective of the project was to design an LNA at 28GHz with lowest possible NF and highest
possible Gain with low power consumption and a stable input and output impedance of 50
ohms. The project work has been divided into three main parts. The first part presents the design
topologies and a comparison with other LNAs topologies and the second part briefs the
common source LNA with inductive degeneration designed in the thesis. The third part consists
two stage LNA design in order to achieve higher gain. This thesis has discussed the various
topologies of LNA and compared them on the basis of NF & gain and the best one is chosen.
To support this statement, the analysed results of different topologies are explained below:

(i) Inductive Degeneration Common Source Cascode LNA: This is the most commonly used
topology. This topology yields the one of the best gain of 15.65dB and lowest NF of 2.1dB
with lowest power consumption. And it is giving the most stable input and output impedance
that is of 50 ohms. Hence, it is chosen for the further procedure.
(ii) Inductive Degeneration Common Gate Cascode LNA: This turns out the worst topology in
terms of noise figure and input output matching. The gain of this topology is 14.8dB with noise
figure of 4.2dB and power consumption of 13mW.
(iii) Transformer-Coupled Input Integrated Matching in Cascode Amplifier: This topology
works on the concept of negative resistance. Although this topology shows the lowest NF but
it is not considerable because it has high power consumption than Inductive Degeneration
Common Source Cascode topology. It achieved the gain of 16.1dB, NF of 1.73dB but with
high power consumption.
(iv) Inductively Source Degenerated Differential Cascode LNA Without Cross Coupled
Capacitor: This is a Differential cascode circuit it works on the half circuit analysis. So, on
theoretical basis this topology must had shown the better results than single ended topology
but it didn’t work out the same way when it came to practical level. This topology gives a gain
of 15.89dB and NF of 2.94dB.
(v) Inductively Source Degenerated Differential Cascode LNA with Cross Coupled Capacitor:
This topology is similar to the previous one. In this Cross Coupled capacitor are used and they
were making the circuit too sensitive when it comes to choose their value, at some value the
circuit was acting like a oscillator. It gives the NF of 2.99dB and gain of 15.73dB.
(vi) Two Stage Inductive Degeneration Common Source Cascode LNA: To improve the gain
of single ended inductive degeneration common Source cascode topology this two-stage
topology has been designed. This topology is giving the desirable gain i.e. higher than 25dB at
schematic level. This topology shows the best performance. It gives the NF of 2.2dB and gain
of 29.2dB and very stable input output matching impedance i.e. of 50 ohms. After getting the
gain of 29.2dB we moved further to layout of the LNA.

All the simulations in this thesis have been performed in “Cadence Virtuoso AnalogaDesign
Environment” using 45nm technology file. The designed LNA circuit is simulated using
“Spectre” simulator. The voltage supply used is 1.1V. Hence, the designed Enhanced Cascode
LNA and Two Stage LNA exhibit a gain of 15.6dB with noise figure (NF) of 2.1dB and gain
of 29.2dB with NF of 2.2dB respectively. After Layout designing and optimization the single
ended inductive degeneration common source cascode topology gives the gain 12.5dB of and
NF 2.4dB.