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SRC
EXTERNAL LOAD
CSSP CSSN
TOP VIEW
CSSN
CSSP
PDS
DHIV
PDS
SRC
PDL
DHIV
DHI
SRC
PDL P2
DCIN
28 27 26 25 24 23 22 MAX1909
VCTL MAX8725 LDO
LDO IINP P1
IINP
ACIN 3 19 PGND
REF CLS DHI
REF 4
MAX1909 18 CSIP ACOK
MAX8725
LDO
GND/PKPRES 5 17 CSIN DLO N1 10μH
8 9 10 11 12 13 14 CCV
CSIN
CCI
BATT
IINP
CLS
ICTL
VCTL
CCI
CCV
CCS
CCS
GND
REF
THIN QFN
Electrical Characteristics
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VVCTL = VICTL = 1.8V, MODE = float, ACIN = 0, CLS =
REF, GND = PGND = 0, PKPRES = GND, LDO = DLOV, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CHARGE VOLTAGE REGULATION
VCTL Range 0 3.6 V
VVCTL = 3.6V (3 or 4 cells);
-0.8 +0.8
not including VCTL resistor tolerances
VVCTL = 3.6V/20 (3 or 4 cells); not including
-0.8 +0.8
Battery Regulation Voltage VCTL resistor tolerances
%
Accuracy VVCTL = 3.6V (3 or 4 cells); including VCTL
-1.0 +1.0
resistor tolerances of 1%
VVCTL = VLDO (3 or 4 cells, default
-0.5 +0.5
threshold of 4.2V/cell)
VVCTL Default Threshold VVCTL rising 4.1 4.3 V
VVCTL = 3V 0 2.5
VCTL Input Bias Current µA
VDCIN = 0, VVCTL = 5V 0 12
CHARGE-CURRENT REGULATION
MAX1909 0 3.6
ICTL Range V
MAX8725 0 3.2
CSIP-to-CSIN Full-Scale Current-
69.37 75.00 80.63 mV
Sense Voltage
MAX1909: VICTL = 3.6V (not including ICTL
-7.5 +7.5
resistor tolerances)
MAX8725: VICTL = 3.2V (not including ICTL
-5 +5
resistor tolerances)
Electrical Characteristics
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VVCTL = VICTL = 1.8V, MODE = float, ACIN = 0, CLS =
REF, GND = PGND = 0, PKPRES = GND, LDO = DLOV, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CHARGE VOLTAGE REGULATION
VCTL Range 0 3.6 V
VVCTL = 3.6V (3 or 4 cells); not including
-0.8 +0.8
VCTL resistor tolerances
VVCTL = 3.6V/20 (3 or 4 cells); not including
-0.8 +0.8
Battery Regulation Voltage VCTL resistor tolerances
%
Accuracy VVCTL = 3.6V (3 or 4 cells); including VCTL
-1.0 +1.0
resistor tolerances of 1%
VVCTL = VLDO (3 or 4 cells, default
-0.8 +0.8
threshold of 4.2V/cell)
VVCTL Default Threshold VVCTL rising 4.1 4.3 V
VVCTL = 3V 0 2.5
VCTL Input Bias Current µA
VDCIN = 0V, VVCTL = 5V 0 12
CHARGE-CURRENT REGULATION
MAX1909 0 3.6
ICTL Range V
MAX8725 0 3.2
CSIP-to-CSIN Full-Scale Current-
69.37 80.63 mV
Sense Voltage
MAX1909: VICTL = 3.6V (not including ICTL
-7.5 +7.5
resistor tolerances)
MAX8725: VICTL = 3.2V (not including ICTL
-5 +5
resistor tolerances)
BATTERY INSERTION
AND REMOVAL RESPONSE SYSTEM LOAD-TRANSIENT RESPONSE
MAX1909/MAX8725 toc01 MAX1909/MAX8725 toc02
5A
ISYSTEMLOAD
17V 0A
VBATT
16V 5A
5A/div IIN
IBATT
VCCV 0A 0A
IIN 5A IBATT
0A 5A/div 0A
CCS
3V 3V
VCCV
VCCI 2V 2V
VCCI VCCI, VCCV VCCI
VCCV
1V 1V
VCCI CCI VCCS
0V 0V
500μs/div 100μs/div
MAX1909/MAX8725 toc04
VDCIN
20V -0.2
INDUCTOR CURRENT
-0.8
VBATT AC-COUPLED
200mV/div
-1.0
1.8V -1.2
VCCV
1.6V -1.4
500μs/div 0 1 2 3 4 5 6 7 8 9 10
LDO CURRENT (mA)
MAX1909/MAX8725 toc06
-0.02
0.05
LDO OUTPUT ERROR (%)
-0.04
-0.06
0
-0.08
-0.10
-0.05
-0.12
-0.10 -0.14
0 10 20 30 0 200 400 600 800 1000
INPUT VOLTAGE (V) REF CURRENT (μA)
MAX1909/MAX8725 toc08
98
4 CELLS
0.05
96
REF OUTPUT ERROR (%)
94
0
EFFICIENCY (%)
92 3 CELLS
-0.05 90
88
-0.10
86
84
-0.15
82
-0.20 80
-40 -15 10 35 60 85 0 0.5 1.0 1.5 2.0 2.5 3.0
TEMPERATURE (°C) CHARGE CURRENT (A)
SWITCHING FREQUENCY vs. VIN - VBATT IINP ERROR vs. INPUT CURRENT
500 4.0
MAX1909/MAX8725 toc10
MAX1909/MAX8725 toc09
450 3.5
CHARGER
SWITCHING FREQUENCY (kHz)
400
3.0 DISABLED
350
2.5
300
IINP (%)
250 2.0
200 1.5
150
1.0
100
0.5
50
0 0
0 2 4 6 8 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VIN - VBATT (V) INPUT CURRENT (A)
MAX1909/MAX8725 toc12
MAX1909/MAX8725 toc11
VBATT = 13V
INPUT CURRENT-LIMIT ACCURACY (%)
6
3
VBATT = 10V
4
IINP ACCURACY (%)
2
2
0 1
VBATT = 16V
-2 VBATT = 12V
0
-4 ICHARGE = 3A
-1
-6
MAX1909 ONLY
-8 -2
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 1.0 1.5 2.0 2.5 3.0
INPUT CURRENT (A) SYSTEM LOAD (A)
MAX1909/MAX8725 toc14
INPUT CURRENT-LIMIT ACCURACY (%)
INPUT CURRENT-LIMIT ACCURACY (%)
3 2
2 1
0 -1
-1 -2
VBATT = 13V VBATT = 10V
-2 -3
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.5 2.0 2.5 3.0 3.5
SYSTEM LOAD (A) VCLS (V)
0V 0V
50μs/div 10μs/div
Pin Description
PIN NAME FUNCTION
1 DCIN DC Supply Voltage Input. Bypass DCIN with a 1μF capacitor to power ground.
2 LDO Device Power Supply. Output of the 5.4V linear regulator supplied from DCIN. Bypass with a 1μF capacitor.
AC Detect Input. This uncommitted comparator input can be used to detect the presence of the charger’s
3 ACIN
power source. The comparator’s open-drain output is the ACOK signal.
4 REF 4.2235V Voltage Reference. Bypass with a 1μF capacitor to GND.
GND MAX1909: Ground this pin.
5
PKPRES MAX8725: Pull PKPRES high to disable charging. Used for detecting presence of battery pack.
AC Detect Output. High-voltage open-drain output is high impedance when ACIN is greater than 2.048V.
6 ACOK
The ACOK output remains a high impedance when the MAX1909/MAX8725 are powered down.
Trilevel Input for Setting Number of Cells and Asserting the Conditioning Mode:
MODE = GND; asserts conditioning mode.
7 MODE
MODE = float; charge with 3 times the cell voltage programmed at VCTL.
MODE = LDO; charge with 4 times the cell voltage programmed at VCTL.
Input Current Monitor Output. The current delivered at the IINP output is a scaled-down replica of the
8 IINP system load current plus the input-referred charge current sensed across CSSP and CSSN inputs. The
transconductance of (CSSP - CSSN) to IINP is 3mA/V.
9 CLS Source Current-Limit Input. Voltage input for setting the current limit of the input source.
10 ICTL Input for Setting Maximum Output Current
11 VCTL Input for Setting Maximum Output Voltage
12 CCI Output Current-Regulation Loop-Compensation Point. Connect 0.01μF to GND.
13 CCV Voltage-Regulation Loop-Compensation Point. Connect 10k in series with 0.1μF to GND.
14 CCS Input Current-Regulation Loop-Compensation Point. Use 0.01μF to GND.
15 GND Analog Ground
16 BATT Battery Voltage Feedback Input
17 CSIN Output Current-Sense Negative Input
18 CSIP Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN.
19 PGND Power Ground
Low-Side Power-MOSFET Driver Output. Connect to low-side NMOS gate. When the MAX1909/MAX8725 are
20 DLO
shut down, the DLO output is low.
21 DLOV Low-Side Driver Supply. Bypass with a 1μF capacitor to ground.
22 DHIV High-Side Driver Supply. Bypass with a 0.1μF capacitor to SRC.
High-Side Power-MOSFET Driver Output. Connect to high-side PMOS gate. When the MAX1909/MAX8725
23 DHI
are shut down, the DHI output is high.
24 SRC Source Connection for Driver for PDS/PDL Switches. Bypass SRC to power ground with a 1μF capacitor.
25 CSSN Input Current Sense for Charger (Negative Input)
26 CSSP Input Current Sense for Charger (Positive Input). Connect a current-sense resistor from CSSP to CSSN.
Power-Source PMOS Switch Driver Output. When the MAX1909/MAX8725 are powered down, the PDS output
27 PDS
is pulled to SRC through an internal 1M resistor.
System-Load PMOS Switch Driver Output. When the MAX1909/MAX8725 are powered down, the PDL output
28 PDL
is pulled to ground through an internal 100k resistor.
P3 RS1 TO
AC ADAPTER 0.01Ω SYSTEM LOAD
C1
22μF
0.1μF 0.1μF
SRC
OUTPUT VOLTAGE: 12.6V
C22
CHARGE I LIMIT: 3.0A 1μF CSSP CSSN
PDS C17
R6 D4
SRC 0.1μF
590kΩ DHIV
R7
1% DCIN
196kΩ
C5
1%
1μF MAX1909
PDL P2
MAX8725
VCTL LDO
R4 C13
LDO 100kΩ 1μF R13
ICTL 33Ω
OUTPUT DLOV
C16
ACIN 1μF
LDO
MODE
(INPUT I LIMIT: 7.5A) P1
R8
1MΩ LDO DHI
REF CLS
ACOK
TO DLO N1
HOST L1
SYSTEM 10μH
LDO PGND
R9
10kΩ CSIP
CCV CSIN
BATT BATT +
CCI
R5 C4
10kΩ CCS GND 22μF
REF
C9
0.01μF C12 BATTERY
C11 C10 1μF
0.1μF 0.01μF
TEMP
GND BATT -
PGND GND
P3 P4 RS1 TO
AC ADAPTER 0.01Ω SYSTEM LOAD
C1
22μF
0.1μF 0.1μF
SRC
OUTPUT VOLTAGE: 16.8V
C15 CSSP CSSN
1μF
PDS C17
R6 D4
SRC 0.1μF
590kΩ DHIV
R7
1% DCIN
196kΩ
C5
1%
1μF MAX1909
PDL P2
MAX8725
LDO VCTL LDO
C13
1μF R13
D/A OUTPUT ICTL 33Ω
OPEN-DRAIN DLOV
C16
OUTPUTS MODE
1μF
ACIN
LDO
P1
R8 DHI
1MΩ
INPUT ACOK
SCL SCL
SDA SDA
TEMP
GND BATT -
PGND GND
DCIN
MAX8725 ONLY
PKPRES LDO
PACK_ON
RDY
0.9 * LDO 5.4V
4.2235V
LINEAR REF
REFERENCE
REGULATOR
ICTLOK
ACIN
CHG ACOK
0.8V
LOGIC
GND
BATT
SRDY 2.048V
DRIVER
DCIN SRC
GND PDS
CHG
CCS SRC-10V DRIVER
PDL
CLS MODE
100kΩ
CSIP
LEVEL Gm IINP
SHIFTER
CSIN
SRC
GMI
DRIVER
ICTL DHI
CCI
DHIV
BATT
MAX1909 ONLY LVC
BATT_UV
DC-DC
CELL SELECT CONVERTER
3.0V/CELL GMV
LOGIC AND
MODE
BATTERY VOLTAGE-
DIVIDER
CCV
REF DLOV
DRIVER
R
9R DLO
VCTL MAX1909
MAX8725 PGND
R
threshold of 7V. The PDS switch turns off, the PDL switch Conditioning Mode
turns on, and the system runs from the battery. The MAX1909/MAX8725 can be programmed to per-
The body diode of the PDL switch prevents the voltage form a conditioning cycle to calibrate the battery’s fuel
on the power source output from collapsing. gauge. This cycle consists of isolating the battery from
Charging can also be inhibited by driving ICTL below the charger and discharging it through the system load.
0.035V, which suspends switching and pulls CCI, CCS, When the battery reaches 100% depth of discharge, it
and CCV to ground. The PDS and PDL drivers, LDO, is then recharged. Driving the MODE pin low places the
input current monitor, and control logic (ACOK) all MAX1909/MAX8725 in conditioning mode, which stops
remain active in this state. Approximately 3mA of sup- the charger from switching, turns the PDS switch off,
ply current is drawn from the AC adapter and 3µA and turns the PDL switch on.
(max) is drawn from the battery to support these To utilize the conditioning mode function, the configura-
functions. tion of the PDS switch must be changed to two source-
In smart-battery systems, PKPRES is usually driven from connected FETs to prevent the AC adapter from sup-
a voltage-divider formed with a low-value resistor or PTC plying current to the system through the MOSFET’s
thermistor inside the battery pack and a local resistive body diode. See Figure 2. The SRC pin must be con-
pullup. This arrangement automatically detects the pres- nected to the common source node of the back-to-
ence of a battery. The MAX8725 threshold voltage is 55% back FETs to properly drive the MOSFETs.
of VLDO, with hysteresis of 1% VLDO to prevent erratic It is essential to alert the user that the system
transitions. is performing a conditioning cycle. If the user termi-
nates the cycle prematurely, the battery can be dis-
AC Adapter Detection and charged even though the system was running off the
Power-Source Selection AC adapter for a substantial period of time. If the AC
The MAX1909/MAX8725 include a hysteretic compara- adapter is in fact removed during conditioning, the
tor that detects the presence of an AC power adapter MAX1909/MAX8725 keep the PDL switch on and the
and automatically delivers power to the system load charger remains off as it would in normal operation.
from the appropriate available power source. When the
In the MAX8725, if the battery is removed during condi-
adapter is present, the open-drain ACOK output
tioning mode, the PKPRES control overrides condition-
becomes high impedance. The switch threshold at
ing mode. When MODE is grounded and PKPRES goes
ACIN is 2.048V. Use a resistive voltage-divider from the
high, the PDS switch starts turning on within 7.5µs and
adapter’s output to the ACIN pin to set the appropriate
the system is powered from the AC adapter.
detection threshold. When charging, the battery is iso-
lated from the system load with the p-channel PDL In the MAX1909, disable conditioning mode before the
switch, which is biased off. When the adapter is absent, battery is overdischarged or removed.
the drives to the switches change state in a fast break-
before-make sequence. PDL begins to turn on 7.5µs DC-DC Converter
after PDS begins to turn off. The MAX1909/MAX8725 employ a buck regulator with
The threshold for selecting between the PDL and PDS a PMOS high-side switch and a low-side NMOS syn-
switches is set based on the voltage difference chronous rectifier. The MAX1909/MAX8725 feature a
between the DCIN and the BATT pins. If this voltage pseudo-fixed-frequency, cycle-by-cycle current-mode
difference drops below 100mV, the PDS is switched off control scheme. The off-time is dependent upon VDCIN,
and PDL is switched on. Under these conditions, the VBATT, and a time constant, with a minimum tOFF of
MAX1909/MAX8725 are completely powered down. 300ns. The MAX1909/MAX8725 can also operate in
The PDL switch is kept on with a 100kΩ pulldown resis- discontinuous conduction for improved light-load effi-
tor when the charger is powered down through ICTL or ciency. The operation of the DC-DC controller is deter-
PKPRES, or when the AC adapter is removed. mined by the following four comparators as shown in
The drivers for PDL and PDS are fully integrated. The pos- Figure 4:
itive bias inputs for the drivers connect to the SRC pin and • CCMP: Compares the control point (lowest voltage
the negative bias inputs connect to a negative regulator clamp (LVC)) against the charge current (CSI). The
referenced to SRC. With this arrangement, the drivers can high-side MOSFET on-time is terminated if the CCMP
swing from SRC to approximately 10V below SRC. output is high.
AC ADAPTER
CSSP CSSN
MAX1909
MAX8725
DHI
CSS DHI
20X
IMAX
1.94V
R Q
COMP
S Q
DLO
DLO
IMIN
0.15V
TOFF
ZCMP
0.1V
LVC CLS
GMS
ICTL
CSIP
LVC GMI
CSI
20X CSIN
VCTL
GMV
BATT
RCCV
The poles and zeros of the voltage-loop transfer function Setting the LTF = 1 to solve for the unity-gain frequency
are listed from lowest frequency to highest frequency in yields:
Table 1.
Near crossover, C CV has a much lower impedance
fCO _ CV = GMOUT × GMV ⎛⎜ RCV ⎞
⎟
than ROGMV. Since CCV is in parallel with ROGMV, CCV ⎝ 2π × COUT ⎠
dominates the parallel impedance near crossover.
Additionally, RCV has a much higher impedance than For stability, choose a crossover frequency lower than
CCV and dominates the series combination of RCV and 1/10th of the switching frequency. Choosing a
CCV, so: crossover frequency of 30kHz and solving for R CV
using the component values listed in Figure 1 yields:
ROGMV × (1 + sCCV × RCV ) MODE = VCC (4 cells)
≅ RCV
(1+ sCCV × ROGMV ) GMV = 0.125µA/mV
COUT also has a much lower impedance than RL near COUT = 22µF
crossover, so the parallel impedance is mostly capaci- VBATT = 16.8V
tive and: RL = 0.2Ω
GMOUT = 3.33A/V
RL 1
≅
(1+ sCOUT × RL ) sCOUT
fCO_CV = 30kHz
fOSC = 400kHz
If RESR is small enough, its associated output zero has
a negligible effect near crossover and the loop-transfer
function can be simplified as follows: 2π × COUT × fCO _ CV
RCV = = 10kΩ
GMV × GMOUT
RCV
LTF = GMOUT × GMV To ensure that the compensation zero adequately can-
sCOUT cels the output pole, select fZ_CV ≤ fP_OUT:
CCV ≥ (RL/RCV) COUT
where CCV ≥ 4nF (assuming 4 cells and 4A maximum
charge current).
Figure 6 shows the Bode plot of the voltage-loop fre-
quency response using the values calculated above.
CCI Loop Compensation
The simplified schematic in Figure 7 is sufficient to
80 0
describe the operation of the MAX1909/MAX8725 when
the battery current loop (CCI) is in control. Since the
60
output capacitor’s impedance has little effect on the
response of the current loop, only a single pole is
PHASE (DEGREES)
MAGNITUDE (dB)
40 -45
required to compensate this loop. ACSI is the internal
gain of the current-sense amplifier. RS2 is the charge
20
current-sense resistor, RS2 = 15mΩ. R OGMI is the
equivalent output impedance of the GMI amplifier,
0 -90
which is greater than 10MΩ. GMI is the charge-current
amplifier transconductance = 1µA/mV. GMOUT is the
-20 MAG DC-DC converter transconductance = 3.3A/V.
PHASE
-40 -135 The loop transfer function is given by:
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz) ROGMI
LTF = GMOUT × A CSI × RS2 × GMI
1+ sROGMI × CCI
Figure 6. CCV Loop Response
100 0
CSIP CSIN MAG
GMOUT 80 PHASE
RS2
60
MAGNITUDE (dB)
CSI 40
-45
20
0
CCI
GMI -20
CCS GMIN
MOSFET Drivers
100 0 The DHI and DLO outputs are optimized for driving
MAG moderately-sized power MOSFETs. The MOSFET drive
80 PHASE capability is the same for both the low-side and high-
side switches. This is consistent with the variable duty
60
factor that occurs in the notebook computer environ-
PHASE (DEGREES)
MAGNITUDE (dB)
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
3 5/15 Updated Benefits and Features section 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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