Arithmetic Logic Unit (ALU)

Storage Elements

Computer Science 104

Today’s Lecture
•  Homework #4 coming soon
•  Building the building blocks…
Outline
•  Review
•  Digital building blocks
•  An Arithmetic Logic Unit (ALU)
•  Storage Elements
•  Register File
Reading
Chapter 4.2
start reading 4.1 & 4.3

© Alvin R. Lebeck CPS 104 2

 Review: Boolean Functions and Expressions

F(A, B, C) = (A * B) + (~A * C)

A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

© Alvin R. Lebeck CPS 104 3

Review: Boolean Gates

•  Gates are electronics devices that implement simple

Boolean functions
Examples

a AND(a,b) a OR(a,b) NOT(a)

a
b b

a XOR(a,b) a NAND(a,b)
b b

a NOR(a,b) a XNOR(a,b)
b b

© Alvin R. Lebeck CPS 104 4

 Review: Boolean Functions, Gates and Circuits

•  Circuits are made from a network of gates. (function

compositions).
a b XOR(a,b)
a 0 0 0
XOR(a,b) F = ~a*b + ~b*a
b 0 1 1
1 0 1
1 1 0
a

F
b

© Alvin R. Lebeck CPS 104 5

Circuit Example: Decoder

I1 I0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

© Alvin R. Lebeck CPS 104 6

 Circuit Example: 2x1 MUX
Multiplexor (MUX) selects one of many inputs

a y
MUX(A, B, S) = (A * S) + (B * ~S)
b

B
Gate 1
Y = (A * S) + (B * ~S)
Gate 3

A Gate 2

© Alvin R. Lebeck CPS 104 7

Example 4x1 MUX

a 1

b 0 a 3

1 b 2
y y
0 c 1
c 1

d 0
d 0

2
s0 s1
S

© Alvin R. Lebeck CPS 104 8

 Arithmetic and Logical Operations in ISA

•  What operations are there?

•  Arithmetic Logic Unit (ALU)
 Hardware that performs operations
 Only one operation at a time
•  How do we implement the operations?
 Consider AND, OR, NOT, and ADD
 Input is two bits, output…

© Alvin R. Lebeck CPS 104 9

Truth Table for 1-bit Addition

01101100 a b Cin Sum Cout

0 0 0 0 0
01101101 0 0 1 1 0
0 1 0 1 0
+00101100 0 1 1 0 1
10011001 1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

What is the circuit for Sum and for Cout?

© Alvin R. Lebeck CPS 104 10

 A 1-bit Full Adder
Cin 01101100
Sum
a 01101101
b +00101100
10011001
a b Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
Cout
1 1 1 1 1

© Alvin R. Lebeck CPS 104 11

Example: 4-bit adder

S3 S2 S1 S0

Cout Full Adder Full Adder Full Adder Full Adder Cin “0”

a3 b3 a2 b2 a1 b1 a0 b0

This is called a Ripple Carry Adder:

There are faster, more complex adder circuits.

© Alvin R. Lebeck CPS 104 12

 ALU Slice (Almost)
Cin

3
a F Q
0 a+b
b 2 1 NOT b
2 a OR b
Q 3 a AND b
1

Adder 0
2

Cout

F
© Alvin R. Lebeck CPS 104 13

Subtraction

•  How do we perform integer subtraction?

•  What is the hardware (circuit)?

© Alvin R. Lebeck CPS 104 14

 ALU Slice
Cin A F Q
0 0 a+b
1 0 a-b
3
- 1 NOT b
a - 2 a OR b
- 3 a AND b
b 2
Q
1

1
0 Adder 0
2
~Add/Sub
Cout

F
© Alvin R. Lebeck CPS 104 15

Overflow
Example1: Example2:
0100000 1000000
01101012 (= 5310) 10101012 (=-4310)
+01010102 (= 4210) +10010102 (=-5410)
10111112 (=-3310) 00111112 (= 3110)

Example3: Example4:
1100000 0000000
01101012 (= 5310) 00101012 (= 2110)
+11010102 (=-2210) +01010102 (= 4210)
00111112 (= 3110) 01111112 (= 6310)
© Alvin R. Lebeck CPS 104 16
 Overflow Detection for 4-bit adder

OVERFLOW

S3 S2 S1 S0

Cout Full Adder Full Adder Full Adder Full Adder Cin “0”

a3 b3 a2 b2 a1 b1 a0 b0

© Alvin R. Lebeck CPS 104 17

The ALU

Overflow = Zero

Qn-1 Qn-2 Q1 Q0

ALU control
ALU Slice ALU Slice ALU Slice ALU Slice

an-1 bn-1 an-2 bn-2 a1 b1 a0 b0

© Alvin R. Lebeck CPS 104 18

 Abstraction: The ALU

•  General structure
•  Two operand inputs
ALU Operation
•  Control inputs
Input A
Zero
ALU Result
Overflow
•  We can build Input B

circuits for
 Multiplication Carry Out
 Division
 They are more
complex
© Alvin R. Lebeck CPS 104 19

The Shift Operation

•  Consider an 8-bit machine

•  How do I implement the shift operation?

© Alvin R. Lebeck CPS 104 20

 Shifter

© Alvin R. Lebeck CPS 104 21

Summary thus far

•  Given Boolean function, generate a circuit that

“realizes” the function.
•  Constructed circuits that can add and subtract.
•  The ALU: a circuit that can add, subtract, detect
overflow, compare, and do bit-wise operations (AND,
OR, NOT)
•  Shifter
Next up: Storage Elements: Registers, Latches, Buses

© Alvin R. Lebeck CPS 104 22

 Memory Elements

•  All the circuits we looked at so far are combinational

circuits: the output is a Boolean function of the
inputs.
•  We need circuits that can remember values.
(registers)
•  The output of the circuit is a function of the input
AND a function of a stored value (state) .
•  Circuits with memory are called sequential circuits.

© Alvin R. Lebeck CPS 104 23

Set-Reset Latch

R 0 R 0
0 1
1 Q 0 Q

0 1
1 0
S 0 Q S 0 Q

R S Q
0 0 Q
0 1 1
1 0 0
1 1 - Don’t set both S & R to 1

© Alvin R. Lebeck CPS 104 24

 Set-Reset Latch (Continued)

R 0 R 0
0 1
1 Q 0 Q

0 1
1 0
S 0 Q S 1 Q

Time

1
S 0

1
R
0

1
Q
0

© Alvin R. Lebeck CPS 104 25

Data Latch (D Latch)

Enable
Q D E Q
0 1 0
1 1 1
- 0 Q
Q
Data
Time
Does not
1 affect Output
D 0

1
E
0

1
Q
0

© Alvin R. Lebeck CPS 104 26

 D Flip-Flop

D D Q D Q Q
D D
latch latch
E E Q Q

  On C D is transferred to the first D latch and the second is stable.

  On C the output of the first stage is transferred to the second

(output), and the first stage is stable.

  Output changes only on the edge of a clock

© Alvin R. Lebeck CPS 104 27

Register File

•  Register File = the set of locations for register values

 E.g., 32 32-bit registers
•  How do I build a Register File using D Flip-Flops?
•  What other components do I need?

© Alvin R. Lebeck CPS 104 28

 Register File

•  Circuit to determine which of 32 registers?

•  Circuit to get just the data from one of 32 registers?

© Alvin R. Lebeck CPS 104 29

Tri-State Driver
  The Tri-State driver is like a (one directional) switch:
  When the Enable is on (E=1) it transfers the input to the output.
  When the Enable is off (E=0) it disconnects the output.

E D E Q
0 1 0
Q 1 1 1
D
- 0 Z

Z :- High Impedance
E

D Q

© Alvin R. Lebeck CPS 104 30

 Bus Connections
  The Bus: Many to many connections.
  Mutual exclusion: At most one Enable is on!
  Control must ensure this!
 Note: Bus sometimes used to denote multiple
parallel wires

© Alvin R. Lebeck CPS 104 31

Register Cells on a bus

Q Q Q Q
D D D D
D D D D
latch latch latch latch
IE E OE IE E OE IE E OE IE E OE
Q Q Q Q

One can “source” and “sink” from any cell on the bus
by activating the right controls,
IE--input enable, and OE--output enable.

© Alvin R. Lebeck CPS 104 32

 3-Port Register Cell
Data-In
Bus-C
Bus-B
Q

Complement Q

Bus-A
DinEnable OutA OutB

•  Stores one bit of a register

•  Can Read onto Bus-A & Bus-B and Write from Bus-C
Simultaneously

© Alvin R. Lebeck CPS 104 33

3-Port Register File

EC EA EB
Bus-C
Bus-B

Bit-1
Q

Bus-A

Bus-C
Bus-B

Q
Bit-0
Bus-A

© Alvin R. Lebeck CPS 104 34

 Address Decode Circuit
Data-in
Bus-C
Bus-B
Register address: 01
Q

Bus-A
DEnable OutA OutB

A0
A1
EA
B0
B1
EB
C0
C1
EC

© Alvin R. Lebeck CPS 104 35

Register File (Four 4-bit Registers)

Reg-3 Reg-2 Reg-1 Reg-0
A3
One-bit Cell One-bit Cell One-bit Cell One-bit Cell B3
C3
A2
One-bit Cell One-bit Cell One-bit Cell One-bit Cell B2
C2
A1
One-bit Cell One-bit Cell One-bit Cell One-bit Cell B1
C1
A0
One-bit Cell One-bit Cell One-bit Cell One-bit Cell B0
C0

A-En
Add-A1
Add-A0
B-En
Add-B1
Add-B0

C-En
Add-C1
Add-C0

© Alvin R. Lebeck CPS 104 36

 Digital Logic Summary

•  Given Boolean function, generate a circuit to “realize”

the function.
•  Constructed circuits that can add and subtract.
•  The ALU: a circuit that can add, subtract, detect
overflow, compare, and do bit-wise operations (AND,
OR, NOT)
•  Shifter
•  Memory Elements: SR-Latch, D Latch, D Flip-Flop
•  Tri-state drivers & Bus Communication vs. MUX
•  Register Files
•  Control Signals modify what circuit does with inputs
 ALU, Shift, Register Read/Write

© Alvin R. Lebeck 37

Summary

•  The ALU & Shifter

•  Storage elements
 S-R latch, D-Latch, D Flip-Flop
•  Register File
•  Next time
 Finite state machines
 HCL

© Alvin R. Lebeck CPS 104 38