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Published in IET Circuits, Devices & Systems

Received on 8th October 2009
Revised on 11th February 2010
doi: 10.1049/iet-cds.2009.0275

ISSN 1751-858X

Modelling of power metal-oxide

semiconductor field-effect transistor
for the analysis of switching characteristics
in half-bridge converters
S. Xu X. Liu W. Sun
National ASIC System Engineering Research Center, Southeast University, Nanjing, Jiangsu 210096, People’s Republic of China
E-mail: xus@seu.edu.cn

Abstract: Considering the power metal-oxide semiconductor field-effect transistor (MOSFET) parasitic elements,
the switching characteristics of half-bridge converters are analysed. First, the switching operation process of the
converter is discussed, including Cdv/dt induced voltage, turn-on and turn-off transient and drain–source voltage
oscillations. Then an analytical model of power MOSFET is deduced and validated. Based on the model and Saber
software, the switching characteristics of half-bridge converters are simulated with different values of parasitic
elements. Finally, according to the simulation results, the design optimisations are presented, and an
experimental prototype is used to validate the proposed approach.

1 Introduction of these various MOSFET elements, such as internal and

Half-bridge converter is one of the most popular power
supply topologies in medium power applications, such as
communication, high-definition television and personal
computer [1, 2]. This type of converter has been
extensively studied in the literature, including modelling,
design optimisation, control method, zero-voltage
switching technology, improved half-bridge topologies, and
so on [3– 5]. With the increased demand for high power
density nowadays, larger current and higher switching
frequency are the new trends for power supplies. In these
circumstances, the effect of circuit parasitic parameters on
the converter’s performance is becoming more and more
significant [6]. In particular, during the switching instant,
it will increase the circuit’s power loss and deteriorate the
system stability.
Power MOSFET is one of the most important
components in power converters, but which has many
inherent parasitic elements [7– 10]. The switching
characteristics of the converters are not well understood
because of the complexity resulting from the involvement
external parasitic inductances [11 –14] and capacitances
[15], gate resistance [16, 17], threshold voltage, package
characteristics [18 –21], driver capability and layout, and so
on. The power loss analysis and modelling of the individual
power MOSFET based on measurement have been
investigated in some previous works [7– 10]. However, the
study of switching characteristics in half-bridge converters
by means of power MOSFET modelling considering all
the parasitic elements has not been performed yet.
This paper will be structured as follows. In Section 2, the
switching operation of the half-bridge converter is
discussed; in Section 3, an analytical model of power
MOSFET for analysing switching characteristics is
derived and validated; in Section 4, based on the model
and Saber software, the switching characteristics of half-
bridge converter are simulated and analysed by choosing
different values of parasitic elements; in Section 5,
according to the simulation results, some design
optimisations are proposed, and an experimental prototype
is established to verify the methods. The paper will be
concluded in Section 6.

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2 Switching operation of the
half-bridge converter
Half-bridge converter has various forms in the applications of
power supply. As an example of symmetric half-bridge
converter, Fig. 1 shows its basic circuit with the main
parasitic elements. S1 and S2 represent ideal MOSFET
switches, and the main parasitic elements to be considered
are gate-to-drain capacitance Cgd , gate-to-source
capacitance Cgs , drain-to-source capacitance Cds , gate series
resistance Rg (internal and external), gate series inductance
Lg and source series inductance Ls . The Lr is made up of
the leakage inductance of the transformer T and the drain
series inductance of S2 .
Ideally, by ignoring all the parasitic elements, the main
switching waveforms are shown in Fig. 2a. The two
switches are turned on and off complementarily but with
two dead times. C1 and C2 are equal and large enough, so
that the voltage of the C2 anode is about Vcc /2. When S1
Figure 1 Basic topology of symmetric half-bridge converter,
considering the main parasitic elements
Figure 2 Main working waveforms of symmetric half-bridge converter
a Not considering all the parasitic elements
b Considering the main parasitic elements
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(or S2) is turned on, Vds2 is equal to Vcc (or zero), and
output current flows through secondary winding Ns2 (or
Ns1). In practice, by considering the effects of the parasitic
elements of the switching power MOSFET, the waveforms
would be similar to Fig. 2b. It can be seen that there are
some voltage ringing and spikes, especially in the switching
instants. To turn-on and turn-off, the MOSFET will take
some time, which are normally called the rise and fall
times, respectively. In this section, these particular
phenomena in the circuit will be discussed in detail.
2.1 Cdv/dt induced voltage
In Fig. 2b, during the interval when the high-side MOSFET
S1 is switched on, a positive voltage called Cdv/dt induced
voltage is induced on the gate of the low-side MOSFET
S2 which should be held off by the gate driver. If the
induced voltage is larger than the gate threshold voltage of
S2 , it will be spuriously turned on while S1 is also on. As a
result, a shoot-through current will flow from the input
voltage bus to the circuit common through S1 and S2 ,
leading to an excessive power dissipation in both
MOSFETs. Even worse, the failure will occur in either one
or both the devices. The mechanism causing this
phenomenon is illustrated in Fig. 3.
During the turn-on period of high-side MOSFET S1 , the
full-input voltage Vcc does not immediately appear at drain of
low-side MOSFET S2 because of the Miller effect caused by
Cgd2 . The drain voltage rise on S2 induces a current that is
coupled through its Miller capacitance Cgd2 . This induced
current generates a voltage drop across the gate resistance
Rg2 and gate inductance Lg2 of S2 , then charges the gate-
to-source capacitance Cgs2 at S2 gate. The amplitude of the
induced gate voltage on S2 is determined by the rate of
change on the drain voltage (dv/dt), Cgd2 , Cgs2 , total gate
resistance Rg2 and gate parasitic inductance Lg2 . The
analytical modelling will be presented in detail later in
Section 3.
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Figure 3 Mechanism causing the Cdv/dt induced voltage on
the gate of low-side MOSFET
Furthermore, at the instant when S1 is turned on, the
capacitance Cgd2 , Cgs2 , Cds2 will be charged. This behaviour
generates a very large charge current (more than 10 A),
which totally flows through the high-side MOSFET S1 ,
adding significant amount of power loss, especially in high
dv/dt situations.
As shown in Fig. 3, the charge current of Cgs2 and Cds2 flows
through the source parasitic inductance Ls2 of low-side
MOSFET S2 . An induced voltage is generated and drives
up the source voltage of S2 , which causes the voltage
reduction of the Vgs2 and prevents the Cdv/dt induced
shoot-through. Thus, on the one hand, large Ls2 can help
keep the Vgs at a lower level and slow down the rate of
change of the MOSFET current to reduce the spikes or
ringing in the circuit. On the other hand, the large source
inductance brings the slow rise and fall times of the
switching MOSFET, which may increase the switching
power dissipation. In the applications of high-frequency
switching converters, the switching dissipation is the
primary source of the total power loss of the power
MOSFET, which decreases the efficiency of converter.
Therefore it is important to choose the appropriate source
inductance to make a trade-off.
The Cdv/dt dissipation is proportional to the switching
frequency. From the simulation and test results, it has been
shown that this power loss could be a significant part in
the total circuit loss at 1 MHz. Even at the prevailing
200– 500 KHz operating frequency, Cdv/dt induced loss
could also be a serious problem in half-bridge converters.
The Cdv/dt induced switching loss imposes challenges on
device and circuit design not only for high frequency, but
also for the applications running at light load conditions
most of the time, such as notebook applications.
2.2 Turn-on and turn-off transient
Owing to the parasitic elements in half-bridge converter, the
waveforms of MOSFETs turn-on and turn-off transient are
not ideal. It can be divided into several intervals, and the
gate-to-source voltage, drain-to-source voltage and current
IET Circuits Devices Syst., 2010, Vol. 4, Iss. 4, pp. 327– 336
doi: 10.1049/iet-cds.2009.0275
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are shown in Fig. 4. Here, the low-side MOSFET S2 is
taken as an example to illustrate the operation, and the
high-side MOSFET S1 is similar.
Turn-on transient:
t0 2 t1: The gate driving voltage is set from zero to high
(about 10– 15 V) at t0 , charging the capacitance Cgd2 and
Cgs2 , and causing the gate-to-source voltage Vgs2 rise.
Before the Vgs2 reaches the threshold voltage Vt , S2 stays in
off state and no current flows through it.
t1 2 t2: When Vgs2 rises up to Vt at t1 , S2 starts to be turned
on, causing the drain current Ids2 and voltage Vds2 to increase
and decrease, respectively. The slope of Vgs2 during t1 2 t2 is
lower than that during t0 2 t1 owing to the negative feedback
induced by Ls2 from switching current to gate voltage.
t2 2 t3: At t2 , the Ids2 is saturated and becomes constant,
which makes the Ls2 induced voltage vanished. The fall
speed of the Vds2 increases, and at the moment, gate
driving current is mainly charging the Cgd2 , and Vgs2 stops
increasing.
t3 2 t4: The gate driving voltage continues charging the Cgs2
and Cds2 after the Vds2 falls to zero at t3 . When Vgs2 reaches
the gate driving voltage, the whole turn-on process is over.
Turn-off transient:
t5 2 t6: When the gate driving voltage drops to zero at t5 , the
Vgs2 starts to fall with the Cgs2 and Cgd2 discharging.
t6 2 t7: When the Vgs2 drops to certain value, Vds2 begins to
rise to maintain the drain current. Because of the rise of Vds2 ,
Cgd2’s discharge current takes the mass of the gate sink
current, causing the small change of Vgs2 .
t7 2 t8: Ids2 starts to drop after the Vds reaches the maximum
voltage. Similar to the turn-on transient, the negative
Figure 4 Waveforms of Vgs2 , Ids2 and Vds2 of low-side
MOSFET at turn-on and turn-off transient
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feedback from switching current to gate voltage caused by Ls2
slows down the fall speed of Vgs2 .
t8 2 t9: At the time of t8 , the Vgs2 falls below the threshold
voltage of S2 which then starts to be off. The Cgs2 and Cgd2
continue discharging until the Vgs2 reaches zero.
switching current id can be expressed as (1), where vgs and
vds is the instantaneous gate-to-source and drain-to-source
voltage, Vt is the gate threshold voltage and Kn is the
device-transconductance parameter. RON represents the on-
resistance of the MOSFET, Vgson is the value of vgs set in
RON measurement, which can be provided by datasheet

The switching characteristic discussed above prolongs the ⎧

⎪ 0, vgs ≤ Vt
rise and fall times of the switching power MOSFET, ⎨
2
which decreases the converter efficiency significantly, id = Kn (vgs − Vt ) , vgs . Vt , vds . (vgs − Vt )
⎪
⎩ 2
especially for applications with high switching frequency. Kn [2(vgs − Vt )vds − vds ], vgs . Vt , vds ≤ (vgs − Vt )
(1)
2.3 Drain – source voltage oscillations
Kn = [2RON (Vgson − Vt )]−1
The circuit total loop parasitic inductance, including the
leakage inductance of the transformer primary winding and
the inductance of MOSFET drain forms a resonant circuit The R2 acts as the equivalent reflected impedance of the
with the two MOSFETs output capacitors Cds1 , Cds2 , output load, and Lpi is the transformer’s inductance which
resulting in drain – source voltage oscillations when either of is neglected in the analysis. The body diode of the
the MOSFET is turned off. Large Cds and loop parasitic MOSFET is also ignored so that there is no diode reverse
inductance will cause long period and high peak ringing, recovery.
especially in high-frequency situations. When the frequency
is above 500 KHz, the ringing will probably occupy the Based on the Kirchoff’s theorem, the differential equations
whole interval of both MOSFETs’ off time. If the for this circuit yield
maximum voltage of the drain-to-source ringing is above
the input voltage Vcc , the body diode of the high-side v1 + v2 = v3 (2)
MOSFET will conduct, causing additional power loss of
the circuit. The similar case will happen when the i1 + i2 = iR (3)
minimum ringing voltage falls below zero. Besides dv1 dv
the power loss, this kind of oscillation can also deteriorate C = i1 + 2 C2 (4)
dt 1 dt
the electromagnetic interference (EMI) noise and stability dv2 dv
of the half-bridge converter system. C + 3 C3 + id = i2 (5)
dt 2 dt
di
3 Analytical modelling R1 i1 + 1 L1 = Vc − R2 iR − v1 − Vin (6)
dt
To derive the analytical solution of the half-bridge converter’s di2
L + v3 = Vc − R2 iR (7)
switching characteristics, an equivalent circuit of the power dt 2
MOSFET for switching transient analysis is shown in
Fig. 5. In this equivalent circuit, the power MOSFET is These equations can be converted to the form of (dX/
operating in the cut off, saturation and linear region during dt) ¼ AX + B
the switching transient. According to [9], the instantaneous
 T
X = i1 i2 v1 v2 v3

all the variables in X are functions of time t

⎡ ⎤
R1 + R2 R 1
⎢− L − 2
L1
−
L1
0 0 ⎥
⎢ 1 ⎥
⎢ ⎥
⎢ R2 R2 1 ⎥
⎢ − − 0 0 − ⎥
⎢ L2 L2 L2 ⎥
⎢ ⎥
⎢ ⎥
⎢ C + C3 C2 ⎥
A=⎢ 2 0 0 0 ⎥
⎢ m m ⎥
⎢ ⎥
⎢ ⎥
⎢ − C3 C1
0 ⎥
⎢ 0 0 ⎥
⎢ m m ⎥
⎢ ⎥
⎣ C2 C1 + C2 ⎦
Figure 5 Equivalent circuit of the power MOSFET for 0 0 0
switching transient analysis m m

330 IET Circuits Devices Syst., 2010, Vol. 4, Iss. 4, pp. 327– 336
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-cds.2009.0275
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⎡ ⎤
Vc − Vin
⎢ L1 ⎥
⎢ ⎥
⎢ Vc ⎥
⎢ ⎥
⎢ ⎥
⎢ L2 ⎥
⎢ ⎥
B=⎢
⎢ −
C2 id ⎥
⎥
⎢ m ⎥
⎢ ⎥
⎢ −
C1 id ⎥
⎢ ⎥
⎢ m ⎥
⎣ (C + C )id ⎦
− 1 2
m
m = C1 C2 + C1 C3 + C2 C3

The analytical solution of this differential equation is

t
x(t) = e X (0) +
At
eA(t−t) B dt (8)
0

where X(0) is the initial value of the variable.

The analytical solution is too long and complex to be fully

visualised. Therefore to understand the effects of the parasitic
elements, numerical calculation is used to solve the equations, Figure 6 Comparison of Cdv/dt induced gate voltage
and the recursive (9) can be derived waveforms between model simulation and practical test
⎡ ⎤ a Simulation waveform
i1j+1 b Test waveform
⎢i ⎥
⎢ 2j+1 ⎥
⎢ ⎥
⎢ v1j+1 ⎥
⎢ ⎥
⎢v ⎥
⎣ 2j+1 ⎦
v3j+1
⎡ ⎤
dt
⎢ i 1j + [−(R 1 + R 2 )i 1j − R 2 i 2j − v 1j + V cj − V inj ⎥
⎢ L1 ⎥
⎢ dt ⎥
⎢ i2j + (−R2 i1j − R2 i2j − v3j + Vcj ) ⎥
⎢ ⎥
⎢ L2 ⎥
⎢ ⎥
=⎢⎢ dt ⎥
v1j + [(C2 + C3 )i1j + C2 i2j − C2 idj ] ⎥
⎢ m ⎥
⎢ ⎥
⎢ dt ⎥
⎢ v2j + (−C3 i1j + C1 i2j − C1 idj ) ⎥
⎢ m ⎥
⎣ dt ⎦
v3j + [C2 i1j + (C1 + C2 )i2j − (C1 + C2 )idj ]
m
(9)

For validating the accuracy of this model, Figs. 6 and 7 show

the comparison of Cdv/dt induced gate voltage, turn-on and
turn-off waveforms between simulation and practical tests.
The power MOSFET used in the comparison is
STP75NF75. According to its datasheet, the values of main
elements are Vt ¼ 3 V, RON ¼ 0.01 V, Vgson ¼ 10 V, Ciss ¼
C1 + C2 ¼ 3700 pF, Coss ¼ C1 + C3 ¼ 730 pF, Crss ¼ C1 ¼
240 pF, so C1 ¼ 240 pF, C2 ¼ 3460 pF, C3 ¼ 490 pF,
L1 ¼ L2 ¼ 10 nH (TO-220). In Fig. 6, R1 ¼ 30 V,
R2 ¼ 0 V, Vin ¼ 0 V, the rising time of Vc from zero to 20 V
is 100 ns. In Fig. 7, R1 ¼ 4.7 V, R2 ¼ 3.8 V, Vc ¼ 40 V, Figure 7 Comparison of turn-on and turn-off gate voltage
the rising and fall times of Vin between zero and 12 V is waveforms between model simulation and practical test
50 ns. It must be pointed out that C1 –C3 of the MOSFET a Simulation waveform
are variable according to the drain-to-source voltage v3 b Test waveform

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actually. The curve of capacitance variations can be provided by Table 1 Power dissipation of the whole circuit and MOSFET
datasheet. For more precise simulation results, the variable under different values of Rg
capacitances must be considered in the numerical calculation.
Rg , V 1 5 10 20 30
As shown in Figs. 6 and 7, (a) is the simulation result and (b) Pall , W 104.4 111.8 119.8 136.4 149.9
is the real test waveform. They are similar with each other in the
overall outline, peak voltage and high-frequency oscillations. PS2 , W 0.206 1.056 1.897 3.184 4.157
Even though there are some differences in minor details, it is
because of the omission of some further parasitic elements in
the circuit for improving the simulation efficiency and the
non-ideality in tests. It shows that the proposed model can
reflect the real situations, and can be used to analyse the half-
bridge converter’s switching characteristics.

4 Simulation results
Referring to the symmetric half-bridge converter circuit
shown in Fig. 1, based on the model presented in Section 3,
the simulations are carried out to observe the effects of
parasitic elements. The MOSFET model is same with
the STP75NF75 presented in Section 3, and the initial
values of the circuit components are f ¼ 200 kHz, Vcc ¼ 50 V,
Vt ¼ 3 V, C1 ¼ C2 ¼ 100 mF, Cds ¼ 490 pF, Cgs ¼ 3460 pF,
Cgd ¼ 240 pF, Ls ¼ Lg ¼ 10 nH, Rg ¼ 5 V, Lr ¼ 100 nH,
Lo ¼ 1.2 mH, Ro ¼ 0.2 V and Co ¼ 680 mH.

4.1 Rg
The simulation results for various values of Rg2 are shown in
Fig. 8. The figure shows the waveform of gate-to-source
voltage Vgs2 of the low-side MOSFET S2 . It can be seen
that a larger gate resistance Rg2 results in a longer rise or
fall slope of the Vgs2 and a higher Cdv/dt induced voltage,
causing higher system switching power loss. The power
dissipations of the whole circuit and low-side MOSFET S2
with different values of Rg2 are summarised in Table 1.

As Table 1 shows, power dissipation increases dramatically

with the increase of Rg . These additional power losses are
mainly switching losses, so this effect will be more crucial in
the higher frequency situations. But this does not mean that a
smaller Rg is better, as it will result in larger voltage
oscillations to worsen the EMI noise and stability of the
whole circuit.
Figure 9 Waveforms of Vgs2 and Ids2 under different values
of Lg in simulations
4.2 Lg
Choosing a small value of Rg2 , say 1 V, the value of Lg2 is
changed. As Fig. 9 shows, the gate parasitic inductance
with the capacitance of MOSFET can make the LC
resonance loop and can produce the ringing in the circuit.
This type of oscillation is triggered by the switching actions
of the MOSFET. At some stage, the MOSFET must be
off, but when the induced ringing makes the Vgs exceed Vt
of the MOSFET, such as the case of Lg2 ¼ 80 nH shown
in Fig. 9, the MOSFET will be turned on with the current
flowing through it, which can bring the additional power
loss. Table 2 shows the power dissipation of the circuit and
S2 with different Lg2 .

Figure 8 Waveforms of Vgs2 under different values of Rg in It can be seen that when Lg2 ¼ 80 and 150 nH, the voltage
simulations ringing will exceed the threshold voltage of the MOSFET,

332 IET Circuits Devices Syst., 2010, Vol. 4, Iss. 4, pp. 327– 336
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-cds.2009.0275
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Table 2 Power dissipation of the whole circuit and MOSFET

under different values of Lg

Lg , nH 1 10 30 80 150
Pall , W 104.6 105.5 105.8 108.3 113.1
PS2 , W 0.182 0.188 0.423 0.780 1.076

which increases the power dissipation. Before Vgs exceeds Vt ,

the values of power dissipation with different Lg2 are almost
the same.

4.3 Ls
For different values of Ls2 , the simulation waveforms of the
MOSFET drain-to-source current Ids2 are shown in
Fig. 10. It shows that with the increase of Ls2 , the rise and
fall slope of Ids2 will be slower, but the spike of the current
will be lower. Combining the two factors, the total power
of the half-bridge circuit has not changed much, as shown
in Table 3. Because of the extended rise and fall times of
Ids2 , the power dissipation of S2 will increase. If the diode
reverse recovery of MOSFET is considered, a minimum Ls
may not be the optimum solution because Ls can reduce
did/dt, which helps to reduce reverse recovery current.

4.4 Lr Figure 11 Waveforms of Vd2 and Icc under different values

Lr is the loop parasitic inductance, mainly consisting of the
leakage inductance of the primary winding of transformer
and the drain inductance of the MOSFET. With different
values of Lr , the simulation waveforms of Vd2 and Icc are
shown in Fig. 11. As can be seen in Fig. 11, larger Lr can
of Lr in simulations
induce larger resonance, which will deteriorate the EMI
noise and stability of the converter. The body diode of
MOSFET will turn on when the ringing voltage exceeds
Vcc or falls below zero, which can result in additional power
dissipation of S2 , as shown in Table 4. But Table 4 also
shows that the converter’s total power dissipation decreases
slightly with the increase of the value of Lr . This is because
small Lr will result in high peak current of Icc at the turn-
on moments of the power MOSFET, such as the case of
Lr ¼ 10 nH shown in Fig. 11. The larger Lr can restrain
the current spike more effectively.

4.5 Other parameters

Figure 10 Waveforms of Ids2 under different values of Ls in
simulations
To sum up, the effect of Rg is more substantial on power
dissipations of whole circuit and power MOSFET than the
other parameters. But it does not mean that small Rg is the
best, small Rg with large Lg will strengthen voltage
oscillations to result in additional power dissipation and

Table 3 Power dissipation of the whole circuit and MOSFET Table 4 Power dissipation of the whole circuit and MOSFET
under different values of Ls under different values of Lr
Ls , nH 1 10 30 50 80 Lr, nH 1 10 50 100 200
Pall , W 111.5 111.7 112.2 112.3 112.3 Pall , W 114.9 114.7 112.6 111.5 108.9
PS2 , W 0.751 1.056 1.664 2.092 2.736 PS2 , W 0.838 0.852 0.897 1.066 1.145

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EMI noise. Ls and Lr have little effect on the total power
dissipation of the converter, but Ls can slow down the rate
of change of MOSFET’s drain– source current and Lr can
induce voltage resonance, which will deteriorate the EMI
noise and stability of the converter. Besides the parameters
discussed above, some influences of other MOSFET
elements to the half-bridge converter can be observed in
simulations, which are summarised as follows:
1. With the increase of gate-to-source capacitance Cgs , the
rise and fall times of the MOSFET gate voltage at the
switching transient will have a delay, but the overall impact
is small.
2. The gate-to-drain capacitance Cgd closely correlates with
the Cdv/dt induced voltage. A small value of Cgd is good,
because large Cgd can be detrimental to the circuit, such as
high peak induced gate voltage of the low-side MOSFET
and series LC resonance.
3. The drain-to-source capacitance Cds and the Lr build up a
LC resonance loop. The value of the Cds decides the
characteristic of the ringing in circuit, especially at the
turn-off moment of the power MOSFET.
The simulations analysed above are all under the same load
condition. If different loading is considered, the efficiency
Figure 12 Waveforms of Vg and Vd in a design optimisation of a practical half-bridge converter
a Before optimisation
b After optimisation
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of the converter will be closely related to the load current.
When the MOSFET parasitic inductances are taken into
account, the larger is the load current, the more power loss
is generated in the half-bridge converter.
5 Design optimisations
Based on the analysis presented above, several design
solutions about the power MOSFET parasitic elements can
be applied to optimise the performance of half-bridge
converter:
1. To reduce the effect of the Cdv/dt induced problem, one
solution is to select the MOSFET with high threshold
voltage, but this may increase the on-resistance of drain-to-
source and result in more conduction power loss. Another
solution is to lower the Miller capacitance Cgd . Thirdly, the
peak-induced gate voltage of low-side MOSFET can be
reduced by increasing the gate-to-source capacitance Cgs in
order to prolong the charging time.
2. Since the Cdv/dt induced turn on at low-side MOSFET
is caused by the fast turn-on of high-side MOSFET,
reducing the switching speed of S1 is one possible solution,
such as increasing the external gate resistance. By adding
one small Schottky diode to bypass the gate resistor, the
fall time of S1 can be preserved.
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3. An AC gate drive for S2 is a more effective way of solving
the Cdv/dt induced turn-on problem. To implement an AC
gate drive, an AC coupling capacitor can be added to the gate
of S2 . The purpose of this method is to pull down the turn-
off gate voltage at S2 to below zero and it will shift the Cdv/dt
induced voltage to below the threshold voltage. Besides, this
circuit can also enhance the driving capability for sinking
current, and shorten the fall time at turn-off.
4. The ringing voltage at gate of MOSFET will cause
unstable switching, which results in additional power loss
and EMI noise. Thus, in practical circuit design, the lead
for gate driver must be as short as possible to avoid this
effect, and this rule of short lead is applied to the
MOSFET’s source and drain leads too.
A prototype of half-bridge converter is established to
perform the tests and optimisations. The specifications of
the converter are Vin ¼ 35– 70 V, Vout ¼ 3.3 V and
Iout ¼ 0 – 20 A. The control integrated circuit (IC) is
LM5035, and the power MOSFET is SI7456DP.
The first edition of the prototype is made with a general
printed circuit board (PCB), and Fig. 12a shows the key
waveforms. It can be seen that the rise and fall times of the
gate-to-source voltage are quite long, with the strong ringing
on the drain voltage. According to the analysis presented in
this paper, several design short-comings are found: (a) The
gate resistance of the MOSFET is too large which is about
100 V. (b) The length of the PCB trace between driver IC
and MOSFET gate is too long, which makes the gate
parasitic inductance large. (c) The leakage inductance of the
transformer primary winding is a bit high. During the
optimisation process, the gate resistance is diminished to
10 V, the PCB layout is readjusted to shorten the gate driver
lead, and the transformer is also redesigned. The photo of
second edition of the prototype is shown in Fig. 13.
Compared to the first edition, the improved converter has less
power loss, and the waveforms are shown in Fig. 12b.
Based on the simulation analysis, Rg is the most substantial
element on total power dissipation. Using the optimised
Figure 13 Prototype of the half-bridge converter for test
IET Circuits Devices Syst., 2010, Vol. 4, Iss. 4, pp. 327– 336
doi: 10.1049/iet-cds.2009.0275
www.ietdl.org
Table 5 Total power dissipation of the prototype under
different values of gate resistance
Pall , W Io ¼ 0 A Io ¼ 2 A Io ¼ 5 A Io ¼ 10 A
Rg ¼ 10 V 1.7 W 8.4 W 18.6 W 35.9 W
Rg ¼ 30 V 5.3 W 12.1 W 22.9 W 40.8 W
Rg ¼ 51 V 15 W 22.5 W 34 W 56.5 W
prototype, tests are performed to observe the total power
dissipation under different values of low-side MOSFET’s
gate resistance, as shown in Table 5. The test conditions
are Vin ¼ 50 V, Vo ¼ 3.3 V, Io ¼ 0, 2, 5, 10 A.
The test data also show that the total power dissipation of
the converter indeed increases dramatically with the Rg
getting larger, under various output current loads.
6 Conclusion
By taking into account the parasitic elements of power
MOSFET, the switching characteristics of half-bridge
converter are analysed. The analytical deduction and
simulations have been performed to observe the effects
caused by parasitic inductances and capacitances of power
MOSFET in detail. It is shown that some of these
parasitic parameters have significant influence on the
performance of the converter, such as increasing power loss
and deteriorating stability of the circuit. Especially, in the
applications requiring high switching frequency, most of
these parameters cannot be ignored and must be optimised
during the design. Some optimisation methods are
proposed and proved to be valid in the experimental
prototype. The power MOSFET model proposed in this
paper ignores the body diode so that there is no diode
reverse recovery which has effect on the switching
characteristics. More study of the body diode modelling
will be performed in the future work. As in the half-bridge
converter, the high-side and low-side power MOSFETs’
complementary driving circuit is a common topology in
many other power converters, such as synchronous buck
converter, class-d power amplifier, brushless direct current
(BLDC) motor driver, full-bridge converter. The research
results in this paper can also be applied to analyse these
types of power converters.
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