3442 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.
12, DECEMBER 2010
Negative-Bias Temperature Instability in
Gate-All-Around Silicon Nanowire
MOSFETs: Characteristic Modeling
and the Impact on Circuit Aging
Changze Liu, Tao Yu, Runsheng Wang, Student Member, IEEE,
Liangliang Zhang, Student Member, IEEE, Ru Huang, Senior Member, IEEE,
Dong-Won Kim, Donggun Park, Fellow, IEEE, and Yangyuan Wang, Fellow, IEEE
Abstract—In this paper, the negative-bias temperature in-
stability (NBTI) in p-type gate-all-around silicon nanowire
MOSFETs (SNWTs) is investigated for circuit aging analysis.
Several important features of NBTI in SNWTs are discussed,
including the impacts of 2-D hydrogen diffusion, the nonuniform
temperature profile caused by self-heating effects, the multiple
crystallographic orientations of nanowire channel surface, the
gate-trimming process-induced additional trapping effects, and
the impacts of oxide hole trapping. A predictive NBTI model for
SNWTs is proposed and adopted in circuit simulation to evaluate
the performance degradations of typical logic and analog circuits,
such as inverter, static random access memory cell, ring oscillator,
and current mirror. Without considering other indirect factors,
the results indicate that the performance degradation directly due
to NBTI alone is relatively small, i.e., within the range of less than
8% degradation for the typical circuits simulated. However, the
NBTI behavior in SNWTs is sensitive to process variations, which
cause enhanced variability problem by inducing time-dependent
threshold voltage fluctuations.
Index Terms—Circuit aging, negative-bias temperature in-
stability (NBTI) modeling, process variations, silicon nanowire
MOSFET (SNWT).
I. I NTRODUCTION
T HE gate-all-around (GAA) silicon nanowire MOSFET
(SNWT) is gaining increasing attention as a promising
candidate for future highly-scaled CMOS technology [1]–[4]
due to its short-channel-effect immunity and improved trans-
Manuscript received May 6, 2010; revised August 25, 2010; accepted
September 3, 2010. Date of publication October 7, 2010; date of current version
November 19, 2010. This work was supported in part by the National Natural
Science Foundation of China under Grant 60625403 and Grant 90207004,
by 973 Projects under Grant 2006CB302701, by the National Science and
Technology Major Project under Grant 2009ZX02035-001, and by the Post-
doctoral Science Foundation. The review of this paper was arranged by Editor
J.-S. Suehle.
C. Liu, T. Yu, R. Wang, L. Zhang, R. Huang, and Y. Wang are with the Key
Laboratory of Microelectronic Devices and Circuits, Institute of Microelectron-
ics, Peking University, Beijing 100871, China (e-mail: ruhuang@pku.edu.cn;
r.wang@pku.edu.cn).
D.-W. Kim and D. Park are with the Device Research Team, Samsung
Electronics Company, Kyungki-Do 449-711, Korea.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2077638
0018-9383/$26.00 © 2010 IEEE
port property. On the other hand, reliability is one of the chal-
lenges with device downscaling, among which the negative-
bias temperature instability (NBTI) is a critical concern for
PMOSFETs [5]–[11]. Recently, experimental results on NBTI
in SNWTs have been reported [12], [13]. Precise reliability
predictions for SNWT-based circuits need further physical
NBTI modeling, which includes the quasi-1D GAA structure
and process dependence. In addition, the resulting circuit per-
formance degradation and other accompanying factors, such as
the process variation-induced NBTI fluctuations, are important
for SNWT-based circuit design. This paper will focus on these
issues.
There are several special behaviors of NBTI in SNWTs.
First, due to the GAA cylinder structure, the cross-sectional
geometry effect can lead to the 2-D diffusion of hydrogen
in SNWTs rather than the traditional 1-D diffusion in planar
devices [14], [15]. Second, considering drain bias dependence,
the nonnegligible self-heating effect in SNWTs [16] will induce
a nonuniform temperature profile along the channel that could
result in hydrogen diffusivity distribution. Moreover, besides
the impacts of interface traps, the oxide hole trapping effect
has been paid more attention in NBTI issues recently [17]–[21].
The hole trapping effect is also important in SNWTs [12], [13],
which may further be enhanced by the strain in gate oxide that is
induced during the self-limiting oxidation process in nanowire
fabrication [22], [23]. All of the aforementioned features give
more challenges for NBTI modeling in SNWTs.
In this paper, the NBTI in GAA p-type SNWTs is com-
prehensively investigated and modeled based on experimental
results, which takes into account the 2-D hydrogen diffusion,
the nonuniform 1-D temperature distribution profile along the
channel, the multicrystal orientation of the nanowire channel
surface, and the impacts of gate-trimming-induced additional
trapping effects, as well as the oxide hole trapping effects.
Then, with the proposed NBTI model SNWTs, the circuit
figure-of-merit (FOM) degradations of the typical logic and
analog circuit are evaluated quantitatively. Finally, the impacts
of process variations on the NBTI fluctuation behavior are also
discussed in terms of variations of channel length, nanowire
radius, and oxide thickness in SNWT.
LIU et al.: NBTI IN GAA SNWTs: MODELING AND IMPACT ON CIRCUIT AGING
Fig. 1. (a) Three-dimensional schematic view and (b) TEM images of the
SNWTs investigated in the experiments.
II. D EVICE S TRUCTURE AND E XPERIMENTS
The devices investigated in this paper are the GAA twin
SNWTs fabricated with the top-down approach, as schemat-
ically shown in Fig. 1. The fabrication details were given in
early work [1]. The key processes include the epitaxial growth
of Si/SiGe layers and the selective removal of SiGe. Twin
nanowires are formed along the edges of the SiN hard mask, and
hydrogen annealing is performed to form the cylindrical shape.
After gate oxidation, the twin nanowires are surrounded with a
TiN metal gate. The channel diameter is 10 nm, and the gate ox-
ide thickness is 3.5 nm, as shown in the TEM images in Fig. 1.
The gate lengths are in the range of 37–427 nm. The NBTI in
PMOS SNWTs was measured using both conventional Id –Vg
sweep measurements and online methods [24]. All of the NBTI
measurements are performed at 105 ◦ C, and the gate stress
voltage Vg is from −2.2 to −2.6 V with Vd = 0 V or −1 V
and Vs = Vwell = 0 V [12], [13].
III. M ODELING OF NBTI IN P-T YPE SNWT S
In traditional reaction–diffusion (RD) theory [14], NBTI
degradation is mainly caused by the continuous breaking of
Si-H bonds. This mechanism can be described as a reversible
reaction in which a Si-H bond is weakened by a hole from the
inversion layer to release the hydrogen and form the interface
trap (Si dangling bond). Moreover, the released H atom can
diffuse into the oxide (some H atoms can form H2 during dif-
fusing away from the interface) or anneal the existing interface
trap. Normally, the interface trapped charge density can be ex-
pressed as [8]
ΔNit = ΔNit (kF , kR , Ni , D) (1)
where kF and kR are the effective bond-breaking and annealing
rates, respectively, Ni is the original Si-H density before stress,
and D is the diffusivity of H atom (or H2 ).
On the other hand, hole trapping effects also contribute to
NBTI due to bulk oxide defects. The holes from the inversion
layer can tunnel into the oxide trap states, which can induce the
generation of the oxide-trapped charges [19], i.e.,
ΔNot = ΔNot (TE , not , ET ) (2)
3443
Fig. 2. Typical power law exponential factors for NBTI degradation in
SNWTs at different time stages (from n1 to n3) and the typical NBTI behavior
in SNWT (inserted figure).
where TE is the tunneling probability, not is the density distrib-
ution of oxide traps, and ET is the energy distribution of oxide
trap states.
The generation of interface and oxide charges results in
the increase of threshold voltage and degrades the transistor
performance, i.e.,
ΔVth (t) = Atn (3)
where n is the power law exponential factor in the time domain
of NBTI degradation.
In this section, we include some special NBTI features of
SNWTs into the modeling of the generation of interface and
oxide traps.
A. Special NBTI Behavior in SNWTs
The typical measured power law exponential factor n for
NBTI in SNWT at different stressing stages is given in Fig. 2.
It is observed that under NBTI stress ΔVth increases fast in
the initial stage with n = 0.42, which is much larger than
0.16–0.25 in traditional planar devices [8]. Meanwhile, the
NBTI degradation saturates quickly, as shown in Fig. 3, which
is also different from planar devices. A higher stress voltage can
result in faster initial Vth shift [Fig. 3(a)] and larger saturation
time [Fig. 3(b)]. The observed saturation time in SNWT is less
than 1000 s for all of the studied devices. The foregoing special
NBTI behavior is caused by the structural nature of GAA
silicon nanowires. First of all, the surrounding gate structure of
SNWT can result in 2-D hydrogen diffusion mode rather than
1-D diffusion mode in traditional planar devices. The cross-
sectional geometry effect of the cylinder structure can cause
faster interface trap generation at the initial stages [14]. In
SNWT, the remarkable enhancement of the electrical field due
to the large curvature of the concentric cylinder capacitance
can also accelerate the interface trap generation, because the
electrical field can impact the reaction rate in the RD model.
Second, since the NBTI is sensitive to the temperature near
the interface, when considering drain bias dependence, the
3444 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 12, DECEMBER 2010

Fig. 3. (a) NBTI-induced Vth shift in SNWTs at different gate stress voltages.
(b) NBTI degradation saturation time (the time when the exponential factor is
less than 0.16) in SNWTs.
Fig. 4. Simulation results of the temperature distribution within the gate stack
of SNWTs by considering the self-heating effect.

nonuniform temperature profile and high channel temperature

to molecular dynamics, the diffusivity as a function of the
due to self-heating in SNWT [16] should be taken into account.
temperature T can be expressed as the empirical formula
A higher temperature can lead to a larger hydrogen diffu-   
sivity, which can also cause faster interface trap generation. B 1 1
D = D0 exp − (4)
In addition to interface traps, the nonnegligible hole trapping Rmol T0 T
effect in SNWTs should also be considered. The enhanced
electrical field near cylinder nanowire surface also enhance the where Rmol = 8. 31 J/mol/K, and B is the effective energy with
hole trapping effects. And in SNWT with small gate-area, the the order of magnitude of 104 J for H or H2 . Temperature can
thin gate oxide only includes a small number of oxide defects. also influence the effective bond-breaking and annealing rates
As a result, the hole trapping effect leads to quick saturation (kF , kR ) in (1), which can be expressed as [15]
behavior. In the following part of this section, we will discuss ∞  
the physical modeling of NBTI in SNWT. −E
kF (R) = kF0 (R) exp DF (R) (E)dE (5)
kB T
0

B. Modeling of Interface Trap Generation in SNWTs where E is the activation energy, and DF (R) is the distribution
function of the hole energy, which can be assumed as the
For interface trap generation, we take into account the fol-
Gaussian distribution. In addition, the aforementioned kF , kR ,
lowing effects in SNWTs.
and diffusivity D are also related to the gate oxide thickness.
Impacts of Self-Heating-Effect-Induced Nonuniform Temper-
In this section, considering the first-order effects, this impact is
ature Profile: Temperature in the device is an important factor
not included for simplicity. But the oxide thickness dependence
that determines the NBTI behavior. In planar bulk devices
is included in oxide hole trapping modeling in Section III-C.
with little self-heating effects, the channel temperature is as-
In our NBTI model, we solve the 1-D thermal transport
sumed the same with the environment when the devices are
equation [16], [25] to get the temperature profile along the
working. However, in SNWTs, the self-heating effects can be
channel direction T(x), i.e.,
very serious because the ultrasmall silicon thickness causes  
the increased power density and the ultrascaled dimension of d dT
κ + I 2 r − g(T − T0 ) = 0 (6)
the nanowire structure limits the heat dissipation [16]. Fig. 4 dx dx
shows the thermal simulation results of SNWT, in which a
nonuniform temperature profile induced by the self-heating where the thermal conductivity κ = κ0 T0 /T considering the
effect can clearly be observed. The experimental ac conduc- small dimensional effect, and r is the effective resistance. The
tance measurements for characterizing the self-heating effect in second part of (6) represents the heat generation of the device,
SNWTs have also been reported in [16]. and the third part represents the heat dissipation from the
Therefore, when we estimate the NBTI degradation in channel to the gate. The differential equation of temperature
nanowire circuit performance, the influence of drain voltage on can be expressed as
the channel temperature cannot be neglected due to the fact that  2  
1 d2 T dT 1 I 2r g(T − T0 )
the drain current can be the source of heat generation, which 2
+ − 2
+ 2
− =0
T dx dx T πR κ0 T0 πR2 κ0 T0
induces nonuniform temperature distribution in the nanowire
(7)
channel. First, the hydrogen diffusivity (D) in the gate oxide
is related to the temperature because the high kinetic energy where R is the radius of the SNWT. Taking the analyti-
of the H atom can accelerate the diffusion motion. According cal temperature profile T (x) [which are obtained from the
LIU et al.: NBTI IN GAA SNWTs: MODELING AND IMPACT ON CIRCUIT AGING 3445

numerical solution of (7)] into (4), we can get a diffusivity
distribution D(x) along the channel direction. To describe the
bond-breaking and annealing rates (kF , kR ) in the SNWT,
we take the average temperature of the distribution along the
channel direction into (5) to get a modified kF and kR . This
simple treatment can help get an analytical result to include the
impact of the self-heating effects.
Impact of Multiple Crystallographic Orientation: Due to
the cylinder nanowire structure, the multiple surface crystallo-
graphic orientations can cause more as-grown Si-H bonds (Ni )
Ni0 ,  if Lgt< x < Lchannel −Lgt
than the planar device, which is usually fabricated on the (100)
wafer. Moreover, the diffusivity (D) will be changed for differ-
ent crystallographic orientations. The multiple crystallographic
orientation effect is inevitable and intrinsic in cylinder nanowire
devices.
We assume that the interface of SNWT consists of many
types (n types) of crystallographic orientations in all the grains,
and the appearance probability of the “i” kind of orientation is
pi . As a result, the total Nit generated is the weighted average
impact is equal to the length of the extension region, and linear
distribution function is adopted in our model. The distribution
of Ni along the channel direction can be expressed as in (9),
shown below, where Lgt is the effective length suffered in the
gate trimming impacts, and the obtained Ni0 is consistent with
the results in [14] and [15]. For the oxide traps not , it is also
assumed with the same distribution along the channel, as in
⎧
⎪
⎪ N (x) = 3− 2x N , if x < Lgt
⎨ i Lgt i0
Ni (x) =
⎪
⎪
⎩Ni (x) = 1+ x−Lchannel +Lgt Ni0 , if x > Lchannel −Lgt .
2Lgt
(9)
2-D Hydrogen Diffusion Mode: In nanowire devices, due to
the GAA cylinder structure, the cross-sectional geometry effect
can lead to the 2-D diffusion of hydrogen in SNWTs. The
generation of interface traps can be estimated by assuming the
hydrogen profile for 2-D diffusion mode. For H diffusion,
the threshold voltage shift can be expressed as [14], [15]
of all the Si-H bonds with single crystallographic orientation,
1
which can be expressed as

n
ΔNit = (pi ∗ ΔNi ). (8)
i=1
We consider only the (100), (110), and (111) crystal orien-
tation here for simplicity and assume that p(100) = p(110) =
p(111) . For the amount of the initial Si-H bonds, N has the
following relationship: N(110) ≈ N(111) > N(100) [26], [27].
The surface atom density (Σ) of the three orientations in face-
centered cubic crystal is recognized as (Σ(111) = 2.31/a2 ) >
(Σ(100) = 2/a2 ) > (Σ(110) = 1. 41/a2 ), where a is the lattice
constant. The diffusion is along the normal direction of the
interface, and the higher surface density corresponds to the
longer mean free path in the normal direction considering
the lattice collision. As a result, the hydrogen diffusivity in the
oxide is D(111) > D(100) > D(110) .
In our model, the amount of the initial Si-H bonds is esti-
mated according to [26] and [27], and the hydrogen diffusiv-
ity is assumed to be proportional to the surface density. We
calculate the interface trap density of each crystallographic
orientation and use the average result to estimate the multiple
crystallographic orientation effect.
Impacts of Gate Trimming Process: To further reduce the
gate length, the gate trimming process is needed in the fabrica-
tion, which could induce more as-grown defects at the interface
and oxide. The damaged region is mainly near the source
and drain. In our model, the distribution of initial Si-H bonds
(Ni ) along the channel direction is considered to include the
gate trimming impact. The effective length suffered from this
⎧  2
⎪ ⎪
1
⎨ (λ + R)(λ + 2R) − 1
2 3 R + R(λ + R) + (λ + R)
ΔVth ∝ (11)
⎪
⎩ R2
1

1 1 R2 +R(R+λ)+(R+λ)2 2
ΔVth∝ √ (λ+R)(2R+λ)−
R 2 3
(10)
where λ is the diffusion length. For H2 diffusion, the threshold
voltage shift can be expressed as (11), shown at the bottom of
the page.
C. Modeling of Oxide Hole Trapping Effects in SNWTs
In addition to the influence of the aforementioned interface
traps, oxide hole trapping effects should also be considered,
which is another critical NBTI mechanism nowadays [28].
In the fabrication of nanowire devices, more stress can be
induced during the self-limiting oxidation process for the cylin-
der nanowire structure [23]. The strain in the gate oxide will
enhance the hole tunneling probability [22]. And the enhanced
electrical field near cylinder nanowire surface also enhance the
hole trapping effects. As a result, hole trapping effects are more
evident for NBTI in SNWTs [12], [13].
During NBTI stress, holes from the inversion layer can be in-
jected into the bulk oxide traps. The tunneling process is mainly
determined by the trap energy lever ET , the distribution of traps
in the position domain, the kinetic energy of the tunneling hole,
the transmission coefficient (TE ) computed by the Wentzel-
Kramers-Brillouin approximation, and the hole surface density
at the interface considering the quantum confinement effects.
To simplify the problem, we assume that the oxide trap states
have uniform distribution. Since the tunneling distance is a
dominant factor of the trapping process, the tunneling proba-
bility for the holes from the inversion layer trapping to the near
 12 ⎫
2
3
2 ⎬
⎪
⎭
3446 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 12, DECEMBER 2010

interface trap is higher than that from the inversion layer to the
deeper oxide trap state. We assume that the holes only occupy
the empty trap states that have the highest tunneling probability
(the empty trap near the interface). When the holes have
filled all the oxide trap states with depth less than x from the
interface, the hole trapping effect can influence the Vth shift as
dNot qnot
dVth(N ot) = q = dx
Cox (x) Cox (x)
εox
Cox (x) = (12)
R ln (1 + (tox − x)/R)

where not is the density of the oxide traps, and Cox (x) is the
effective cylinder capacitance related to the oxide traps with
depth of x. With the increase of the filled depth x, the hole
trapping probability from channel to trap state is decreasing.
However, the hole detrapping probability from the trap state
to the metal gate is increasing at the same time. When the
Fig. 5. Modeling flow for NBTI degradation in SNWTs.
holes have equal trapping and detrapping probabilities, the
oxide-trap-induced Vth shift saturates. For circuit degradation
estimation, we focus on the long time range condition (stress
time is longer than 10 s). The filling depth x is proportional to
the logarithm of the stress time, and an empirical formula [29],
[30] can be given by x ∝ ln t.

D. Predictive NBTI Model for SNWT Circuit Simulation

Considering all the aforementioned effects, the NBTI impact
induced by the interface traps can be expressed  as in (13),
shown at the bottom of the page, where λ = Di (x) × t is
the diffusion length. The distribution of Ni (x) is obtained from
(9). In addition, kF and kR are obtained according to [14]
and [15]. In circuit aging analysis, we focus on the NBTI
prediction after long-time stress, which can be estimated by
adopting H2 diffusion assumption.
The NBTI impact induced by oxide traps is Fig. 6. Experimental results of NBTI in SNWT and the modeled curves
  x   with/without self-heating effects, considering the drain bias dependence.
qnot R (tox − x)
ΔVth(N ot) = ln 1 + dx (14)
εox R
0 IV. NANOWIRE C IRCUIT D EGRADATION
D IRECTLY D UE TO NBTI
where x = x0 ln(t/t0 ). In (14), the obtained not , x0 , and t0 are
consistent with the results of [28] and [30]. Using the theoretical model of the proposed NBTI, we study
The modeling process for NBTI mechanisms in p-type the performance degradation of circuit aging directly due to
SNWTs is shown in Fig. 5, which takes into account all the NBTI behavior alone (without considering any other indirect
mechanisms previously mentioned. The proposed model agrees factors). For logic nanowire circuits, the degradation of gate
well with experiment results for NBTI in SNWTs, as shown delay in the basic inverter is discussed. In addition, we study
in Fig. 6 (considering the drain bias dependence). In addition, the degradation of static noise margin (SNM) in the 6T static
the comparison between the modeling results with and without random access memory (SRAM), as well as the frequency
self-heating effects indicates the impacts of drain voltage during shift due to NBTI in the basic ring oscillator (RO). For analog
stress, which should be considered in the circuit degradation nanowire circuits, we focus on the output current degradation
analysis. of the basic current mirror (CM).

⎛ ⎧ ⎫2 ⎞
⎡  2  ⎤ 12 ⎪ 3

Lchannel⎪
⎨ k  1 1 ⎬
1 
n
⎜ 1 (λ+R)(λ+2R)− 3 R +R(λ+R)+(λ+R)2
⎟
ΔVth(N it) = ⎜ F
Ni (x) ⎣ 2 ⎦ dx⎟
n ⎝ Lchannel ⎪ kR R ⎪ ⎠ (13)
i=1 ⎩ ⎭
0
LIU et al.: NBTI IN GAA SNWTs: MODELING AND IMPACT ON CIRCUIT AGING
Fig. 7. Calculated results of the revised compact I–V model for nanowire
devices and the experiment data.
Fig. 8. Comparison of the relative change of gate delay (Δτ /τ ) between
nanowire inverters and traditional planar CMOS inverters [32]. Nanowire
inverters that consist of (1) five PMOS and two NMOS, (2) 500 PMOS and
200 NMOS, and (3) two-stage inverter chain are considered.
To evaluate the influence of NBTI-induced Vth shift in
nanowire circuits, we modified the I–V model for nanowire
devices based on [31] and adopt it in circuit simulations, which
fits well with the experimental result, as shown in Fig. 7. For
transient circuit simulation, the parasitic capacitance in SNWT
is estimated based on the simulation results. Then, the I–V
core model and the NBTI degradation model for SNWT are
implemented into HSPICE to estimate the typical logic and
analog circuit degradation due to NBTI.
Fig. 8 shows the NBTI-induced gate delay of the nanowire
inverter (the degradation is normalized to the performance of
the fresh circuit). The number ratio of PMOS versus NMOS
(with the same radius) nanowire device is assumed to be 5/2
for the best matching of the inverter. The degradation analysis
is not much sensitive to the ratio assumed. The results show
that the NBTI directly induced gate delay degradation of the
nanowire inverter is only 8%, which is much smaller than
traditional planar devices [32]. Moreover, it can be observed
that the degradation of nanowire gate delay has a smaller slope
than that of the planar devices. This degradation behavior is due
to the quick-saturation NBTI behavior caused by the ultrasmall
gate area for nanowires, which is discussed in Section III.
3447
Fig. 9. NBTI-induced performance degradation of nanowire SRAM cells.
Fig. 10. NBTI-induced degradation for nanowire inverter, RO, and CM.
Averaging the degradation for a long time, the quick saturation
of NBTI leads to a relatively small time exponential factor. The
multiple-wire inverter (the number of PMOS and NMOS is 500
and 200, respectively) and the two-stage inverter present even
smaller degradations of less than 5%. The results indicate that
nanowire-device-based inverters do not suffer much directly
from the NBTI degradation due to the special NBTI behavior
in SNWTs.
The FOM degradations of the SRAM cell have similar results
as the nanowire inverter, which is shown in Fig. 9. The impacts
of multiple crystallographic orientation effect are also studied
by calculating the three components, i.e., orientation (110),
(100), and (111), respectively. The total effect is estimated by
averaging all the orientations in the NBTI model. The results
indicate that, in terms of SNM, read delay, and write delay, the
performance degradation induced by NBTI alone is very small
under the Vdd condition for ten years.
Compared with the performance degradation of the nanowire
inverter, the RO and the output current of CM are less sensitive
to NBTI degradation and show only 4% degradation, as shown
in Fig. 10. The degradation of RO or CM is relatively constant
with device scaling considering the impacts of NBTI behavior
in SNWT. The impacts of oxide hole trapping and the gate
trimming process are evaluated in Fig. 11, which show more
than 10% impact on circuit degradation. With the device scaling
3448
Fig. 11. Impact of oxide traps and gate trimming process in SNWTs on circuit
performances.
down, hole trapping effects would be more important due to
the increasing of tunneling probability with the scaling of oxide
thickness.
It should be noted that, although the circuit performance
degradation directly due to NBTI alone is relatively small in
SNWTs, several accompanied other factors may enlarge the
NBTI degradation indirectly. First, the NBTI in such small
devices can have degradation fluctuations [12], and could be
combined with random telegraph noise [33] which may further
degrade the circuit. Moreover, after the NBTI saturation in
longer stresses, the devices may suffer additional soft break-
down or/and time-dependent dielectric breakdown issues due
to high field. In addition, the process variation would induce
NBTI fluctuation, which is a dynamic variability issue. We
will discuss the last issue in the next section as an example
of indirect impacts on NBTI degradation. Other issues will be
discussed somewhere else in the future.
V. P ROCESS VARIATION -I NDUCED NBTI
F LUCTUATIONS IN SNWT S
Variation is another concern for small-dimensional devices.
For fresh devices, process variations can cause static Vth mis-
match, which is time independent. After device aging, the
device-to-device fluctuations of NBTI degradation can induce
additional time-dependent Vth mismatch. The total standard
deviation of Vth can be expressed as
σVth = (σVth ,static )2 + (σVth ,NBTI (t))2
where σVth ,static is the Vth mismatch in fresh devices, and
σVth ,NBTI (t) is the additional Vth mismatch induced by NBTI
degradation. Therefore, it is necessary to investigate whether
process variations can cause additional NBTI fluctuations in
SNWTs. In this section, we will focus on the latter component.
δ(ΔVth ) |ΔVth (ξ) − ΔVth (ξ + Δξ)| + |ΔVth (ξ) − ΔVth (ξ − Δξ)|
= (16)
ΔVth
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 12, DECEMBER 2010
Fig. 12. Impact of process-induced variations of (a) channel length
(Lchannel ), (b) channel diameter (R), and oxide thickness (Tox ) on NBTI
degradation.
First, the impact of channel length variation on the NBTI
degradation is discussed. Based on the previously proposed
NBTI model of SNWTs, the impact of channel length variation
(ΔL) on NBTI effect is estimated under the ten-year Vdd
condition, with ΔL assumed as ±1, ±2, and ±5 nm for each
channel length in the calculation. The relative ΔVth fluctuation
from NBTI degradation can be calculated as (16), shown at the
bottom of the page, where ξ stands for the variation parameter.
As shown in Fig. 12(a), this impact is relatively serious, and
the fluctuations of NBTI are larger than 8% for all the SNWTs
with channel length scaling to 45 nm in the case of ΔL = 2 nm.
The fluctuations decrease with longer Lchannel , which is a direct
consequence of reducing the ΔL/Lchannel ratio. The relative
ΔVth fluctuations can be less than 10% for Lchannel < 22 nm
in the case of ΔL = 1 nm. Therefore, the variation of channel
length should be controlled to be less than 1 nm to obtain
robust circuit aging performance. The influences of oxide
thickness (Tox ) and radius (R) variations are also calculated,
with the assumed variation ΔTox = 0.2, 0.4, 0.6 nm and ΔR =
0.4, 0.6, 1.0 nm. As shown in Fig. 12(b), these impacts on the
NBTI behavior are also nonnegligible. Furthermore, the radius
variation-induced NBTI fluctuation is more distinct compared
with the variations of channel length and oxide thickness. The
results indicate that the NBTI behaviors of SNWTs are sensitive
to process variations, and thus the induced NBTI fluctuations
can cause serious time-dependent Vth mismatch for nanowire
(15) circuits.
It can be concluded that although the circuit performance
degradation directly due to NBTI alone is relatively small, the
fluctuations of NBTI behavior induced by process variations
are nonnegligible and can cause significant Vth mismatch.
This problem should be taken into account in nanowire circuit
design, particularly for circuits based on highly scaled devices.
2ΔVth
LIU et al.: NBTI IN GAA SNWTs: MODELING AND IMPACT ON CIRCUIT AGING
VI. C ONCLUSION
In this paper, the NBTI mechanism in SNWT has been ex-
perimentally investigated and analytically modeled considering
the unique structure nature of GAA SNWTs. In addition to
the oxide hole trapping/detrapping effect, the proposed NBTI
model for SNWTs takes into account the following impacts
on interface trap generation: the 2-D hydrogen diffusion, the
self-heating-effect-induced nonuniform temperature profile, the
multiple crystallographic orientation of nanowire surfaces, and
the impacts of gate trimming process. In addition, the per-
formance degradations of the typical logic and analog circuit
induced by NBTI are estimated by simulation. The results
indicate that compared with planar CMOS circuits, the per-
formance degradation directly due to NBTI alone is relatively
small without considering the process variations, which is less
than the 8% degradation for the nanowire inverter, SRAM cell,
RO, and CM circuits. However, the NBTI behavior of SNWTs
is sensitive to process variations, which can cause obvious time-
dependent Vth mismatch for nanowire circuits.
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3450 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 12, DECEMBER 2010
Changze Liu received the B.S. degree in physics in
2008 from Peking University, Beijing, China, where
he is currently working toward the Ph.D. degree with
the Institute of Microelectronics, Peking University.
His research interests mainly include nano-CMOS
device reliability, characterization, and modeling.
Tao Yu was born in Liaoning, China, in 1988. He
is currently working toward the B.S. degree with the
Department of Microelectronics, Peking University,
Beijing, China.
Since 2008, he has been an Undergraduate Re-
search Assistant with the Institute of Microelectron-
ics, Peking University, where he is involved in a
project on the variability of nanoscale MOSFETs.
From July 2010 to September 2010, he was an
exchange student at UCLA, Los Angeles, CA. His
research interests include nanoscale MOS device
structure, simulation, and modeling.
Mr. Yu was honored the 2010 National Scholarship by the Department of
Education, China.
Runsheng Wang (S’07) received the B.S. and Ph.D.
(highest honors) degrees in microelectronics from
Peking University, Beijing, China, in 2005 and 2010,
respectively.
From November 2008 to August 2009, he was
a Visiting Scholar with Purdue University, West
Lafayette, IN. He is currently a Postdoctoral Fellow
with the Institute of Microelectronics, Peking
University. He has authored or coauthored over
40 papers and is the holder of three patents. His re-
search interests include novel nanodevice simulation
and fabrication, nanoscale MOSFET reliability and characterization, and RF
MOS device design.
Dr. Wang received the 2008 IEEE Electron Devices Society (EDS) Ph.D.
Student Fellowship and many other awards. He coestablished the IEEE EDS
Peking University Chapter and has been serving as the Chairman since 2008.
Liangliang Zhang (S’08) received the B.S. and M.S.
degrees in microelectronics from Peking University,
Beijing, China, in 2007 and 2010, respectively. He is
currently working toward the Ph.D. degree with the
School of Electrical Engineering, Stanford Univer-
sity, Stanford, CA.
He is currently working on ALD of high-k dielec-
tric materials on germanium MOSFETs. His research
interests include NBTI and RTS noise of MOS de-
vices with novel materials and structures.
Ru Huang (M’98–SM’06) received the B.S. (highest
honors) and M.S. degrees in electronic engineer-
ing from Southeast University, Nanjing, China, in
1991 and 1994, respectively, and the Ph.D. degree
in microelectronics from Peking University, Beijing,
China, in 1997.
Since 1997, she has been a Faculty Member with
Peking University, where she is currently a Professor
and the Head of the Department of Microelectronics.
She is the holder of 21 patents and has authored or
coauthored four books and over 200 papers. Her re-
search interests include nanoscale CMOS devices, nonvolatile memory devices,
and new devices for RF and harsh-environment applications.
Dr. Huang is the recipient of the National Science Fund for Distinguished
Young Scholars and many other awards in China, including the Chang–Jiang
Scholar Distinguished Professor of the Department of Education, the National
Youth Science Award, and the Science and Technology Progress Award. She
is an Editor of IEEE T RANSACTIONS ON E LECTRON D EVICES and the
Associate Chief Editor of SCIENCE CHINA. She was the Technical Program
Cochair of the 7th and 9th International Conferences on Solid-State and
Integrated Circuit Technology (ICSICT), a Far East Committee Member of the
2004 International Solid-State Circuits Conference (ISSCC), and a committee
member of many other international conferences and symposia.
Dong-Won Kim, photograph and biography not available at the time of
publication.
Donggun Park (F’08), photograph and biography not available at the time of
publication.
Yangyuan Wang (SM’89–F’01) received the degree
from Peking University, Beijing, China, in 1958.
Since 1958, he has been a faculty member with
the Institute of Microelectronics, Peking University,
where he is currently the Chair Professor in micro-
electronics. From 1982 to 1983, he was a Visiting
Scholar with the Electrical Engineering and Com-
puter Science Department, University of California,
Berkeley. He also served as the Chairman of the
Board of Semiconductor Manufacturing Interna-
tional Corporation (SMIC), China. He has published
over 200 papers and six books, and is the holder of more than 20 patents.
His research interests include SOI technologies, MEMS technologies, small-
dimensional device physics, and reliability.
Dr. Wang is an Academician (Fellow) of the Chinese Academy of Science.
He is the recipient of many awards in China, including the National Science
Conference Award, the National Invention Award, the first-class Science and
Technology Progress Award of the National Education Committee, and the
Cai Yuan-Pei Distinguished Professor Award of Peking University. He was the
General Cochair of the International Conferences on Solid-State and Integrated
Circuit Technology (ICSICT).