Owned by Dipl. Ing.

Mario Blunk
Buchfinkenweg 3
99097 Erfurt / Germany

Phone +49 (0)361 6022 5184

Email info@blunk-electronic.de
Internet www.blunk-electronic.de
Doc. Vers. 2017-08-10
 Design Reviews Surveys Consulting
HW/SW Engineering (Eagle, KiCad, VHDL, Verilog, Ada, Linux)
 Agenda
Day #1 Day #2 Day #3
●
schematic capture ●
part placement ●
creating/editing parts in
●
defining net classes ●
texts in copper the library
●
electrical rule check ●
silk screen ●
symbols, packages,
(ERC) ●
design rules (DRC) devices
●
schematic structure ●
layer setup, via types ●
library structure
●
exercises & consulting ●
routing ●
naming conventions
●
preparing PCB layout ●
communication with ●
resource management
●
outlines of the board suppliers and assembly ●
CAM processor
●
fiducials, mounting holes houses ●
Gerber/drill data
●
exercises & consulting

Day #4
●
project & schematic structure
●
practicing with modular and hierarchic designs
●
naming conventions / style guides
●
introduction to agile HW development
●
design for test & manufacturing (DFT/DFM)
●
scripting & automation
 Create Project

right-click /
new project
 Create Schematic #1

right-click on
project name /
new schematic
Create Schematic #2
 Schematic Frame
command ADD
 Schematic Capture #1
commands ADD, USE, MOVE, DELETE,
GROUP, NAME, VALUE, CHANGE, SMASH
 Schematic Capture #2
commands NET, NAME, LABEL, SPLIT,
JUNCTION, SHOW
 Schematic Capture #3
command INVOKE or across sheets
use INVOKE V1
 Nets
commands LABEL, MOVE, DELETE
 Gate Swap
command GATESWAP

before after
 Busses
commands BUS, NAME, LABEL, SPLIT
Schematic Structure
 Schematic Layers

commands

DISPLAY,
LAYER,
CHANGE LAYER
Documentation #1
Documentation #2
 Drawing Grid
command
GRID

alternative
grid:

Ctrl+Alt
 Schematic Sheets

command
EDIT .s2

reordering by
EDIT .s2 .s1
 Net Classes #1
define minimum constraints:
track with via drills clearance between tracks

command
CLASS
 Net Classes #2
commands
INFO,
CHANGE CLASS
 Texts #1

commands TEXT, INFO

 Texts #2
command TEXT
>PROJECT
Part Numbering
 Assembly Variants #1
command VARIANT
Assembly Variants #2
 ERC
commands ERC, ERROR
SCRIPTING #1
 SCRIPTING #2

1. 2.
 SCRIPTING #3

Executes automatically on EAGLE start !

https://github.com/Blunk-electronic/lbr_eagle/blob/master/scr/eagle.scr
 SCRIPTING #4

More on EAGLE scripting here :

Scripting Tutorial

http://www.blunk-electronic.de/pdf/Scripting_de.pdf
 PCB / PCBA

Thanks to: Key Design Electronics Ltd. http://www.kdel.co.uk

26 Lancaster Way, Scalby, Scarborough, YO13 0QH, England
+44 (0) 1723 341809
 Create Board

command
Board
 Board Outline
commands MOVE, WIRE, SPLIT, DELETE, CIR,
ARC

$/€

grid metric / inch ?

Metrisch vs. Inch

0.1inch x inch wanted

=
2.54 mm y mm given

0.1 inch=100 mil

 Mounting Holes #1
commands

ADD,
DELETE,
MOVE
 Mounting Holes #2
commands

COPY,
DELETE,
MOVE,
LOCK grid
metric / inch ?
 Fiducials #1
command
ADD
 Fiducials #2

commands MOVE, DELETE, COPY, LOCK

Contact PCB-
assembly house !
 Fiducials #3

Contact PCB-
assembly house !
 Measuring #1
commands MARK, MARK;
 Measuring #2

command DIM
 Part Placement #1
commands LOCK, MOVE R77, GROUP, CHANGE,
ROTATE R-45, MIRROR, RATSNET
 Part Placement #2

mirrored !

keep out
 Texts #1
commands
TEXT,
CHANGE
- TEXT
- SIZE
- RATIO
- LAYER
Texts #2
Texts #3
Board Layer
commands
DISPLAY,
LAYER
CHANGE LAYER
 Restricted Areas #1

commands

WIRE,
POLY,
DELETE,
MOVE,
SPLIT,
GROUP
 Restricted Areas #2

commands

WIRE,
DELETE,
MOVE,
SPLIT,
GROUP
 Restricted Areas #3

commands

POLY,
DELETE,
MOVE,
GROUP
 Routing #1

commands

ROUTE,
WIRE,
SPLIT,
RIPUP,
RATSNET,
MOVE
VIA,
CHANGE
 Routing #2

commands

WIRE,
VIA
NAME,
RATSNET,
...
 Via Properties
commands INFO, CHANGE SHAPE / DIA / DRILL
 Ripup
Ripup all nets:
RIPUP (not reasonable !)

Ripup all nets except:

RIPUP ! GND +5V

Ripup selected nets:

RIPUP GPIO_* JTAG_TCK
Polygons #1
 Polygons #2
command POLY, RATSNEST
 Polygons #3
command RATSNET, NAME, RIP @ yxz;
 Polygons #4
command CHANGE ISO / THERMAL /
ORPHAN / POUR / WIDTH, RIP @ xyz
 Track Length Trimming

command MAEANDER 50
settings for max. deviation & gap in : DRC/MISC

ULP: length
 Autorouter #1
An Autorouter needs preparation and constraints
for useful results !

route all nets:

AUTO (not reasonable)

route all except:

AUTO ! GND +5V

route only:
AUTO GPIO_*
Use restricted areas !
Autorouter #2

Not nice, but fast !

 DRC #1
command
DRC

https://github.com/Blunk-electronic/lbr_eagle/tree/master/dru
 DRC #2
command
DRC
 DRC #3
command
DRC
 DRC #4
command
DRC
 DRC #5
command
DRC

Via drills greater 0.3mm without solder stop !

 DRC #6

exposed via inside an SMD-pad

CAUTION: - DRC-setting clearance/same signals SMD-Via=0 required !

- Contact assembly house ! Solder may drain into via !
 Solder Stop vs. Vias

covered via

exposed via

Do not use as test pad for ICT or

FPT geeignet ! Contact assembly
house !
 Multilayer PCBs

1. Need of multilayer PCB ?

2. Assignment of supply and signal layers ?

3. Layer Setup

4. Vias

5. Contact PCB manufacturer !

Layer Assignment #1
signals

VCC

GND

signals + decoupling
+ signal access
+ crosstalk

- radiation & shielding

- impedance PWR/GND
Layer Assignment #2
VCC

signals

signals

GND
+ radiation & shielding
+ impedance PWR/GND

- decoupling
- signal access
- crosstalk
Layer Assigment #3
VCC

GND

signals

GND
+ decoupling
signals
+ crosstalk
+ radiation & shielding
GND + impedance PWR/GND

- signal access
 Layer Setup #1
command DRC

prepreg

core
 Layer Setup #2

prepreg
core
core
core
prepreg

- 4 layers - 6 layers
- 1 x core - 2 x core
- 2 x prepreg - 3 x prepreg

1+2*15+16 1+2*3+14*15+16
 Vias

through buried blind micro

(connects outer
layer and adjacent
(1+2*15+16) 1+(2*15)+16 [15:1+2*15+16] inner layer only)

[1+2*15+16:15]
 Routing Inner Layers
Blind-Via from top
to layer 2

Buried-Via from layer 2

to layer 15

Blind-Via from layer 15

to layer 16

Through-Via

Test Pads for ICT, FPT, … ?

http://www.blunk-electronic.de/pdf/Design_Checklist_en.pdf
 Documentation #1

Layer 21/22 and 51/52 before:

commands:
SMASH,
MOVE,
GROUP,
CHANGE after:
- SIZE
- RATIO
 Documentation #2
Layer 51/52 (tDocu / bDocu)

commands: TEXT, WIRE, MOVE, GROUP,

CHANGE TEXT / SIZE / RATIO
 Documentation #3
Layer 21/22 (tPlace / bPlace)
 Documentation #4
Drawing Frame
Layer 48 (Document)

commands:
ADD,
MOVE,
GROUP
 Bill of Material (BOM)
& Netlist ...
File/Export/Import/...

RUN bom
RUN export-ict-netlist-pad-coordinates
RUN ipc-d-356

RUN statistic-brd

- assembly variants
- export from BRD/SCH
- special characters
Library Structure #1

https://github.com/Blunk-electronic/lbr_eagle
Library Structure #2
Library Structure #3
 Edit Symbols

commands:
WIRE,
PIN,
TEXT,
CHANGE
- DIR
- FONT
- SIZE
 Edit Packages/Footprints
commands:

LAYER,
PAD,
SMD,
WIRE,
MOVE,
GROUP,
DEL,
NAME,
CHANGE
 Slitted Holes #1
commands:

PAD,
WIRE,
NAME

Layer Millings

Notify PCB
manufacturer !!!
 Slitted Holes #2

Notify PCB manufacturer !

!!! MIND INNER LAYERS !!!

 Create Device
commands: ADD, PAC, CON, PRE, ATTR, VAL
ON/OFF
http://www.blunk-electronic.de/pdf/library_tutorial.pdf
EMS

Technikron
Owned by Ronald Nehring
12627 Berlin / Germany
Tel. +49 (0) 30 8631 7631

www.technikron.de
service@technikron.de

Jenaer Leiterplatten GmbH

Prüssingstraße 31
07745 Jena / Germany

www.jlp.de
 CAM Processor #1

https://github.com/Blunk-electronic/lbr_eagle/tree/master/cam
CAM Processor #2
CAM Processor #3
CAM Processor #4
 CAM Processor #5
Edit file [EXCELLON]
eagle.def
(Version 7.x) Type = DrillStation
Long = "Excellon drill station, coordinate format 2.5 inch"
Init = "%%\nM48\nM72\n"
Reset = "M30\n"
ResX = 10000
ResY = 10000
;Rack = ""
DrillSize = "%sC%0.5f\n" ; (Tool code, tool size)
AutoDrill = "T%02d" ; (Tool number)
FirstDrill = 1
BeginData = "%%\n"
Units = Inch
Select = "%s\n" ; (Drill code)
Drill = "X%1.0fY%1.0f\n" ; (x, y)
Info = "Drill File Info:\n"\
"\n"\
" Data Mode : Absolute\n"\
" Units : 1/10000 Inch\n"\
"\n"
 PentaLogix ViewMate

Helmut Mendritzki
Software-Beratung-Vertrieb
Dahlienhof 1
25462 RELLINGEN / GERMANY
Tel.: +49 (0) 4101 - 20 60 51
Fax: +49 (0) 4101 - 20 60 53
Mobile: +49 (0) 171 - 2155852
Email: mendritzki@aol.com
Web: www.pentalogix.com
 Gerbv

http://gerbv.geda-project.org
 Literature #1

Printed Circuit Board Design

Techniques for EMC
Compliance: A Handbook for
Designers

(IEEE Press Series on

Electronics Technology)
 Literature #2

Joachim Franz
EMV
Störungssicherer Aufbau
elektronischer Schaltungen
(German)

ISBN 3-519-10397-4
Boundary Scan System M-1

Detect manufacturing faults, bring-up and

test of prototypes and systems ?

OpenSource Boundary Scan / JTAG

http://blunk-electronic.de/products.html
What is Boundary Scan ?
 Links
PCB Manufacturing:
www.q-print.de (prototypes)
www.jlp.de (high volume)

Distributors and EMS:

www.ax-electronic.de
www.blunk-electronic.de
www.technikron.de
Thanks for your attention !