Integrated RH-CPA AppNote 18.1.3

RedHawk-CPA Application Notes 18.1.
3 Page |1
RH-CPA Application Notes

RedHawk™
Version 18.1.3
Aug. 3, 2017
TABLE OF CONTENTS
Introduction .................................................................................................................................................. 2
Key features ............................................................................................................................................. 2
Supported Packages ................................................................................................................................ 3
Performance............................................................................................................................................. 3
GSR Keywords Usage ................................................................................................................................. 3
CPA_FILES .............................................................................................................................................. 3
TEMPERATURE ...................................................................................................................................... 4
IMPORT_REGION ................................................................................................................................... 4
THERMAL_ANALYSIS ............................................................................................................................. 5
CPA_MODEL ........................................................................................................................................... 6
TCL Commands ........................................................................................................................................... 6
Setup Nets ............................................................................................................................................... 6
Setup Parts .............................................................................................................................................. 7
Setup Components ................................................................................................................................... 8
Setup Dynamic Probes ............................................................................................................................. 9
Setup Material .......................................................................................................................................... 9
Setup Layer .............................................................................................................................................10
Setup Stackup .........................................................................................................................................10
Setup Solder Ball .....................................................................................................................................10
Setup Solder Bump .................................................................................................................................11
Setup Bondwire .......................................................................................................................................11
Setup Bondwire Profile ............................................................................................................................11
Setup External Environment ....................................................................................................................12
Setup General Configuration....................................................................................................................12
Setup PLOC ............................................................................................................................................12
Setup Unconnected Die Domain ..............................................................................................................13
Setup VRM ..............................................................................................................................................13
Setup Auto ..............................................................................................................................................14
Setup EM Limit ........................................................................................................................................14
Setup Thermal .........................................................................................................................................14
Power Setup ........................................................................................................................................14
TSV Setup ...........................................................................................................................................15
Export a new CTM with power scales in regions ...................................................................................15
Convert MHS to CTM V0......................................................................................................................15
Material Editing ....................................................................................................................................16
Work Area ............................................................................................................................................17
Boundary Setup ...................................................................................................................................17
Simulation Options Setup .....................................................................................................................17
Save Modified..........................................................................................................................................18
Perform DRC Check ................................................................................................................................18
Perform Channel Extraction .....................................................................................................................18
Perform CPM+CPA .................................................................................................................................18
Perform Co-Sim Simulation .....................................................................................................................18
Perform Thermal Simulation ....................................................................................................................18
HTML Report Generation.........................................................................................................................19
© 2017 Ansys Inc

RedHawk-CPA Application Notes 18.1.3 Page |2
Post-Processing ......................................................................................................................................19
EM Check for Current Density Map ......................................................................................................19
Neu2Ans ..............................................................................................................................................21
Convert Multi-Heat Source to T-aware CTM .........................................................................................22
Example TCL Flow ..................................................................................................................................22
User Interface .............................................................................................................................................22
Canvas Operation....................................................................................................................................23
Configuration Buttons ..............................................................................................................................23
Result Buttons .........................................................................................................................................24
Query Buttons .........................................................................................................................................25
User Setup ..................................................................................................................................................25
Extraction Setup for Electrical Users ........................................................................................................26
PDN Channel Setup .............................................................................................................................26
Simulation Options ...............................................................................................................................33
CPM + CPA Modeling ..........................................................................................................................34
Thermal Setup for Thermal Users ............................................................................................................35
PKG Config ..........................................................................................................................................36
Die .......................................................................................................................................................36
Material ................................................................................................................................................43
Boundary .............................................................................................................................................43
Heat Sink .............................................................................................................................................44
Simulation ............................................................................................................................................46
Results .......................................................................................................................................................52
Graphical Results ....................................................................................................................................53
Text File Results ......................................................................................................................................55
Impedance Analysis ................................................................................................................................56
Appendix A .................................................................................................................................................58
SUtility.....................................................................................................................................................58
Select Curves.......................................................................................................................................58
Utilites->Impedance Extractor ..............................................................................................................59
Zoom-in, Zoom-out, Pan and Fit-all features on the S-parameter curves...............................................60
Change plotting line width, color and type for the curves .......................................................................60
Resizable window ................................................................................................................................61
Auto-tip display when mouse pointer is placed on a curve ....................................................................61
Real part, Imaginary part, and Inductance plots ....................................................................................62
Numeric Axis Display ...........................................................................................................................62
Marker .................................................................................................................................................62
Introduction
Released in RedHawk 14.2.1, RH-CPA brings the integrated GUI to RedHawk users for chip-package
analysis in a seamless flow. In RedHawk GUI, user can explore and edit the package design conveniently
with the newly designed user interface. Generating package model and importing into RedHawk is a ‘one-
click’ operation thanks to the automated design setup and the natively created interface files. RH-CPA
provides TCL commands that incorporate package model preparing setup into the existing RedHawk flows.
In addition to the integrated GUI, RH-CPA continues to provide per-bump resolution modeling capability and
high performance analysis solution.
Released in RedHawk 15.2.1, RH-CPA brings the integrated thermal GUI to RedHawk users for chip-
package thermal co-analysis in a seamless flow. In RedHawk GUI, thermal shares the same geometry
editing UI of RH-CPA. It enhances the usability of thermal and helps user performing thermal analysis more
efficiently. RH-CPA user can setup and perform thermal analysis using the same data folder and files for
signal integrity analysis.
Key features
 Integrated GUI and flow in RedHawk
© 2017 Ansys Inc
 Supports 2D and 3D view

 Fully automated setup and analysis
 Support TCL commands
 Newly designed Layout manager for package layout viewing and editing
 Re-designed database that brings over 5X performance improvement for larger layout file operation.
 Per-bump resolution package model
 3D Fast Finite Element Method Engine
 Color contours to display results
Supported Packages
RH-CPA/CTA user can construct models for the following types of package structures:
 Flip-Chip, Wire-bond, Leadframe
 System-in-Package (SiP)
 Image Sensor
Performance
Integrated thermal can perform the following thermal analysis:
 Automatic thermal model generation and analysis based on exact metal distributions in BGA substrate.
 Interface with realistic temperature-dependent layer-aware power map on chips (Chip-Thermal-Model,
or CTM) from RedHawk/Totem and back-annotation for Electro Migration (EM) reliability on chip.
 Pre-layout package modeling and analysis.
 Include GSR keyword setting in “Options” GUI pages for easy mesh and performance controls.
Released in RedHawk 17.1.1, CPA engine improves consistency, accuracy, and efficiency of package
extraction model. The new engine highlights:
1) Simulation time speeds by maximum 30%.
2) Generates Multi-Port Package IBIS v5.0 model <jobname>.pkg.
3) Corrected Lumped-L calculation when decaps are involved. In old versions, Lumped-L counts all the extracted
port locations (DIE + decaps). This is not correct and user expects to see the Lumped-L at the Die port
locations only. This has been fixed in the new CPA solver.
4) Supports temperature dependent RL Extraction.
Released in RedHawk 17.1.2, CPA engine continues to improve consistency of package extraction model.
The enhancements include:
1) Fixed extraction failure when a package pin without PLOC connection was grouped with a package pin
with PLOC connection;
2) BGA port names include domain net name;
3) Port names of channel and die components use underline “_” instead of dot “.” as separator.
Released in RedHawk 18.0.3, CPA engine continues to improve consistency, accuracy, and efficiency of
package extraction model.
GSR Keywords Usage

CPA_FILES
Use the keyword CPA_FILES in GSR for integrated RH-CPA flow.
Syntax:
CPA_FILES {
PACKAGE <package_layout_filename>
MODEL <project_path>
}
© 2017 Ansys Inc

 PACKAGE: specifies the package layout file to be displayed and imported into RH-CPA. The supported
formats are .xfl, .mcm, .sip, .brd and .pre. The layout file can be located at a remote area with
read only permission. The layout file name is used as the project name.
 MODEL: defines the path to CPA project directory. A new directory will be created if don’t exist. If the
MODEL keyword points to a previously saved project, the existing project will be loaded, and the
package layout will not be re-imported.
If keyword MODEL does not exist in .GSR, a default work folder adsCpa will be used instead.
Note 1: Cadence APD, SiP, Allegro designs in .mcm, .sip and .brd files require CAD translation during
importing, therefore the CDSROOT environment variable must point to the APD folder.
Note 2: TCL commands for co-simulation ”perform cpa –static/hotspot” does not work with
CPA_FILES flow
Note 3: TCL command for thermal simulation is available since RedHawk 15.2.2.
Note 4: .pre package file is only supported for thermal flow.
For backward compatibility, the CPA model generated by standalone RH-CPA can be used in the new
flow.
If the standalone RH-CPA project is located at <old_project_path>, define the CPA_FILES keyword as:
CPA_FILES {
PACKAGE <old_project_path>/Result/adsCPA/dB/layout_filename.xfl
MODEL <old_project_path>/Result/adsCPA
}
CPA is able to read layout geometry and GUI configuration from SiWave CPA project folder following below
operations:
1) In SiWave
a) Run CPA simulation, get result folder. For example, <design_name.
siwaveresults/0000_CPA_Sim_1>
b) Export->XFL File. For example, export the package into test.xfl
2) In RH
In .GSR, configure PACKAGE and MODEL keywords in CPA_FILES { }
a) PACKAGE test.xfl
b) MODEL <design_name.siwaveresults/0000_CPA_Sim_1>/adsCPA
3) After launching RH, CPA shows the package geometry and GUI setup read from SiWave project
folders.
TEMPERATURE
Use the keyword TEMPERATURE to specify analysis temperature, for temperature dependent RL extraction.
Syntax:
TEMPERATURE analysis_temperature
IMPORT_REGION
Use the keyword IMPORT_REGION to specify a selective chip area.

In RH, chip region is automatically imported when parsing. GSR file. It transports to CPA and takes effect
while doing PLOC connection. As a result, only those PLOCs inside the IMPORT_REGION will be connected
and used for extraction. All other PLOCs laying outside the IMPORT_REGION will be excluded from PLOC
connection.
Manually connecting a PLOC outside the IMPORT_REGION, you shall see warning message “Below pins
are not connected due to net constraints: <PLOC>/<pkg pin name>” in left bottom of FootPrint Connection
© 2017 Ansys Inc

dialog.
THERMAL_ANALYSIS
Use the keyword THERMAL_ANALYSIS to turn CPA and/or CTA on or off.

Syntax:
THERMAL_ANALYSIS 0: supports CPA only analysis.
THERMAL_ANALYSIS 1: supports CTA only analysis.
THERMAL_ANALYSIS 2: supports both CPA and CTA analysis.
In RH .GSR, keyword PACKAGE can point to the pre package file
If users have no package design in ECAD form, using simple pre-design parameters in the .pre file, one
can still perform chip-in-BGA thermal simulation. Here is an example of the .pre file
PreDesign_layer {
top 0.04m S 20 # ”top” layer of 0.04mm thickness is a signal layer with 20% metal
d1 0.10m D 1 # “d1” layer is a drill layer
bottom 0.04m S 20
}
PreDesign_substrate { # (xll,yll) and (xur,yur) of BGA substrate
-10.000m -10.000m
10.000m 10.000m
}
PreDesign_solder { # full solder array definition
x_pitch 1.000000m
y_pitch 1.000000m
x_number 18
y_number 18
}
PreDesign_solder_void { # range w/o solder array
-5.00m -5.00m 5.00m 5.00m
}
PreDesign_die { #10x10x0.2mm die at (0, 0) on “top” layer
U1 -5.00m -5.00m 5.00m 5.00m 0.20m 0.00m 0.00m top # Repeat for multiple dies on top layer or die
}
PreDesign_mold { # molding range and height
mold -10.00m -10.00m 10.00m 10.00m 1.00m
}
PreDesign_bump { # bump pitch of a die, bump array associated with each
U1 0.5m
}
© 2017 Ansys Inc

For backward compatibility, the thermal model generated by standalone Sentinel-TI can be used in the
new follow. If the standalone Sentinel-TI project is located at <old_proejct_path>, define the CPA_FILES
keyword as:
CPA_FILES {
PACKAGE <old_project_path>/layout_filename.xfl
MODEL <old_project_path>
}
Rename <old_project_path>/Results_TI to <old_project_path>/thermal.
CPA_MODEL
Use the keyword CPA_MODEL to support standalone CPA folder.

Syntax:
CPA_MODEL <project_path>
Note: This flow is used for including a previously generated CPA model in RedHawk analysis, while not
intended for layout visualization, package extraction and co-simulation. CPA license is not required for this
flow.
For backward compatibility, the CPA model generated by standalone RH-CPA can be used in this flow by
defining CPA_MODEL keyword as:
CPA_MODEL <old_project_path>/Result/adsCPA
TCL Commands
Setup Nets
setup cpa net [-name [<netname> | all] | -file <filename>] ? -type [power |
ground| signal]? ?-include [true(1) | false(0)]?
-name <netname> | all: specifies the nets. <netname> is a list of net names (case sensitive) separated by
space. It is allowed to use * to indicate any characters (e.g. VDD* stands for all nets whose name starts
with VDD). To select all nets, use “-name all”.
-file <filename>: specifies a file that contains listed net names which are separated by space or newline.
-type [power | ground | signal]: sets the net type. This option is not required.
-include [true(1) | false(0)]: specifies whether to include the net(s) in package extraction. This option is
not required.
Examples:
1. Set VDD to be power net, and VSS to be ground net. Include those two nets in CPA extraction.
setup cpa net –name VDD –type power –include 1
setup cpa net –name VSS –type ground –include 1
2. Clear the net selection, and include the nets listed in a file.
setup cpa net –name all –include 0
setup cpa net –file PG_nets.txt –include 1
where PG_nets.info contains a listed net names, e.g.
VDD
VDD_15
VSS
TCL command to combine nets. The syntax is

setup cpa net ?-combine? ?-name <netname_list|all>?
-combine: specifies to combine nets
-name <netname_list>: specifies the net name list to be combined; all nets are allowed.
TCL command to remove degassing holes as void composite. The syntax is:
© 2017 Ansys Inc

setup cpa net del ?-name <net..> -layer <layer...>? -voidnp <num_points>?
-name: specifies net name list. If net name does not exist, work on all nets;
-layer: specifies layer name list. If layer is not specified, work on all layers;
-voidnp: specifies number of points (typically 4) of void composite to be deleted.
Setup Parts
setup cpa part –name <partname> ?-type [die | resistor | inductor | capacitor
| bga |other]?
?-r <R_value>? ?-l <L_value>? ?-c <C_value>?
?-neverflip <true|false>?
?-netlist <filename>? ?-subckt <subckt_name>? ?-pinmap {pin1, node1, … }?
?-pingroup [H_division V_division | perpin]? ?-net <netname>?
?-thickness <value>?
-name <partname>: specifies the parts. <partname> can be a list of part names (case sensitive) which
are separated by space.
-type [die | resistor | inductor | capacitor | bga |other]: sets the type for the specified parts. This
option is not required.
-r <R_value> -l <L_value> -c <C_value>: if the type of a part is resistor, inductor, capacitor or other,
this option assigns a generic circuit model to the part with the RLC value. Only a numeric number need
to be given as the R/L/C value, and the unit will be determined automatically. Scale symbols are allowed
as R/L/C value, e.g. 1m=0.001, 1n=1e-9. Note: if the part has 2 pins, the connection between pins and
circuit nodes will be made automatically.
-neverflip <true|false>: specifies NeverFlip is on (true) or off (false).
-netlist <filename>: specifies a circuit model to the part. <filename> can be a .sp file that contains one
or more subckt. It is not allowed to mix the use of -netlist option and -r/-l/-c option.
-subckt <subckt_name>: specifies the subckt name when there are multiply subckts defined in the .sp
file. It not specified, the first subckt will be used. This option has to be used together with -netlist.
-pinmap {pin1, node1, …}: connects the pins of the part to the nodes of the specified circuit model.
Every two entries within the bracket is a pair. In this example, pin1 connects to node1. This option has to
be used together with -netlist. Note: if the -pinmap option is not used, but the part has 2 pins and the
circuit model has 2 nodes, an attempt of connection will be made.
-pingroup [H_division V_division | perpin]: specifies the pin grouping of a part. There are two usages
of this tcl: 1) group by grid. “-pingroup m n” divides the part into an m by n grid, the pins inside one
division become one group; 2) group each pin. “-pingroup perpin” creates a group for each pin.
Use “-pingroup 1 1” to lump all pins together.
-net <netname>: specifies the net that the pin grouping is applying to. If not specified, the pin grouping
is applied to all nets by default. This option has to be used together with -pingroup.
-thickness value: specifies part thickness.
Examples:
1. Specify the type of part “U2” as bga.
setup cpa part -name U2 -type bga
2. Set the type of part “DECAP” as capacitor, and assign the RLC value.
setup cpa part -name DECAP -type capacitor -r 1m -c 10p
3. Assign a circuit model to part “DECAP”, specify the subckt name and connect and pins to circuit nodes.
setup cpa part -name DECAP -netlist decap_model.sp -subckt decap_1 -pinmap
{pin1, vdd, pin2,vss}
4.Group the VDD pins of the part “FCHIP” into 3 by 2 grid.
setup cpa part -name FCHIP -pingroup 3 2 -net VDD
5.Lump all VSS pins of part “FCHIP”.
setup cpa part -name FCHIP -pingroup 1 1 -net VSS
6. Group each pin of part “FCHIP” for all nets.
setup cpa part -name FCHIP -pingroup perpin
TCL to Create Molding Part. The syntax is

setup cpa part ?-add? -name <partname> ?-type molding? ?-size <LLX LLy URx
URy>?
© 2017 Ansys Inc
-add: specifies to add a new part;

-name partname: specifies the new added molding part name;
-type molding: specifies molding part type. We only support to create a new molding part by TCL.
-size LLx LLy URx URy: specifies molding position.
Examples
7. Create a new molding part MOLD_PART at <-5 -5 5 5>
setup cpa part -add -name MOLD_PART -type molding -size -5 -5 5 5
TCL to Delete Part. The syntax is

setup cpa part -del -name <part list>
-name <part list>: specifies part list to delete.
Setup Components
setup cpa component -name <componentName> ? -mount <layerName>?
?-position [above|below]? ?-dx <value>? ?-dy <value>? ?-rot <rotationAngle>? –
include [1|0][-thermal -power xx (W) | –ctm ctmfile | -mhs mhs.file]
-name <componentname>: specifies component(s).
-mount <layerName>: specifies a mounting layer for a component.
-position [above|below]: specifies mounting direction.
-dx <value>: specifies offset size along the x direction.
-dy <value>: specifies offset size along the y direction.
-rot <rotationAngle>: specifies rotation angle.
-include [true(1) | false(0)]: determines whether to include the component in package extraction. At
least one die and one bga component need to be included.
-thermal: this option is used only for die components in thermal simulation
-power: assign constant power for a die component in BGA package.
-ctm: specifies CTM path for a die component.
-mhs: specifies multi-heat source file for a die component.
Examples
1. Specify CTM path for a die component
setup cpa component -name FCHIP -thermal -ctm ./run_dir/adsThermal.tar.gz
2. Specify CTM v0 path for a die component
setup cpa component -name FCHIP -thermal -ctm ../package_cpa_model/FCHIP_T-
aware.ctm
3. Specify mounting layer as below M6 for the BGA component
setup cpa component -name BGA –mount M6 –position below
4. Dis-include few cap. components
setup cpa component –name C1 C2 C3 –include 0
TCL to Create Molding Component. The syntax is

setup cpa component ?-add? ?-name <component> ?-part <partname>? ?-layer
<layername>?
-add: specifies to add a new component;
-name component: specifies the name of molding component;
-part partname: specifies the name of molding part;
-layer layername: specifies the mounting layer for molding component.
Example
5. Create a new molding component Molding mounting on TOP layer
setup cpa component -add -name Molding -part MOLD_PART -layer TOP
TCL to Delete Component. The syntax is

setup cpa component -del -name <component list>
-name <component list>: specifies component list to delete
© 2017 Ansys Inc

Setup Dynamic Probes

setup cpa probe ?-nx <x_grid> -ny <y_grid>? ?-layer <layer_names>? ?-net
<net_names>? ?-bbox <llx, lly, urx, ury>(mm)? ?-bump? ?-file <file_name>?
This TCL command sets up dynamic probes by grid size, net and by bounding box. The usage is described
below:
-nx <x_grid>: specifies grid boxes along X-axis;.
-ny <y_grid>: specifies grid boxes along Y-axis;
-layer <layer_names>: specifies metal layer list;
-net <net_names>: specifies net name list;
-bbox <llx, lly, urx, ury>(mm): specify boundary box in mm unit;
-bump: this option shall go with “-net” and “-layer”, will generate differential probe pairs in the exact bump
locations for specified net on specified metal layer.
-file: reads probe coordinates from a file. The format for each line looks like <probe name> <layer>
<x> <y> <ref layer> <ref x> <ref y>. Please note, we only generate differential probe pair in
same metal layer, so <ref layer> must be same as <layer>.
setup cpa probe -deldynamic

This TCL command removes dynamic probe setup
Tips:
1. Settings will be saved. If you do not use the previous setting, please remember to execute setup cpa
probe -deldynamic.
2. The settings will not be executed until CPA run extraction. You can view the probe points in
MODEL/AutoProbe.txt file.
Examples
1. All layers will have 10x10 grid per each net, except net VDD_15 on TOP has 5x5 grid in bounding box
(-3 3 4 4)
setup cpa probe -nx 10 -ny 10
setup cpa probe -nx 5 -ny 5 -layer TOP -bbox -3 3 4 4 -net VDD_15
2. Generate probes in the exact bump locations for power VDD_CPU1 and ground VSS in TOP layer
setup cpa probe -bump -net VDD_CPU1 VSS -layer TOP
Setup Material
setup cpa material -add -type [conductor | dielectric] -name <material_name> ?-p
<relative_permittivity>? ?-m <relative_permeability>? ?-l <loss_tangent>? ?-c
<conductivity>?
-add: currently, it is only allowed to add a material. This option is required.
-type [conductor | dielectric]: specifies the material type. For conductor, only conductivity is needed.
For dielectric materials, relative permittivity, relative permeability, loss tangent and conductivity need to be
specified.
-name <material_name>: specifies the material name.
-p <relative_permittivity>: is required for dielectric material.
-m <relative_permeability>: applied to dielectric material. If not specified, the default value is 1.
-l <loss_tangent>: applied to dielectric material. If not specified, the default value is 0.
-c <conductivity>: is required for conductor material. For dielectric material, if not specified, the default
value is 0. The unit is S/mm.
Examples:
1. Add a new material “my_copper”.
setup cpa material -add -type conductor -name my_copper -c 59600
2. Add a new material “my_FR4”.
© 2017 Ansys Inc

RedHawk-CPA Application Notes 18.1.3 P a g e | 10
setup cpa material -add -type dielectric -name my_FR4 -p 4.7 -m 1 -l 0.018
–c 0
TCL command to specify temperature coefficients and reference temperature.

setup cpa material -name <all | material_name> [-rt1 <float> -rt2 <float> -
tref <t>]
-name material_name: specify the conductor material that it need the modeling to be applied.
-rt1 <float>: specifies temperature coefficient rt1. Default value of rt1 is zero.
-rt2 <float>: specifies temperature coefficient rt2. Default value of rt2 is zero.
-tref <t>: specifies reference temperature in degree Centigrade.
Setup Layer
setup cpa layer –name <layername> ?-type [dielectric | signal | power]?
?-thickness <value>? ?-cond_mat <material_name>? ?-diel_mat <material_name>?
-name <layername>: specifies an existing layer.
-type [dielectric | signal | power]: specifies/changes the layer type.
-thickness <value>: specifies the thickness of a layer. The unit is mm.
-cond_mat <material_name>: specifies the conducting material for the layer.
-diel_mat <material_name>: specifies the dielectric material for the layer.
Examples:
1. Modify the thickness of a dielectric layer, and specifies its type and material.
setup cpa layer -name Diel_1 -type dielectric -thickness 0.35
2. Specifies its material of a signal layer.
setup cpa layer -name TOP -type signal -cond_mat COPPER -diel_mat AIR
Setup Stackup
setup cpa layer [-add | -del] -name <layername> ?[-above | -below] -newname
<layername>?
[-add | -del]: to add or delete a layer from the stackup.
-name <layername>: specifies the layer name to be added from or deleted.
[-above | -below]: determines to add above or below the specified layer. This option is required for
adding a layer.
-newname <layername>: specifies the name for the added layer. This option is required for adding a
layer.
setup cpa layer -del ?-name <layername_list>?

-del: to delete layers from the stackup
Examples:
1. Add a layer above “TOP” layer.
setup cpa layer -add -name TOP -above -newname Diel_0
2. Delete layers “Die*” “DIE_AP” “T*” “BOTTOM”.
setup cpa layer -del -name Die* DIE_AP T* BOTTOM
Setup Solder Ball

setup cpa ball -d1 <value> -d2 <value> -dmax <value> -ht <value>
?-material [solder | gold | silver | copper | <material_name>]?
-d1 <value> -d2 <value> -dmax <value> -ht <value>: specifies the dimension of the solder ball for
BGA component. The unit is mm.
-material [solder | gold | silver | copper | <material_name>]: specifies the material of solder ball. It
can be the material in the default library or user defined material. If this option is not use, “solder” is used
by default.
Examples:
1. Specify the dimension and material of solder ball.
© 2017 Ansys Inc
setup cpa ball -d1 0.4 -d2 0.4 -dmax 0.5 -ht 0.5 -material solder
Setup Solder Bump

setup cpa bump -d1 <value> -d2 <value> -dmax <value> -ht <value>
?-material [solder | gold | silver | copper | <material_name>]? ?-component
[<component_name> | all]?
-d1 <value> -d2 <value> -dmax <value> -ht <value>: specifies the dimension of the solder bump for
die component. The unit is mm.
-material [solder | gold | silver | copper | <material_name>]: specifies the material of solder bump. It
can be the material in the default library or user defined material. If this option is not use, “gold” is used
by default.
-component [<component_name> | all]: specifies the component if multiple die components exist in
the design. “-component all” applied the dimension and material of solder ball to all die components.
Examples:
1. Specify the dimension and material of solder bump for “FCHIP”.
setup cpa bump -d1 0.08 -d2 0.08 -dmax 0.1 -ht 0.1 -material solder -
component FCHIP
Setup Bondwire
setup cpa bondwire -autowireends
With system-in-a-package (SiP) applications, the imported 2-D bond wire information does not specify the
die connections. The Auto Wire Ends function connects the wires to their proper die pins in three
dimensions.
Setup Bondwire Profile

setup cpa bwprofile -name <bwprofile_name> -diameter <value> -material
<material_name> -height <value>
-name <bwprofile_name>: specifies the name of bondwire profile
-diameter <value>: specifies diameter value. Default unit is mm. A data value with unit is allowed.
-material <material_name>: specifies conducting material for bondwire profile.
-height <value>: specifies height value.
Examples
© 2017 Ansys Inc

1. Change the diameter of bondwire profile BWProfile1 to 20um with GOLD material.
setup cpa bwprofile -name BWProfile1 -diameter 20um -material GOLD
setup cpa bwprofile -name BWProfile1 -diameter 0.02 -material GOLD
Setup External Environment

setup cpa env ? –h1 <h1_height>? ? –h2 <h2_height>? [?-ground <1|0>?] [?-
mdensity <value>?]
–h1 <h1_height>: specifies h1 height
–h2 <h2_height>: specifies h2 height
-ground <1|0>: specifies a ground plane or not;
-mdensity <value>: specifies the plane metal density value.
Setup General Configuration

The TCL syntax to set General configuration for extraction
setup cpa general -esd [1|0] -freq <value(MHz)> -cpu <number> -lossmodel
[1|2|3] -holes [auto|value(mm)]
-esd [1|0]: specify to extract a pure-resistance ESD model or not.
-freq <value(MHz)>: specifies extraction frequency in MHz. Default frequency = 100 MHz.
-cpu <number>: specifies cpu number. By default, all CPU is used.
-lossmodel [1|2|3]: specifies level of complexity in the loss model.
-holes [auto|value(mm)]: specifies auto-detect small holes; or set a hole diameter value in mm unit
Examples:
1. Specify to extract an ESD model
setup cpa general -esd 1
2. Specifies extraction frequency = 400 MHz, loss model Level2, auto-detect small holes to ignore during
extraction.
setup cpa general -esd 0 -freq 400 -lossmodel 2 -holes auto
3. Specifies extraction frequency = 400 MHz, loss model Level2, ignore holes smaller than 0.05mm
setup cpa general -esd 0 -freq 400 -lossmodel 2 -holes 0.05
Setup PLOC
setup cpa ploc [-auto | -manual] ?-component <componentname>? ?-ploc
<filename>? ?-scale <value>? ?-byname? ?-shiftx <value>? ?-shifty <value>? ?-
rot <value>? ?-flip [yes | no]? ?–tolerance <value>?
-auto | -manual: determines the ploc connection mode.
-component <componentname>: specifies the die component for ploc connection for multi-die
situation.
If the design has only one die component, this option can be omitted.
-ploc <filename>: chooses the .ploc file for connection. If not specifies, the ploc file specified by
© 2017 Ansys Inc

PAD_FILES in the GSR file will be used.

-scale <value>: defines the scale for ploc footprint. This option is required for manual mode, but
optional for auto mode, where two attempts with scale 0.9 and 1.0 will be made automatically.
-byname: performs the ploc connection by matching the ploc name and package pin name. This option
is only applicable to auto mode.
-shiftx <value>: specifies the shift in x-direction in micrometer. This option is required in manual mode.
-shifty <value>: specifies the shift in y-direction in micrometer. This option is required in manual mode.
-rot <value>: specifies the rotation of ploc footprint. This option is required in manual mode.
-flip [yes | no]: determines whether to flip the ploc footprint or not. This option is required in manual
mode.
-tolerance <value>: specifies the tolerance in micrometer. The die/package pin pair whose distance is
smaller than the specified tolerance will be connected.
Examples:
1. Perform automatic ploc connection using the given ploc file, scale and tolerance.
setup cpa ploc -auto -ploc ./chip.ploc -scale 0.9 –tolerance 2
2. Perform automatic ploc connection using ploc name and package pin name. Specify the component
for ploc connection.
setup cpa ploc -auto -component FCHIP -ploc ./chip.ploc -byname
3. Perform manual ploc connection.
setup cpa ploc -manual -ploc ./chip.ploc -scale 1.0 -shiftx 1500 -shifty -
2500 -rot 90 -flip yes -tolerance 25
TCL to Perform Dummy PLOC Connection. The syntax is

setup cpa ploc -auto -component <component_name> -dummyploc
-component <component_name>: specifies die component.
This TCL will create a dummy PLOC file for specified die component and auto connects between package
and PLOC with scale 1.
Setup Unconnected Die Domain

setup cpa ucplocnet –net <net1, net2...> ?-float? ? -volt <voltage_value>?
-net: specifies a net or nets list
-float: floating the ploc unconnected die domain nets
-volt: specifies voltage value of ideal voltage source.
setup cpa ucplocpin -pin <pin1, pin2, ...> ?-float? ?-volt <voltage_value>?
-pin: specifies unconnected PLOCs list
-float: floating the unconnected PLOC
-volt: specifies voltage value of ideal voltage source.
Setup VRM
setup cpa vrm ?-net <netname>? ?-volt <voltage_value>? ?-file <filename>?
-net <netname>: specifies the nets.
-volt <voltage_value>: assigns the voltage value. This option has to be used together with -net.
-file <filename>: specifies the file that contains the vrm information.
Examples:
1. Set the net VDD_15 to be 1.5V, and VSS to be 0V.
setup cpa vrm -net VDD_15 -volt 1.5
setup cpa vrm -net VSS -volt 0
2. Specify the VRM using a file.
setup cpa vrm -file vrm.info
where vrm.info contains:
VDD_15 1.5
VSS 0
© 2017 Ansys Inc

setup cpa vrm ?–gsr?

-gsr: specifies the VRM voltage to the values mentioned in the GSR VDD_NETS section.
setup cpa vrm ?-use_bgamodel [true|false]?

When BGA attaches a PCB model, after finishing part/circuit model node connection, the rest circuit
nodes can be specified VRM voltages with Use BGA Model option checked. This TCL command is to
check this option.
Note: the other options to specify VRM voltage to un-connected PCB nodes will be ready in next
version.
Setup Auto
setup cpa auto
This tcl command performs the automatic setup that:
1. Perform automatic ploc connection using the ploc file specified by PAD_FILES in GSR.
2. Select the P/G nets specified in GSR for extraction.
3. Setup VRM with the voltage specified in GSR.
Note: auto ploc connection does not work if there are multiple dies included.
Setup EM Limit
setup cpa layer -name <layer names> ?-em <float>?
-name <layer names>: specifies layer name list;
-em <float>: specifies EM limit(s) in format of floating number with unit A/Sq.m.
Examples
1. Set EM limit of 1000 A/sq.m to TOP and BOTTOM layers
setup cpa layer -name TOP BOTTOM -em 1000
2. Set EM limit of 500A/sq.m to VSS_C1 layer
setup cpa layer -name VSS_C1 -em 500
3. Set EM limit of 1000 A/sq.m and 500 A/sq.m to TOP and BOTTOM layers
setup cpa layer -name TOP BOTTOM -em 1000 500
Setup Thermal
Power Setup
setup cpa thermal -die <name>
?-ctm ?<file>? ?
?-power <value(W)>?
?-mhs <mhsfile>?
?-flip [true|false]? ?-axis [x|y]? ?-rot <value>?
-die name: specifies the die component name;
-ctm file: specifies CTM file. By default, the ./adsThermal.tar.gz under current RH run directory is used;
-power: specifies constant power;
-mhs mhsfile: specifies multi-heat source file. For this usage flow, user needs to specify die power
source coming from MHS then execute MHS edit command.
-flip true/false: tells engine whether applies power on bottom/top of the die.
-axis x/y: specifies flip along X-axis or along Y-axis when die power map faces down.
-rot value: specifies rotation angle in degrees.
Example
setup cpa thermal -die FCHIP -ctm -flip false -axis x -rot 90
Note 1: For CTM and multi-heat source flows, when power faces up, rotation and axis will be ignored. For
constant power flow, rotation and axis will be ignored no matter face up or down.
© 2017 Ansys Inc

Note 2: For multi-heat source flow, user needs to specify die power source coming from MHS then execute
MHS edit command.
TCL syntax to flip multi-heat map along X-axis or along Y-axis and/or rotate.
setup cpa thermal -die <name> -mhs -edit ?-flip [true|false]? ?-axis [x|y]? ?-
rot <value>?
-die name: specifies the die component name;
-mhs: to flag this tcl command is for MHS;
-edit: to flag this tcl command is for editing multi-heat source;
-flip: specifies to flip the multi-heat power map or not. If yes, then select to flip along X-axis or along Y-
axis.
-rot value: specifies rotation angle in degrees.
TSV Setup
setup cpa thermal -die <name> -tsv <file> ?-model <line | solid>? ?-diameter
<value>?
-die <name>: specifies die component name;
-tsv <file>: specifies tsv file;
-model <line | solid>: specifies tsv model type, line element or solid element (default);
-diameter <value>: specifies diameter.
Export a new CTM with power scales in regions

report cpa thermal -ctm ?<file>? -o <file> -region <LLX LLy URx URy>(um) ..
<LLX LLy URx URy>(um) -scale <float>.. <float>
This command exports a new CTM by specifying power scaling by regions through coordinates
-ctm <file>: specifies ctm file path. Default file path is ./adsThermal.tar.gz
-o <file>: specifies the new ctm file path;
-region <LLX LLy URx URy>(um): specifies block region coordinates in um;
-scale <float>: specifies power scaling factor.
Tip: when specifying multiple power scaling factors for multi-regions, the number of regions must match the
number of power scaling factors in the list.
Example
1. Cut off 4 power blocks and export the new ctm to a .tar.gz file.
report cpa thermal -ctm ./adsThermal.tar.gz -o ./reduced.tar.gz -region -
179.477 3827.94 2633.49 5307.9 2497.04 3743.98 5341.5 5160.96 -22.0345 -
55.6356 2129.68 4037.87 1835.79 -244.567 5331.01 3481.57 -scale 0 0 0 0
Convert MHS to CTM V0

report cpa thermal -ctmv0 -die <name> -i <pd file> -o <file>
?-flip <x|y>? ?-tempDependent <t1 t2 t3 t4 t5>?
This command convert a multi-heat source file into a T-aware CTM file.
-die name: specifies die component;
-i pd_file: specifies multi-heat source input file;
-o file: specifies CTM v0 file path to export.
-flip x | y: specifies flip along X-axis or along Y-axis;
-tempDependent: specifies temperatures;
© 2017 Ansys Inc

Material Editing
CTA provided four TCL commands for editing materials, to change material for a part; to create a material; to
add or modify material properties; to delete certain temperature. The usage details are described below.
setup cpa thermal -material ?-part <part_name>? ?-mat <material_name>?

This command changes material for a part.
-part <part_name>: specifies part name, marked in below picture. Part name with spaces is allowed.
-mat <material_name>: specifies material name, marked in below picture. Material name with spaces is
allowed.
Example
1. Assign material “Quantum QMI 509” to part “PWB Metal”
setup cpa thermal -material -part PWB Metal -mat Quantum QMI 509
setup cpa thermal -material -add -name <material_name> -category <EncapCoat |

External Heat Sink | External Heat Sink Pad | Joinbond | Laminate | MetalCC |
Package_Window | Semiconductor>
This command adds a material
-name <material_name>: specifies a new material. Material name with spaces is allowed.
-category <EncapCoat | External Heat Sink | External Heat Sink Pad | Joinbond | Laminate |
MetalCC | Package_Window | Semiconductor>: specifies material category. It should be one of
EncapCoat | External Heat Sink | External Heat Sink Pad | Joinbond | Laminate | MetalCC |
Package_Window | Semiconductor.
Tip: For the new created material, default temperature is 25 centigrade; default direction is xyz; default value
for k, density and cp is -1 respectively.
Example
1. Create new material “TEST 12” in category “External Heat Sink”, with default material property.
setup cpa thermal -material -add -name TEST 12 -category External Heat Sink
setup cpa thermal -material -name <material_name> ?-category <EncapCoat |

External Heat Sink | External Heat Sink Pad | Joinbond | Laminate | MetalCC |
Package_Window | Semiconductor>? ?-temperature <value>? ?-direction <xyz>? ?-k
<k_value>? ?-density <d_value>? ?-cp <cp_value>?
This command adds or modifies material properties for a material
-name <material_name>: specifies an existing material name; material name with spaces is allowed;
-category <EncapCoat | External Heat Sink | External Heat Sink Pad | Joinbond | Laminate |
MetalCC | Package_Window | Semiconductor>: specifies material category. It shall be one of
EncapCoat | External Heat Sink | External Heat Sink Pad | Joinbond | Laminate | MetalCC |
Package_Window | Semiconductor.
-temperature <value>(C): specifies temperature in centigrade C;
-direction <xyz>: default direction is “xyz”.
-k <k_value>: specifies “k” value; default -1 W/m-C.
-density <d_value>: specifies “density” value, default -1 g/cm^3.
-cp <cp_value>: specifies “cp” value, default -1 J/gm-C.
Here is the List of material categories for BGA type material.

Die (Semiconductor)
Die Attach/underfill/Solder/Bump (JoinBond)
© 2017 Ansys Inc
Substrate (Laminate)
Metal traces (MetalCC)
Molding compound (EncapCoat)
Mask (Laminate)
TSV (MetalCC)
RDL (MetalCC)
PWB (Laminate)
PWB Metal (MetalCC)
Example
1. Add temperature 50 C for material “TEST 12” with k = 0.2 W/m-C.
setup cpa thermal -material -name TEST 12 -temperature 50 -k 0.2
setup cpa thermal -material -name <material_name> ?-deltemperature <value>?

The syntax to delete material properties of certain temperature for a material
-name <material_name>: specifies an existing material name; material name with spaces is allowed;
-deltemperature <value>: specifies temperature to be deleted.
Example
1. Delete Temp = 50 C and its property for material “TEST 12”.
setup cpa thermal -material -name TEST 12 -deltemperature 50
Work Area
setup cpa thermal ?-pkgconfig -workarea <LLx LLy URx URy>(mm)?
-workarea <LLx LLy URx URy>: specifies coordinates of work area.
Boundary Setup
setup cpa thermal -boundary
?-temperature <value>?
?-airspeed <value>?
?-BC_T <Temperature(C) LLx LLy LLz URx URy URz(mm)>?
?-HTC <pkgTop pkgSide pcbTop pcbBottom>?
-temperature value: specifies ambient temperature (C);
-airspeed value: specifies air speed in unit of m/s.
-BC_T: specifies a fixed temperature for a volume starting from (LLX LLY LLZ) to (URx URy URz);
-HTC: specifies heat transfer coefficients (HTC) on Pkg Top, Pkg Side, PCB top and PCB bottom in
the unit of (W/C-m2)
Example
setup cpa thermal -boundary -temperature 25 -airspeed 1
Simulation Options Setup

setup cpa thermal -simulation
?-solver <direct | iterative>?
?-smeared [true|false]?
?-bumpmodel [default | line |solid]?
?-pkgmesh [off |<die name1, value1> <die name2, value2>…]?
?-chipmesh <value>?
?-pkgmeshing [off | all | layer_list]?
?-cavity <Bottom X1(mm) Y1(mm) Top1 X2(mm) Y2(mm) Top2> ?
© 2017 Ansys Inc

-solver: uses direct solver or iterative solver;

-smeared: specifies the smeared option on or off;
-bumpmodel: specifies the bump model, default model, line model or solid model;
-pkgmesh: specifies package mesh resolution for each die component. -pkgmesh off, to clear resolution
setup;
-chipmesh value: specifies Chip Mesh Resolution in um.
-pkgmeshing: specifies detailed meshing for package layers. -pkgmeshing off, to turn off detailed
meshing for all package layers. -pkgmeshing layer_list, to turn on detailed meshing for the specified
layer names.
-cavity: specifies cavity sizes following drawing chart in UI.
Save Modified
setup cpa save
This tcl command saves the imported package layout file and simulation setups into project directory
Perform DRC Check

perform cpa drc
This is a command to run DRC check for included nets at any time. PLOC connection is not needed.
Perform Channel Extraction

perform cpa extraction
This is a package extraction command that:
1. Save project files to <project_path>;
2. DRC check;
3. Generate package model and interface files that connects package model to RedHawk.
Perform CPM+CPA
perform cpa cpmcpa ?-i <CPM file>?
-i <CPM file>: specifies cpm file path. Default file path is adsRpt/CPM/PowerModel.sp
This command combines an existing CPM and CPA models to get combined spice CPM_CPA.sp and
benchmark spice for AC and transient analysis.
Perform Co-Sim Simulation

perform cpa cosim -static ?-padcurrent <user_defined_pad.current_file>?
-padcurrent <user_defined_pad.current_file>: specifies pad.current from RH static analysis.
This is a chip+pkg co-simulation command that:

1. Given channel extraction model by MODEL
2. Given pad.current from RedHawk static analysis.
3. Perform chip+pkg co-simulation.
Examples:
1. set pad.current to perform chip+pkg co-simulation.
perform cpa cosim -static ?-padcurrent ./run_dir/pad.current
Perform Thermal Simulation

perform cpa thermal
This is a thermal simulation command that:
1. Save project files to <project_path>;
2. DRC check;
© 2017 Ansys Inc

3. Generate package thermal profile.
HTML Report Generation

report cpa html ?-o <html_file>?
- o <html_file>: specifies the HTML file path for extraction report.
report cpa html -cosim ?-o <html_file>?

- o <html_file>: specifies the HTML file path for DC co-sim report.
report cpa thermal -html <html_file>

-html <html_file>: specifies the html file path for thermal report.
Post-Processing
EM Check for Current Density Map

report cpa emcheck ?[-o <emcheck_file>]? ?-i <tech_file>? ?-layer <layer1,
layer2, ...>? ? -limit <limit1, limit2, ...>?
-o <emcheck_file>: specifies EM check report file path. If no file is specified, by default RH CPA
exports the report to MODEL/cosim/<jobname>_EMCheck.txt;
-i <tech_file>: specifies the input .tech file. It is a must for EM check;
-layer <layer1, layer2, ...>: specifies the package metal layer list;
-limit <limit1, limit2, ...>: specifies the EM limit list. It shall be consistent with the number of layer list.
CPA conducts post-processing EM check to find out current density violations with user-customized EM
limits, for Current Density Map (A/Sq.m) result type and user option EM Violations checked.
Check EM Violations Set EM Limits
Check EM Violations. In the pop-up dialog, you can import a tech file which contains EM limits; or you can
modify the EM limit for each package layer.
Click Import, choose a .tech file which specifies EM limits. Here is an example file sample.tech
units {
length 1u
current 1m
}
metal top {
© 2017 Ansys Inc

EM 100
}
metal bottom {
EM 50
}
Format:
Units of current density = current / (length * length)
top and bottom are layer names, which are non case-senstive.
If you do not read .tech file, you can configure EM limits directly in the EM table through UI.
Click OK, to save the EM limits configuration.
Note: you can read a .tech file or modify EM limits any time by clicking Edit button. RH CPA will pop-up the
same dialog.
Uncheck EM Violations radio, the two sub-options EM Limits and EM Report will disappear.
After Clicking OK.
The color map changes from Current Density map to EM Violations map as below demo picture.
Current Density (A/Sq.m) EM Violations (%)
Click Export, by default RH CPA exports the EM report to MODEL/cosim/<jobname>_EMCheck.txt. You

can re-direct the report to another file and click Save.
© 2017 Ansys Inc

Export EM Report to A .txt File

Here is an example file <jobname>_EMCheck.txt
#Metal Layers
x(mm) y(mm) metal layer current density EM limit violation(%)
….
#Vias
x(mm) y(mm) start metal layer end metal layer current density EM limit
violation(%)
Neu2Ans
TCL Command to Export Ansys Model. The syntax is
report cpa thermal -ansysmodel ?-i <file>? ?-o <file>?
?-type [thermal | structural | coupled]?
-i file: specifies the .neu file path;
-o file: specifies the .ans file path;
-type: specifies application type, for thermal, structural, or coupled.
After thermal simulation, post-processing provides option Neu2Ans to convert finite element thermal model
to general purpose program, Ansys/M input commands in <jobname>.ans file.
For Thermal model, solid70 thermal elements will be used with appropriate thermal boundary condition. For
Structural model, solid185 structural elements will be used. For Coupled Thermal/ Structural model,
solid185 structural elements will be used.
Click Export Ansys Model button, in the pop-up dialog select Application Type and click OK to proceed the
conversion. Click to change the .neu or .ans file path.
© 2017 Ansys Inc

Convert Multi-Heat Source to T-aware CTM

TCL command to convert a multi-heat source file into a T-aware CTM file. The syntax is
report cpa thermal -ctmv0 ?-die <name>? ?-flip <x|y>? ?-tempDependent <t1 t2
t3 t4 t5>? -i <pd file> -o <file>
-die name: specifies die component; this option is optional;
-flip x | y: specifies flip along X-axis or along Y-axis; this option is optional.
-tempDependent: specifies temperatures; this option is optional;
-i pd_file: specifies multi-heat source input file;
-o file: specifies CTM v0 file path to export.
Example TCL Flow

import GSR demo.gsr
setup design
setup cpa net -name VDD_15 -type power -include 1 # include VDD_15 net
setup cpa net -name VSS -type ground -include 1 # include VSS net
setup cpa ploc -auto -ploc chip.ploc # perform ploc connection
setup cpa part -name FCHIP -pingroup perpin # setup perpin extraction
setup cpa vrm -net VDD_15 -volt 1.5 # set voltage for VDD_15
setup cpa vrm -net VSS -volt 0 # set voltage for VSS
perform cpa extraction # perform extraction
perform pwrcalc
perform extraction -power -ground
perform analysis -static
perform cpa cosim –static # perform co-sim simulation
User Interface
In order to view/edit package layout and perform extraction, you can start the integrated RH-CPA GUI in the
following step:
1. Define CPA_FILES keywords in GSR file.
2. Create a command file that contains:
import gsr <GSR_file>
setup design
3. Run RedHawk from GUI by executing the command file that created in step 2:
%redhawk -f <command_file>
(Note: Integrated RH-CPA cannot be launched in script mode with redhawk -b).
4. When setup design completes, click on “PKG” radio button to switch to RH-CPA GUI.
© 2017 Ansys Inc

Figure 1. Integrated RH-CPA GUI
Canvas Operation
Mouse Keyboard (Single Key Navigation Panel
mode enabled)
Zoom in/out Wheel scroll
Zoom Box Context menu->Zoom Box

Pan Context menu->Pan Arrow Keys
Fit All Context menu->Fit All F
Go Back One Level
In addition, you have those two options that can be accessed through canvas context menu:
 Filled / Unfilled – Selecting Filled displays solid shapes. Selecting Unfilled displays shape outlines.
 Colored by Layer/ Net – Colored by Layer displays all shapes on the same layer in one color.
Colored by Net displays all shapes on the same net in one color.
Configuration Buttons
Figure 2. Configuration buttons of RH-CPA
There are four configuration buttons used by RH-CPA:

 Edit Data: brings up the Layout Manager dialog, where you can view and edit nets, layer stackup,
components, parts, solder balls/bumps, bondwires, and vias. The layout data is organized in
spreadsheet format for conveniently searching, sorting and filtering any fields
© 2017 Ansys Inc

Tip 1: RH-CPA thermal simulation does not take net inclusion done through Layout Manager. By
default, all nets are going to be involved in thermal simulation.
 Setup
 Extraction Setup: brings up the extraction setup dialog that contains four tabs: PDN Channel
Setup, General, Environment, and Polygon Merge.
 Thermal Setup: brings up the thermal setup dialog that contains six tabs: PKG Config, Die,
Material, Boundary, Heat Sink and Simulation.
 Do Extraction
 Extraction: performs DRC check first. If any violation is found, a DRC report will be ready before
continuing to extraction. In the case of bondwire intersections reported, right click Bondwires
category and you see two GUI options Auto Fix and Delete. Auto Fix allows user to auto adjust
bondwire profile height for intersected bondwires. Delete enables user to delete all bondwire
intersections. You can choose either method. After this step, user needs to close the DRC Report
dialog and re-run extraction. Then user will see less bondwire intersections reported in the new
DRC report. This procedure is repeatable.
When extraction finishes, the package model and the annotated PLOC file are generated in
<project_path>/Extraction.
 DC Co-Sim: perform chip-pkg DC co-analysis after PKG extraction and RedHawk static run.
Channel extraction model and static pad.current are required for DC co-analysis. When co-
analysis finishes, four color maps of current through vias, voltage drop map, current density maps,
current density vector maps are generated in <project_path>/cosim.
 CPM + CPA: wrappers CPM model and CPA model into a combined spice file
CPM_CPA/CPM_CPA.sp. In this file, the BGA ports, ports on channel components and probe points
from CPA model are the external nodes. CPA also copies PowerModel.sp, <jobname>.sp, to
CPM_CPA folder. Meanwhile, there are two test bench files testbench_AC_xxx.sp and
testbench_Trans.sp in SPICE format generated in the same location. One is for AC
(impedance) analysis; another one is for transient simulation.
 Thermal-Sim: performs electrical DRC check first. If any violation is found, a DRC report will be
ready before continuing to extraction.
Thermal simulation user can ignore the electrical DRC reports to continue thermal simulation.
When simulation finishes, three color maps of nodal temperature, heat flux and power density are
generated in <project_path>/thermal.
 Save Modified: save the imported package layout file and simulation setups into project directory.
Tip 2: The net selection, geometry editing or simulation setups does not write back to package file.
Result Buttons
Figure 3. Result buttons of RH-CPA
After package extraction, the PinR, PinL, LoopL result buttons can be used to quickly view the extraction
results graphically:
 PinR: per-pin resistance of die component.
 PinL: per-pin partial inductance of die component.
 LoopL: per-pin loop inductance of die component.
 PKG: return to normal package view.
© 2017 Ansys Inc

After DC co-analysis, the ViaC, VolM, CurDM, CurDV result buttons can be used to quickly view the co-
analysis results graphically.
 ViaC: current through vias.
 VolM: voltage map, which shows static IR, drop.
 CurDM: current density map.
 CurDV: current density vector map.
After thermal simulation, the Temp, HeatF, PwrD result buttons can be used to quickly view the thermal
results graphically:
 Temp: temperature contour per metal layer.
 HeatF: heat flux vector plots
 PwrD: power density contour in each layer of die.
Query Buttons
Figure 4. Query buttons of RH-CPA
 Query: RH-CPA brings up PKG/Die Pad Info report window where you can view the ploc connected
pkg pin properties, including pkg net, pkg pin (x, y) coordinates, pin group, pin resistance, pin partial
inductance, pin loop inductance, pin dc voltage, current through pin, voltage drop. Right click on pin and
select Zoom to this pin through context menu, layout view highlights the selected pin on layout view.
 Impedance Analysis: this button is enabled after pkg extraction.
 Impedance Analysis: after pkg extraction, RH-CPA allows user to generate ports based on
extracted spice model to execute impedance analysis for pkg only.
 SUtility: after impedance analysis, SUtility tool is launched to display the S parameter. Please refer
to Appendix A for SUtility usage.
 Report
 Run DRC: perform DRC individually at any time without PLOC connection. When the DRC report is
up, you can interact with layout manager and layout view.
 View DRC: view DRC report at any time. When the DRC report is up, you can interact with layout
manager and layout view.
 Extraction Report: after channel extraction, RH-CPA generates a user customized html report. It
summarizes design information, DRC Reports, extraction setup and results. You can click on the
links in the table of contents to directly access the section of interest.
‘Go to top’ hyperLink in the bottom right corner of HTML report, enables user go back to top of
HTML anytime.
RH-CPA does not auto launch web browser, user need to start the web browser manually and load
html file.
Default html file path is <MODEL>/report/report.html.
 DC Co-Sim Report: after co-analysis, RH-CPA generates a user customized html report. The
report summarizes the design information, DRC Reports, extraction setup and co-analysis DC
results.
‘Go to top’ hyperLink in the bottom right corner of HTML report, enables user go back to top of
HTML anytime.
 Thermal Report: after thermal simulation, RH-CTA allows you to generate a customized html
report. The report summaries the design information, simulation setup and thermal results.
User Setup
For electrical analysis, you can setup PDN channel through Setup->Extraction Setup to extract a spice
model for RedHawk DC analysis then perform a chip-package co-analysis.
For thermal users, you can interface with realistic temperature-dependent layer-aware power map on chips
seamlessly generated from RedHawk for thermal modeling and analysis of packages or SIPs on PCB.
Moreover, through Setup->Thermal Setup UI, you can use Thermal BC of package from Icepak for system-
© 2017 Ansys Inc

aware chip-package thermal co-analysis. User can also export a simplified power density map based on
CTM.
Extraction Setup for Electrical Users
PDN Channel Setup

To start setting up PDN channel for electrical extraction, click Setup->Extraction Setup. The PDN Channel
Setup dialog is shown in the first tab of the pop-up window. The selected nets and components are
displayed in the dialog, which consists of three parts.
 Die: specifies the component that connects to the PLOC file. Once connected, the generated CPA
model has spice nodes on the die component that hooks up to RedHawk automatically. Multiply die
components are allowed, however, only one component can connect to PLOC.
 Channel: consists of components other than Die and BGA, such as decaps. Click on Setup Part to
specify a RLC model or a generic spice model to the selected component. If it is desired to setup a port
for a component instead of absorbing its parasitic into channel model, choose YES for Setup Port.
 VRM: specifies the supply voltage for selected nets on BGA component. Multiply supplies are allowed,
but they all must have the same Negative net.
 Unconnected Die Domain: By default, for die PLOC that un-connects to package pin, CPA
connects it to ideal voltage source. This option allows user to float un-connected PLOC, or to
connect it to ideal voltage source.
After ploc connection, unconnected PLOCs show in the left table of Footprint
Connection->Die/PKG tab. These PLOC names transfer back to “Unconnected Die Domain”
section in Model Extraction Setup dialog, so user can assign float, or DC voltage source. Default
is to float the unconnected .PLOC.
 Use BGA Model: When BGA attaches a spice model, after finishing part/circuit model node
connection, the rest circuit nodes can be specified VRM voltages with this option checked.
By default Die component shows in source Die section; BGA component shows in sink VRM section; and
other included components show in Channel section. CPA also provides up and down arrows
to move components between various sections.
© 2017 Ansys Inc

Figure 5. PDN Channel Setup
Automatic Setup
To minimize user’s GUI operations, automatic channel setup is performed when importing a package layout
for the first time. The automation does the following:
 Load PLOC file specified by PAD_FILES in GSR file.
 Perform automatic PLOC connection for die component.
 Group component pins based on the grouping information in PLOC file (if available).
 Select connected nets for channel modeling.
 Specify supply voltage in VRM from the VDD_NETS section of GSR file.
Launching the channel setup dialog (by clicking Extraction Setup) will interrupt the automation process,
which is running in the background. In such situation, user has the option to proceed to manual setup or wait
until the automation finishes.
Automatic setup will not overwrite the saved settings of the existing projects.
Die Setup
Select the die component. If user has no PLOC, click on PLOC->Dummy Connect to generate a dummy
PLOC, save it to a file and enter Footprint Connection dialog. If user has PLOC and the connection status
is empty, click on PLOC->Connect to choose the PLOC file and enter Footprint Connection dialog. If the
connection status is Connected, user may click on PLOC->Edit to view and edit the connection, or click on
PLOC->Disconnect to disconnect connection.
© 2017 Ansys Inc

Figure 6. PLOC Connection
Footprint
Display Area
Control
Panel
Pin List
Figure 7. Footprint Connection dialog
The Footprint Connection dialog consist of three parts:

 Footprint Display Area: displays package pins of the die component (blue box) and die pins from the
PLOC file (red box). A unique color is assigned for each PG net before establishing a connection. When
stopping the mouse on a pin, the pin name and net name are display in a tooltip text box. You can single
click to select a pin, or hold down Ctrl button for multi-selection. Switching Mouse Operation from Probing to
Shift, you can click and drag the die pins onto package pins.
 Pin Lists: consist of two tabs, Die/Pkg and Connection. In the first tab, die pins (left side) and package
© 2017 Ansys Inc

pins (right side) are listed in spreadsheets, which allow quickly sorting and filtering pins with respect to pin
names and net names. The selected pins on canvas are highlighted in the pins list, and similarly, the
selected pins in the list are highlighted on the canvas.
The connected pin pairs are 1) highlighted in solid blue on the footprint canvas; 2) added to Connection tab;
and 3) removed from Die/Pkg pin list.
 Control Panel: consists of the following area
 View Operation: You can Pan, Zoom and Fit all on the canvas.
 Geometric Operation: Specifies Scaling, Shift, Rotation and Flip for die pins.
 Automatic Connection:
 Net Connection: sets connection rules. User can determine whether to include signal nets for
PLOC connection, configures connection by net name.
 Net Connection Controls: Check or Uncheck UI option Exclude signal nets, to exclude
or include signals into mapping.
 Net Connection: Configures mapping by net name. Select a net from PLOC file, and
select a package net, click Connect->Selected Nets, the net pair displays in Net
Mapping table. You can also click Connect->Nets with same name, the net pairs with
identical names auto show up in Net Mapping table.
 Fully Automatic: attempts to match two sets of pins based on pin locations and user defined
scaling factor. Under certain conditions (e.g. the pattern of pins is symmetric, the net
connection rules), the automatic algorithm may find more than one mappings, all of which are
listed in the drop list under Fully Automatic button. Although, the first mapping is most likely
the correct one, it is recommended to go through the Connection tab for violations.
 Connect by Pin Overlay: if Fully Automatic does not find a desired match, you can manually
adjust the geometric setting or move the die pins by clicking and dragging any die pin (after
switching Mouse Operation from Probing to Shift). Once the die pins overlay with package
pins, click Connect by Pin Overlay to connect pin pairs within the user defined Tolerance.
 Connect by Selected Pin Pairs: attempts to complete the connection of all pins based on
selected pin pairs. You can add a pin pair by selecting one die pin and one package pin on the
canvas, and clicking Connect Sel. Pins button. It is recommended to add 3 pin pairs and
select them all in Connection tab to perform this automatic connection.
 Connect by Pin Name: attempts to complete the connection by same pin name in .ploc file
and in package.
 Manual Connection:
 Connect Sel. Pins: connects selected die pin and package pin. The pins can be selected on
canvas or in the pin lists.
 Connect Near Pins: is used for connecting remaining pins after automatic and manual
connection. It connects the unconnected die pin to the nearest package pin that belongs to be
same net. This option is not for making initial connection.
 Mapping Results: lists the net mapping information between die and package based on the pins
mapping in a pop-up dialog. It is recommended to review net mapping results after automatic or
manual connection for net violations. For example, as shown in Fig 8, there is a VSS pin on die
connected to a signal pin on package. You can reject the incorrect net mapping by clicking Forbid
Nets Mapping, which disconnects the pins belong to associated nets.
User can remove a net from Forbidden Net Mapping list, so can still perform PLOC connection for
this net.
To view the PLOC connection summary, user can check Connection Info page. It summarizes
PLOC connection report in three sections, Connection Statistics, Connected Nets and
Unconnected Nets.
➢ In Connection Statistics section, it summarizes the number of connected PLOCs versus total
number of input PLOCs; the number of connected package pins versus total number of
package pins, for the whole package design.
➢ In Connected Nets section, one die domain net might connect to several package nets. So for
each pair of die domain net and PLOC connected package net, it lists the number of connected
PLOCs versus total number of PLOCs for die domain net; also the number of connected
package pins versus total number of package pins for the package net.
➢ In Unconnected Nets section, it lists all the unconnected die domain net and unconnected
package net individually.
© 2017 Ansys Inc

 Mouse Operation:
 Probing: when in probing mode, single click on a pin to select it on canvas and in pin lists.
Hold down Ctrl button for multi-selection.
 Shift: after switching to shift mode, click and drag any die pins will shift the die footprint.
 Attributes: allows users to change the size and color of displayed pins.
Figure 8. Mapping Results dialog
After the completion of PLOC connection, click on Pin Group to specify the pin grouping for die component.
If the PLOC file already contains the annotation column, it will be loaded into the pin grouping dialog;
otherwise, per-pin grouping will be used by default. User can specify pin grouping in the following ways:
 Lump all pins: Select one net in the Net Selection section, and do not select any pins in the Pin
Group section, then click Group. All pins of the selected net will be lumped together.
 By Selection: Select pins in the Pin Group section, or draw a box on canvas to select pins graphically,
then click Group. All selected pins will be lumped into one group.
 By Grid: You can specify the number to partition the die component into n by m grid. The pins covered
by each partition are lumped into one group. The horizontal and vertical grid lines can be moved by
“click and drag” them on canvas. The grid lines can also be added or removed through the context menu
when right click on canvas.
 By “Group Each Pin”: Assign a unique group to each pin.
For pin selection, you can Ctrl-click to select multiply pins, or click on the first pin and then Shift-click on the
last pin to select them all. Select a group in the Pin Group section and click Ungroup to clear the group. Any
ungrouped pins are treated as individual groups.
© 2017 Ansys Inc

Figure 9. Pin Grouping dialog
Channel Setup
All included components, which do not exist in Die and VRM section, are listed here.
Part Model column shows whether a Spice model is specified to the component. Setup Port is an option to
create a port for the associated component in the channel model; if selected No, the component model will
be absorbed in the channel model and no port will be created for the component. Note that, if the component
model contains a capacitor, it is required to choose Yes for this option.
The imported layout model may include pin connections to components, but not the components themselves.
When simulated, these connections would appear as open circuits. For better results, you can define and
connect a model of these components and include them in the simulation. Select a component and click
Setup part to jump to the part manager dialog to specify a circuit model or perform pin grouping for this
component. Click Edit in the Circuit Model pull-down menu to open Part Circuit Model Library dialog,
where you can create the circuit model of the following types:
 RLC: Start by typing a name for the new part, for example decap_1, in the text box next to Name. Next,
click Create and select RLC Part from the pull-down menu. decap_1 appears as an RLC type part in
the part tree. Click decap_1 in the tree to select it, checkmark the properties that you wish to define, for
example the capacitance C, and type a value. Type names for Pin1 and Pin2 to identify the pins in the
sample diagram or accept the default names that appear.
 VRM: First Create a VRM Model named VRM_1. Click Add Pin, a pin appears in the Pin list with a
default name. To rename the pin, click the name and type a new name. To specify the voltage, click the
default Voltage value and type a new value. Repeat for as many pins as needed.
 Spice: First Create Spice Model named decap_2. Then, type the SPICE model in the right-hand-side
text boxes. List only the sub-circuit nodes in the upper text box. Add the model body in the lower text
box. The example shows a capacitor model with two pins. To rename a part, select it in the tree, type a
new name in the text box next to Name, and click Rename. To remove a part, select it in the tree, and
click Delete.
 Import Spice: Use this option to import a Spice netlist.
© 2017 Ansys Inc

Figure 10. Steps to assign the circuit model to components
Figure 11. Create a VRM model Figure 12. Create a Spice model
Supply Voltage
VRM Setup
The selected solder ball type component will display in VRM section by default.
Only selected nets in the VRM component will be listed in this section. CPA will select a net, which has the
most pin number to be the Negative net by default highlighted in Green. Select From GSR, the supply
voltage between positive and negative net is set automatically based on the “VDD Net Section” in GSR file.
You can set the voltage manually. Select nets from the list, specify desired voltage in Voltage box, and click
Apply->Voltage.
You can assign another ground net as negative net. Select the interest net, click Apply->Reference Net, it
will highlight in Green in VRM section.
Unconnected Die Domain

For the die PLOC that unconnected to package pins, through this GUI configuration, CPA enables user to connect
it to ideal voltage source or float it. It depends on the real situation for the voltage source from package side.
© 2017 Ansys Inc

Simulation Options
After having completed all the other setups described earlier, you are now ready to set conditions for the
analysis. Click Extraction Setup button to bring up setup dialog, and use the General, Environment, and
Polygon Merge tabs to set the extraction conditions.
General
Click the General tab to display the general extraction parameters. Review the following parameter
descriptions and edit them to fit your design requirements:
 Extraction Type: Uses CPA extraction solver. Non editable.
 Maximum CPU: Number of CPU cores to use. Using all available cores produces best speed
performance. Default: 8.
 Temp Work Folder: The temporary work folder. The default is given by MODEL keyword.
 Improved Loss Model: To measure metal loss in P/G nets with greater accuracy at low frequency,
typically in the kHz range, you can apply additional levels of complexity in the loss model. We
recommend using Level1 because the higher-order loss models substantially increase run time. For
signal simulations that require higher accuracy, Level2 should suffice. To change the level, click the
selection box next to Improved loss model and select a level.
 Ignore Small Holes: P/G metal often contains small hole cuts, without other objects inside them, that
the simulation can safely ignore. The simulator, which runs faster if it ignores such small holes, can
auto-detect these holes. Alternatively, you can set a hole diameter size below which the simulator
should ignore the hole. To change the hole diameter size, select the radio button next to Diameter
smaller than, click in the text box, and type a new value.
 ESD_Model: Traditional CPA extractions extracted RLGC parameters. But for ESD applications, for
Totem and other tools, we only need resistance network. Model Extraction Setup->General
tab->ESD_Model option does that. When this option is checked, The CPA spice model has only
resistors; color maps show only resistance.
 Extraction Frequency (MHz): editable option for accurate extraction of frequency dependent loop
inductance.
Environment
In a real system, packages mount onto a PCB and PCB metal plates can affect net impedances in the
package. If the PCB artwork is unavailable, you can use the Environment tab to model the package/PCB
external environment. Adding PCB metal plates and the dielectric insulation improves the model accuracy.
Click the Environment tab to display the available parameters. Edit them to fit your design requirements.
Clicking the box next to Metal Plane #1 or Metal Plane #2 adds a plane to the model. Clicking a box again
deselects it.
By default, RH CPA dis-selects metal plane. Select Ground, CPA adds a 5um thickness metal plane over
DIE component. The ground plane shorts to reference net. This configuration affects the inductance and
capacitance of the package nets.
By default, Metal Density is set to 100%. The metal density is editable; it affects the resistance of package
nets.
Note: If there is Die component on top layer, then user can only select Metal Plane #2. If there is a Die
component on bottom layer, then only user can select Metal Plane #1.
Polygon Merge
RH-CPA performs a polygon merge before the model extraction. Click the Polygon Merge tab to display the
available parameters:
 Circle Discretization: Number of polygon vertices used to approximate a circle. Default: 12.
 Merge Tolerance: Gap below which the polygon merge joins two nearby shapes into one. Default: 10-9
mm.
 Enable DRC: Sets the polygon merge to perform design rule checking (the default).
© 2017 Ansys Inc

 Invalid Geom Autofix: If enabled, attempts to correct certain error types found by the DRC check:
 SELF-TOUCH: Polygon touching itself
 SELF-INTERSECT: Self-crossing polygon edge
 TOUCH: Two polygons in the same net touching each other
 Pin Connectivity: Checks for unconnected net segments (the default).
 Nets Across Components: If enabled, merges net connecting to a component with component net.
CPM + CPA Modeling

This function is enabled only when there is an existing CPA model. Clicking it, CPA launches CPM+CPA
Model Generation dialog.
• Use Existing CPM: assume you have an existing CPM model. You can check this option, specify CPM
file and click Validate for syntax check.
For a valid CPM model, CPA pops up message Imported CPM file is valid.
For a bad CPM model, CPA pops up message Below imported CPM file does not match with current
CPA model. xxxxx
• Generate CPM:
 Specify CPM Options: CPA lists several common options for generating CPM model. You can
take advantage of these options. For the other options, you can check By Tcl command radio box.
 By TCL command: For user who are familiar with different command options in CPM model
generation, you can manually input all the options in the text box.
• Generate: Click Generate. CPA creates CPM_CPA folder, wrappers CPM model and CPA model into a
spice file CPM_CPA.sp. In this file, the BGA ports, ports on channel components and dynamic probes
from CPA model are the external nodes. CPA also copies PowerModel.sp, <jobname>.sp, to
CPM_CPA folder. Meanwhile, there are two test bench files testbench_AC_xxx.sp and
testbench_Trans.sp in SPICE format generated in the same location. One is for AC (impedance)
analysis; another one is for transient simulation.
© 2017 Ansys Inc

Below picture lists CPM+CPA Model Generation Flow
Thermal Setup for Thermal Users

For chip-package co-analysis, RH-CTA imports the Chip Thermal Model (CTM) generated by
RedHawk/Totem. RH-CTA automatically aligns the CTM temperature-dependent power maps to the
associated chips in package. Alternatively, RH-CTA also lets users specify power distribution or uniform
power manually. Applying the finite-element method (FEM), CTA discretizes the 3-D physical model, solves
thermal diffusion equations to generate temperature profile.
To start setting up for thermal simulation, click Setup->Thermal Setup. The pop-up window has six tabs
where you can set up PKG Config, assign CTM to Die or deploy constant power or multiple heat, cast
external conditions, enable heat sink and setup simulation options for thermal simulation.
Figure 13. RH-CPA thermal co-analysis flow
© 2017 Ansys Inc

PKG Config
By default, RH-CTA treats all package designs as BGA PKG. Its Die Attach height is non-editable, same as
bump height. For Lead Frame PKG CTA uses 0.025mm as default die attach height, user can modify this
height to a proper size.
Figure 14. PKG Config dialog
Molding
If a package design contains a Molding component, its coordinates and height properties show in Molding
section for view. User need go to Layout Manager->Part manager or Layout Manager->Comp manager
to modify its coordinate or height value.
Work Area
The work area defined in CAD file is sometimes not exactly the same as the sizes of a BGA package. We
provide this UI option so that, if needed, users can adjust for the correct BGA package sizes. This option is
for BGA PKG only.
PoP
This section is to specify in PoP package which die sits on top of another die.
Die
User specifies power and configures TSV for each die in this tab.
For each die, RH-CPA can assign any one of below three power types:
 Input a constant power behind Constant Power->Uniform Power text box. By default, a 1watt power is
used for all dies.
 Distributed heat through Multi-Heat Source Editor. Import an existing power map in the format
of .txt, pd.out or manually draw a power map here. Only if Temperature Dependent is checked
and Save T-aware CTM is checked, there will be a .ctm file saved for future usage.
 CTM, a temperature-dependent power library from RedHawk or Toteam.
By default, our tool reads .PLOC path from .GSR and shows it in CTM Mapping section, after setup design.
© 2017 Ansys Inc

OD Trench File is an option for the block power with “deep trench”. It is to consider more details of BJT (Bi-
Polar FET) which has impact to delta T inside the device. Block powers are commonly not covered by CTM
generation. The purpose is to enhance the final solution in CTM flow.
Note, at this moment, the OD Trench File option is to work with the CTM flow, for 1-die case only.

Figure 15. Die tab
Multi-Heat Source MHS
Check Multi-Heat Source radio, click RH-CPA brings up Multi-Heat Source Editor dialog with color
bar on bottom left. There are four ways to define or import non-CTM power map on a chip.
Figure 16. Multi-Heat Source Editor dialog
 Manual Input (w): Moving mouse inside the rectangle power map area, pressing the left button to draw
a rectangle box, its coordinates LLx, LLy, URx, URy auto display in the right table. Next you input power
© 2017 Ansys Inc

onto this rectangle block. You can repeat this operation till you are satisfied with the distributed heat.
Select one block, right click and choose Delete from Context menu, you can delete that one.
Right click anywhere inside the table, you can manually append one block by choosing Add from
context menu..
There are three map edit buttons, Flip X/Y, R+, R-. Use the combination of R+/R- and Flip for flipping
along Y axis or other desired condition. Only 90 degree increment in R+/R- allowed.
 Flip: flip the power map along the X-axis or Y-axis;
 R+: rotate the power map clockwise. The rotation angle displays next to R+ button.
 R-: rotate the power map counter-clockwise. The rotation angle displays next to R- button.
 Import CTA Block-based Power Map (mW)
After manually drawing power blocks in Multi-Heat Source Editor dialog and power assignment, you can
Export the power map to a block-based power file .block. Later on import this drawing power map to
another similar package design to re-use the power map.
Here is an example file test.block

#llx(mm) lly(mm) urx(mm) ury(mm) power(mw)
0.500000 0.500000 1.500000 9.500000 100.000000
8.500000 0.500000 9.500000 9.500000 100.000000
2.000000 8.500000 8.000000 9.500000 100.000000
In .block file, each line needs to follow the same syntax: block coordinates (mm) in lower left; block
coordinates (mm) in upper right and block power (mW).
 Import RedHawk/Totem Power map (w)
Figure 17. Import power map
Click Import Power Map, choose a pd.out file. pd.out is a power density map dumped from
RedHawk, it has a list of power blocks.
Here is an example file pd.out
1 -6.03 0 2172.76 2179.12
2 900 30 30
3 -6.03 0 66.5963 72.6373 0
4 66.5963 0 139.223 72.6373 0
5 139.223 0 211.849 72.6373 0
6 211.849 0 284.475 72.6373 0
7 284.475 0 357.102 72.6373 0
8 357.102 0 429.728 72.6373 0
9 429.728 0 502.354 72.6373 0
10 502.354 0 574.981 72.6373 0
….
100 502.354 217.912 574.981 290.549 1.33E-06
101 574.981 217.912 647.607 290.549 1.61E-06
102 647.607 217.912 720.233 290.549 1.61E-06
103 720.233 217.912 792.86 290.549 1.61E-06
104 792.86 217.912 865.486 290.549 8.44E-07
© 2017 Ansys Inc

105 865.486 217.912 938.112 290.549 0

Format: The first line is LL and UR coordinates in chip. The second line is the power cell numbers. The
lines below are the LL and UR coordinates (um) of power cells and cell power in Watts.
 Import MxN power cells (mW)
Click Import Power Map, choose the spreadsheet power map Excel_mhs.txt. Here is an example
file Excel_mhs.txt.
Figure 18. Example sample file Excel_mhs.txt
Enable Temperature Dependent, a power map with an extra temperature scale factor shows in the bottom
right table. While Temperature Dependent is checked and Save T-aware CTM is checked, you can export
a .ctm file to MODEL/ctm_files/<die_name>_T-aware.ctm. This is a non-layer aware ctm.
The exported ctm file can import back to integrated thermal by two procedures: through Die tab->CTM, or by
typing the file path in text box below Enable T-aware CTM option.
Enable T-aware CTM option is optional. It is by default auto selected after clicking Save T-aware CTM
button. Checking this option, user could select a .ctm as power for thermal simulation. Otherwise, the multi-
heat source would be used for thermal simulation.
CTM Explorer
Through CTM Viewer, you can review CTM power map; query instances in Tile, update CTM and pack as a
new CTM file.
© 2017 Ansys Inc

Figure 19. Steps to launch CTM Viewer
Check CTM radio, click on to choose a CTM file. RH-CPA supports three types of ctm format, .tar.gz,
.tar, .ctm. Open CTM file, click CTM Viewer and bring up CTM Viewer dialog (Figure 19 and Figure 20).
Figure 20. CTM Viewer dialog
Select a dot in viewer area, check Probe Power check box and RH-CPA pop up T-P Curve to show
temperature/power curves on the selected dot.
© 2017 Ansys Inc

Instance or OD file is used to identify the names of devices at hot spots, they are dumped from RedHawk or
Totem respectively.
Check Show Inst/OD checkbox, click to open an instance or OD file. After Inst/OD File is found, mouse
hovering on a location RH-CPA will show the instance name on screen.
Check Append Block checkbox, click to open a txt format power block file. Next user can Export a
new CTM file, which replaces the block coordinates in existing CTM file with this new one.
PD (Power Density) map is for use by Icepak. Icepak cannot take complex power map like CTM directly.
When the CTM-equivalent PD map is exported, the total number of ‘heating objects’ or tiles in CTM will be
reduced to the user-specified number, greater than 100 and less than 1000. For example, if 500 is specified,
there will be about 400 heating objects generated in the CTM-equivalent power map for Icepak.
Scaling of CTM allows user to perform block power editing to an existing CTM and export the modified CTM
to a new file.
Check Scaling of CTM option. While Select mode is on, draw a rectangle box to select a block on the CTM
map. The block power and block coordinates would auto show in the middle table. You can modify the scale
value, for example, to be zero, as a result to remove the specified block power.
Hover mouse on the middle table, right click and select Add from context menu, you can manually input the
block coordinates LLx, LLy, URx, URy. The block power is non-editable and calculated by our program. The
scale value is editable.
Select a block line in the table, right click and select Delete from context menu, you can remove the block from
table.
TSV Setup for 3D-IC

In Thermal Setup->Die tab, click TSV Setup in the bottom to launch TSV Setup dialog to setup for the die
with TSVs embedded.
TSVs can be modeled as Solid Elements (default) or Line Elements. If Solid Element is selected, the
individual TSV will be modeled with a square column with the area equivalent to the diameter specified. User
can use Line Elements for efficiency when TSV counts are extremely large, e.g., 10000 in one 3D IC.
TSV File is a file with tsv extension. Its file contents are listed below:
SI_INTERPOSER ----------------DIE name
92 ----------------TSV count below
0.060000 ----------------default TSV diameter (mm)
-1.950000 -2.450000 0.060000 ----------------(x, y) and diameter of individual TSV in mm
-1.950000 -2.250000 0.060000 ----------------(x, y) are of 3D IC package coordinates.
-2.450000 -1.950000 0.060000
-2.250000 -1.950000 0.060000
….
Click View and Edit TSV File button, open a tsv file and TSV Viewer dialog pops up. From this window,
user can edit coordinates (x, y) and diameter for each existing tsv, double click a point at the display area to
auto create a tsv, or click +/- to add/delete a tsv. Its usage is illustrated in following paragraph:
Die Name
It lists all the die components, where you can specify a die to work on.
Set
Default tsv diameter is 0.06mm. User can input a different value and click Set to apply it to all tsvs.
© 2017 Ansys Inc

+/-
Click +, CTA auto adds a blank line to the end of table. Select a line, click - to delete it.
Export
When done editing, click Export to dump the tsv table to a new file with tsv extension.
Set TSV
When this button is enabled, e.g., after Export, click Set TSV to return to the TSV Setup dialog using the
new tsv file.
Click to specify
TSV file path
Click to import tsv file

and view its pattern
© 2017 Ansys Inc

Material
Figure 21. Thermal material setup dialog
Material Library linked to Layout manager applies to electrical analysis only. Thermal simulation deploys
Thermal Setup->Material tab to view or edit material properties that apply to thermal co-analysis.
Boundary
User configures Ambient Temperature, heat dissipation to air, Thermal BCs, prescribed temperature through
Thermal Setup->Boundary tab.
Default Ambient Temperature is 20C. It sets heat sink temperature on board or on package top.
CTA supports any one of below three thermal BCs:
 Air Speed: Typical speeds are 0, 1, 2, 3 and 4 m/s. Default to 0 m/s for still air.
 User Defined HTC (W/C-m2): This is useful when using a top cooling plate to represent a passive heat
sink. For passive heat sink, usually the heat resistance (R) to ambient temperature is in specification for
different air speeds. The equivalent HTC on a cooling plate with area A could be estimated as 1/(R*A).
 Import Icepak Thermal BC File: Thermal BC of package from system level CFD analysis (Icepak) can
be extracted (in binary form) and used for system-aware chip-package thermal analysis.
Another optional option is, user can Add/Delete a prescribed temperatures (C) in certain volume (mm^3).
This provide user flexibility to apply fixed temperature on the analysis model. For example, if one of the
board edge is attached to a structure with fixed temperature, user could define a "volume" enclosing the
board edge with the fixed temperature. You need to know the volume in the analysis model through layer
stackup, with bottom of PWB being Z=0 mm.
© 2017 Ansys Inc

Figure 22. Set Conditions for thermal analysis
Heat Sink
To reduce temperature on chip, a heat spreader can be placed on top of the chip to spread the heat to a
larger area on package top. The heat spreader can be attached to flip chip directly or cover the exposed top
of a molded wire-bond chip. On top of the package, with or w/o heat spreader, to further reduce the chip
temperature an external heat sink with fins or/and fan can be attached. In thermal modeling of the external
heat sink, an equivalent cooling plate of the same sizes of the base is commonly used for the same cooling
effect using 1/(RxA) as HTC. Here R in C/W is measured or simulated thermal resistance of the heat sink
and A in mm^2 is the top exposed area of the cooling plate. Figure 23 is the GUI parameters available to
describe heat spreader and the heat sink shown in Figure 24.
© 2017 Ansys Inc

Figure 23. Heat Sink dialog
Figure 24. Heat Sink Illustration
© 2017 Ansys Inc

Simulation
Simulation tab provides different simulation options for BGA PKG and Lead Frame PKG designs.
Simulation options for BGA PKG

For BGA PKG, you can configure Simulation options through dialog in Figure 25.
Depending on memory capacity in user machines, user can use direct solver or iterative solver by changing
Thermal Setup->Simulation->Solver. The default is the Direct solver, which is fast but takes more memory
and may hang if system memory is insufficient. In a server with small memory capacity, user can switch to
the Iterative solver which takes less memory to run through efficiently
Show Layer
By default, CTA generates package layer-based color maps as old versions. User can turn off this option so
engine will generate component based color maps.
Figure 25. Simulation setup for BGA package
Modeling Options
Smeared Substrate
Check Smeared Substrate option, it reduces model size & solution time, lump all BGA substrate layers to
one block component in analysis model.
Cluster in SoC
A cluster is a small "CTM chip", like a core in a multi-core CPU. Users only have the design of the cluster and
generated CTM for the cluster only. As the cluster and the SoC are overlapping volumes and they are in one
chip (SoC), the bump pattern for SoC will be ignored under the cluster, this setup allows the complete bump
patterns in the final analysis model.
A keyword will be written to the <jobname>.gsr file for each cluster.
Note that the cluster name refers to a ctm chip in SoC and the names of cluster are unique chip names.
The valid examples are "<cluster1> in SoC", and/or "<cluster2> in SoC", here <clusterx> is the component
name of a chip in geometry editor.
The co-work flow to use the CTM as a cluster in a SoC is:
© 2017 Ansys Inc

1) Create a new component CLUSTER, placing above TOP metal layer.

2) In Die tab, Assign constant power to die component; attach CTM to CLUSTER component.
3) Assign a high value of heat transfer coefficient, like 1e+6 in Boundary->User Defined HTC (W/C-m2),
for 0th Loop. It will yield an almost uniform temperature distribution, and minimize temperature sensitivity
to CTM power.
4) Import Icepak heat transfer coefficients, for 1st, 2nd, …, nth loops.
5) Specify Cluster Name/SoC Name through Simulation->Cluster in SoC option.
Figure 26. Cluster in SoC
Cavity for Image Sensor

Image sensor packages with cavity in ceramic substrate to place die(s). Typically, there are two cavities
stacked together for the full space to place dies, i.e., the bottom cavity and the top cavity.
The cavity in an image sensor is the green and red volume in Figure 27. The cavity can be described by the
parameters in the table. The red volume is from the "Bottom" layer to the "Top1" layer. The green volume is
from the Top1 layer to the Top2 layer.
Dies for image sensor are on the layers defined by Thermal Setup-> Simulation ->Cavity for Image Sensor GUI
configuration. Refer to the illustration picture on UI, assign practical cavity sizes that fits in the package
without geometric conflicts.
Die stackup is defined in Layout Manager->Comp sheet with the top die mounting on the bottom die. The
top die size must be equal or smaller than the bottom die. The stacked dies will be placed in the combined
lower/upper cavities as in the picture.
CTA engine will model the geometry based on the information specified here.
© 2017 Ansys Inc

Figure 27. Cavity for image sensor picture
Bump Model
Bumps have its cross-section area and pattern that affect heat dissipation. For a small amount of bumps,
e.g. <500, thermal engine models the bumps as equivalent Solid elements. But, for bump counts >500, there
will be too many individual block to be included in the CPS model and Line elements will be used instead of
3D blocks to reduce model size, but with equivalent effects. Users also has the choice to force the modeling
by line elements or solid elements.
Criteria for Convergence

Power Difference (W)/Power Ratio
You can specify power difference in absolute value or ratio for convergence in iterations of CTM power
maps. The tool will stop iterations when either of these criteria are met.
Package Mesh Resolution (CTM chip)

This is a keyword to control the mesh fineness in the CTM chip of the CPS model. A keyword of
"RESOLUTION_CTM_CHIP <chipname> [res]" will be generated in the <jobname>.gsr so that thermal
solver will generate FE mesh accordingly. It is a user-defined resolution control with a real number for hard
point grid spacing in CTM chips. For example, Resolution = 30um for 30um grid points inside the particular
chip area. The grid points will appear in the final mesh file for package. If this keyword is not defined, default
to 50um.
Figure 28. Package Mesh Resolution (CTM chip) setup
© 2017 Ansys Inc

Chip Mesh Resolution (Layer-aware sub-model)

This is a keyword to control the mesh fineness in the CTM chip in the multi-layer chip sub-model.
‘Pcm_grid_size size]" will be generated in the <jobname>.gsr so that thermal solver will generate FE
mesh accordingly, in the chip sub-model. It controls chip model grid size in CTM analysis. Default to 50um.
Advanced Options
Package Mesh
It is package mesh control to use Detail Meshing or not. Detail Meshing would require longer run time and
bigger hard disc for thermal simulation. We recommend user to leave it off.
User can modify Via Metal(%) for equivalent K calculation.
Figure 29. Package Mesh setup
BGA/LF Meshing Controls
Figure 30. Meshing Controls setup
Add fine grid points to rectangular regions to refine mesh density for accuracy at critical locations
Board Settings
Board setup in CTA is general and not limited to JESD51 boards. The sizes, relative location to package
center, metal layer number and metal contents, and board orientation should be specified by user.
© 2017 Ansys Inc

Figure 31. Board Settings
Multi-Activities
This feature is to support thermal transient simulation of chip activities.
The task flow is illustrated in below chart:

Define Power Activities for CTM
Chips
Add More
Activities? Display: Transient Curves
at Selected Locations
Save Thermal Results for Define Activity Duration,

Run Layer-Aware CTM-
Multi-Activity Processing Cycles and Locations
based thermal analysis
Transients and Calculate
To use this new feature, user needs to enable Multi-Activities by checking Thermal Setup -> Simulation ->
Multi-Activities->Enable option. Configure the setup in Multi-Activity Setup dialog by clicking Edit Setup
button; add or remove chip activity by clicking +/- button. Then run thermal simulation. When thermal
simulation is completed; go to RH panel Query->Multi-Activity Result dialog to enter transient setup GUI.
Click on +/- command button, select chip activities in scroll down menu, N/A for idle; enter location by
coordinates; click on Show Transient to display transient curves at selected points in each CTM chip.
In Multi-Activity Setup dialog, for each activity, user can select die component from the scroll down menu and
configure constant power or CTM path to it. Run Yes to run this activity. Done Simulation is a status column
to indicate if the activity run is done. Click OK to save the setup and exit the dialog.
© 2017 Ansys Inc

Simulation Setup for Lead Frame PKG

The control options are almost the same as BGA PKG design, except LF Package option. It is for advanced
thermal simulation usage.
Click Generate Mesh, RH-CPA launches meshing function. When meshing is completed, the layer stackup
shows all the layers generated during meshing.
For LF package or user-stackup model, constant power must be defined in the stackup GUI as shown in Figure
33. Power windows can only on die.
You can view mesh in each layer and assign materials by left clicking a polygon, selecting a desired material
and Assign the material to selected polygon (Figure 34).
Figure 32. LF Package setup
© 2017 Ansys Inc

Figure 33. Generate Mesh for LF Package
Figure 34. Assign material for LF package
Results
After analysis, you can view the results graphically or as text files.
© 2017 Ansys Inc

Graphical Results
Click the ten result buttons in the View Results section to plot RH-CPA results in color maps overlaid on the
transparent package layout. You can also open Layout Manager, select Post Processing, and choose the
desired color maps.
Figure 35. CurDV color map
After CPA extraction, you can view PinR, PinL, and LoopL color plots. If user created dynamic probes, after
RH dynamic simulation, CPA generated probe voltage contours on the grid boxes. You can view the plots by
selecting Probe Voltage (V) Result Type.
For PinR, PinL and LoopL results, you have the following options:
 Net: Filter the displayed pins by nets.
 Pin Size: Adjust this value to control the pin size displayed. The canvas synchronously refresh plot to
display the pin of new size after you input a pin size. Default is 0.2mm.
 Constraint Violation: It can identify violations, and highlight the pins with issues in the canvas as
controlled by the user specified constraint. There are two ways to set the constraints:
 Absolute: Any value larger than this constraint is identified as a violation and highlighted with a
color. You can click the Color panel to change the highlight color.
 Relative (%): An average resistance or inductance is calculated. Any value that is out of this
average percentage is identified as a violation, and highlighted by a color.
 Contour Range: Set the min and max of the color range. It can be determined automatically or
specified by user.
 Transparency: Set the transparency level for the package layout. Larger value means more transparent
layout.
 Flip Color Map: This is a useful option to view the voltage drop on power nets, where small voltage
value means larger drop.
 Query by Mouse: Hover the mouse over the color maps, a tool tip will show the value at current
location.
For Probe Voltage (V) results, Clicking Export, you can dump the probe voltages to a txt format file.
Default file name is <jobname>_ProbeReport.txt. Here is an example of output file.
© 2017 Ansys Inc

Pin x(mm) y(mm) Voltage_Max(v) Voltage_Min(v) Voltage_Drop(v)

Voltage_Bounce(v)
ProbeD_TOP_1_VDD_15 -1.500000 4.500000 1.000000 1.000000 -0.000000 -
0.000000
ProbeD_TOP_1_VSS -1.750000 4.500000 0.000000 0.000000 0.000000
0.000000
ProbeD_TOP_2_VDD_15 -1.500000 -4.500000 1.000000 1.000000 -0.000000 -
0.000000
ProbeD_TOP_2_VSS -1.750000 -4.500000 0.000000 0.000000 0.000000
0.000000
…
Since RH 17.1.1, CPA conducts post-processing EM check to find out current density violations with user-
customized EM limits, for Current Density Map (A/Sq.m) result type and user option EM Violations
checked.
Click Export, by default CPA exports the EM report to “MODEL/cosim/<jobname>_EMCheck.txt”. You
can re-direct the report to another file and click Save.
For the other color maps, besides an option to toggle on/off the color map for each layer, you also have the
following options:
 Fill, WireFrame, Node: modify the 2-D display with different options.
 Uniform Length, Vector Length Factor, Vector: modify the 2-D display with different vector length.
 Text Color: modify the text color in color maps.
 Preciseness: control the number of digits after the decimal point, for the data value in color maps.
 EM Violations: conducts post-processing EM check to find out current density violations with user-
customized EM limits, for Current Density Map (A/Sq.m) result type.
 Vector: For thermal analysis type, post-processing enhanced Vector option to adjust vector length and
vector size, according to the contour values through two sub-options Unfirm Length and Vector
Length Factor.
After CTA thermal modeling you can view by-layer temperature, heat flux and power density color contours.
The contour display in CTA depends on the selections of the die/package/board layers. For a good contour
display, one should not mix more than one component. Also all the layers shall be unchecked so that the
color contours will not be masked by layout of the substrate metals.
Multi-Activity Results is a post-processing dialog from where CTA can display time to steady state curve for
the last thermal analysis, for T_max in package.
After thermal simulation, user need to manually add or delete activity name to show transient curve by
clicking +/- button. For each activity, the below property page will display the chips’ CTM setup.
Here is the illustration for command buttons

Add>>: add coordinates specified by X(um) and Y(um) to the coordinate list;
Del<<: select a coordinate from the list, click Del<< to remove it;
Grid: calculate coordinates in chip by gridding method and add the grid centers to coordinate list;
Load: load coordinates’ list from a text format file;
Clear: remove the coordinates list;
Show Transient: display transient curves at selected points in each CTM chip.
Save: save the configuration and exit dialog.
© 2017 Ansys Inc

Select an Activity in scroll down menu, N/A for idle
Activity_1 will last for 100 sec then idle for 100 sec in one cycle.
For selected activity, echo for the power setup
Die range (um)

in chip design
Show for 5 cycles Enter location by coordinates (um)
Text File Results

The generated package extraction model is located in <project_path>/Extraction folder:
File name Description
<job_name>.sp RLCK Spice model of the package
<job_name>_component.sp Subckt model of the components with ports
<job_name>_component.cpp CPP header specifies components with ports
cpa_annotated.ploc Annotated PLOC file (encrypted)
cpa_rh_pkg_wrapper.sp Top level netlist for RedHawk (encrypted)
unconnected_plocs.txt Lists the ploc pins that are not used or floating for PLOC connection
Lumped_L.txt Effective inductance for each domain
Partial_L.txt Partial inductance for each package pin
Chip_PKG_NetMap.txt Chip->Pkg net connections
Combined CPM+CPA spice files are located in <project_path>/CPM_CPA folder.

<job_name>.sp RLCK Spice model of the package
PowerModel.sp CPM model
© 2017 Ansys Inc

PowerModel.sp.inc Include file of CPM model

CPM_CPA.sp Wrapper spice model for CPM+CPA
testbench_AC_xxx.sp Benchmark spice for AC (impedance) analysis
testbench_Trans.sp Benchmark spice for transient analysis
The generated co-sim results are located in <project_path>/cosim folder:

<job_name>.glb 3-D result file with voltage drop and current flow
<job_name>_Via.cur Current flowing through via
After thermal analysis:

 In the thermal folder, the following files are useful in review.
PowerCal.summary CTM thermal results summary showing Tmax on each CTM chip and
total power
PowerCal.log The process of T-P iteration, useful in judging if the CTM thermal
analysis is successfully finished
<jobname>.ja_summary This is the result summary for non-CTM thermal analysis showing
Tmax and Theta-JA of the package
 In the <chip> sub-folder under thermal folder, there are the layer-aware results after CTM flow,
including the tile-based back-annotation file for RH/Totem (chip_thermal_profile.bin). The
chip_T.dat has similar contents to the bin file and is used for CPS_thermal_profile in the wire
self-heat flow for wire EM evaluation in RH/Totem.
 In the T_map sub-folder under thermal folder, temperature on die and substrate will be exported here:
Die_T_summary.txt Die Name, Tmax, Tmin, and Tavg on each die
<die_name>_T_map.txt temperature of 100x100 array of points on top surface of each die,
space delimited)
<die_name>_XYT.txt temperature of 10000 points uniformly distributed on top surfaces of
each die, with 10000 lines of x, y, and T
<die_name>_XYZT.txt nodal coordinates and temperature on each die
sub_T_summary.txt Layer Name, Tmax, Tmin, and Tavg for each metal layer on substrate
Impedance Analysis
After package extraction, you could execute impedance analysis for package only.
Select the Die component which connected to ploc, choose positive pin/group(s) and negative pin/group(s),
type the port reference impedance in the Z_ref(ohm) text box, click Create Port to add port(s). For an
existing port, you can double click its Z_ref to modify the value.
Choose positive pin/group(s) and negative pin/group(s), type the port reference impedance in the Z_ref(ohm)
text box, click AutoGen, RH-CPA creates ports for each non-RefNet pin/group to its closest RefNet
pin/group automatically.
The frequency bandwidth, sweep type and sampling method can be configured by clicking Edit…
© 2017 Ansys Inc

Figure 36. Impedance analysis dialog
Click Run, RH-CPA performs impedance analysis. After impedance analysis, the S parameter file is located
in <project_path>/impedance folder. RH-CPA launches SUtility to view the S parameter results.
Please refer to Appendix A for SUtility usage.
© 2017 Ansys Inc

Appendix A
SUtility
SUtility is an add-on tool for S-parameter viewing and processing in RH-CPA. You can refer to the detailed
usage by clicking Help->User Manual. The major enhancements and new features are introduced in
Appendix A.
Figure 37. Sutility tool
Select Curves
Port List control is inside the Select Curves control. It separates Port# i and Port# j into two lists. Select
Port# i and Port# j respectively, and click Add Curves into Selected Curves List to place the plot Si,j into
Selected Curves list in the right panel. User can do multi-selection with CTRL or SHIFT pressed when
selecting curves.
User can show or hide the selected curves by Show Selected Curves or Hide Selected Curves. Click Exit
to exit the Select Curves dialog box (shown in Figure. 38). With the new dialog, user can easily switch
between the projects, and quickly select the desired port parameters.
© 2017 Ansys Inc

Figure 38. Select Curves Control
Utilites->Impedance Extractor
SUtility uses auto-detection of port pairs to produce characteristic impedances for multiple nets, it can now
process a large number of ports automatically.
In the Impedance Extractor dialog, user is able to perform impedance extraction for multiple port pairs.
Select Port# i and Port# j with CTRL or SHIFT pressed, and click Add Pair to place it into the Port Pairs list
in the right panel. User can do multi-selection using CTRL or SHIFT pressed when selecting port pairs. Auto
Detect by Net will pick all the port pairs automatically. When Extract button is clicked, the characteristic
impedance for each port pair is extracted. Each port pair will have a Characteristic impedance curve (shown
in Figure. 39 and 40).
Figure 39. Impedance Extractor
© 2017 Ansys Inc

Figure 40. Multiple characteristic impedance curves
Zoom-in, Zoom-out, Pan and Fit-all features on the S-parameter curves

The new zoom-in and auto-tip features improve ease of use
User can zoom in and zoom out the plots by scrolling the middle mouse wheel forward and backward. When
the Zoom Window button in the Utilities Bar, or the right click of Mouse is used, user can zoom in curves by
drawing a rectangle box from the top to bottom or from the bottom to the top.
Figure 41. Utilities Bar
Change plotting line width, color and type for the curves
SUtility provides option to change the trace type, width and color from Legend control by right click when
cursor is over the selected curve. By clicking Property, it will bring up the Curve(s) Property dialog shown in
Figure 42. User can customize the style, width and color, and then click OK to make the change to take
effect. User can also left click the Color column when cursor is over the selected curve to present up the
Curve(s) Property dialog. Trace style has Solid, Dash, Dot, Dash Dot, Dash Dot Dot types. Clicking color
button brings up the system color palette as shown in Figure 43.
Figure 42. The Legend and Curve(s) property dialog
© 2017 Ansys Inc

Figure 43. Color Palette
Resizable window
SUtility window is resizable from its default size to its maximum size. The default size is 1011X770 pixels.
Auto-tip display when mouse pointer is placed on a curve

Click View->Curve Tooltip. When cursor hovers over a data point, a tool tip with curve name, port# i and
port# j names, and the x-y data value pops up (shown in Figure. 44).
Figure 44. Auto tip is on

© 2017 Ansys Inc
Real part, Imaginary part, and Inductance plots

S-Utility displays S, Y, and Z parameter in real and imaginary format also. The inductance curve is calculated
from Z parameters (Im{Z}/2*pi*f).
Figure 45. Data Type Section
Numeric Axis Display

Instead of using scientific notation to display the x- and y-axis values at grid lines, a compact floating point
notation has been used. This makes it easy to read the numerical values
Marker
User can now add markers at desired points on the curves to display the x- and y-axis values at those points.
Go to View->Marker and select it. Click the right mouse button and select Add Marker to place it as shown
below
Figure 46. Steps to Add Marker
© 2017 Ansys Inc

Apache Design, Inc.

Subsidiary of ANSYS, Inc.
2645 Zanker Road

San Jose, CA 95134
Main: 408-457-2000
Fax: 408-428-9569
ANSYS and any and all ANSYS, Inc. brand, product, service and feature names, logos and slogans are
registered trademarks or trademarks of ANSYS, Inc. or its subsidiaries in the United States or other
countries. All other brand, product, service and feature names or trademarks are the property of their
respective owners
© 2017 Ansys Inc

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RedHawk-CPA Application Notes 18.1.

RH-CPA Application Notes

© 2017 Ansys Inc

 Supports 2D and 3D view

GSR Keywords Usage

Use the keyword CPA_FILES in GSR for integrated RH-CPA flow.

© 2017 Ansys Inc

Use the keyword IMPORT_REGION to specify a selective chip area.

© 2017 Ansys Inc

Use the keyword THERMAL_ANALYSIS to turn CPA and/or CTA on or off.

In RH .GSR, keyword PACKAGE can point to the pre package file

© 2017 Ansys Inc

Use the keyword CPA_MODEL to support standalone CPA folder.

TCL command to combine nets. The syntax is

© 2017 Ansys Inc

TCL to Create Molding Part. The syntax is

-add: specifies to add a new part;

TCL to Delete Part. The syntax is

TCL to Create Molding Component. The syntax is

TCL to Delete Component. The syntax is

© 2017 Ansys Inc

Setup Dynamic Probes

setup cpa probe -deldynamic

© 2017 Ansys Inc

TCL command to specify temperature coefficients and reference temperature.

setup cpa layer -del ?-name <layername_list>?

Setup Solder Ball

Setup Solder Bump

Setup Bondwire Profile

© 2017 Ansys Inc

Setup External Environment

Setup General Configuration

© 2017 Ansys Inc

PAD_FILES in the GSR file will be used.

TCL to Perform Dummy PLOC Connection. The syntax is

Setup Unconnected Die Domain

© 2017 Ansys Inc

setup cpa vrm ?–gsr?

setup cpa vrm ?-use_bgamodel [true|false]?

© 2017 Ansys Inc

Export a new CTM with power scales in regions

Convert MHS to CTM V0

© 2017 Ansys Inc

setup cpa thermal -material ?-part <part_name>? ?-mat <material_name>?

setup cpa thermal -material -add -name <material_name> -category <EncapCoat |

setup cpa thermal -material -name <material_name> ?-category <EncapCoat |

Here is the List of material categories for BGA type material.

setup cpa thermal -material -name <material_name> ?-deltemperature <value>?

Simulation Options Setup

© 2017 Ansys Inc

-solver: uses direct solver or iterative solver;

Perform DRC Check

Perform Channel Extraction

Perform Co-Sim Simulation

This is a chip+pkg co-simulation command that:

Perform Thermal Simulation

© 2017 Ansys Inc

3. Generate package thermal profile.

HTML Report Generation

report cpa html -cosim ?-o <html_file>?

report cpa thermal -html <html_file>

EM Check for Current Density Map

Check EM Violations Set EM Limits

© 2017 Ansys Inc