AIM: Designing an efficient amplifier circuit that will be used to amplify an input signal of 100mV

peak-peak to give an output signal of 3.5V peak-peak. This circuit will also be required to drive a
100Ω load.

METHOD: Through DC analysis and also making some later verified assumptions to derive the values
of the components, using passive components and transistors only. The circuit will be built on
breadboard, PCB and also tested on proteus IDE. The cct. must contain at least 2 stages. In this case
Class A and Class AB amplifiers are used for the 2 stages respectively.

EQUIPMENT: Oscilloscope, voltmeter, amperemeter, power supply.

CIRCUIT DESIGN

CIRCUIT ANALYSIS

Vin pk−pk = 100mV, desired Vout pk−pk = 3.5V, R L = 100Ω

Vout pk−pk 3.5
Avt = = = 35
Vin pk−pk 0.1

Avt = −Avce x Avcc

Assume Avcc = 0.99 and Avt = 35,

Therefore Avce = 35 ÷ 0.99 = -35.35

STAGE 2;

2*lbias*R = Vcc -1.4

Vcc−1.4 Vcc 15
R= 2∗lbias
, lbias = Icq = 4% of Ic(sat), Ic(sat) = 2∗R = 2∗100 = 0.075A
L

Ibias = 4% x 0.075 = 3mA

15−1.4
R = 2∗0.003 = 2.3k Ω = 2.4kΩ (from E24 series res.)

Zin(base) = hFE x R L = 1k x 100 = 100kΩ

240M
Zin(stage) = R // Zin(base) = 2.4k // 100k = 102.4𝑘
= 2.4kΩ ,

Zineq(stage) = 2.4kΩ ÷ 2 = 1.2kΩ

STAGE 1;

Assume R C = 1.1kΩ, R L = 1.2kΩ,

VE = 10% of Vcc = 10% x 15 = 1.5V,

𝑉𝑅𝐶
IE = VE ÷ R E , but IE = IC = RC
= 6.75 ÷ 1.1k = 6.14mA
 15−1.5
VRC = 2
= 6.75V,

So, R E = 1.5 ÷ 6.14m = 244Ω = 330Ω (resistor standard value),

𝑟𝑒 ′ = 25mV ÷ IE = 25mV ÷ 6.14mA = 4.07Ω,

VB = VE + 0.7 = 1.5 + 0.7 = 2.2V,

VCE = Vcc - IC ∗ (R C + R E ) = 15 – 6.14m*(1.1k + 330) = 6.2V,

IB = IC ÷ β, where β= 200, IB = 6.14m ÷ 200 = 30.7µA,

since the current passing through 𝑅1 𝑎𝑛𝑑 𝑅2 is 10*IB , then;

V𝑐𝑐 15
𝑅1 +𝑅2
= 10IB , 𝑅1 +𝑅2
= 307µA, 𝑅1 + 𝑅2 = 48.86𝑘,

V𝑐𝑐−VB 15−2.2 V
𝑅1 = 10IB
= 307µ
= 41.69kΩ = 45kΩ, 𝑅2 = 10IB = 2.2 ÷ 307µA = 7.166kΩ = 7.5kΩ,
B

−(RC // RL ) −( 1.1k//1.2k)
Avce = 𝑟𝑒 ′
= 4.07
= 141, but this value is >> 35.35 that we need.

Therefore, I added another resistor, re, in series with R E , then the new equation is Avce =
−(RC // RL )
𝑟𝑒 ′ +re

Making re the subject of formula; when Avce = 35.35

re = 430.0385 ÷ 35.35 = 12.17Ω = 16Ω.

EFFICIENCY OF THE AMPLIFIER

STAGE 2;

𝑉𝑖𝑛𝑝𝑘−𝑝𝑘 3.52
Pin = 8∗𝑍𝑖𝑛
= 8∗1200 = 1.276mW

𝑉𝑜𝑢𝑡𝑝𝑘−𝑝𝑘 3.52
Pin = 8∗𝑅𝑙
= 8∗100 = 15.31mW

Pout 15.31𝑚
Power gain; Ap = Pin
= 1.276m
= 11.99W

Pout(max) 𝑉𝑐𝑐 2 ÷8Rl

ɳ= Pdc
= Vcc∗Idc

Idc = Ibias + [Vcc/(2*Rl*𝛱)] = 3m + (15/(2*100*𝛱)] = 26.87mW

152 ÷8∗100
ɳ= = 69.78%
15∗26.87mW

STAGE 1;
 P 2Vcc∗2Ic 2∗15∗2∗6.14𝑚
ɳ = Pac = 8Vcc∗Ic
= 8∗15∗6.14m = 50%
dc

RESULT

For proper functioning of the circuit, I have tested the 2 stages separately.

STAGE 2

Vout pk−pk = 3.5V, Vout rms = (3.5 ÷ 2) ÷ 1.414 = 1.2V,

Pout = V 2 out rms ÷ R L ; = 1.22 ÷ 100, Pout = 14.4𝑚𝑊

Probably there won’t be any need for heat sink since the Pmax for TIP12XG at 25°C is 65W @ 0.52
W/°C (from datasheet).

Without input signal, quiescent power, P, dissipated by R; P= IR *VR

15−1.4
Bias current, IR = 2∗2.4𝑘 = 2.83mA, R=2.4kΩ,

VR = 2.83mA x 2.4k = 6.792V

P = 2.83m*6.792 = 19.22mW
DC VOLTAGES WITHOUT INPUT SIGNAL

TYPICAL/CALCULATED VALUE (V) MEASURED (V)

Base - Emitter voltage of Q1 0.7 0.63
Collector Emitter voltage at Q1 - 7.49
Voltage at point D 3.5 0

WITH INPUT SIGNAL of 3.5V pk−pk and frequency of 1kHz;

Using the oscilloscope to see the waveform at point C;

Figure downloaded from proteus simulation.

Using the peak value of the voltage to calculate the current through R L and hence the power
dissipated by the Q1. Do you advise that a heatsink should be used for Q1 and Q2?

Vout pk−pk = 3.5V, Vout rms = (3.5 ÷ 2) ÷ 1.414 = 1.2V, Vout pk = 1.75V,

IL = Vout pk ÷ R L ; IL = 1.75 ÷ 100 = 17.5 mA,

Pout = IL ∗ Vout pk ; = 17.5𝑚 ∗ 1.75, Pout = 30.63𝑚𝑊

Pout = V 2 out rms ÷ R L ; = 1.22 ÷ 100, Pout = 14.4𝑚𝑊

Pout = V 2 out pk ÷ R L ; = 1.752 ÷ 100, Pout = 30.63𝑚𝑊

Probably there won’t be any need for heat sink for the 2 transistors since the Pmax for TIP12XG at
25°C is 65W @ 0.52 W/°C (from datasheet). Ref.

STAGE 1

DC VOLTAGES WITHOUT INPUT SIGNAL

CALCULATED VALUE (V) MEASURED (V)

Base voltage 2.2 2.16
Emitter voltage 1.5 1.49
Collector voltage 6.75 6.22
Collector Emitter voltage 6.22 5.64
Base - Emitter voltage 0.7 0.66
Emitter current 6.14mA 5.85mA
Collector current 6.14mA 5.83mA
Base current 30.7uA 29.9uA
WITH INPUT SIGNAL of 100mV pk−pk and frequency of 1kHz;

Using the oscilloscope to see the waveform at the output;

The output is 3.5V with a phase difference of 180⁰

Yellow is the input while blue is the output waveforms.

Figure downloaded from proteus simulation.

TESTING STAGES 1&2 TOGETHER

WITH INPUT SIGNAL of 100mV pk−pk and a frequency of 1kHz;

Using the oscilloscope to see the waveform at the output;

The output is 3.5V with a phase difference of 180⁰, this phase shift is coming from stage 1 as seen
earlier.
Figure downloaded from proteus simulation.
The above amplifier was also built on a PCB, and similar results were recorded.

CONCLUSION
The results obtained from the built circuit is very much similar to the analysis conducted. Although
there were few adjustments made in the values of some component;

 Value of resistor, re calculated was 12.17Ω, but in practice this value was giving out a lower
output of about 2 to 3.2Vpk-pk. This resistor value had to be increased a little so that the
output of 3.5Vpk-pk can be obtained. The value chosen must be in the range 14Ω ≤re<18Ω
as anything out of this range will give a V_out lower or higher than the desired output
because it either increases or decreases the gain of the amplifier. A value of 16Ω was used in
the circuit.
This might have happened due to some errors in the rounding up of the numbers during
calculation.
 Every component was rounded up to their closest value according to the E series standard.
 There was no need for heat sinks for the transistors since the output power calculated was
lesser than the power ratings from the datasheet. Likewise in practise, the transistors didn’t
heat-up and no heat sinks were needed both on the breadboard and the PCB designs.
 The circuit on the breadboard has an efficiency of 69.78% for stage 2 and 50% for stage 1.

On the PCB, there was clipping in the positive half cycle of the output voltage obtained, although a
3.5Vpk-pk was still gotten.

This clipping is occurring from the common emitter amplifier (stage 1).

This clipping might have occurred because there is too much bias and the Q-point lies in the
upper half of the load line.

Another reason for the clipping might be because a large input signal is being amplified by the
circuit gain which leads to the circuit being over-driven.

Another reason could be because of some faults on the track-lines of the PCB since the same
exact components were used to carry out the experiment on the breadboard, but with a
different result as there was no clipping on the breadboard.

 The stage 1 of the amplifier on PCB is not quite efficient since the distortion affects the
efficiency of an amplifier and one of the main functions of the class A amplifier is to
remove the distortion.