Lenovo G50-45 NM-A281P ACLU5-ACLU6

A B C D E
1 1
LCFC Confidential
G Project M/B Schematics Document
2 2
AMD FT3B Beema SOC with DDRIIIL

AMD JET-LE
2014-2-12
3
REV:0.4 3
4 4
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A281 0.4
Date: Thursday, February 20, 2014 Sheet 1 of 60

A B C D E
A B C D E
LCFC confidential
File Name : ACLU5&6
AMD Jet LE/ Topaz XT
S3 Package: 23mmX23mm PCI-Express
Page 18~24
4x Gen2 Memory BUS (DDR3L)
Single Channel DDR3L-SO-DIMM X2
PEG 0~3 Page 14,15
VRAM 256/128*16
1
1.35V DDR3L 1600 MT/s 1
DDR3L*4 2GB/1GB UP TO 8G x 2
Page 25~26
HDMI
HDMI Conn. USB Left
Page 34 USB 3.0 1x
AMD FT3b APU USB 2.0 Port8
USB 3.0 Port0
VGA USB 2.0 2x JUSB2
CRT Conn. USB 2.0 Port3
Page 36 JUSB1 Page 41
eDP x2 Lane
eDP Conn
USB2.0 1x
Beema 15W /2.4G USB 2.0 1x Touch Screen
Int. Camera Page 33 USB2.0 Port4
USB2.0 Port5
(Integrated FCH)
2 2
Int. MIC Conn.
Page 33 USB2.0 1x USB Right

USB2.0 Port0
(Debug Port) JUSB3
SATA HDD SATA Gen3 USB2.0 1x

Page 42 SATA Port0 Cardreader Realtek SD/MMC Conn.
BGA-769 RTS5170 USB2.0 Port2
24.5mm*24.5mm USB Board
SATA ODD SATA Gen1
Page 42 SATA Port1
USB 2.0 1x
NGFF Card
LAN Realtek PCIe 1x WLAN&BT
RJ45 Conn. PCIe 1x PCIe Port1
Page 38
RTL8111GUL (1G) Page 40 USB2.0 Port6 Sub-board ( for 14")
RTL8106EUL (10M/100M)
3 3
Page 37 PCIe Port2
SPI BUS SPI ROM 0 POWER BOARD NS-A272
HD Audio
Page 4~9 8MB Page 07
USB Board NS-A271
Codec SPK Conn.

Conexant CX20752 Page 43
Page 43
Sub-board ( for 15")
EC
ITE IT8586E-LQFP POWER BOARD NS-A273
Page 44
HP&Mic Combo Conn. USB Board NS-A275
USB Board
Touch Pad Int.KBD Thermal Sensor ODD Board NS-A274
4 Page 45 Page 45 NCT7718W
Page 39
4

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Block Diagram
Custom
NM-A281 0.4

A B C D E
A B C D E
Voltage Rails ( O --> Means ON , X --> Means OFF ) Board ID need to be update!
SIGNAL BOARD
+5VS STATE SLP_S3# SLP_S5# +VALW +V +VS Clock Config. GPIOxx GPIOxx GPIOxx Function
+3VS 0 0 0
S0 (Full ON) HIGH HIGH ON ON ON ON
+1.8VS
power +1.5VS S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
plane B+ +5VALW +1.35V +0.95VS
S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF
1
(+VSYSMEN) +0.675VS 1
VL +3VALW S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF

+APU_CORE
+APU_CORE_NB S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VL +1.8VALW
+VGA_CORE
State
+0.95VALW +3VGS
+1.8VGS
+1.35VGS
USB Port Table BOM Structure Table
+0.95VGS
3 External BOM Structure BTO Item
USB 2.0 USB 3.0 Port
USB Port
@ Not stuff
S0 O O O O 0 RIGHT USB (2.0)
ME@ Connector
1 N/A For 14" part
14@
S3
2 Card Reader
O O O X 3 LEFT USB (2.0)
15@ For 15" part
EHCI UMA@ UMA SKU ID part
4 Touch Screen Discrete GPU SKU ID part
S5 S4/AC
PX@
2 O O X X 5 Camera
8106EUL@ 8106EUL LAN part 2
6 Blue Tooth 8111GUL LAN Part

8111GUL@
S5 S4/ Battery only
7 N/A
O X X X 0 8 LEFT USB (3.0)
GIGA@ Giga LAN Part
xHCI TS@ Touch Screen part
1 9 N/A Zero Power ODD part
S5 S4/AC & Battery
ZODD@
don't exist X X X X AOAC@ AOAC support part
HDT@ HDT Debug part
Kabini@ Kabini APU part
SMBUS Control Table PCIE PORT LIST SDV@ SDV PWR part
Port Device
SOURCE GPU BATT IT8586E SODIMM
WLAN Thermal APU Charger 0 N/A
Sensor
GPP
1 WLAN
EC_SMB_CK1 2 LAN
IT8586E
X V IT8586E
X X X X V
EC_SMB_DA1 APU_SIC
+3VALW +3VALW APU_SID
3 N/A
0
3 3
EC_SMB_CK2 1
IT8586E V X IT8586E
X X V V X GFX GPU
EC_SMB_DA2 APU_SIC
+3VS +3VS_VGA +3VS APU_SID
2
3
APU_SCLK0 APU
APU
APU_SDATA0 +3VS X X X V V X X S2G@ X76 SAMSUNG 2G
+3VS
M2G@ X76 MICRON 2G
H2G@ X76 HYNIX 2G
VRAM X76 SAMSUNG 1G
S1G@
M1G@ X76 MICRON 1G
EC SM Bus1 address EC SM Bus2 address H1G@ X76 HYNIX 2G
Device Address Device Address

Battery 0X16 Thermal Sensor 1001_100xb
Charger 0001 0010 b GPU 0x41(default)
APU Thermal Diode TBU
4
APU SM Bus address 4
Device Address
DDR DIMMA 1001 000Xb
DDR DIMMB 1001 010Xb
WLAN RSVD
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Notes List
Size Document Number
Rev
Custom
NM-A281 0.4

A B C D E
5 4 3 2 1
Beema (MEM & PCIE I/F)
D D
UC1A
OK<14,15> DDRA_MA[15..0] MEMORY
DDRA_DQ[63..0] <14,15>OK
DDRA_MA0 AG38 M_ADD0 M_DATA0 B30 DDRA_DQ0
DDRA_MA1 W35 M_ADD1 M_DATA1 A32 DDRA_DQ1
DDRA_MA2 W38 M_ADD2 M_DATA2 B35 DDRA_DQ2
DDRA_MA3 W34 M_ADD3 M_DATA3 A36 DDRA_DQ3
DDRA_MA4 U38 M_ADD4 M_DATA4 B29 DDRA_DQ4
DDRA_MA5 U37 M_ADD5 M_DATA5 A30 DDRA_DQ5
DDRA_MA6 U34 M_ADD6 M_DATA6 A34 DDRA_DQ6
DDRA_MA7 R35 M_ADD7 M_DATA7 B34 DDRA_DQ7
DDRA_MA8 R38 M_ADD8
DDRA_MA9 N38 M_ADD9 M_DATA8 B37 DDRA_DQ8
DDRA_MA10 AG34 M_ADD10 M_DATA9 A38 DDRA_DQ9
DDRA_MA11 R34 M_ADD11 M_DATA10 D40 DDRA_DQ10
DDRA_MA12 N37 M_ADD12 M_DATA11 D41 DDRA_DQ11
DDRA_MA13 AN34 M_ADD13 M_DATA12 B36 DDRA_DQ12
DDRA_MA14 L38 M_ADD14 M_DATA13 A37 DDRA_DQ13
DDRA_MA15 L35 M_ADD15 M_DATA14 B41 DDRA_DQ14
M_DATA15 C40 DDRA_DQ15 UC1B
OK<14,15> DDRA_BS0#
DDRA_BS0# AJ38 M_BANK0 PCIE
OK<14,15> DDRA_BS1#
DDRA_BS1# AG35 M_BANK1 M_DATA16 F40 DDRA_DQ16
OK<14,15> DDRA_BS2#
DDRA_BS2# N34 M_BANK2 M_DATA17 F41 DDRA_DQ17
OK<14,15> DDRA_DM[7..0] M_DATA18 K40 DDRA_DQ18 R10 P_GPP_RXP0 P_GPP_TXP0 L2 Net name changed to same as ACLU1
DDRA_DM0 B32 M_DM0 M_DATA19 K41 DDRA_DQ19 R8 P_GPP_RXN0 P_GPP_TXN0 L1
DDRA_DM1 B38 M_DM1 M_DATA20 E40 DDRA_DQ20
DDRA_DM2 G40 M_DM2 M_DATA21 E41 DDRA_DQ21 PCIE_PRX_DTX_P4 R5 P_GPP_RXP1 P_GPP_TXP1 K2 PCIE_PTX_DRX_P4 .1U_0402_10V6-K 1 2 CC21 PCIE_PTX_C_DRX_P4
<40> PCIE_PRX_DTX_P4 PCIE_PTX_C_DRX_P4 <40>
DDRA_DM3 N41 M_DM3 M_DATA22 J40 DDRA_DQ22 OK WLAN <40> PCIE_PRX_DTX_N4
PCIE_PRX_DTX_N4 R4 P_GPP_RXN1 P_GPP_TXN1 K1 PCIE_PTX_DRX_N4 .1U_0402_10V6-K 1 2 CC22 PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_N4 <40>WLAN OK
DDRA_DM4 AG40 M_DM4 M_DATA23 J41 DDRA_DQ23
DDRA_DM5 AN41 M_DM5 PCIE_PRX_DTX_P3 N5 P_GPP_RXP2 P_GPP_TXP2 J2 PCIE_PTX_DRX_P3 .1U_0402_10V6-K 1 2 CC19 PCIE_PTX_C_DRX_P3
<37> PCIE_PRX_DTX_P3 PCIE_PTX_C_DRX_P3 <37>
DDRA_DM6 AY40 M_DM6 M_DATA24 M41 DDRA_DQ24 OK LAN <37> PCIE_PRX_DTX_N3
PCIE_PRX_DTX_N3 N4 P_GPP_RXN2 P_GPP_TXN2 J1 PCIE_PTX_DRX_N3 .1U_0402_10V6-K 1 2 CC20 PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_N3 <37>LAN OK
DDRA_DM7 AY34 M_DM7 M_DATA25 N40 DDRA_DQ25
TC10 @ 1 T_DDRA_DM8 Y40 M_DM8 M_DATA26 T41 DDRA_DQ26 N10 P_GPP_RXP3 P_GPP_TXP3 H2
+0.95VS_GFX_APU +0.95VS_GFX_APU
M_DATA27 U40 DDRA_DQ27 OK N8 P_GPP_RXN3 P_GPP_TXN3 H1 OK
DDRA_DQS0 B33 M_DQS_H0 M_DATA28 L40 DDRA_DQ28
C DDRA_DQS#0 A33 M_DQS_L0 M_DATA29 M40 DDRA_DQ29 1 2 P_TX_ZVDD W8 P_TX_ZVDD_095 P_RX_ZVDD_095 W7 P_RX_ZVDD 2 1 C
DDRA_DQS1 B40 M_DQS_H1 M_DATA30 R40 DDRA_DQ30 RC7 1.69K_0402_1% 1K_0402_1% RC8
DDRA_DQS#1 A40 M_DQS_L1 M_DATA31 T40 DDRA_DQ31
DDRA_DQS2 H41 M_DQS_H2
DDRA_DQS#2 H40 M_DQS_L2 M_DATA32 AF40 DDRA_DQ36 PCIE_CRX_GTX_P0 L5 P_GFX_RXP0 P_GFX_TXP0 G2 PCIE_CTX_GRX_P0 .1U_0402_10V6-K 1 2 CC11 PX@ PCIE_CTX_C_GRX_P0
OK <14,15> DDRA_DQS[0..7]
DDRA_DQS[0..7] DDRA_DQS3 P41 M_DQS_H3 M_DATA33 AF41 DDRA_DQ37 swap DQ32/33 and DQ36/37 @ 09/06 PCIE_CRX_GTX_N0 L4 P_GFX_RXN0 P_GFX_TXN0 G1 PCIE_CTX_GRX_N0 .1U_0402_10V6-K 1 2 CC12 PX@ PCIE_CTX_C_GRX_N0
DDRA_DQS#3 P40 M_DQS_L3 M_DATA34 AK40 DDRA_DQ34
OK<14,15> DDRA_DQS#[0..7]
DDRA_DQS#[0..7] DDRA_DQS4 AH41 M_DQS_H4 M_DATA35 AK41 DDRA_DQ35 PCIE_CRX_GTX_P1 J5 P_GFX_RXP1 P_GFX_TXP1 F2 PCIE_CTX_GRX_P1 .1U_0402_10V6-K 1 2 CC13 PX@ PCIE_CTX_C_GRX_P1
DDRA_DQS#4 AH40
DDRA_DQS5 AP41
M_DQS_L4
M_DQS_H5
M_DATA36
M_DATA37
AE40
AE41
DDRA_DQ32
DDRA_DQ33
PCIE_CRX_GTX_N1 J4 P_GFX_RXN1 P_GFX_TXN1 F1 PCIE_CTX_GRX_N1 .1U_0402_10V6-K 1 2 CC14 PX@ PCIE_CTX_C_GRX_N1
GPU
DDRA_DQS#5 AP40 M_DQS_L5 M_DATA38 AJ40 DDRA_DQ38 PCIE_CRX_GTX_P2 G5 P_GFX_RXP2 P_GFX_TXP2 E2 PCIE_CTX_GRX_P2 .1U_0402_10V6-K 1 2 CC15 PX@ PCIE_CTX_C_GRX_P2
DDRA_DQS6 BA40 M_DQS_H6 M_DATA39 AJ41 DDRA_DQ39 PCIE_CRX_GTX_N2 G4 P_GFX_RXN2 P_GFX_TXN2 E1 PCIE_CTX_GRX_N2 .1U_0402_10V6-K 1 2 CC16 PX@ PCIE_CTX_C_GRX_N2
DDRA_DQS#6 AY41 M_DQS_L6
DDRA_DQS7 AY33 M_DQS_H7 M_DATA40 AM41 DDRA_DQ40 PCIE_CRX_GTX_P3 D7 P_GFX_RXP3 P_GFX_TXP3 D2 PCIE_CTX_GRX_P3 .1U_0402_10V6-K 1 2 CC17 PX@ PCIE_CTX_C_GRX_P3
DDRA_DQS#7 BA34 M_DQS_L7 M_DATA41 AN40 DDRA_DQ41 PCIE_CRX_GTX_N3 E7 P_GFX_RXN3 P_GFX_TXN3 D1 PCIE_CTX_GRX_N3 .1U_0402_10V6-K 1 2 CC18 PX@ PCIE_CTX_C_GRX_N3
TC15 @ 1T_DDRA_DQS8 AA40 M_DQS_H8 M_DATA42 AT41 DDRA_DQ42
TC16 @ 1T_DDRA_DQS#8 Y41 M_DQS_L8 M_DATA43 AU40 DDRA_DQ43 OK<19> PCIE_CRX_GTX_P[0..3]
ROUTE PCIE-LINK DIFF PAIR @ 85 OHM +/- 10%
PCIE_CTX_C_GRX_P[0..3] OK
<19>
M_DATA44 AL40 DDRA_DQ44
<14> DDRA_CLK0
DDRA_CLK0 AC35 M_CLK_H0 M_DATA45 AM40 DDRA_DQ45 OK<19> PCIE_CRX_GTX_N[0..3]
FT3 REV 0.53
PCIE_CTX_C_GRX_N[0..3] OK
<19>
DDRA_CLK0# AC34 M_CLK_L0 M_DATA46 AR40 DDRA_DQ46 @ Beema FT3-REV-0P53_BGA769
<14> DDRA_CLK0#
OK SODIMM0 DDRA_CLK1 AA34 M_CLK_H1 M_DATA47 AT40 DDRA_DQ47
<14> DDRA_CLK1
DDRA_CLK1# AA32 M_CLK_L1
<14> DDRA_CLK1#
DDRA_CLK2 AE38 M_CLK_H2 M_DATA48 AV41 DDRA_DQ48
<15> DDRA_CLK2
DDRA_CLK2# AE37 M_CLK_L2 M_DATA49 AW40 DDRA_DQ49
<15> DDRA_CLK2#
OK SODIMM1 DDRA_CLK3 AA37 M_CLK_H3 M_DATA50 BA38 DDRA_DQ55
<15> DDRA_CLK3
DDRA_CLK3# AA38 M_CLK_L3 M_DATA51 AY37 DDRA_DQ51
<15> DDRA_CLK3# swap DQ55 and DQ50 @ 09/06
M_DATA52 AU41 DDRA_DQ52
MEM_MA_RST# G38 M_RESET_L M_DATA53 AV40 DDRA_DQ53
<14,15> MEM_MA_RST#
MEM_MA_EVENT#AE34 M_EVENT_L M_DATA54 AY39 DDRA_DQ54
<14,15> MEM_MA_EVENT#
M_DATA55 AY38 DDRA_DQ50
DDRA_CKE0 L34 M0_CKE0
<14> DDRA_CKE0
OK SODIMM0 DDRA_CKE1 J38 M0_CKE1 M_DATA56 BA36 DDRA_DQ56
<14> DDRA_CKE1
DDRA_CKE2 J37 M1_CKE0 M_DATA57 AY35 DDRA_DQ57
<15> DDRA_CKE2
OK SODIMM1 DDRA_CKE3 J34 M1_CKE1 M_DATA58 BA32 DDRA_DQ58
<15> DDRA_CKE3
M_DATA59 AY31 DDRA_DQ59
DDRA_ODT0 AN38 M0_ODT0 M_DATA60 BA37 DDRA_DQ60
<14> DDRA_ODT0
OK SODIMM0 DDRA_ODT1 AU38 M0_ODT1 M_DATA61 AY36 DDRA_DQ61
<14> DDRA_ODT1
DDRA_ODT2 AN37 M1_ODT0 M_DATA62 BA33 DDRA_DQ62
<15> DDRA_ODT2
OK SODIMM1 DDRA_ODT3 AR37 M1_ODT1 M_DATA63 AY32 DDRA_DQ63
<15> DDRA_ODT3
B B
DDRA_CS0# AJ34 M0_CS_L0 M_CHECK0 V41
<14> DDRA_CS0#
OK SODIMM0 DDRA_CS1# AR38 M0_CS_L1 M_CHECK1 W40
<14> DDRA_CS1#
DDRA_CS2# AL38 M1_CS_L0 M_CHECK2 AB40
<15> DDRA_CS2#
OK SODIMM1 DDRA_CS3# AN35 M1_CS_L1 M_CHECK3 AC40 ECC
<15> DDRA_CS3#
M_CHECK4 U41
OK<14,15> DDRA_RAS#
DDRA_RAS# AJ37 M_RAS_L M_CHECK5 V40
OK<14,15> DDRA_CAS#
DDRA_CAS# AL34 M_CAS_L M_CHECK6 AA41
OK<14,15> DDRA_WE#
DDRA_WE# AL35 M_WE_L M_CHECK7 AB41
+VSYSMEM_APU
OK
+MEM_VREF AD40 M_VREF
@ 1 T_APU_M_VREFDQ AC38 M_VREFDQ M_ZVDDIO_MEM_S AD41 2 1
TC35 RC1 39.2_0402_1%
FT3 REV 0.53
@ Beema FT3-REV-0P53_BGA769 R103 connection to VDDIO_SUS should

be directly to the plane without a long trace
+VSYSMEM_APU
OK
1
RC4 MEM Reference Voltage
1K_0402_1%
EVENT# pull high
2
+MEM_VREF
+VSYSMEM_APU
OK
1
1000P_0402_50V7K
.1U_0402_10V6-K
.47U_0402_6.3V6K
RC5 1 1 1 UC1 UC1 UC1 UC1

CC115
1K_0402_1%
CC1
CC2
RC6 1 2 1K_0402_5% MEM_MA_EVENT#

@
2
2 2 2
BEEMA AM6400ITJ44JB 2.4G ZM181103J4470 1.8G ZM151103J4470 1.5G ZM1332M2J2370 1.35G

Layout: Place within 1000 SA000065O10 SA000067O00 SA000067P00 SA000067Q00
A mils of the APU socket. ZZZ A
PCB NM-A281
DA60000U810

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Beema (MEM & PCIE I/F)
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
Beema (DISPLAY/CLK/MISC)
@ S0
APU_SIC RC2281 TB RS 2 0_0402_5%
EC_SMB_CK2 <20,39,44>
@
APU_SID RC2291 TB RS 2 0_0402_5% +3VS
EC_SMB_DA2 <20,39,44>
RC67 1 2 1K_0402_5%
APU_CRT_HSYNC RC66 1 @ 2 1K_0402_5%
NOTE: APU_CRT_HSYNC PU FOR AMD INTERNAL,PD FOR CUSTOMER
D D
+3VS
OK APU_HDMI_DDC_CLK RC160 1 2 4.7K_0402_5%

OK APU_HDMI_DDC_DATA RC161 1 2 4.7K_0402_5%
UC1C OK APU_HDMI_HPD @ RC162 1 2 2.2K_0402_5%
DISPLAY/SVI2/JTAG/TEST OK APU_CRT_DDC_CLK RC53 2 1 4.7K_0402_5%
<34> APU_HDMI_TX2+
APU_HDMI_TX2+ A9 TDP1_TXP0 DP_150_ZVSSB16 DP_150_ZVSS RC10 1 2 150_0402_1% OK OK APU_CRT_DDC_DATA RC54 2 1 4.7K_0402_5%
<34> APU_HDMI_TX2-
APU_HDMI_TX2- B9 TDP1_TXN0 DP_2K_ZVSS A21 DP_2K_ZVSS RC11 1 2 2K_0402_1% OK +3VS
B17 O PCH_ENBKL
DP_BLON
PCH_ENBKL <33>OK
A17 O PCH_ENVDD
<33>OK
APU_HDMI_TX1+ A10 TDP1_TXP1 DP_DIGON
<34> APU_HDMI_TX1+ PCH_ENVDD
DP_VARY_BL A18 O PCH_EDP_PWM OK OK
OK HDMI <34> APU_HDMI_TX1-
APU_HDMI_TX1- B10 TDP1_TXN1
In I2C mode AUXP pins change to SCL, and AUXN pins change to PCH_EDP_PWM
SDA. <33>
OK
ALERT#
APU_PROCHOT#_R
RC13
RC14
2
2
1
1
1K_0402_5%
1K_0402_5%
APU_HDMI_TX0+ A11 DisplayPort Auxiliary Channel pins are dual-mode pins.
TDP1_TXP2
<34> APU_HDMI_TX0+
<34>OK
APU_HDMI_TX0- B11 D17 APU_HDMI_DDC_CLK The processor asserts PROCHOT_L when the hardware thermal control (HTC) is active.
TDP1_TXN2 TDP1_AUXP
<34> APU_HDMI_TX0- APU_HDMI_DDC_CLK
TDP1_AUXN E17 APU_HDMI_DDC_DATA
APU_HDMI_DDC_DATA OK
<34>
External hardware can assert PROCHOT_L to reduce
APU power consumption by forcing HTC activation.
APU_HDMI_CLK+ A12 TDP1_TXP3
<34> APU_HDMI_CLK+
APU_HDMI_CLK- B12 TDP1_TXN3 TDP1_HPD H19 IPD APU_HDMI_HPD OK
<34> APU_HDMI_CLK- APU_HDMI_HPD <34>
+1.8VS_APU
<33>OK
CPU_EDP_TX0+ A4 LTDP0_TXP0 LTDP0_AUXP D15 CPU_EDP_AUX
<33> CPU_EDP_TX0+ CPU_EDP_AUX
<33> CPU_EDP_TX0-
CPU_EDP_TX0- B4 LTDP0_TXN0 LTDP0_AUXN E15 CPU_EDP_AUX#
CPU_EDP_AUX# OK
<33>
OK eDP <33> CPU_EDP_TX1+
CPU_EDP_TX1+ A5 LTDP0_TXP1 LTDP0_HPD H17 IPD CPU_EDP_HPD CPU_EDP_HPD OK
<33>
RC31 1
RC32 1
2
2
300_0402_5%
300_0402_5%
APU_RST#
APU_PWROK
CPU_EDP_TX1- B5 LTDP0_TXN1
<33> CPU_EDP_TX1-
DAC_RED B14
APU_CRT_R OK
<36>
Net name changed to same as ACLU1 TC62 @ 1 T_TDP0_TXP2 A6 LTDP0_TXP2 RC21 1 2 150_0402_1% CPU_EDP_HPD RC163 1 2 100K_0402_5%
TC63 @ 1 T_TDP0_TXN2 B6 LTDP0_TXN2 DAC_GREEN A14
APU_CRT_G OK
<36>
RC22 1 2 150_0402_1%
TC52 @ 1 T_TDP0_TXP3 A7 LTDP0_TXP3 DAC_BLUE B15
APU_CRT_B OK
<36>
TC53 @ 1 T_TDP0_TXN3 B7 LTDP0_TXN3 RC23 1 2 150_0402_1%
2 Lane is OK to support FHD Panel

DAC_HSYNC G19 I/OAPU_CRT_HSYNC
APU_CRT_HSYNC <36>
TC17 @ 1 T_DISP_CLKP K15 DISP_CLKIN_H DAC_VSYNC E19 O
APU_CRT_VSYNC <36>
TC18 @ 1 T_DISP_CLKN H15 DISP_CLKIN_L STUDY
C DAC_SCL D19 APU_CRT_DDC_CLK C
I G31 APU_CRT_DDC_CLK <36>
OK <59> APU_SVT
APU_SVT SVT DAC_SDA D21 APU_CRT_DDC_DATA
APU_CRT_DDC_DATA <36>
SVID I/F: Do not terminate. OK <59> APU_SVC O D27 SVC
APU_SVC I/O E29
Avoid plane splits and signal plane changes,
route on single routing layer. OK <59> APU_SVD
APU_SVD SVD DAC_ZVSS A16 DAC_ZVSS RC18 1 2 499_0402_1% OK
OK APU_SIC B22 SIC TEST4 H27 APU_TEST4_THERMDA 1 @ TC19
OK 3.3V Level APU_SID B21 SID TEST5 H29 APU_TEST5_THERMDC 1 @ TC20 Thermal Sensor?
TEST6 D25 APU_TEST6 NC 1 @ TC21
OK 1.8V APU_RST# I B20 APU_RST_L TEST14 A27 APU_TEST14_BP0 RC55 1 @ 2 1K_0402_5%
RC28 1 Kabini@ 2 0_0402_5% APU_RST#_R OD A20 LDT_RST_L TEST15 B27 APU_TEST15_BP1 RC56 1 @ 2 1K_0402_5%
Output to APU Vcore VR SVID EN Pin A20 For STAMP APU_TEMPIN1 A26 APU_TEST16_BP2 RC57 1 @ 2 1K_0402_5%
TEST16
OK <59> 1.8V APU_PWROK I B19 APU_PWROK TEST17 B26 APU_TEST17_BP3 RC58 1 @ 2 1K_0402_5% OK
APU_PWROK OD A19
RC29 1 Kabini@ 2 0_0402_5% APU_PWROK_R LDT_PWROK TEST18 B28 I APU_TEST18_PLLTEST1 RC44 1 2 1K_0402_5%
@ A19 For STAMP APU_TEMPIN2
TEST19 A28 I APU_TEST19_PLLTEST0 RC45 1 2 1K_0402_5%
B24 I +1.8VS_APU
OK
<44> H_PROCHOT# RC147 1 2 0_0402_5% APU_PROCHOT#_R A22 PROCHOT_L TEST25_H RC59 1
APU_TEST25_H_BYPASSCLK 2 510_0402_1%
TB RS
1 1 OK ALERT# OD B18 ALERT_L TEST25_L A24 I RC1491
APU_TEST25_L_BYPASSCLK 2 510_0402_1%
TEST28_H AV35 APU_TEST28_H_PLLCHARZ 1 @ TC22
CC3 CC4 APU_TDI D29 TDI TEST28_L AU35 APU_TEST28_L_PLLCHARZ 1 @ TC23
150P_0402_50V8-J 150P_0402_50V8-J APU_TDO D31 TDO TEST31 E33 APU_TEST31_MEM_TEST 1 @ TC24 +1.8VS_APU
@ 2 2 @ APU_TCK D35 TCK
A29 For STAMP APU_TEMPIN0
APU_TMS D33 TMS RSVD A29 APU_TEST34_L_TSTCLKIN_L 1 @ TC28 RC60 1 @ 2 1K_0402_5%
APU_TRST# G27 TRST_L TEST36 H21 APU_TEST36 RC61 1 @ 2 1K_0402_5%
APU_DBRDY B25 DBRDY TEST37 H25 APU_TEST37 RC62 1 @ 2 1K_0402_5%
1.8V APU_DBREQ# A25 DBREQ_L RC63 1 @ 2 1K_0402_5%
TEST42 AJ10 APU_TEST42_USB_ATEST0 1 @ TC25
OK
<59> APU_VDDNB_SEN_H
D23 VDDCR_NB_SENSE TEST43 AJ8 APU_TEST43_USB_ATEST1 1 @ TC26 OK
OK
<59> APU_VDD_SEN_H
G23 VDDCR_CPU_SENSE TEST39 R32 APU_TEST39 1 @ TC29
TC31 @ 1 VDDIO_SUS_SENSE E25 VDDIO_MEM_S_SENSE TEST40 N32 APU_TEST40 1 @ TC30
+1.8VS_APU
OK
<59> APU_VDD_SEN_L
E23 VSS_SENSE TEST41 AP29 APU_TEST41_TMON_CAL 1 @ TC27
TC60 @ 1 VDD_095_FB_H AV33 VDD_095_FB_H DP_STEREOSYNC E21 O APU_TEST35_STEREOSYNC RC65 1 @ 2 1K_0402_5%

TC61 @ 1 VDD_095_FB_L AU33 VDD_095_FB_L
To drive active shutter glasses for RC64 1 @ 2 1K_0402_5%
stereoscopic 3D viewing on 120-Hz panels
VDDIO_MEM & VDD_0.95 return path is optional, so remove.
FT3 REV 0.53
B @ Beema FT3-REV-0P53_BGA769 B
OK
+1.8VS_APU +1.8VS_APU HDT+ Header +1.8VS_APU
+1.8VS_APU +1.8VS_APU
JHDT1 @ RCP4 HDT@
1 1 2 APU_TCK 8 1
1 2
1
HDT@ 7 2
1
CC5 RC38 3 4 APU_TMS 6 3

.1U_0402_10V6-K RC27 RC33 1K_0402_5% 3 4 5 4
HDT@ 2 300_0402_5% 300_0402_5% 5 6 APU_TDI
HDT@ HDT@ 5 6 1K_0804_8P4R_5%
A A
2
.1U_0402_10V6-K
UC2 HDT@ 7 8 APU_TDO 1

2
APU_PWROK 3 4 APU_PWROK_BUF 7 8 CC29

2A 2Y APU_TRST# 9 10 APU_PWROK_BUF
2 5 9 10
GND VCC 1 8 11 12 APU_RST#_BUF 2
APU_RST# 1 6 APU_RST#_BUF 2 7 11 12
1A 1Y 3 6 13 14 APU_DBRDY
SN74LVC2G07YZPR_WCSP6 Change to SN74LVC2G07DCK SOT 4 5 13 14
15 16 APU_DBREQ#
10K_0804_8P4R_5% 15 16
APU_PWROK RC2031 @ 2 0_0402_5% APU_PWROK_BUF RCP1 HDT@ 17 18 APU_TEST19_PLLTEST0
APU_RST# RC1931 @ 2 0_0402_5% APU_RST#_BUF 17 18
19 20 APU_TEST18_PLLTEST1
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Beema (DISPLAY/CLK/MISC)
19 20
SAMTE_ASP-136446-07-B Zx05 Symbol

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
Beema (GEVENT/GPIO/SD/AZ) Broad ID OK SMB_CLK_S3 OK

+3VS
PLT_RST# & APU_LPC_RST OK ID0 HI is 15' , LO is 14'
+3VS
<19,37,40> PLT_RST#
RC75 1 2 33_0402_5% PCIE_RST#_R ID1 HI is UMA , LO is DIS
2
1 RC186 RC185 RC190 RC210
1
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
RC78 CC121 15@ UMA@ @ @ RC170 RC171 DIMM1, DIMM2, Mini CARD
100K_0402_5% 150P_0402_50V8-J 2.2K_0402_5% 2.2K_0402_5%
1
@ 2 GPIO49 BOARD_ID0 Default is H
GPIO51 BOARD_ID1
2
GPIO71 BOARD_ID2
GPIO70 BOARD_ID3 SMB_CLK_S3
SMB_CLK_S3 <14,15,40>
RC74 1 2 33_0402_5% LPC_RST#_R
<44> APU_LPC_RST#
2
1 RC187 RC189 RC188 RC209
D D
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
CC6 14@ PX@ @
150P_0402_50V8-J SMB_DATA_S3
SMB_DATA_S3 <14,15,40>
1
2
GPIO49/51/71 require external PH or PL, so used for Board ID

GPIO70 is reserved and has interanl PH
RSMRST# OK RCP2
+3VS
OK CMOS_ON# 8 1
OK PCH_BT_OFF# 7 2
+3VALW_EC +3VALW +1.8VALW_APU OK PCH_WLAN_OFF# 6 3
5 4
1
1
100K_0402_5%
@ 10K_0804_8P4R_5%
1
10K_0402_5%
RC82 OK
RC86 10ms T (CRB PWR Dealy: 47K/1uF) UC1D Provided test points or other means to
allow access for debug purposes. OK LAN_CLKREQ# 10K_0402_5% 2 1 RC168
RC81 ACPI/SD/AZ/GPIO/RTC/MISC WLAN_CLKREQ# 10K_0402_5% 2 @ 1 RC169
DC2 10K_0402_5% LPC_RST#_R O AY4 LPC_RST_L SD_PWR_CTRL BA23 SD_PWR_CNTL 1 @ TC36 CLK_REQ#0 10K_0402_5% 2 @ 1 RC172
2
PCIE_RST#_R O AY9 PCIE_RST_L SD_CLK/GPIO73 AY22 I PU SD_CLK_R 1 @ TC37 CLK_REQ#3 10K_0402_5% 2 @ 1 RC173
2
1 2 RSMRST#_R GPU_CLKREQ# 10K_0402_5% 2 @ 1 RC174

<44> EC_RSMRST# 1.8V RSMRST#_R I AY5
1 RSMRST_L SD_CMD/GPIO74 AY23 I PUSD_CMD_R 1 @ TC38 VGA_PWROK_R 10K_0402_5% 2 @ 1 RC230
RB751V-40_SOD323-2 CC122 SD_CD/GPIO75 AY20 I PU SD_CD# 1 @ TC39
1U_0402_6.3V6K PBTN_OUT# RC79 1 TB @
RS 2 0_0402_5% PWRBTN#_R I BA8 PWR_BTN_L SD_WP/GPIO76 BA20 I PU SD_WP 1 @ TC40
<44> PBTN_OUT# 1.8V IAM19
Need update symobol @ SYS_PWRGD_R PWR_GOOD
2 IPU S5 Strap Pin PH I PU AY7 SYS_RESET_L/GEVENT19_L SD_DATA0/GPIO77 BA22 I PUSD_DATA0_R 1 @ TC41 +3VALW_APU
<9> SYS_RESET#
SB00000PF0J Panjit: BSS138 PCIE_WAKE#_RA I PUAW11 WAKE_L/GEVENT8_L SD_DATA1/GPIO78 AY21 I PUSD_DATA1_R 1 @ TC42
SD_DATA2/GPIO79 AY24 I PUSD_DATA2_R
SB50111001J NXP: BSH111 TB RS 1 @ TC43 PCIE_WAKE#_RA 100K_0402_5% 2 1 RC91
Other one: FDV301N OR AO3414 PM_SLP_S3# RC87 1 TB @
RS 2 0_0402_5% PM_SLP_S3#_R O AY3 SLP_S3_L SD_DATA3/GPIO80 BA24 I PUSD_DATA3_R 1 @ TC44 PBTN_OUT# 10K_0402_5% 2 1 RC83
<44> PM_SLP_S3# O BA5
+3VALW_EC +3VALW +1.8VALW_APU PM_SLP_S5# RC88 1 @ 2 0_0402_5% PM_SLP_S5#_R SLP_S5_L PM_SLP_S3# 2.2K_0402_5% 2 @ 1 RC89
<44> PM_SLP_S5# S4/S5 is Low TB RS
SD_LED/GPIO45 AY25 O SD_LED 1 @ TC45 PM_SLP_S5# 2.2K_0402_5% 2 @ 1 RC90
TC51 @ 1 APU_TEST0 AU13 TEST0 AC_PRESENT_R 10K_0402_5% 2 1 RC208
1
1
100K_0402_5%
@ TC64 @ 1 APU_TEST1 AY10 TEST1/TMS SCL0/GPIO43 AU25 SMB_CLK_S3 OK S0 PWR Domain ODD_EN 10K_0402_5% 2 1 RC214
1
10K_0402_5%
RC84 TC65 @ 1 APU_TEST2 AY6 TEST2 SDA0/GPIO47 AV25 SMB_DATA_S3 OK S5 PWR Domain ODD_DETECT# 10K_0402_5% 2 1 RC218
RC93 OK APU_SCLK1 2.2K_0402_5% 2 @ 1 RC109
RC85 I PU AR23 KBRST_L SCL1/GPIO227 AY11 APU_SCLK1 RC164 1 2 10K_0402_5% OK APU_SDATA1 2.2K_0402_5% 2 @ 1 RC110
<44> KBRST# I PU
C DC4 10K_0402_5% AR31 GA20IN/GEVENT0_L SDA1/GPIO228 BA11 APU_SDATA1 RC165 1 2 10K_0402_5% ODD_DA# 10K_0402_5% 1 @ 2 RC219 C
<44> GATEA20
2
I PU AN5 LPC_PME_L/GEVENT3_L OK APU_GEVENT22# 10K_0402_5% 1 2 RC216

<44> EC_SCI#
2
1 2 SYS_PWRGD_R I PU AL7 LPC_SMI_L/GEVENT23_L GPIO49 AP27 I S0 GPI BOARD_ID0 OK USB_OC0# 10K_0402_5% 2 @ 1 RC94
<44> EC_SYS_PWRGD
GPIO50 AY28 CMOS_ON# USB_OC1# 10K_0402_5% 2 1 RC95
I S0 GPI CMOS_ON# <33>
OK
OK
RB751V-40_SOD323-2 1 GPIO51 BA28 BOARD_ID1 USB_OC2# 10K_0402_5% 2 1 RC96
CC9 AC_PRESENT_R I PU AP15 AC_PRES/IR_RX0/GEVENT16_L DEVSLP[0]/GPIO55 AV23 IPU S0 =>GPO
RC194 2 @ 1 0_0402_5% OK USB_OC3# 10K_0402_5% 2 @ 1 RC97
IPU S0 =>GPO SATA0_DEVSLP <42>
Need update symobol 1U_0402_6.3V6K ODD_DETECT# GPI IPU S5 AV13 IR_TX0/GEVENT21_L GPIO57 AP21 PCH_BT_OFF# OK
<42> ODD_DETECT# IPU S0 =>GPO PCH_BT_OFF# <40>
2
@ TC48 @ 1 IR_TX1 BA9 IR_TX1/GEVENT6_L GPIO58 BA26
IPU S0 GPI
PCH_WLAN_OFF#
PCH_WLAN_OFF# OK
<40>
TC49 @ 1 IR_RX1 BA10 IR_RX1/GEVENT20_L DEVSLP[1]/GPIO59 AV19 APU_GPIO59 1
ODD_EN =>GPO IPU S5 AV15 IR_LED_L/LLB_L/GPIO184 GPIO64 AY27 IPU S0 =>GPO PXS_RST#_R @ TC57
@TC57 OK APU_TEST2 15K_0402_5% 2 1 RC16
<42> ODD_EN
SPKR/GPIO66 BA27
PCH_BEEP OK
<43>
APU_TEST1 15K_0402_5% 2 1 RC3
CLK_REQ#0 I PU AU29 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 GPIO68 AU21 IPU S0 =>GPO PXS_PWREN_R APU_TEST0 15K_0402_5% 2 1 RC2
I PU AW29 IPU S0 =>GPO
EC_WAKE# OK <40> WLAN_CLKREQ#
WLAN_CLKREQ#
LAN_CLKREQ# I PU AR27
CLK_REQ1_L/GPIO61
CLK_REQ2_L/GPIO62
GPIO69
GPIO70
AY26
AV21 IPU S0 GPI
VGA_PWROK_R
BOARD_ID3
GPU_CLKREQ# 10K_0402_5% 2
RSMRST#R PD is support Mirror core
1 RC204
<37> LAN_CLKREQ# I PU AV27 I S0 GPI
CLK_REQ#3 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 GPIO71 AM21 BOARD_ID2 RSMRST#_R 100K_0402_5% 2 1 RC206
PCIE_WAKE#_RA 2 @ 1 RC192 GPU_CLKREQ# I PU AY29 CLK_REQG_L/GPIO65/OSCIN GPIO174 BA3 I S5 APU_GPIO174 SYS_PWRGD_R 100K_0402_5% 2 @ 1 RC207
<20> GPU_CLKREQ#
0_0402_5% HDA_BITCLK 10K_0402_5% 1 @ 2 RC103
USB_OC0# AY8 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L GEVENT2_L AV17 Strap Pin PL OK HDA_SDIN0_R 10K_0402_5% 1 @ 2 RC104
GEVENT2# <9>
APU_GEVENT22# 2 @ 1 RC184 EC_WAKE# <44> USB_OC1# AW1 USB_OC1_L/TDI/GEVENT13_L GEVENT4_L BA4 APU_GEVENT4# HDA_SDIN1 10K_0402_5% 1 @ 2 RC105
<41>
OC1# for USB2.0x1 USB_OC1#
0_0402_5% USB_OC2# AV1 USB_OC2_L/TCK/GEVENT14_L GEVENT7_L AR15 APU_GEVENT7# HDA_SDIN2 10K_0402_5% 1 @ 2 RC106
<45>
OC1# for USB3.0x2 USB_OC2#
USB_OC3# AY1 USB_OC3_L/TDO/GEVENT15_L GEVENT10_L AP17 APU_GEVENT10#1 @ TC54 HDA_SDIN3 10K_0402_5% 1 @ 2 RC107
2 1 Integrated PU is not supported when the pin is configured for USB over current function
DC3 GEVENT11_L AP11 APU_GEVENT11#1 @ TC55
HDA_BITCLK AN2 AZ_BITCLK GEVENT17_L AN8 IPU S5 ODD_DA# OK
Strap Pin PH IPU S5 ODD_DA# <42>
<9> OK
SDM10U45LP-7_DFN1006-2-2 HDA_SDOUT AN1 AZ_SDOUT BLINK/GEVENT18_L AU17
IPU S5 GPI BLINK
@ RC1021 @ 2 0_0402_5% HDA_SDIN0_R AK2 AZ_SDIN0/GPIO167 GEVENT22_L BA6 APU_GEVENT22#
<43> HDA_SDIN0
HDA_SDIN1 AK1 AZ_SDIN1/GPIO168 OK
HDA_SDIN2 AM1 AZ_SDIN2/GPIO169 GENINT1_L/GPIO32 BA29 APU_GPIO321 @ TC56
HDA_SDIN3 AL2 AZ_SDIN3/GPIO170 GENINT2_L/GPIO33 AP23 IPU S0 GPI VR_VGA_PWRGD OK
VR_VGA_PWRGD <19,58>
HDA_SYNC AM2 AZ_SYNC
HDA_RST# AL1 AZ_RST_L FANOUT0/GPIO52 AV31 APU_GPIO521 @ TC58
FANIN0/GPIO56 AU31 APU_GPIO561 @ TC59
+3VS 32K_X1 AJ2 X32K_X1

These 3 GPIO pin use same one as Kabini CRB.
RC221 1 PX@ 2 10K_0402_5% PXS_PWREN_R
Strap Pin PH IPU S5
<40,9>OK
RTCCLK AV11
SUSCLK
RC222 1 PX@ 2 10K_0402_5% PXS_RST#_R YC1 1 2 32K_X2 AJ1 X32K_X2
FT3 REV 0.53
RC223 1 @ 2 10K_0402_5% VR_VGA_PWRGD 32.768KHZ_12.5PF_200458-PG14 @ Beema FT3-REV-0P53_BGA769

VGA VR side has PH to +3VS
B B
RC108 1 2
1 20M_0402_5% 1
CC118 CC119
RC224 1 @ 2 100K_0402_5% PXS_PWREN_R 20P_0402_50V8 20P_0402_50V8
2 2
RC225 1 @ 2 100K_0402_5% PXS_RST#_R
RC205 1 UMA@ 2 2K_0402_5% VR_VGA_PWRGD VIL Max is 0.7V
OK <44> AC_PRESENT
RC92 1 @ 2 0_0402_5% AC_PRESENT_R
OK <23,58> PXS_PWREN
RC12 1 PX@ 2 1K_0402_5% PXS_PWREN_R
OK <19> PXS_RST#
RC9 1 PX@ 2 0_0402_5% PXS_RST#_R
OK
<19,44,58> VGA_PWROK
RC15 1 PX@ 2 0_0402_5% VGA_PWROK_R
+3VALW_APU Output to GPU Vcore VR SVID EN Pin
APU_GEVENT4# 10K_0402_5% 1 @ 2 RC226 1

APU_GEVENT7# 10K_0402_5% 1 @ 2 RC227 CC141
APU_GPIO174 10K_0402_5% 1 @ 2 RC211 .1U_0402_10V6-K
@
RCP3 2
APU_GPIO174 8 1
APU_GEVENT4# 7 2
APU_GEVENT7# 6 3
5 4
10K_0804_8P4R_5%
A A
RCP6
1 8 HDA_RST#
<43> HDA_RST_AUDIO#
2 7 HDA_SYNC
<43> HDA_SYNC_AUDIO
3 6 HDA_BITCLK
<43> HDA_BITCLK_AUDIO
4 5 HDA_SDOUT
<43> HDA_SDOUT_AUDIO
33_0804_8P4R_5%
T PN change Idea pad PN:SD300003700
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Beema (GEVENT/GPIO/SD/AZ)
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
Beema (SATA/USB/LPC/SPI/CLK)
D D
Net name changed to same as ACLU1 UC1E

CLK/SATA/USB/SPI/LPC
SATA_PTX_DRX_P0 BA14 SATA_TX0P W4
USBCLK/14M_25M_48M_OSC CLK_USB48M 1 @ TC34
<42> SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 AY14 SATA_TX0N
<42> SATA_PTX_DRX_N0
OK HDD USB_ZVSS AG4 USB_RCOMP RC138 1 2 11.8K_0402_1% OK
SATA_PRX_DTX_N0 BA16 SATA_RX0N
<42> SATA_PRX_DTX_N0
<42> SATA_PRX_DTX_P0
SATA_PRX_DTX_P0 AY16 SATA_RX0P USB_HSD0P AL4 USB20_P0
USB20_P0 OK
<45>
USB_HSD0N AL5 USB20_N0
USB20_N0 OK
<45> RIGHT USB (2.0)
<42> SATA_PTX_DRX_P1
SATA_PTX_DRX_P1 AY19 SATA_TX1P AMD Debug port!
SATA_PTX_DRX_N1 BA19 SATA_TX1N USB_HSD1P AJ4
<42> SATA_PTX_DRX_N1
OK ODD SATA_PRX_DTX_N1 AY17 SATA_RX1N
USB_HSD1N AJ5
<42> SATA_PRX_DTX_N1
<42> SATA_PRX_DTX_P1
SATA_PRX_DTX_P1 BA17 SATA_RX1P USB_HSD2P AG7 USB20_P3
USB20_P3 OK
<45>
USB_HSD2N AG8 USB20_N3 OK Card Reader P2
+0.95VS_APU USB20_N3 <45>
RC114 1 2 1K_0402_1% SATA_CALRN AR19 SATA_ZVSS
OK RC115 1 2 1K_0402_1% SATA_CALRP AP19 SATA_ZVDD_095 USB_HSD3P AG1 USB20_P2

USB20_P2 OK
<41>
P2&P3 exchanged as layout request @ 09/12
USB_HSD3N AG2 USB20_N2 OK LEFT USB (2.0) P3
+3VS USB20_N2 <41>
2 10K_0402_5% APU_GPIO67 O BA30 OK
OK RC113 1 @ SATA_ACT_L/GPIO67 USB_HSD4P
USB_HSD4N
AF1
AF2
USB20_P4
USB20_N4
USB20_P4 <33>
OK Touch Screen
USB20_N4 <33>
AY12 SATA_X1
USB_HSD5P AE1 USB20_P5
USB20_P5 OK
<33>
If the integrated clock generator is used,
these pins are left unconnected.
USB_HSD5N AE2 USB20_N5
USB20_N5 OK
<33> Camera
BA12 SATA_X2 USB_HSD6P AD1 USB20_P6
USB20_P6 OK
<40>
USB_HSD6N AD2 USB20_N6
USB20_N6 OK
<40> Blue Tooth
CLK_PCIE_GPU RC116 1 @ 2 0_0402_5% CLK_PCIE_GPU_R U4 GFX_CLKP USB_HSD7P AC1
<19> CLK_PCIE_GPU
OK
<19> CLK_PCIE_GPU#
CLK_PCIE_GPU# RC117 1 @ 2 0_0402_5% CLK_PCIE_GPU#_R U5 GFX_CLKN USB_HSD7N AC2
AC8 GPP_CLK0P USB_HSD8P AB1 USB20_P1

USB20_P1 <41> P8
AC10 GPP_CLK0N USB_HSD8N AB2 USB20_N1
USB20_N1 OK
<41> LEFT USB (3.0)
<40> CLK_PCIE_WLAN
CLK_PCIE_WLAN RC118 1 @ 2 0_0402_5% CLK_PCIE_WLAN_R AE4 GPP_CLK1P USB_HSD9P AA1 Net name changed to same as ACLU1
C
OK <40> CLK_PCIE_WLAN#
CLK_PCIE_WLAN# RC119 1 @ 2 0_0402_5% CLK_PCIE_WLAN#_R AE5 GPP_CLK1N USB_HSD9N AA2
C
+0.95VALW_USB3
<37> CLK_PCIE_LAN
CLK_PCIE_LAN RC120 1 @ 2 0_0402_5% CLK_PCIE_LAN_R AC4 GPP_CLK2P USB_SS_ZVSS AE10 USBSS_CALRN RC130 1 2 1K_0402_1% OK
OK <37> CLK_PCIE_LAN#
CLK_PCIE_LAN# RC121 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R AC5 GPP_CLK2N AE8
USB_SS_ZVDD_095_USB3_DUAL USBSS_CALRP RC131 1 2 1K_0402_1% OK
AA5 GPP_CLK3P USB_SS_0TXP T2 USB30_TX_P1
USB30_TX_P1 <41>
AA4 GPP_CLK3N USB_SS_0TXN T1 USB30_TX_N1
USB30_TX_N1 <41>
LEFT USB (3.0)OK
TC32 @ 1 X14M_25M_48M_OSC O AP13 X14M_25M_48M_OSC USB_SS_0RXP V2 USB30_RX_P1
USB30_RX_P1 <41>
USB_SS_0RXN V1 USB30_RX_N1
USB30_RX_N1 <41>
48M_X1 N2 X48M_X1
USB_SS_1TXP R1 Net name changed to same as ACLU1
OK USB_SS_1TXN R2
48M_X2 N1 X48M_X2 USB_SS_1RXP W1

USB_SS_1RXN W2
OK RC122 1 2 33_0402_5% LPCCLK0 Strap Pin PL AY2 LPCCLK0

<44,9> CLK_PCI_EC Strap Pin PH AW2
OK <9> LPC_CLK1
RC123 1 2 0_0402_5% LPCCLK1 LPCCLK1 SPI_CLK/GPIO162 AU7 SPI_CLK_R RC135 1 @ 2 0_0402_5% SPI_CLK
SPI_CLK <44>
@ SPI_CS1_L/GPIO165 AW9 SPI_CS0#_R RC134 1 @ 2 0_0402_5% SPI_CS0#
SPI_CS0# <44>
OK<44> LPC_AD0
AT2 LAD0 SPI_CS2_L/GPIO166 AR4
OK<44> LPC_AD1
AT1 LAD1 10
SPI_DO/GPIO163 AR11 SPI_SI_R RC136 1 @ 2 0_0402_5% SPI_SI
SPI_SI <44> OK
OK<44> LPC_AD2 AR2 LAD2 SPI_DI/GPIO164 AR7 SPI_SO_R RC137 1 @ 2 0_0402_5% SPI_SO
SPI_SO <44>
OK<44> LPC_AD3 AR1 LAD3 10
SPI_HOLD_L/GEVENT9_L AU11 SPI_HOLD#_R RC178 1 @ 2 0_0402_5% SPI_HOLD#
OK Strap Pin PH AP2 LFRAME_L SPI_WP_L/GPIO161 AU9 SPI_WP#_R RC179 1 @ 2 0_0402_5% SPI_WP#
<44,9> LPC_FRAME#
TC47 @ 1 AP1 LDRQ0_L
OK <44> SERIRQ AV29 SERIRQ/GPIO48
TC33 @ 1 AP25 LPC_CLKRUN_L
TC46 @ 1 AV2 LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L
FT3 REV 0.53
@ Beema FT3-REV-0P53_BGA769
OK
+3VALW_APU +3VS APU SPI is ALW PWR +3V_SPI
B B
RC175 1 @ 2 0_0402_5%
+3V_SPI
RC125 1 @ 2 0_0402_5%
TB RS
8M ROM +3V_SPI
RC127 1 2 10K_0402_5% SPI_WP#

RC128 1 2 10K_0402_5% SPI_HOLD#
RC129 1 2 10K_0402_5% SPI_CS0#
Change to PR???
48MHz/10pF Crystal
@
SPI_CLK RC126 1 @ 2 10_0402_5% CC127 1 2 10P_0402_50V8J
For EMI
48M_X1 OK
+3V_SPI
48M_X2 OK 8MB SPI ROM
SA000039A2J 64M W25Q64FVSSIG
1
RC191 1 2 1M_0402_5% SA00005Z100 64M GD25B64BSIGR
CC10
.1U_0402_10V6-K
YC2 UC5 2
SPI_CS0# 1 8
1 4 CS# VCC
OSC1 NC2 SPI_SO 2 7 SPI_HOLD#
2 3 DO HOLD#
NC1 OSC2 SPI_WP# 3 6 SPI_CLK
A A
WP# CLK
1 1
48MHZ_10PF_7V48000017 4 5 SPI_SI
CC123 CC124 GND DI
12P_0402_50V8-J 12P_0402_50V8-J
2 2
W25Q64FVSSIG_SO8

SJ10000IO00 TXC: 7V48000017 (48MHz) Issued Date 2013/08/15 Deciphered Date 2013/08/15 Beema (SATA/USB/LPC/SPI/CLK)
Change to 15pF as vendor suggest THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
C
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
Beema (POWER & DECOUPLING)

+1.35V J10 +VSYSMEM APU GND
2 1
2 1
@ JUMP_43X118
Need Short
+3VS +3VS_APU UC1G
+1.8VS_APU +1.8VS
@
200mA All RLC follow CRB, need dobulc check with DG. @
UC1H
GND GND
RC30 1 2 0_0603_5% CC69 1 2 1U_0402_6.3V6K RC1321 TB @
RS 2 0_0603_5% A8 J3 W29 AL39
VSS_1 VSS_63 VSS_125 VSS_187
RC1331 2 0_0603_5% A13 VSS_2 VSS_64 J7 W39 VSS_126 VSS_188 AL41
TB RS CC71 1 2 1U_0402_6.3V6K TB RS A23 For STAMP APU_TEMPRETURN A23 J8 W41 AM11
+VSYSMEM +VSYSMEM_APU UC1F +APU_CORE CC66 1 2 10U_0603_6.3V6M A31 VSS_4 VSS_66 J39 Y1 VSS_128 VSS_190 AM27
@J8
@ J8 POWER 20/25A A35 VSS_5 VSS_67 K11 Y2 VSS_129 VSS_191 AM31
CC72 1 2 180P_0402_50V8-J 1 2 J35 VDDIO_MEM_S_1 VDDCR_CPU_1 L21 A39 VSS_6 VSS_68 K13 AA3 VSS_130 VSS_192 AN3
D D
2.9A L32 VDDIO_MEM_S_2 VDDCR_CPU_2 L23 CC67 1 2 1U_0402_6.3V6K B8 VSS_7 VSS_69 K17 AA7 VSS_131 VSS_193 AN7
PAD-OPEN 4x4m L37 VDDIO_MEM_S_3 VDDCR_CPU_3 L25 B13 VSS_8 VSS_70 K19 AA8 VSS_132 VSS_194 AN39
N35 VDDCR_CPU_4 L27 CC73 1 2 1U_0402_6.3V6K B23 K21 AA11 AP31
Need Short R31
VDDIO_MEM_S_4
VDDIO_MEM_S_5 VDDCR_CPU_5 L29 B31
VSS_9
VSS_10
VSS_71
VSS_72 K23 AA15
VSS_133
VSS_134
VSS_195
VSS_196 AR3
R37 VDDIO_MEM_S_6 VDDCR_CPU_6 N21 CC68 1 2 1U_0402_6.3V6K B39 VSS_11 VSS_73 K25 AA19 VSS_135 VSS_197 AR13
+3VALW_APU @J13
@ J13 U32 VDDIO_MEM_S_7 VDDCR_CPU_7 N23 C1 VSS_12 VSS_74 K27 AA25 VSS_136 VSS_198 AR17
1 2 U35 VDDIO_MEM_S_8 VDDCR_CPU_8 N27 CC74 1 2 1U_0402_6.3V6K C2 VSS_13 VSS_75 K29 AA29 VSS_137 VSS_199 AR21
W31 VDDIO_MEM_S_9 VDDCR_CPU_9 R21 C5 VSS_14 VSS_76 K31 AA39 VSS_138 VSS_200 AR25
PAD-OPEN 4x4m W32 VDDIO_MEM_S_10 VDDCR_CPU_10 R23 CC75 1 2 1U_0402_6.3V6K C7 VSS_15 VSS_77 L3 AC3 VSS_139 VSS_201 AR29
CC102 1 2 1U_0402_6.3V6K W37 VDDCR_CPU_11 R27 C9 L7 AC7 AR39
Need Short AA31
VDDIO_MEM_S_11
VDDIO_MEM_S_12 VDDCR_CPU_12 U21 CC76 1 2 1U_0402_6.3V6K C11
VSS_16
VSS_17
VSS_78
VSS_79 L8 AC11
VSS_140
VSS_141
VSS_202
VSS_203 AR41
CC101 1 2 1U_0402_6.3V6K AA35 VDDIO_MEM_S_13 VDDCR_CPU_13 U23 C13 VSS_18 VSS_80 L10 AC15 VSS_142 VSS_204 AU1
AC32 VDDIO_MEM_S_14 VDDCR_CPU_14 U27 CC77 1 2 1U_0402_6.3V6K C15 VSS_19 VSS_81 L11 AC19 VSS_143 VSS_205 AU2
AC37 VDDIO_MEM_S_15 VDDCR_CPU_15 W21 C17 VSS_20 VSS_82 L15 AC25 VSS_144 VSS_206 AU3
AE31 VDDIO_MEM_S_16 VDDCR_CPU_16 W23 C19 VSS_21 VSS_83 L19 AC29 VSS_145 VSS_207 AU15
AE35 VDDIO_MEM_S_17 VDDCR_CPU_17 W27 CC70 1 2 180P_0402_50V8-J C21 VSS_22 VSS_84 L31 AC31 VSS_146 VSS_208 AU19
AG32 VDDIO_MEM_S_18 VDDCR_CPU_18 AA21 C23 VSS_23 VSS_85 L39 AC39 VSS_147 VSS_209 AU23
AG37 VDDIO_MEM_S_19 VDDCR_CPU_19 AA23 C25 VSS_24 VSS_86 L41 AC41 VSS_148 VSS_210 AU27
AJ35 VDDIO_MEM_S_20 VDDCR_CPU_20 AA27 C27 VSS_25 VSS_87 M1 AE3 VSS_149 VSS_211 AU39
AL32 VDDIO_MEM_S_21 VDDCR_CPU_21 AC21 C29 VSS_26 VSS_88 M2 AE7 VSS_150 VSS_212 AV9
AL37 VDDIO_MEM_S_22 VDDCR_CPU_22 AC23 C31 VSS_27 VSS_89 N3 AE25 VSS_151 VSS_213 AW3
+1.8VALW +1.8VALW_APU AR35 VDDIO_MEM_S_23 VDDCR_CPU_23 AC27 C33 VSS_28 VSS_90 N7 AE29 VSS_152 VSS_214 AW7
@ @ VDDCR_CPU_24 AE21 C35 VSS_29 VSS_91 N15 AE32 VSS_153 VSS_215 AW13
RC1401 2 0_0603_5% CC117 1 2 180P_0402_50V8-J VDDCR_CPU_25 AE23
+VDDIO_AZ_APU +1.5VS C37 VSS_30 VSS_92 N19 AE39 VSS_154 VSS_216 AW15
VDDCR_CPU_26 AE27
+APU_CORE_NB C39 N25 AG3 AW17
1 VSS_31 VSS_93 VSS_155 VSS_217
TB RS RC139 1 TB @
RS 2 0_0402_5% C41 N29 AG5 AW19
CC93 CC126 1 2 4.7U_0603_6.3V6K VDDCR_NB_1 L13 13/17A Wake-on-Ring supported: Connect to +1.5V S5 rail
D9 VSS_33 VSS_95 N31 AG10 VSS_157 VSS_219 AW21
180P_0402_50V8-J VDDCR_NB_2 L17 D11 VSS_34 VSS_96 N39 AG11 VSS_158 VSS_220 AW23
2 VDDCR_NB_3 N11
Wake-on-Ring not supported: Connect to +1.5V S0 rail D13 VSS_35 VSS_97 P1 AG13 VSS_159 VSS_221 AW25
CC94 1 2 1U_0402_6.3V6K VDDCR_NB_4 N13 E3 VSS_36 VSS_98 P2 AG15 VSS_160 VSS_222 AW27
VDDCR_NB_5 N17 CC125 1 2 4.7U_0603_6.3V6K E4 VSS_37 VSS_99 R3 AG19 VSS_161 VSS_223 AW31
CC95 1 2 1U_0402_6.3V6K VDDCR_NB_6 R11 E9 VSS_38 VSS_100 R7 AG25 VSS_162 VSS_224 AW33
VDDCR_NB_7 R13 CC89 1 2 1U_0402_6.3V6K E11 VSS_39 VSS_101 R15 AG29 VSS_163 VSS_225 AW35
CC96 1 2 1U_0402_6.3V6K VDDCR_NB_8 R17 E13 VSS_40 VSS_102 R19 AG31 VSS_164 VSS_226 AW37
VDDCR_NB_9 U13 CC90 1 2 180P_0402_50V8-J E27 VSS_41 VSS_103 R25 AG39 VSS_165 VSS_227 AW39
CC97 1 2 1U_0402_6.3V6K VDDCR_NB_10 U17 E31 VSS_42 VSS_104 R29 AG41 VSS_166 VSS_228 AW41
C91,C89,C90 PLACE ON TOP LAYER
VDDCR_NB_11 W13 E35 VSS_43 VSS_105 R39 AH1 VSS_167 VSS_229 AY13
CC98 1 2 1U_0402_6.3V6K VDDCR_NB_12 W17 E38 VSS_44 VSS_106 R41 AH2 VSS_168 VSS_230 AY15
VDDCR_NB_13 AA13 CC91 1 2 1U_0402_6.3V6K E39 VSS_45 VSS_107 U1 AJ3 VSS_169 VSS_231 AY18
C CC99 1 2 1U_0402_6.3V6K VDDCR_NB_14 AA17 G3 VSS_46 VSS_108 U2 AJ7 VSS_170 VSS_232 AY30 C
VDDCR_NB_15 AC13 CC92 1 2 1U_0402_6.3V6K G7 VSS_47 VSS_109 U3 AJ15 VSS_171 VSS_233 BA2
@ VDDCR_NB_16 AC17 G11 VSS_48 VSS_110 U7 AJ17 VSS_172 VSS_234 BA7
CC100 1 2 180P_0402_50V8-J VDDCR_NB_17 AE15 G13 VSS_49 VSS_111 U8 AJ19 VSS_173 VSS_235 BA13
VDDCR_NB_18 AE17 G15 VSS_50 VSS_112 U11 AJ23 VSS_174 VSS_236 BA15
+VDDIO_AZ_APU VDDCR_NB_19 AE19 G17 VSS_51 VSS_113 U15 AJ25 VSS_175 VSS_237 BA18
0.1A VDDCR_NB_20 AG17 G21 VSS_52 VSS_114 U19 AJ29 VSS_176 VSS_238 BA21
AL10 VDDIO_AZ_ALW_1 VDDCR_NB_21 AG21 G25 VSS_53 VSS_115 U25 AJ31 VSS_177 VSS_239 BA25
AL11 VDDIO_AZ_ALW_2 G29 VSS_54 VSS_116 U29 AJ32 VSS_178 VSS_240 BA31
+1.8VALW_APU +1.8VS_APU +0.95VS_APU G35 VSS_55 VSS_117 U31 AJ39 VSS_179 VSS_241 BA35
0.5A B1 VDD_18_ALW_1 VDD_18_1 A2 1.5A G37 VSS_56 VSS_118 U39 AL3 VSS_180 VSS_242 BA39
S5 DOMAIN +0.95VALW +0.95VALW_USB3 B2 VDD_18_ALW_2 VDD_18_2 A3 G39 VSS_57 VSS_119 W3 AL8 VSS_181 VSSBG_DAC A15
VDD_18_3 B3 CC79 1 2 1U_0402_6.3V6K G41 VSS_58 VSS_120 W5 AL15 VSS_182 VSS_243 AL31
@ @ +3VALW_APU VDD_18_4 C3 H11 VSS_59 VSS_121 W11 AL17 VSS_183 VSS_244 AM29
+3VS_APU
RC1421 2 0_0603_5% CC103 1 2 10U_0603_6.3V6M 0.2A 0.2A CC84 1 2 1U_0402_6.3V6K H13 VSS_60 VSS_122 W15 AL19 VSS_184
AL13 VDD_33_ALW_1 VDD_33_1 AM15 H23 VSS_61 VSS_123 W19 AL25 VSS_185
TB RS CC106 1 2 10U_0603_6.3V6M AM13 AM17 CC85 1 2 1U_0402_6.3V6K H31 W25 AL29
VDD_33_ALW_2 VDD_33_2 VSS_62 VSS_124 VSS_186
S0 DOMAIN +0.95VS_APU +0.95VALW_USB3 +0.95VS_APU @ J9 +0.95VS
FT3 REV 0.53 FT3 REV 0.53
1A AR5 VDD_095_USB3_DUAL_1 VDD_095_1 AG23 1 2 CC86 1 2 1U_0402_6.3V6K
RC143 1 @ 2 0_0603_5% CC105 1 2 1U_0402_6.3V6K AU4 VDD_095_USB3_DUAL_2 VDD_095_2 AG27 3A @ FT3-REV-0P53_BGA769 @ FT3-REV-0P53_BGA769
AV7 VDD_095_USB3_DUAL_3 VDD_095_3 AJ21 PAD-OPEN 4x4m CC87 1 2 1U_0402_6.3V6K Beema Beema
CC107 1 2 1U_0402_6.3V6K AW5 AJ27
+0.95VALW_APU
VDD_095_USB3_DUAL_4 VDD_095_4
VDD_095_5 AL21
Need Short
CC108 1 2 1U_0402_6.3V6K 0.5A AE11 VDD_095_ALW_1 VDD_095_6 AL23 CC78 1 2 10U_0603_6.3V6M
AE13 VDD_095_ALW_2 VDD_095_7 AL27
@ AJ11 VDD_095_ALW_3 VDD_095_8 AM23
+0.95VS_GFX_APU +0.95VS_APU CC83 1 2 10U_0603_6.3V6M
CC104 1 2 180P_0402_50V8-J AJ13 VDD_095_ALW_4 VDD_095_9 AM25 0.6A
VDD_095_GFX_1 U10 RC145 1 @ 2 0_0402_5% CC88 1 2 1U_0402_6.3V6K
4.5uA VDD_095_GFX_2 W10
TB RS
+RTCBATT_APU AN4 VDDBT_RTC_G VDD_095_GFX_3 AA10
FT3 REV 0.53

1 CC82 1 2 1U_0402_6.3V6K CC80 1 2 180P_0402_50V8-J
@ Beema FT3-REV-0P53_BGA769
+0.95VALW +0.95VALW_APU CC110
0.22U_0402_10V6K CC81 1 2 10U_0603_6.3V6M
2 UC4
RC144 1 @ 2 0_0402_5% CC109 1 2 1U_0402_6.3V6K
2
TB RS CC111 1 2 1U_0402_6.3V6K GND
B +VCCRTC B
RC1461 2 10K_0402_5% 3
CC112 1 2 1U_0402_6.3V6K Vout
1 RC148 1 2 10K_0402_5%
CC113 1 2 1U_0402_6.3V6K Vin
1
1
JCOMS1 @ AP2138N-1.5TRG1_SOT23-3 CC114

SHORT PADS 1U_0402_6.3V6K
2
2
SA000063Q00 BCD: AP2138N-1.5TRG1
SA000063O00 ANPEC: APL510215AITRG
+APU_CORE_NB
CC53 CC54 CC55 CC120 CC56 CC65 CC57 CC58 CC59 CC60 CC61 CC62 CC63 CC64 +VSYSMEM_APU
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
180P_0402_50V8-J
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 CC23 CC24 CC25 CC26 CC27 CC28 CC139 CC130 CC131 CC132 CC133
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
180P_0402_50V8-J
180P_0402_50V8-J
180P_0402_50V8-J
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2
A A
+VSYSMEM
+APU_CORE
CC38 CC39 CC40 CC41 CC42 CC43 CC44 CC45 CC46 CC47 CC48 CC49 CC50 CC51 CC52
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
180P_0402_50V8-J
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC145 CC146
22U_0805_6.3V6M 22U_0805_6.3V6M
@ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Beema (POWER & DECOUPLING)
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
Beema (STRAPS & OTHERS)
+3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU
1
D D
RC150 RC151 RC152 RC153 RC154 RC176 RC181
EC S0 PWR, PH +3VS??? 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @
Or need isloate~~
2
RC154,RC176,RC181 change to @ due to internal PH
<44,7> LPC_FRAME#
<7> LPC_CLK1
<44,7> CLK_PCI_EC
<6> GEVENT2#
<6> SYS_RESET#
<40,6> SUSCLK
<6> BLINK
STRAP PINS
Signal LFRAME_L LPCCLK1 LPCCLK0 GEVENT2_L SYS_RESET_L RTCCLK BLINK
1
RC155 RC156 RC157 RC158 RC159 RC177 RC180
Type II II II II I I I 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
@ @ @ @ @
2
SPI ROM Internal Boot Fail Timer 1.8V SPI Normal Power Up Coin Battery LDT_RST#/
PULL CLK Gen Enabled &Reset Timing LDT_PWRGD
HIGH output to APU
C Default Default Default Default Default C
LPC ROM Exteranl Boot Fail Timer 3.3V SPI Reserved Direct DC Reserved
PULL CLK Gen Disabled
LOW
Default Default
Type I straps become valid immediately after capture with the rising edge of RSMRST_L.
Type II straps become valid after PWR_GOOD is asserted
All Strap pins must be configured with either external pull-up or pull-down resistors.
B B
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Beema (STRAPS & OTHERS)
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Blank

C
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

C
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

C
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

C
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
DDRA_DQ[0..63]
DDRA_DQ[0..63] <15,4>
DDR3 SO-DIMM A DDRA_DQS[0..7]
DDRA_DQS[0..7] <15,4>
DDRA_DQS#[0..7]
DDRA_DQS#[0..7] <15,4>
DDRA_MA[0..15]
+VREF_DQ DDRA_MA[0..15] <15,4>
JDDR1
1 2 DDRA_DM[0..7]
VREF_DQ VSS1 DDRA_DM[0..7] <15,4>
3 4 DDRA_DQ4
D DDRA_DQ0 5 VSS2 DQ4 6 DDRA_DQ5 D
DDRA_DQ1 7 DQ0 DQ5 8
9 DQ1 VSS3 10 DDRA_DQS#0
DDRA_DM0 11 VSS4 DQS0# 12 DDRA_DQS0
13 DM0 DQS0 14
DDRA_DQ2 15 VSS5 VSS6 16 DDRA_DQ6 +VSYSMEM +VSYSMEM
DDRA_DQ3 17 DQ2 DQ6 18 DDRA_DQ7
19 DQ3 DQ7 20
VSS7 VSS8
1
DDRA_DQ8 21 22 DDRA_DQ12
DDRA_DQ9 23 DQ8 DQ12 24 DDRA_DQ13 RD10 RD12
25 DQ9 DQ13 26 1K_0402_1% +VREF_DQ 1K_0402_1% +VREF_CA
DDRA_DQS#1 27 VSS9 VSS10 28 DDRA_DM1
DDRA_DQS1 29 DQS1# DM1 30 MEM_MA_RST#
MEM_MA_RST# <15,4> 15mil 15mil
2
31 DQS1 RESET# 32
DDRA_DQ10 33 VSS11 VSS12 34 DDRA_DQ14
DQ10 DQ14
1
1000P_0402_50V7K
1000P_0402_50V7K
.1U_0402_10V6-K
.1U_0402_10V6-K
37 DQ11 DQ15 38 RD11 RD25
VSS13 VSS14 1 1 1 1
DDRA_DQ16 39 40 DDRA_DQ20 1K_0402_1% 1K_0402_1%
DQ16 DQ20
CD116
CD117
CD118
CD119
43 DQ17 DQ21 44
2
DDRA_DQS#2 45 VSS15 VSS16 46 DDRA_DM2 2 2 2 2
DDRA_DQS2 47 DQS2# DM2 48
49 DQS2 VSS17 50 DDRA_DQ22
DDRA_DQ18 51 VSS18 DQ22 52 DDRA_DQ23
55 DQ19 VSS19 56 DDRA_DQ28
65 DM3 DQS3 66
C DDRA_DQ27 69 DQ26 DQ30 70 DDRA_DQ31 C
+VSYSMEM DQ27 DQ31 +VSYSMEM 3A@1.5V
71 72
VSS25 VSS26 +VSYSMEM
Layout Note:
DDRA_CKE0 73 74 DDRA_CKE1
<4> DDRA_CKE0
75 CKE0 CKE1 76
DDRA_CKE1 <4> Place near DIMM1
77 VDD1 VDD2 78 DDRA_MA15
NC1 A15
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
<15,4> DDRA_BS2# DDRA_BS2# 79 80 DDRA_MA14
81 BA2 A14 82 CD16 CD17 CD18 CD19 CD20 CD22 CD21 CD23 CD58 CD59 CD60 CD61
VDD3 VDD4 1 1 1 1 1 1 1 1 1 1 1 1
DDRA_MA12 83 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88 @ @ @ @ @
DDRA_MA8 89 VDD5 VDD6 90 DDRA_MA6 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
DDRA_MA3 95 VDD7 VDD8 96 DDRA_MA2
99 A1 A0 100
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1 +VSYSMEM
<4> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <4>
<4> DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1#
CK0# CK1# DDRA_CLK1# <4>
105 106 EMI
DDRA_MA10 107 VDD11 VDD12 108 DDRA_BS1#
A10/AP BA1 DDRA_BS1# <15,4>
<15,4> DDRA_BS0# DDRA_BS0# 109 110 DDRA_RAS#
BA0 RAS# DDRA_RAS# <15,4>
0.047U_0402_16V7K
0.047U_0402_16V7K
0.047U_0402_16V7K
RF
22U_0805_6.3V6M
22U_0603_6.3V6-M
111 112
VDD13 VDD14
10U_0805_10V6K
10U_0805_10V6K
<15,4> DDRA_WE# DDRA_WE# 113 114 DDRA_CS0# 1 1 1 1 1 1 1 1
WE# S0# DDRA_CS0# <4>
<15,4> DDRA_CAS# DDRA_CAS# 115 116 DDRA_ODT0 CD62 CD63 CD66 CD67 @ @ @
CAS# ODT0 DDRA_ODT0 <4>
CD5
CD6
CD7
117 118 CD11
DDRA_MA13 119 VDD15 VDD16 120 DDRA_ODT1 @ 33P_0402_50V8J
A13 ODT1 DDRA_ODT1 <4> 2 2 2 2 2 2 2 2
<4> DDRA_CS1# DDRA_CS1# 121 122 @
123 S1# NC2 124 +VREF_CA
125 VDD17 VDD18 126
127 TEST VREF_CA 128
B DDRA_DQ32 129 VSS27 VSS28 130 DDRA_DQ36 B
133 DQ33 DQ37 134
DDRA_DQS4 137 DQS4# DM4 138
DDRA_DQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRA_DQ44
VSS34 DQ44 Layout Note:
DDRA_DQ41 149 DQ40 DQ45 150 Place near DIMM
151 DQ41 VSS35 152 DDRA_DQS#5 +0.675VS
155 DM5 DQS5 156
DQ43 DQ47
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
161 162
DQ48 DQ52 1 1 1 1
DDRA_DQ49 165 166 DDRA_DQ53 CD24 CD25 CD26 CD27
167 DQ49 DQ53 168
DDRA_DQS#6 169 VSS41 VSS42 170 DDRA_DM6 @ @
DDRA_DQS6 171 DQS6# DM6 172 2 2 2 2
DDRA_DQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRA_DQ60
DDRA_DQ57 183 DQ56 DQ61 184
189 DM7 DQS7 190
A DDRA_DQ59 193 DQ58 DQ62 194 DDRA_DQ63 A
195 DQ59 DQ63 196
197 VSS51 VSS52 198 MEM_MA_EVENT#
SA0 EVENT# MEM_MA_EVENT# <15,4>
199 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <15,40,6>
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 <15,40,6>
1 1 203 204 +0.675VS
VTT1 VTT2
CD28 CD29 205 206 1 0.65A@0.75V Title
2.2U_0402_6.3V6M .1U_0402_10V6-K 207 GND1 GND2 208 CD70 Security Classification LC Future Center Secret Data
2 2 BOSS1 BOSS2 33P_0402_50V8J
@
Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIII SO-DIMM A
LCN_DAN06-K4406-0103 2
ME@ For RF Size Document Number
Rev
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM B DDRA_DQ[0..63]

DDRA_DQ[0..63] <14,4>
DDRA_DQS[0..7]
DDRA_DQS[0..7] <14,4>
DDRA_DQS#[0..7]
DDRA_DQS#[0..7] <14,4>
+VREF_DQ JDDR2 DDRA_MA[0..15]
DDRA_MA[0..15] <14,4>
1 2
3 VREF_DQ VSS1 4 DDRA_DQ4 DDRA_DM[0..7]
VSS2 DQ4 DDRA_DM[0..7] <14,4>
D DDRA_DQ1 7 DQ0 DQ5 8 D
DDRA_DM0 11 VSS4 DQS#0 12 DDRA_DQS0
13 DM0 DQS0 14
19 DQ3 DQ7 20
25 DQ9 DQ13 26
DDRA_DQS1 29 DQS#1 DM1 30 MEM_MA_RST#
DQS1 RESET# MEM_MA_RST# <14,4>
31 32
DDRA_DQ11 35 DQ10 DQ14 36 DDRA_DQ15 +VREF_DQ +VREF_CA
37 DQ11 DQ15 38
15mil 15mil
DDRA_DQ17 41 DQ16 DQ20 42 DDRA_DQ21 +VREF_DQ +VREF_CA
43 DQ17 DQ21 44
DQS#2 DM2
.1U_0402_10V6-K
1000P_0402_50V7K
.1U_0402_10V6-K
1000P_0402_50V7K
DDRA_DQS2 47 48
49 DQS2 VSS17 50 DDRA_DQ22 CD44 CD35 CD45 CD36
VSS18 DQ22 1 1 1 1
55 DQ19 VSS19 56 DDRA_DQ28
DDRA_DQ24 57 VSS20 DQ28 58 DDRA_DQ29 2 2 2 2
65 DM3 DQS3 66
C 71 DQ27 DQ31 72 C
+VSYSMEM VSS25 VSS26 +VSYSMEM
<4> DDRA_CKE2 DDRA_CKE2 73 74 DDRA_CKE3

CKE0 CKE1 DDRA_CKE3 <4>
75 76
77 VDD1 VDD2 78 DDRA_MA15
DDRA_BS2# 79 NC1 A15 80 DDRA_MA14
<14,4> DDRA_BS2# BA2 A14 3A@1.35V
81 82
DDRA_MA12 83 VDD3 VDD4 84 DDRA_MA11 +VSYSMEM
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
A9 A7 EMI
87 88
DDRA_MA8 89 VDD5 VDD6 90 DDRA_MA6
A5 A4
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
330U_D2_2VM_R9M
0.047U_0402_16V7K
93 94 1
VDD7 VDD8
10U_0805_10V6K
10U_0805_10V6K
DDRA_MA3 95 96 DDRA_MA2 CD43 1 CD42 1 CD64 1 CD65 1 CD68 1 CD69 1 CD30@ 1 1 1
DDRA_MA1 97 A3 A2 98 DDRA_MA0 + CD72 CD73 @
A1 A0
CD10
99 100
DDRA_CLK2 101 VDD9 VDD10 102 DDRA_CLK3
<4> DDRA_CLK2 CK0 CK1 DDRA_CLK3 <4> 2 2 2 2 2 2 2 2 2 2
<4> DDRA_CLK2# DDRA_CLK2# 103 104 DDRA_CLK3#
CK0# CK1# DDRA_CLK3# <4>
105 106
DDRA_MA10 107 VDD11 VDD12 108 DDRA_BS1#
A10/AP BA1 DDRA_BS1# <14,4>
<14,4> DDRA_BS0# DDRA_BS0# 109 110 DDRA_RAS#
BA0 RAS# DDRA_RAS# <14,4>
111 112
DDRA_WE# 113 VDD13 VDD14 114 DDRA_CS2#
<14,4> DDRA_WE# WE# S0# DDRA_CS2# <4>
<14,4> DDRA_CAS# DDRA_CAS# 115 116 DDRA_ODT2
CAS# ODT0 DDRA_ODT2 <4>
117 118
DDRA_MA13 119 VDD15 VDD16 120 DDRA_ODT3
A13 ODT1 DDRA_ODT3 <4>
<4> DDRA_CS3# DDRA_CS3# 121 122
123 S1# NC2 124 +VREF_CA
125 VDD17 VDD18 126
127 NCTEST VREF_CA 128
B DDRA_DQ32 129 VSS27 VSS28 130 DDRA_DQ36 B
133 DQ33 DQ37 134
DDRA_DQS4 137 DQS#4 DM4 138
VSS32 DQ38 Layout Note:
DDRA_DQ35 143 DQ34 DQ39 144 Place near DIMM
145 DQ35 VSS33 146 DDRA_DQ44 +0.675VS
DDRA_DQ41 149 DQ40 DQ45 150
DM5 DQS5
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
155 156
DQ42 DQ46 1 1 1 1
DDRA_DQ43 159 160 DDRA_DQ47 CD32 CD31 CD33 CD34
161 DQ43 DQ47 162
DDRA_DQ48 163 VSS39 VSS40 164 DDRA_DQ52 @ @
DDRA_DQ49 165 DQ48 DQ52 166 DDRA_DQ53 2 2 2 2
167 DQ49 DQ53 168
DDRA_DQS6 171 DQS#6 DM6 172
DDRA_DQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRA_DQ60
DDRA_DQ57 183 DQ56 DQ61 184
189 DM7 DQS7 190
A DDRA_DQ59 193 DQ58 DQ62 194 DDRA_DQ63 A
195 DQ59 DQ63 196
RD22 1 2 10K_0402_5% 197 VSS51 VSS52 198 MEM_MA_EVENT#
+3VS SA0 EVENT# MEM_MA_EVENT# <14,4>
199 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 <14,40,6>
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 <14,40,6>
203 204 +0.675VS
VTT1 VTT2
1 1 0.65A@0.75V
205 206 1 Title
CD54 CD48 G1 G2 CD71 Security Classification LC Future Center Secret Data
2.2U_0402_6.3V6M .1U_0402_10V6-K LCN_DAN06-K4406-0102 33P_0402_50V8J
2 2
ME@ @
Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIII SO-DIMM B
2
For RF Size Document Number
Rev
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
VGA Note list need to be update!
D D
Power-Up/Down Sequence Without BACO option :
"Mars" has the following requirements with regards to power-supply sequencing to PE_GPIO0 : Low ‐> Reset dGPU ; High ‐>Normal operation
PE_GPIO1 : Low ‐> dGPU Power OFF ; High ‐> dGPU Power ON
avoid damaging the ASIC:
dGPU Power Pins Voltage Max current
‧All the ASIC supplies must reach their respective nominal voltages within 20 ms
VDD_CT, DP_VDDR, SPLL_PVDD, MPLL_PVDD,
of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. PCIE_PVDD, TSVDD, VDDR4, AVDD, VDD1DI 1.8V 1243mA
The maximum slew rate on all rails is 50 mV/米s.
The external pull ups on the DDC/AUX signals (if applicable) should ramp up before
DP_VDDC, SPLL_VDDC, PCIE_VDDC, BIF_VDDC 0.95V 4560mA
or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC should reach
90% before VDD_CT starts to ramp up (or vice versa). VDDR3 3.3V 25mA
For power down, reversing the ramp-up sequence is recommended.
VDDR1 1.5V 1.5A
VDDC 0.8~1.125V TBD
VDDCI 0.8~1.1V 8.8A
C C
0 ~ 20ms
VDDR3(+3VGS)
0ms min.
PX5.5
VDDC(+VGA_CORE)
PE_GPIO0 (PXS_RST#)
FCH dGPU
VDDCI(+VGA_CORE) +0.95VGS
BIF_VDDC
PE_GPIO1
(PXS_PWREN)
PCIE_VDDC(+0.95VGS)
+3VS MOS
+3VGS
VDDR1(+1.5VGS) 1
100ms min. Short PX_MODE and PX_PWREN
VDD_CT(+1.8VGS) +5VALW Regulator

+0.95VGS
2
B
+1.5VS MOS
+1.5VGS B
PERSTb(GPU_RST#) 3
default 1ms +3VS +1.8VGS
LDO
REFCLK(CLK_PCIE_VGA) 6 B+ +VGA_CORE
100us min. Regulator
4
Straps Reset
Name Pin Assignment
Straps Valid PE_GPIO0 GPIO191
Global ASIC Reset PE_GPIO1 GPIO192
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 VGA Notes List
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
OK<4> PCIE_CTX_C_GRX_P[3..0]
PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0]
PCIE_CRX_GTX_P[3..0] <4>OK
UV1A
OK<4> PCIE_CTX_C_GRX_N[3..0]
PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0]
PCIE_CRX_GTX_N[3..0] <4>OK
PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 .1U_0402_10V6-K 1 2 PX@ CV1 PCIE_CRX_GTX_P0

PCIE_CTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 .1U_0402_10V6-K 1 2 PX@ CV2 PCIE_CRX_GTX_N0
PCIE_RX0N PCIE_TX0N
D PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 .1U_0402_10V6-K 1 2 PX@ CV3 PCIE_CRX_GTX_P1 D

PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1 .1U_0402_10V6-K 1 2 PX@ CV4 PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N
PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 .1U_0402_10V6-K 1 2 PX@ CV5 PCIE_CRX_GTX_P2

PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 .1U_0402_10V6-K 1 2 PX@ CV6 PCIE_CRX_GTX_N2
PCIE_RX2N PCIE_TX2N
PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 .1U_0402_10V6-K 1 2 PX@ CV7 PCIE_CRX_GTX_P3

PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 .1U_0402_10V6-K 1 2 PX@ CV8 PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N
Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
VRAM 1G
W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26 ZZZ M2G@ ZZZ S2G@ ZZZ H2G@
PCIE_RX7N PCIE_TX7N
V30 W24
C U31 NC#V30 NC#W24 W23 C
NC#U31 NC#W23
MICRON 2G SAMSUNG 2G HYNIX 2G
U29 V27
T28 NC#U29 NC#V27 U26 X7603112002 X7603112001 X7603112003
NC#T28 NC#U26
PCI EXPRESS INTERFACE

T30 U24
NC#T30 NC#U24
R31
NC#R31 NC#U23
U23 VRAM 2G
R29 T26 ZZZ M1G@ ZZZ S1G@ ZZZ H1G@

P28 NC#R29 NC#T26 T27
NC#P28 NC#T27
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23
MICRON 1G SAMSUNG 1G HYNIX 1G
N29 P27 X7603112005 X7603112004 X7603112006
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26
M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23
L29 M27
K30 NC#L29 NC#M27 N26
B NC#K30 NC#N26 B
CLOCK
OK<7> CLK_PCIE_GPU
CLK_PCIE_GPU AK30
PCIE_REFCLKP
OK<7> CLK_PCIE_GPU#
CLK_PCIE_GPU# AK32
PCIE_REFCLKN
+0.95VGS
CALIBRATION
Y22 RV3 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
OK<20> GPU_RST#
GPU_RST# AL27
PERSTB
1
JET-S3-LE_FCBGA631
RV6 PX@
100K_0402_5%
PX@
2
RV7 1 @ 2 0_0402_5%
OK DV3 PX@
GPU_RST# 2
+3VGS 1 VGA_PWROK
VGA_PWROK OK
<44,58,6>
OK
<58,6> VR_VGA_PWRGD
VR_VGA_PWRGD 3
5
A
UV2 BAT54AWT1G_SOT323-3 A
VCC
OK<6> PXS_RST#
1
IN1 4 GPU_RST#
OUT
OK 2
GND
<37,40,6> PLT_RST# IN2

MC74VHC1G08DFT2G_SC70-5
3
PX@ Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_PCIE

A3
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
+3VGS UV1B ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
+3VGS +1.8VGS GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
CV222 PX@ CV223 PX@ AF2

NC#AF2
2
1 2 1 2 AF4 MLPS Bit Strap Name Description RECOMMENDED
RV235 RV236 NC#AF4 SETTINGS
10K_0402_5% 10K_0402_5% .1U_0402_10V6-K .1U_0402_10V6-K N9 AG3 PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
PX@ UV11 L9 DBG_DATA16 NC#AG3 AG5
@ PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
AE9 DBG_DATA15 NC#AG5 X
DPA PS_0[3] ROM_CONFIG[2]
1
1 8 Y11 DBG_DATA14 AH3 100 = 256MB
VCC(A) VCC(B) AE8 DBG_DATA13 NC#AH3 AH1
GPU_VID3_R 2 7 GPU_SVD_R AD9 DBG_DATA12 NC#AH1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
1A 1B AC10 DBG_DATA11 AK3
GPU_VID4_R 3 6 GPU_SVC_R AD7 DBG_DATA10 NC#AK3 AK1 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
2A 2B AC8 DBG_DATA9 NC#AK1 PS_0[5] X
DVO PINSTRAP[0] indicates the number of audio-capable display outputs.
5 4 AC7 DBG_DATA8 AK5
DIR GND DBG_DATA7 NC#AK5
2
2
AB9 AM3 1 = PCIe GEN3 is supported.
RV237 RV238 AB8 DBG_DATA6 NC#AM3 PS_1[1] STRAP_BIF_GEN3_EN_A 0= Not support X
0 = PCIe GEN3 is not supported.
10K_0402_5% 74AVCH2T45GD_XSON8_3X2 AB7 DBG_DATA5 AK6
10K_0402_5% DBG_DATA4 NC#AK6
PX@ @ PX@ AB4 AM5 0 = The CLKREQB power management capability is disabled
AB2 DBG_DATA3 NC#AM5 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
DPB
1
RV241 PX@ Y8 DBG_DATA2 AJ7

D
2 1 Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0 D
+3VGS DBG_DATA0 NC#AH6
10K_0402_5%
AK8 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
10U_0603_6.3V6M
.1U_0402_10V6-K
RVP2 PX@ NC#AK8 AL7 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
2 1 NC#AL7
CV236 CV31 GPU_SVD 1 8 GPU_SVD_R 0 = Tx deemphasis disabled.
PX@ PX@ GPU_SVC 2 7 GPU_SVC_R W6 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
1 2 GPU_VID3 3 6 GPU_VID3_R V6 NC#W6
GPU_VID4 4 5 GPU_VID4_R NC#V6 V4 PS_2[1] N/A Reserved. NA
AC6 NC#V4 U5
NC#AC6 NC#U5
Reserve OK 33_0804_8P4R_5%
T PN change Idea pad PN SD300003700
AC5
NC#AC5
NC#W3
W3 VGA_VSSI_SEN 1 TV10 PAD @
PS_2[2] N/A Reserved. NA
AA5 V2 0 = Disable the external BIOS ROM device.

AA6 NC#AA5 NC#V2 PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X
DPC
+3VGS NC#AA6 Y4
NC#Y4 W5 0 = VGA controller capacity enabled.
NC#W5 PS_2[4] STRAP_BIF_VGA_DIS 0
1 = The device will not be recognized as the system＊s VGA
10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 U1 AA3 controller.
TV11 @ 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2 PS_2[5] N/A Reserved NA
PAD U3 NC#W1 NC#Y2
Y6 NC#U3 J8 Board configuration related strapping, such as for memory ID
10K_0402_5% 1 @ 2 RV9 GPU_GPIO0 TV12 @ 1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 PS_3[1] BOARD_CONFIG[0] 100 = Hynix 1G 000 = Hynix 2G X
10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 PAD NC#AA1 PS_3[2] BOARD_CONFIG[1] 111 = Micron 1G 010 = Micron 2G
10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 PS_3[3] BOARD_CONFIG[2] 110 = Samsung 1G 001 = Samsung 2G
10K_0402_5% 1 @ 2 RV14 GPU_GPIO10
Determines the maximum number of digital display audio endpoints
I2C that will be presented to the OS and user.(Combine with PS_0[5])
111 = No usable endpoints.
10K_0402_5% 1 @ 2 RV81 GPU_GPIO22 R1 AUD_PORT_CONN_ 110 = One usable endpoint.
10K_0402_5% 1 @ 2 RV97 GPU_VID1 R3 SCL PS_3[4] PINSTRAP[1] 111= No usable endpoints.
101 = Two usable endpoints.
10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 SDA X
100 = Three usable endpoints.
10K_0402_5% 1 @ 2 RV99 GPU_VID5 AM26 PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
10K_0402_5% 1 @ 2 RV106 GPU_VID2 NC_R AK26
NC_AVSSN#AK26 PINSTRAP[2] 010 = Five usable endpoints.
GPU_GPIO0 U6 GENERAL PURPOSE I/O
001 = Six usable endpoints.
U10 GPIO_0 AL25
Reserve NC_GPIO_1 NC_G 000 = All endpoints are usable.
T10 AJ25
VGA_SMB_DATA U8 NC_GPIO_2 NC_AVSSN#AJ25
RB751V-40_SOD323-2 VGA_SMB_CLK U7 SMBDATA AH24
SMBCLK NC_B
OK <44> VGA_AC_BATT
DV1 1 2 GPU_GPIO5 T9
GPIO_5_AC_BATT NC_AVSSN#AG25
AG25 +1.8VGS +1.8VGS
GPU_VID5 T8
T7 GPIO_6 DAC1 AH26
NC_GPIO_7 NC_HSYNC
1
OK <58> GPU_VR_HOT#
RV104 1 @ 2 0_0402_5% GPU_GPIO8 P10
GPIO_8_ROMSO NC_VSYNC
AJ27
GPU_GPIO9 P4 RV71 RV74
GPU_GPIO10 P2 GPIO_9_ROMSI 8.45K_0402_1% 10K_0402_5%
N6 GPIO_10_ROMSCK AD22 PX@ @
N5 NC_GPIO_11 NC_RSET
2
N3 NC_GPIO_12 AG24 PS_0 PS_1
Y9 NC_GPIO_13 NC_AVDD AE22
NC_GPIO_14 NC_AVSSQ
1
OK <58> GPU_SVD
GPU_SVD 0_0402_5% 1 @ 2 RV103 GPU_VID3 N1
GPIO_15_PWRCNTL_0 1 1
C 1 @ 2 GPU_GPIO16 M4 AE23 RV77 CV15 RV80 CV16 C
10K_0402_5% RV67 R6 GPIO_16 NC_VDD1DI AD23 2K_0402_1% .01U_0402_16V7-K 4.75K_0402_1% .01U_0402_16V7-K
W10 GPIO_17_THERMAL_INT NC_VSS1DI PX@ @ PX@ @
10K_0402_5% 1 PX@ 2 RV68 GPIO_19_CTF M2 NC_GPIO_18 2 2
FutureASIC/SEYMOUR/PARK
2
GPIO_19_CTF
OK <58> GPU_SVC
GPU_SVC 0_0402_5% 1 @ 2 RV105 GPU_VID4 P8
GPIO_20_PWRCNTL_1 CEC_1
AM12 CEC_1 1 @ TV5
GPU_GPIO21 P7 PAD
GPU_GPIO22 N8 GPIO_21
GPU_VID2 AK10 GPIO_22_ROMCSB AK12 +1.8VGS +1.8VGS
GPU_VID1 AM10 GPIO_29 NC_SVI2#AK12 AL11
GPIO_30 NC_SVI2#AL11
OK<6> GPU_CLKREQ#
0_0402_5% 1 PX@ 2 RV124 GPU_CLKREQ#_R N7
CLKREQB NC_SVI2#AJ11
AJ11
1
JTAG_TRSTB L6 RV60 RV63
+3VGS JTAG_TDI L5 JTAG_TRSTB 10K_0402_5% 8.45K_0402_1%
JTAG_TCK L3 JTAG_TDI @ X76@
PAD JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1 TV1 PAD @
2
10K_0402_5% 1 @ 2 RV72 JTAG_TRSTB TV7 @ 1JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13 GENLK_VSYNC 1 TV2 PAD @ PS_2 PS_3
10K_0402_5% 1 @ 2 RV75 JTAG_TDI RV64 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
TESTEN
1
10K_0402_5% 1 @ 2 RV78 JTAG_TMS 1K_0402_5% AF24 1 1
NC#AF24 AG13 RV69 CV18 RV70 CV19
10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
AB13 NC_SWAPLOCKB PX@ @ X76@ X76@
W8 NC_GENERICA 2 2
2
W9 NC_GENERICB
W7 NC_GENERICC AC19 PS_0
AD10 NC_GENERICD PS_0
AJ9 NC_GENERICE_HPD4 AD19 PS_1
NC#AJ9 PS_1
AL9
DBG_CNTL0 Bit BOM
PS_2
AE17 PS_2 MLPS
AC14
NC_HPD1 5 4 3 2 1 R_pu(Ω) R_pd(Ω) C(nF)
PAD TV6 @ 1 PX_EN AB16 AE20 PS_3
PX_EN PS_3
PS_0[5:1] 1 1 0 0 1 RV71=8.45k RV77=2K CV15=NC
4.7K_0402_5% 1 @ 2RV54
PX@ 2 1 CV25 XTALIN
TS_A
AE19 PS_1[5:1] 1 1 0 0 0 RV74=NC RV77=4.75K CV16=NC
AC16
NC_DBG_VREFG
10P_0402_50V8J PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV16=NC
PS_3[5:1] 1 1 X X X RV60=X76 RV69=X76 CV16=X76
DDC/AUX
2
AE6
27MHZ_10PF_7V27000050
YV1 PLL/CLOCK NC_DDC1CLK AE5 R_pu (次) R_pd (次) Bits [3:1]
GND1
OSC1
PX@ NC_DDC1DATA
1
AD2 NC 4750 000

RV46 NC_AUX1P AD4
1M_0402_5% NC_AUX1N 8450 2000 001
GND2
OSC2
PX@ AC11
NC_DDC2CLK AC13 4530 2000 010
2
NC_DDC2DATA
XTALIN AM28 AD13 6980 4990 011
3
XTALOUT AK28 XTALIN NC_AUX2P AD11

XTALOUT NC_AUX2N 4530 4990 100
B Capacitor Value (nF) Bits [5:4] B
10K_0402_5% 1 PX@ 2 RV45 XO_IN AC22 AD20
10K_0402_5% 1 PX@ 2 RV50 XO_IN2 AB22 XO_IN NC#AD20 AC20 680 00 3240 5620 101
XO_IN2 NC#AC20
PX@ 2 1 CV32 XTALOUT AE16 82 01 3400 10000 110
NC#AE16 AD16
10P_0402_50V8J NC#AD16 10 10 4750 NC 111
SEYMOUR/FutureASIC AC1
PAD TV13@ 1 GPU_DPLUS T4 NC_DDCVGACLK AC3 NC 11
DPLUS THERMAL NC_DDCVGADATA Note: 0402 1% resistors are required.
PAD TV14@ 1 GPU_DMINUS T2
DMINUS
+1.8VGS +VDDIO_GPU
+3VS RV41 1 @ 2 GPIO_28_FDO R5
10K_0402_5% LV3 1 2 PX@ +TSVDD AD17 GPIO28_FDO
+1.8VGS TSVDD SVC SVD Output Voltage (V)
BLM15AG121SH1D_2P AC17 RV234 1 PX@ 2
TSVSS
CV21
0 0 1.1 0_0402_5%
1U_0402_6.3V6K
2
(1.8V@20mA TSVDD) 1
RV42 0 1 1.0
10K_0402_5% JET-S3-LE_FCBGA631
PX@ PX@
* 1 0 0.9
2
2
PX@
1
1 1 0.8 RV205 RV204

10K_0402_5% 10K_0402_5%
@ PX@
Connect GPIO_28 to 10K pull
1
down to enable MLPS.
ACLU5 has no THRMTRIP#, so to EC WRST#? OK GPU_SVD
GPU_SVC
+3VGS WRST# <44>
2
1
RV206 RV207
RV242 10K_0402_5% 10K_0402_5%
1
0_0402_5% PX@ @
RV127 PX@
1
20K_0402_5%
2
@
2
3
E
B
QV12 2
MMBT3906_SOT23-3 C
@
1
C QV13
RV128 1 PX@ 2 2 MMBT3904WH_SOT323-3 Internal VGA Thermal Sensor
2.2K_0402_5% B PX@
CV215
.1U_0402_10V6-K
E
3
1
+3VGS
1
PX@ RV129 RV130 RV131 +3VGS
GPU_RST# 1 2 DV2 20K_0402_5% 20K_0402_5% 1K_0402_5%
<19> GPU_RST# FOR ONE TIME CTF USE 47K @ @ PX@
1
A SDM10U45LP-7_DFN1006-2-2 FOR RESETABLE CTF USE 2K 2 A

2
1 2
RV43 RV44
2
C 47K_0402_5% 47K_0402_5%
G
GPIO_19_CTF 1 PX@ 2 RV132 RV133 1 @ 2 2 PX@ PX@

47K_0402_5% 47K_0402_5% B
2
2
CV216
.01U_0402_16V7-K
E
3
1
QV14 VGA_SMB_CLK QV4A 1 6 PX@

S
1 EC_SMB_CK2 <39,44,5>
D
RV134 MMBT3904_SOT23-3
5
100K_0402_5% @ 2N7002KDWH_SOT363-6
G
@
2
@
2
VGA_SMB_DATA QV4B 4 3 PX@

S
EC_SMB_DA2 <39,44,5>
D
2N7002KDWH_SOT363-6
RV135 1 PX@ 2 0_0402_5%
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_Main_MSIC
No GPIO Reserve for NV GPU THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
UV1F
D D
AB11
NC_VARY_BL AB12
NC_DIGON
AL15
NC_UPHYAB_TMDPA_TX0N AK14
NC_UPHYAB_TMDPA_TX0P
AH16
NC_UPHYAB_TMDPA_TX1N AJ15
AL17
NC_UPHYAB_TMDPA_TX2N AK16
AH18
NC_UPHYAB_TMDPA_TX3N AJ17
AL19
NC_TXOUT_L3P AK18
NC_TXOUT_L3N
C C
TMDP
AH20
NC_UPHYAB_TMDPB_TX0N AJ19
NC_UPHYAB_TMDPB_TX0P
AL21
NC_UPHYAB_TMDPB_TX1N AK20
AH22
NC_UPHYAB_TMDPB_TX2N AJ21
AL23
NC_UPHYAB_TMDPB_TX3N AK22
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N
JET-S3-LE_FCBGA631
B PX@ B
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_TMDP
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
+1.8VGS (1.8V@425mA DP_VDDR)

@
RV48 1 2 +DP_VDDR
UV1G UV1E
PX@
PX@
0_0603_5%
10U_0603_6.3V6M
1U_0402_6.3V6K
DP POWER NC/DP POWER
1 1
AG15 AE11 AA27 A3
AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
D D
AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
2 2 NC_DP_VDDR#AF16 NC#AE13 GND_3 GND_67
CV39
CV40
AG17 AF13 AC24 AA16
AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
AE27 GND_8 GND_72 AD6
+0.95VGS AF32 GND_9 GND_73 AD8
(0.95V@560mA DP_VDDC) GND_10 GND_74
@ AG27 AE7
RV47 1 2 +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
NC_DP_VDDC#AG20 NC#AF6 GND_12 GND_76
CV38
CV37
AG21 AF7 K28 AH10
0_0603_5% AF22 NC_DP_VDDC#AG21 NC#AF7 AF8 K32 GND_13 GND_77 AH28
NC_DP_VDDC#AF22 NC#AF8 GND_14 GND_78
1U_0402_6.3V6K
.1U_0402_16V7K
AG22 AF9 L27 B10
AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
1 1 DP_VDDC#AD14 GND_16 GND_80
N25 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
2 2 AG14 AE1 P32 GND_19 GND_83 B20
NC_DP_VSSR_1 NC#AE1 GND_20 GND_84
PX@
PX@
AH14 AE3 R27 B22
AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
AG23 NC_DP_VSSR_6 NC#AF10 AG9 V32 GND_25 GND_89 C1
C
AM20 NC_DP_VSSR_7 NC#AG9 AH8 W25 GND_26 GND_90 C32 C
AM22 NC_DP_VSSR_8 NC#AH8 AM6 W26 GND_27 GND_91 E28
AM24 NC_DP_VSSR_9 NC#AM6 AM8 W27 GND_28 GND_92 F10
AF19 NC_DP_VSSR_10 NC#AM8 AG7 Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
DP_VSSR_13 GND_96 F18
GND_97 F2
GND_98 F20
RV49 1 2 @ AF17 AE10 M6 GND_99 F22
150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24
N16 GND_33 GND_101 F26
N18 GND_34 GND_102 F6
JET-S3-LE_FCBGA631 N21 GND_35 GND
GND_103 F8
PX@ P6 GND_36 GND_104 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
B B
U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2
U20 GND_49 GND_117 K22
U9 GND_50 GND_118 K6
V13 GND_51 GND_119
V16 GND_52
V18 GND_53
Y10 GND_54
Y15 GND_55
Y17 GND_56
Y20 GND_57
R11 GND_58 A32
T11 GND_59 VSS_MECH_1 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
N11 GND_62
V11 GND_63
GND_64
JET-S3-LE_FCBGA631
PX@
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_DP Power
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
+1.35VGS
For DDR3/GDDR5, 1500mA@1.5V
CV48
CV51
CV52
CV53
CV54
CV55
CV56
CV217
RF
10U_0603_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
.1U_0402_16V7K
.01U_0402_16V7-K
1 1 1 1 1 1 1 1 1 UV1D +1.8VGS
(1.8V@100mA PCIE_PVDD)
CV501 AM30
PCIE_PVDD
PCIE
MEM I/O
CV46
CV47
33P_0402_50V8J
2 2 2 2 2 2 2 2 2
PX@
10U_0603_6.3V6M
1U_0402_6.3V6K
@ H13 AB23
VDDR1_1 NC#AB23
PX@
PX@
PX@
PX@
PX@
PX@
PX@
H16 AC23 1 1
H19 VDDR1_2 NC#AC23 AD24
J10 VDDR1_3 NC#AD24 AE24
J23 VDDR1_4 NC#AE24 AE25
VDDR1_5 NC#AE25 2 2
PX@
PX@
J24 AE26
D J9 VDDR1_6 NC#AE26 AF25 D
K10 VDDR1_7 NC#AF25 AG26
+1.8VGS +VDD_CT K23 VDDR1_8 NC#AG26 +0.95VGS
(1.8V@13mA VDD_CT) VDDR1_9
K24 (0.95V@2500mA PCIE_VDDC)
LV7 1 @ 2 0_0402_5% K9 VDDR1_10 L23
VDDR1_11 PCIE_VDDC_1
CV144
L11 L24
CV64
CV65
CV66
CV67
CV68
CV69
CV71
1U_0402_6.3V6K
L12 L25
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 L13 L26
L20
M22 1 1 1 1 1 1 1 1 RF
L21 N22
L22 VDDR1_16 PCIE_VDDC_6 N23 CV502
2 VDDR1_17 PCIE_VDDC_7
PX@
N24 33P_0402_50V8J
PCIE_VDDC_8 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
R22 @
PCIE_VDDC_9 T22
LEVEL PCIE_VDDC_10 U22
TRANSLATION PCIE_VDDC_11 V22
AA20 PCIE_VDDC_12 +VGA_CORE
AA21 VDD_CT_1
AB20 VDD_CT_2 AA15
+3VGS AB21 VDD_CT_3 CORE VDDC_1 N15
(3.3V@25mA VDDR3) VDD_CT_4 VDDC_2
CV73
CV74
CV75
CV76
CV77
CV141
CV143
CV146
CV148
CV150
CV152
CV84
CV159
CV133
CV137
CV151
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
N17
LV8 1 @ 2 0_0402_5% +VDDR3 VDDC_3 R13
I/O VDDC_4
CV149
R16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VDDC_5
1U_0402_6.3V6K
AA17 R18
AA18 VDDR3_1 VDDC_6 Y21
1 VDDR3_2 VDDC_7
AB17 T12
VDDR3_3 VDDC_8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
AB18 T15
VDDR3_4 VDDC_9 T17
2 VDDC_10
PX@
V12 T20
Y12 NC_VDDR4_1 VDDC_11 U13
+1.8VGS U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13 U18
(1.8V@130mA MPLL_PVDD) VDDC_14
PX@ V21
LV4 1 2 +MPLL_PVDD VDDC_15 V15
VDDC_16
CV26
CV34
CV27
CV139
CV153
CV156
CV160
CV134
CV135
GBK160808T-221Y-N V17
VDDC_17
CV24
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
V20
VDDC_18
POWER
RF
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
Y13 1 1 1 1 1 1 1
VDDC_19
.1U_0402_16V7K
1 1 1 Y16
VDDC_20 Y18 CV503
1 VDDC_21 AA12 33P_0402_50V8J
VDDC_22 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
C
For EMC M11 @ C
2 2 2 VDDC_23 N12
2 VDDC_24 U11
VDDC_25
PX@
PX@
PX@
@
PLL
+0.95VGS
(0.95V@1400mA BIF_VDDC)
+1.8VGS R21
BIF_VDDC_1 U21
(1.8V@75mA SPLL_PVDD) BIF_VDDC_2
PX@ 1
LV5 1 2 +SPLL_PVDD +MPLL_PVDD L8 CV41
MPLL_PVDD
CV29
CV30
BLM15AG121SH1D_2P +VGA_CORE 1U_0402_6.3V6K

CV28
ISOLATED PX@
2
10U_0603_6.3V6M
1U_0402_6.3V6K
CORE I/O (GDDR3/DDR3 8.8A@1.12V VDDCI)

.1U_0402_16V7K
1 1 M13
+SPLL_PVDD H7 VDDCI_1 M15
1 SPLL_PVDD VDDCI_2 M16
+0.95VGS VDDCI_3
CV218
CV219
CV158
CV132
CV136
CV138
M17
For EMC 2 2 VDDCI_4
10U_0603_6.3V6M
10U_0603_6.3V6M
CV220
.1U_0402_16V7K
.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
(0.95V@100mA SPLL_VDDC) M18
2 VDDCI_5
PX@
VDDCI_6
M20 1 1 1 1 1 1 1 1 RF
PX@
PX@
LV6 1 2 +SPLL_VDDC H8 M21

SPLL_VDDC VDDCI_7
CV35
CV36
BLM15AG121SH1D_2P N20 CV504

VDDCI_8
@
CV33
J7 33P_0402_50V8J
SPLL_PVSS 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
1U_0402_6.3V6K
.1U_0402_16V7K
@
.1U_0402_16V7K
1 1
1
JET-S3-LE_FCBGA631
For EMC PX@
2 2
2
PX@
@
@
B B
+3.3VS TO +3VGS +1.35V TO +1.35VGS

Need OPEN
+3VS +3VGS +1.35V
Need OPEN +1.35VGS
JV1 1 2 @ JV2 1 2 @
1 2 1 2 CV214 CV210 CV211 CV212
10U_0603_6.3V6M
1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
.1U_0402_16V7K
JUMP_43X39 CV140 CV142 CV208 CV209 JUMP_43X118
330U_D2_2V_Y
1
1
1
1 1 1 1 AON6414AL_DFN8-5 1 1 1
RV51 + RV91
470_0603_5% 1 470_0603_5%
S
QV6 3 1 PX@ @ 2 @
2 2 2 2 @2 2 2 2
PX@
PX@
PX@
PX@
PX@
@
LP2301ALT1G_SOT23-3 5 3
2
1 2
D QV10
G
2
+5VALW D QV7 QV9 PX@ 2 PXS_PWREN#

4
2 +VSB G
PXS_PWREN# <46>
1 PX@ 2 RV52 PXS_PWREN# 1 PX@ 2 RV53 G
20K_0402_5% 20K_0402_5% 1 PX@ 2 RV92 S 2N7002KW_SOT323-3
3
1 S 2N7002KW_SOT323-3 100K_0402_5% @
3
@
1
D CV145 1
1
OK
<58,6> PXS_PWREN
PXS_PWREN 2 QV8
2
.1U_0402_16V7K D RV118
G PX@ PXS_PWREN# 2 QV11 120K_0402_5% CV213
A G PX@ .1U_0402_16V7K A
1
PX@ S 2 PX@
3
RV1000 2N7002KW_SOT323-3 PX@ S

3
100K_0402_5% 2N7002KW_SOT323-3
PX@
2

Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_Power
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
UV1C
FBA_D[63..0]
FBA_D[63..0] <25,26> GDDR5/DDR3 GDDR5/DDR3
FBA_D0 K27 K17 FBA_MA0
FBA_MA[15..0] FBA_D1 J29 DQA0_0 MAA0_0/MAA_0 J20 FBA_MA1
FBA_MA[15..0] <25,26> DQA0_1 MAA0_1/MAA_1
FBA_D2 H30 H23 FBA_MA2
FBA_BA[2..0] FBA_D3 H32 DQA0_2 MAA0_2/MAA_2 G23 FBA_MA3
FBA_BA[2..0] <25,26> DQA0_3 MAA0_3/MAA_3
FBA_D4 G29 G24 FBA_MA4
FBA_D5 F28 DQA0_4 MAA0_4/MAA_4 H24 FBA_MA5
FBA_D6 F32 DQA0_5 MAA0_5/MAA_5 J19 FBA_MA6
D DQA0_6 MAA0_6/MAA_6 D
FBA_D7 F30 K19 FBA_MA7
FBA_D8 C30 DQA0_7 MAA0_7/MAA_7 G20 FBA_MA13
FBA_D9 F27 DQA0_8 MAA0_8/MAA_13 L17 FBA_MA15
FBA_D10 A28 DQA0_9 MAA0_9/MAA_15
FBA_D11 C28 DQA0_10 J14 FBA_MA8
FBA_D12 E27 DQA0_11 MAA1_0/MAA_8 K14 FBA_MA9
FBA_D13 G26 DQA0_12 MAA1_1/MAA_9 J11 FBA_MA10
FBA_D14 D26 DQA0_13 MAA1_2/MAA_10 J13 FBA_MA11
FBA_D15 F25 DQA0_14 MAA1_3/MAA_11 H11 FBA_MA12
FBA_D16 A25 DQA0_15 MAA1_4/MAA_12 G11 FBA_BA2
FBA_D17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 FBA_BA0
FBA_D18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 FBA_BA1
FBA_D19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 FBA_MA14
FBA_D20 E23 DQA0_19 MAA1_8/MAA_14 L16
MEMORY INTERFACE
FBA_D21 F23 DQA0_20 MAA1_9/RSVD
DQA0_21 FBA_DQM[7..0] <25,26>
FBA_D22 D22 E32 FBA_DQM0
FBA_D23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 FBA_DQM1
FBA_D24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 FBA_DQM2
FBA_D25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 FBA_DQM3
FBA_D26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 FBA_DQM4
FBA_D27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 FBA_DQM5
FBA_D28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 FBA_DQM6
FBA_D29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 FBA_DQM7
FBA_D30 A17 DQA0_29 WCKA1B_1/DQMA1_3
DQA0_30 FBA_DQS[7..0] <25,26>
FBA_D31 C17 H28 FBA_DQS0
FBA_D32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 FBA_DQS1
FBA_D33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 FBA_DQS2
C DQA1_1 EDCA0_2/QSA0_2 C
+1.35VGS FBA_D34 F15 E19 FBA_DQS3
FBA_D35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 FBA_DQS4
FBA_D36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 FBA_DQS5
DQA1_4 EDCA1_1/QSA1_1
1
FBA_D37 F13 D6 FBA_DQS6

RV61 FBA_D38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 FBA_DQS7
40.2_0402_1% FBA_D39 C13 DQA1_6 EDCA1_3/QSA1_3
DQA1_7 FBA_DQS#[7..0] <25,26>
PX@ FBA_D40 E11 H27 FBA_DQS#0
FBA_D41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 FBA_DQS#1
2
+VDD_MEM15_REFDA FBA_D42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 FBA_DQS#2

FBA_D43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 FBA_DQS#3
DQA1_11 DDBIA0_3/QSA0_3B
1
1 FBA_D44 A9 C15 FBA_DQS#4

RV65 CV154 FBA_D45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 FBA_DQS#5
100_0402_1% 1U_0402_6.3V6K FBA_D46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 FBA_DQS#6
PX@ PX@ FBA_D47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 FBA_DQS#7
2 FBA_D48 E7 DQA1_15 DDBIA1_3/QSA1_3B
2
FBA_D49 A7 DQA1_16 L18 FBA_ODTA0

DQA1_17 ADBIA0/ODTA0 FBA_ODTA0 <25>
FBA_D50 C7 K16 FBA_ODTA1
DQA1_18 ADBIA1/ODTA1 FBA_ODTA1 <26>
FBA_D51 F7
FBA_D52 A5 DQA1_19 H26 FBA_CLKA0
DQA1_20 CLKA0 FBA_CLKA0 <25>
FBA_D53 E5 H25 FBA_CLKA0#
DQA1_21 CLKA0B FBA_CLKA0# <25>
FBA_D54 C3
FBA_D55 E1 DQA1_22 G9 FBA_CLKA1
DQA1_23 CLKA1 FBA_CLKA1 <26>
FBA_D56 G7 H9 FBA_CLKA1#
DQA1_24 CLKA1B FBA_CLKA1# <26>
+1.35VGS FBA_D57 G6
FBA_D58 G1 DQA1_25 G22 FBA_RASA0#
DQA1_26 RASA0B FBA_RASA0# <25>
FBA_D59 G3 G17 FBA_RASA1#
DQA1_27 RASA1B FBA_RASA1# <26>
1
B FBA_D60 J6 B
RV62 FBA_D61 J1 DQA1_28 G19 FBA_CASA0#
DQA1_29 CASA0B FBA_CASA0# <25>
40.2_0402_1% FBA_D62 J3 G16 FBA_CASA1#
DQA1_30 CASA1B FBA_CASA1# <26>
PX@ FBA_D63 J5
DQA1_31 H22 FBA_CSA0#
FBA_CSA0# <25>
2
+VDD_MEM15_REFSA +VDD_MEM15_REFDA K26 CSA0B_0 J22

+VDD_MEM15_REFSA J26 MVREFDA CSA0B_1
MVREFSA
1
1 G13 FBA_CSA1#
CSA1B_0 FBA_CSA1# <26>
RV66 CV157 J25 K13
100_0402_1% 1U_0402_6.3V6K RV55 1 2 PX@ K25 NC#J25 CSA1B_1
PX@ PX@ 120_0402_1% MEM_CALRP0 K20 FBA_CKEA0
2 CKEA0 FBA_CKEA0 <25>
J17 FBA_CKEA1
FBA_CKEA1 <26>
2
CKEA1
G25 FBA_WEA0#
WEA0B FBA_WEA0# <25>
DRAMRST L10 H10 FBA_WEA1#
DRAM_RST WEA1B FBA_WEA1# <26>
PAD @ TV8 1 CLKTESTA K8
PAD @ TV9 1 CLKTESTB L7 CLKTESTA
CLKTESTB
JET-S3-LE_FCBGA631
PX@
A DRAMRST RV56 1 PX@ 2 RV57 1 2 PX@ A

FBA_RST# <25,26>
10_0402_5% 51.1_0402_1%
1
RV58 1
4.99K_0402_1% CV147
PX@ 120P_0402_50V8-J Title
PX@ Security Classification LC Future Center Secret Data
2
2
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_MEM IF
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
FBA_MA[15..0] <24,26>
ACLU5 swap the VRAM Data @ 08/26
FBA_BA[2..0] <24,26> VRAM 8 pcs change to 4 pcs @ 09/26
FBA_DQS[3..0] <24>
FBA_DQM[3..0] <24>
Memory Partition A - Lower 32 bits FBA_DQS#[3..0]
FBA_D[31..0]
<24>
<24>
UV6
D UV5 D
+FBA_VREFC0_L M8 E3 FBA_D19
+FBA_VREFC0_U M8 E3 FBA_D1 H1 VREFCA DQL0 F7 FBA_D16 +1.35VGS +1.35VGS
H1 VREFCA DQL0 F7 FBA_D6 VREFDQ DQL1 F2 FBA_D23
VREFDQ DQL1 DQL2
DQL2
F2 FBA_D2 FBA_MA0 N3
A0 DQL3
F8 FBA_D21 Group2 (IN1)
1
FBA_MA0 N3 F8 FBA_D7 FBA_MA1 P7 H3 FBA_D22
A0 DQL3 A1 DQL4
FBA_MA1 P7
A1 DQL4
H3 FBA_D0 Group0 (IN3) FBA_MA2 P3
A2 DQL5
H8 FBA_D18 RV18 RV20
FBA_MA2 P3 H8 FBA_D5 FBA_MA3 N2 G2 FBA_D20 4.99K_0402_1% 4.99K_0402_1%
FBA_MA3 N2 A2 DQL5 G2 FBA_D3 FBA_MA4 P8 A3 DQL6 H7 FBA_D17 PX@ PX@
FBA_MA4 P8 A3 DQL6 H7 FBA_D4 FBA_MA5 P2 A4 DQL7
2
FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5 CV100 +FBA_VREFC0_U CV101 +FBA_VREFC0_L
FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D9
A6 A7 DQU0
.1U_0402_10V6-K
.1U_0402_10V6-K
FBA_MA7 R2 D7 FBA_D31 FBA_MA8 T8 C3 FBA_D10
A7 DQU0 A8 DQU1
1
FBA_MA8 T8 C3 FBA_D27 FBA_MA9 R3 C8 FBA_D13 1 1
A8 DQU1 A9 DQU2
FBA_MA9 R3
A9 DQU2
C8 FBA_D30 FBA_MA10 L7
A10/AP DQU3
C2 FBA_D12 Group1 (TOP) RV19 RV21
FBA_MA10 L7 C2 FBA_D25 FBA_MA11 R7 A7 FBA_D8 4.99K_0402_1% 4.99K_0402_1%
A10/AP DQU3 A11 DQU4
@
FBA_MA11 R7
A11 DQU4
A7 FBA_D28 Group3 (BOT) FBA_MA12 N7
A12/BC DQU5
A2 FBA_D14 PX@
2
PX@
2
FBA_MA12 N7 A2 FBA_D24 FBA_MA13 T3 B8 FBA_D15
2
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D29 FBA_MA14 T7 A13 DQU6 A3 FBA_D11
FBA_MA14 T7 A13 DQU6 A3 FBA_D26 A14 DQU7
A14 DQU7 +1.35VGS
+1.35VGS
FBA_BA0 M2 B2
FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA2 M3 BA1 VDD_2 G7
FBA_BA2 M3 BA1 VDD_2 G7 BA2 VDD_3 K2
BA2 VDD_3 K2 VDD_4 K8
VDD_4 K8 VDD_5 N1
VDD_5 N1 FBA_CLKA0 J7 VDD_6 N9
FBA_CLKA0 J7 VDD_6 N9 FBA_CLKA0# K7 CK VDD_7 R1
<24> FBA_CLKA0 CK VDD_7 CK VDD_8
FBA_CLKA0# K7 R1 FBA_CKEA0 K9 R9
<24> FBA_CLKA0# CK VDD_8 CKE VDD_9
FBA_CKEA0 K9 R9
<24> FBA_CKEA0 CKE VDD_9
FBA_ODTA0 K1 A1
FBA_ODTA0 K1 A1 FBA_CSA0# L2 ODT VDDQ_1 A8
C <24> FBA_ODTA0 ODT VDDQ_1 CS VDDQ_2 C
FBA_CSA0# L2 A8 FBA_RASA0# J3 C1
<24> FBA_CSA0# CS VDDQ_2 RAS VDDQ_3
FBA_RASA0# J3 C1 FBA_CASA0# K3 C9
<24> FBA_RASA0# RAS VDDQ_3 CAS VDDQ_4
FBA_CASA0# K3 C9 FBA_WEA0# L3 D2
<24> FBA_CASA0# CAS VDDQ_4 WE VDDQ_5
FBA_WEA0# L3 D2 E9
<24> FBA_WEA0# WE VDDQ_5 VDDQ_6
E9 F1
VDDQ_6 F1 FBA_DQS2 F3 VDDQ_7 H2
FBA_DQS0 F3 VDDQ_7 H2 FBA_DQS1 C7 DQSL VDDQ_8 H9
FBA_DQS3 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
DQSU VDDQ_9
FBA_DQM2 E7 A9
FBA_DQM0 E7 A9 FBA_DQM1 D3 DML VSS_1 B3
FBA_DQM3 D3 DML VSS_1 B3 DMU VSS_2 E1
DMU VSS_2 E1 VSS_3 G8
VSS_3 G8 FBA_DQS#2 G3 VSS_4 J2
FBA_DQS#0 G3 VSS_4 J2 FBA_DQS#1 B7 DQSL VSS_5 J8
FBA_DQS#3 B7 DQSL VSS_5 J8 DQSU VSS_6 M1
DQSU VSS_6 M1 VSS_7 M9
VSS_7 M9 VSS_8 P1
VSS_8 P1 FBA_RST# T2 VSS_9 P9 FBA_CLKA0
FBA_RST# T2 VSS_9 P9 RESET VSS_10 T1
<24,26> FBA_RST# RESET VSS_10 VSS_11
T1 L8 T9
VSS_11 ZQ VSS_12
1
L8 T9
ZQ VSS_12 RV26
J1 B1 40.2_0402_1%
NC1 VSSQ_1
1
1
J1 B1 L1 B9 PX@
RV15 RV16 L1 NC1 VSSQ_1 B9 RV17 J9 NC2 VSSQ_2 D1
2
10K_0402_5% 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% L9 NC3 VSSQ_3 D8 CV104 PX@
@ PX@ L9 NC3 VSSQ_3 D8 PX@ FBA_MA15 M7 NC4 VSSQ_4 E2 1 2
FBA_MA15 M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8
2
NC5 VSSQ_5 E8 VSSQ_6 F9 .01U_0402_16V7-K

VSSQ_6 VSSQ_7
1
F9 G1
VSSQ_7 G1 VSSQ_8 G9 RV27
VSSQ_8 G9 VSSQ_9 40.2_0402_1%
VSSQ_9 96-BALL PX@
B 96-BALL SDRAM DDR3 B
2
SDRAM DDR3 K4W4G1646B-HC11_FBGA96
K4W4G1646B-HC11_FBGA96 FBA_CLKA0#
+1.35VGS UV5 SIDE +1.35VGS UV6 SIDE

CV78 CV79 CV80 CV81 CV82 CV83 CV89 CV90 CV91 CV92 CV93 CV94
10U_0603_6.3V6-M
10U_0603_6.3V6-M
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1 1 1 1 1 1 1 1 1 1 1 1
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2 2 2 2 2
+1.35VGS
UV5 SIDE +1.35VGS UV6 SIDE
CV155 CV85 CV86 CV87 CV88 CV95 CV96 CV97 CV98 CV99
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
1 1 1 1 1 1 1 1 1 1
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2 2 2
A A
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_VRAM_A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
FBA_MA[15..0] <24,25>
FBA_BA[2..0] <24,25>
FBA_DQS[7..4] <24>
Memory Partition A - Upper 32 bits FBA_DQM[7..4]
FBA_DQS#[7..4]
<24>
<24>
FBA_D[63..32] <24>
UV7 UV8
+FBA_VREFC1_U M8 E3 FBA_D38 +FBA_VREFC1_L M8 E3 FBA_D56

H1 VREFCA DQL0 F7 FBA_D35 H1 VREFCA DQL0 F7 FBA_D59
D D
VREFDQ DQL1 F2 FBA_D37 VREFDQ DQL1 F2 FBA_D57
FBA_MA0 N3 DQL2 F8 FBA_D32 FBA_MA0 N3 DQL2 F8 FBA_D61 +1.35VGS +1.35VGS
A0 DQL3 A0 DQL3
FBA_MA1 P7
A1 DQL4
H3 FBA_D36 Group4 (IN1) FBA_MA1 P7
A1 DQL4
H3 FBA_D60 Group7 (IN3)
FBA_MA2 P3 H8 FBA_D34 FBA_MA2 P3 H8 FBA_D62
A2 DQL5 A2 DQL5
1
FBA_MA3 N2 G2 FBA_D39 FBA_MA3 N2 G2 FBA_D63 RV30
FBA_MA4 P8 A3 DQL6 H7 FBA_D33 FBA_MA4 P8 A3 DQL6 H7 FBA_D58 RV32
FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7 4.99K_0402_1% 4.99K_0402_1%
FBA_MA6 R8 A5 FBA_MA6 R8 A5 PX@ PX@
FBA_MA7 R2 A6 D7 FBA_D40 FBA_MA7 R2 A6 D7 FBA_D55
2
FBA_MA8 T8 A7 DQU0 C3 FBA_D45 FBA_MA8 T8 A7 DQU0 C3 FBA_D51 CV127 +FBA_VREFC1_U CV128 +FBA_VREFC1_L
FBA_MA9 R3 A8 DQU1 C8 FBA_D43 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
FBA_MA10 L7 A9 DQU2 C2 FBA_D44 FBA_MA10 L7 A9 DQU2 C2 FBA_D48
A10/AP DQU3 A10/AP DQU3
1
.1U_0402_10V6-K
.1U_0402_10V6-K
FBA_MA11 R7
A11 DQU4
A7 FBA_D42 Group5 (TOP) FBA_MA11 R7
A11 DQU4
A7 FBA_D52 Group6 (BOT) 1 1
FBA_MA12 N7 A2 FBA_D46 FBA_MA12 N7 A2 FBA_D50 RV31 RV33
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D41 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D53 4.99K_0402_1% 4.99K_0402_1%
A13 DQU6 A13 DQU6
PX@
FBA_MA14 T7 A3 FBA_D47 FBA_MA14 T7 A3 FBA_D49 PX@ PX@
A14 DQU7 A14 DQU7 2 2
2
+1.35VGS +1.35VGS
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA2 M3 BA1 VDD_2 G7
BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 K8 VDD_4 K8
VDD_5 N1 VDD_5 N1
FBA_CLKA1 J7 VDD_6 N9 FBA_CLKA1 J7 VDD_6 N9
<24> FBA_CLKA1 CK VDD_7 CK VDD_7
FBA_CLKA1# K7 R1 FBA_CLKA1# K7 R1
<24> FBA_CLKA1# CK VDD_8 CK VDD_8
FBA_CKEA1 K9 R9 FBA_CKEA1 K9 R9
<24> FBA_CKEA1 CKE VDD_9 CKE VDD_9
FBA_ODTA1 K1 A1 FBA_ODTA1 K1 A1
<24> FBA_ODTA1 ODT VDDQ_1 ODT VDDQ_1
FBA_CSA1# L2 A8 FBA_CSA1# L2 A8
<24> FBA_CSA1# CS VDDQ_2 CS VDDQ_2
FBA_RASA1# J3 C1 FBA_RASA1# J3 C1
<24> FBA_RASA1# RAS VDDQ_3 RAS VDDQ_3
FBA_CASA1# K3 C9 FBA_CASA1# K3 C9
C <24> FBA_CASA1# CAS VDDQ_4 CAS VDDQ_4 C
FBA_WEA1# L3 D2 FBA_WEA1# L3 D2
<24> FBA_WEA1# WE VDDQ_5 WE VDDQ_5
E9 E9
VDDQ_6 F1 VDDQ_6 F1
FBA_DQS4 F3 VDDQ_7 H2 FBA_DQS7 F3 VDDQ_7 H2
FBA_DQS5 C7 DQSL VDDQ_8 H9 FBA_DQS6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 D3 DML VSS_1 B3 FBA_DQM6 D3 DML VSS_1 B3
DMU VSS_2 E1 DMU VSS_2 E1
VSS_3 G8 VSS_3 G8
FBA_DQS#4 G3 VSS_4 J2 FBA_DQS#7 G3 VSS_4 J2
FBA_DQS#5 B7 DQSL VSS_5 J8 FBA_DQS#6 B7 DQSL VSS_5 J8
DQSU VSS_6 M1 DQSU VSS_6 M1
VSS_7 M9 VSS_7 M9
VSS_8 P1 VSS_8 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
<24,25> FBA_RST# RESET VSS_10 RESET VSS_10
T1 T1 FBA_CLKA1
L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12
1
1
1
J1 B1 J1 B1 RV38
RV28 L1 NC1 VSSQ_1 B9 RV29 L1 NC1 VSSQ_1 B9 40.2_0402_1%
243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 PX@
PX@ L9 NC3 VSSQ_3 D8 PX@ L9 NC3 VSSQ_3 D8
2
FBA_MA15 M7 NC4 VSSQ_4 E2 FBA_MA15 M7 NC4 VSSQ_4 E2 CV131 PX@
2
2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 1 2
VSSQ_6 F9 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1 .01U_0402_16V7-K
VSSQ_8 VSSQ_8
1
G9 G9
VSSQ_9 VSSQ_9 RV39
96-BALL 96-BALL 40.2_0402_1%
SDRAM DDR3 SDRAM DDR3 PX@
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
2
B B
FBA_CLKA1#

CV105 CV106 CV107 CV108 CV109 CV110 CV116 CV117 CV118 CV119 CV120 CV121
10U_0603_6.3V6-M
10U_0603_6.3V6-M
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1U_0402_10V6-K
1 1 1 1 1 1 1 1 1 1 1 1
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2 2 2 2 2

CV111 CV112 CV113 CV114 CV115 CV122 CV123 CV124 CV125 CV126
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
1 1 1 1 1 1 1 1 1 1
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2 2 2
A A
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_VRAM_B

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
B+ to +LEDVDD POWER OK OK
LCD POWER CIRCUIT OK B+ +LEDVDD
need rework to +3VS 0_0805_5%

CMOS Camera
+3VS +LCDVDD_CON 2A 80 mil 2A 80 mil
R17 2 1 @
+3VS
Need Short
4.7U_0805_25V6-K
U7 C14 +3VS_CMOS_R
5 1 +LCDVDD_CON 1 J1 @
IN2 OUT 1 2
2 1 2
1 4.7U_0603_6.3V6-K 1
C1 GND JUMP_43X39
1U_0402_6.3V6K 4 3 PCH_ENVDD C2 2 +3VS_CMOS
IN1 EN
2 2
G5243AT11U_SOT23-5 LP2301ALT1G_SOT23-3
SA00005XJ00 W=40 mils @ W=40mils
D
D Q7 3 1 R3 1 2 D
0_0603_5%
PCH_ENVDD @ 1
<5> PCH_ENVDD
C3
G
2
1
.1U_0402_10V6-K
R35
100K_0402_5% 2
2
R5 1 @ 2
<6> CMOS_ON#
100K_0402_5%
1
C10
.1U_0402_10V6-K
@
2
JEDP1
+3VS
OK +LEDVDD 1
1
2
3 2
4 3
4
2
OK
<5> CPU_EDP_TX0+
CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 5
5
R10 OK
<5> CPU_EDP_TX0-
CPU_EDP_TX0- C16 1 2 .1U_0402_10V6-K EDP_TX0- 6
6
PCH_ENBKL R11 1 @ 2 4.7K_0402_5% 7
C 7 C
0_0402_5% @ OK
<5> CPU_EDP_TX1+
CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 8
8
OK
<5> CPU_EDP_TX1-
CPU_EDP_TX1- C18 1 2 .1U_0402_10V6-K EDP_TX1- 9
1
10 9
+3VS 10
OK <44> BKOFF#
R12 1 2 0_0402_5% DISPOFF# OK<5> CPU_EDP_AUX
CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 11
11
@ OK<5> CPU_EDP_AUX#
CPU_EDP_AUX# C21 1 2 .1U_0402_10V6-K EDP_AUX# 12
12
13
13
OK<5> PCH_ENBKL
R14 1 2 0_0402_5% ENBKL
ENBKL <44> OK DISPOFF# 14
14
2
@ 15
15
1
R8 R9 OK ACLU5 INVT_PWM
ACLU1 has two PCH PWM Pin
16
16
R16 100K_0402_1% 100K_0402_1% 17
+3VS 17
100K_0402_5% OK 18
18
@ @ 19
<5> CPU_EDP_HPD
1
R21 1 @ 2 20 19
2
0_0402_5% 21 20
1 +LCDVDD_CON 21
EDP_AUX W=60mils 22
EDP_AUX# C22 23 22
+3VS 23
+3VS
680P_0402_50V7K
2 OK<43> DMIC_DATA 24
24
@ OK <43> DMIC_CLK 25
25
2
26 31
R13 R15 27 26 G1 32
27 G2
2
100K_0402_1% 100K_0402_1% OK<7> USB20_P5

R182 1 @ 2 0_0402_5% USB20_P5_R 28
28 G3
33
R18 OK<7> USB20_N5
R183 1 @ 2 0_0402_5% USB20_N5_R 29
29 G4
34
1K_0402_5% @ @ +3VS_CMOS 30 35
1
@ 30 G5
2
W=40mils ACES_50406-03071-001
1
C24 ME@
OK<5> PCH_EDP_PWM
R19 1 2 0_0402_5% INVT_PWM OK 0.047U_0402_16V7K
1
@
1
R20
100K_0402_5%
EMI request
2
B B
Touch Screen OK .1U_0402_10V6-K

R22 1 TS@ 2 C23 1 2 TS@
<44> EC_TS_ON#
100K_0402_5%
+3VS_TS_R +3VS_TS
LP2301ALT1G_SOT23-3
D
3 1
Q11 TS@ JTS1
1 1
C25 R28 2 TS@ 1 10K_0402_5% TS_RS 2 1
G
2
.1U_0402_10V6-K 3 2
@ R23 1 TS@ 2 0_0402_5% USB20_N4_CONN 4 3
2 <7> USB20_N4 4
R24 1 TS@ 2 0_0402_5% USB20_P4_CONN 5 7
EMI request <7> USB20_P4
6 5 GND1 8
6 GND2
DMIC_CLK DISPOFF# INVT_PWM ACES_87213-00601-P01
+3VS +3VS_TS_R +3VS_TS
470P_0402_50V7K
USB20_P4_CONN ME@
C11
C12
C13
470P_0402_50V7K
100P_0402_50V8J
R25 1 TS@ 2 0_0402_5% R26 1 @ 2 0_0402_5% +3VS_TS USB20_N4_CONN

1 1 1 Touch Screen
2
+3VALW
2 2 2 R27 1 @ 2 0_0402_5%
1
@ @ @ @
D2
1
For EMI
L13 @ D1
A A
2
USB20_N4 1 2 USB20_N4_CONN AZC199-02S.R7G_SOT23-3
For EMI 1 2 @
2
OK USB20_P5 1
L12 @
2 USB20_P5_R USB20_P4 4 3 USB20_P4_CONN
AZ5215-01F_DFN1006P2E2
1
1 2 4 3
CMM21T-900M-N_4P For EMI
USB20_N5 4 3 USB20_N5_R
4 3
CMM21T-900M-N_4P Title
Security Classification LC Future Center Secret Data
Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/ CMOS/Touch screen
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
L2 @
OK HDMI_CLK-_C 1
1 2
2 HDMI_CLK-_CON 1 2
C26 3.3P_0402_50V8-C
@
OK HDMI_CLK+_C 4
4 3
3
HDMI_CLK+_CON 1 2
C27 3.3P_0402_50V8-C
HDMI2012F2SF-900T04_4P
+3VS
D L3 @ D
OK HDMI_TX0-_C 1
1 2
2 HDMI_TX0-_CON 1 2
C28 3.3P_0402_50V8-C
@
OK HDMI_TX0+_C 4
4 3
3
HDMI_TX0+_CON 1 2
C29 3.3P_0402_50V8-C
HDMI2012F2SF-900T04_4P
5
D3
G
L4 @ Q1B HDMI_DET 1 1 10 9 HDMI_DET
OK HDMI_TX1-_C 1
1 2
2 HDMI_TX1-_CON 1 2
C30 3.3P_0402_50V8-C HDMIDAT_R 2 2 9 8 HDMIDAT_R
@ 4 3 HDMICLK_R
S
4 4 7 7
D
OK HDMI_TX1+_C 4
4 3
3
HDMI_TX1+_CON 1 2 OK<5> APU_HDMI_DDC_CLK APU_HDMI_DDC_CLK HDMICLK_R HDMICLK_R
C31 3.3P_0402_50V8-C 2N7002KDWH_SOT363-6
2
HDMI2012F2SF-900T04_4P +5VS_HDMI 5 5 6 6 +5VS_HDMI
G
Q1A
L5 @ 3 3
OK HDMI_TX2-_C 1
1 2
2 HDMI_TX2-_CON 1 2
C32 3.3P_0402_50V8-C OK<5> APU_HDMI_DDC_DATA 1 6 HDMIDAT_R 8
S
APU_HDMI_DDC_DATA
D
@
OK HDMI_TX2+_C 4
4 3
3 HDMI_TX2+_CON 1 2 2N7002KDWH_SOT363-6
C33 3.3P_0402_50V8-C AZ1045-04F_DFN2510P10E-10-9
HDMI2012F2SF-900T04_4P @
For EMC
For EMC
C
OK HDMI_CLK-_C R29 1 2 499_0402_1% C
OK HDMI_CLK+_C R30 1 2 499_0402_1%

+5VS
+5VS +5VS_HDMI_F +5VS_HDMI
OK HDMI_TX0-_C R31 1 2 499_0402_1%
D5
2
OK HDMI_TX0+_C R32 1 2 499_0402_1% 2 F1
D4 1 1 2
OK HDMI_TX1-_C R33 1 2 499_0402_1%
+3VS @
3
RB491D_SOT23-3 0.5A_8V_KMC3S050RY
OK HDMI_TX1+_C R34 1 2 499_0402_1%
BAT54S-7-F_SOT23-3 1 2
1
OK HDMI_TX2-_C R37 1 2 499_0402_1% R36 0_0805_5% @
Follow Zx05 1
OK HDMI_TX2+_C R38 1 2 499_0402_1% C34
1
C .1U_0402_10V6-K
1
Provide DC bias RTMDS 499 ohm Q43 2 R202 1 2 150K_0402_5%
B R39 R40 2
1
D Q13 E MMBT3904WH_SOT323-3 2K_0402_5% 2K_0402_5%
3
+3VS 2
G
OK<5> APU_HDMI_HPD
2N7002KW_SOT323-3
2
1
1
S R205 R203 JHDMI1
3
100K_0402_5% 100K_0402_5% HDMI_DET 19

R42 1 @ 2 18 HP_DET
17 +5V
2
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
CEC
OK<5> APU_HDMI_CLK- APU_HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12
CK- GND1
20
11 21
CK_shield GND2
B
OK<5> APU_HDMI_CLK+ APU_HDMI_CLK+ C36 2 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10
CK+
B
OK<5> APU_HDMI_TX0- APU_HDMI_TX0- C37 2 1 .1U_0402_10V6-K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9

D0- GND3
22
8 23
D0_shield GND4
OK<5> APU_HDMI_TX0+ APU_HDMI_TX0+ C38 2 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
D0+
D1-
5
D1_shield
D1+
D2-
2
D2_shield
D2+
FOX_QJ111A1-RC0AH1-8H
ME@
Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON
HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON
HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON
HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

A A
3 3 3 3
8 8
AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

@ @ Security Classification LC Future Center Secret Data Title
Issued Date 2013/08/15 Deciphered Date 2013/08/15 HDMI_CONN
Rev
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Rev
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
+CRT_VCC_CON +5VS_HDMI
+5VS @
RVG39 1 2 0_0603_5%
CRT Connector 2
D16 @
1 1
F2 @
2 +CRT_VCC_CON
3 1
RB491D_SOT23-3 0.5A_8V_KMC3S050RY
1
C164
.1U_0402_10V6-K D26
W=40mils
1
2
AZ5425-01F_DFN1006P2E2
D D
2
2
JCRT1
@
6
@ PAD 1 CRT_DET# 11
T5
OK <5> APU_CRT_R
L17 1 2 CRT_R_CON 1
FCM1608CF-121T03_2P 7 For EMC
CRT_DDC_DAT_CON 12
OK <5> APU_CRT_G
L18 1 2 CRT_G_CON 2
FCM1608CF-121T03_2P 8
HSYNC_CON 13
OK <5> APU_CRT_B
L19 1 2 CRT_B_CON 3
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
FCM1608CF-121T03_2P 9
2
1 1 1 1 1 1 VSYNC_CON 14
R199 R200 R201 4
C156
C157
C158
C150
C149
C148
150_0402_1% 150_0402_1% 150_0402_1% 10 G 16
CRT_DDC_CLK_CON 15 G 17
2 2 2 2 2 2 5
1
1
@ SUYIN_070546HR015M25KZR
CLOSE TO CONN C139 ME@
100P_0402_50V8J
2
+5VS
R204
1 @ 2
1
C 0_0402_5% C
@ C166 OE#
.1U_0402_10V6-K
2 U4
1
74AHCT1G125GW_SOT353-5
L20
OE#
OK<5> APU_CRT_HSYNC
2
A Y
4 CRT_HSYNC_1 CRT_HSYNC_R 1 2 HSYNC_CON
10P_0402_50V8J
PBY100505T-800Y-N
1
3
D18
1 1 10 9
C135
CRT_R_CON CRT_R_CON
R215 1 @ 2 0_0402_5% @
2 2 2
CRT_G_CON 9 8 CRT_G_CON
CRT_B_CON 4 4 7 7 CRT_B_CON
+5VS CRB use 27 ohm SR L20/L21 Change to 0 ohm???
CRT_DET# 5 5 6 6 CRT_DET#
1 3 3
C167 OE# 8
.1U_0402_10V6-K
2 U5
5
74AHCT1G125GW_SOT353-5 AZ1045-04F_DFN2510P10E-10-9
L21 @
P
OE#
OK<5> APU_CRT_VSYNC
2
A Y
4 CRT_VSYNC_1 CRT_VSYNC_R 1 2 VSYNC_CON
10P_0402_50V8J
G
PBY100505T-800Y-N 1
3
C136
@
B R216 1 @ 2 0_0402_5% 2 B
D19
HSYNC_CON 1 1 10 9 HSYNC_CON
+3VS +5VS VSYNC_CON 2 2 9 8 VSYNC_CON
CRT_DDC_CLK_CON 4 4 7 7CRT_DDC_CLK_CON
CRT_DDC_DAT_CON 5 5 6 6CRT_DDC_DAT_CON
1
1
2K_0402_5%
2K_0402_5%
2
3 3
G
R197 R198
8
2
OK<5> 1 6 CRT_DDC_DAT_CON_R CRT_DDC_DAT_CON

S
APU_CRT_DDC_DATA
D
AZ1045-04F_DFN2510P10E-10-9
Q38A @
5
2N7002KDWH_SOT363-6
G
AMD require 33 ohm SR

For EMC
OK<5> 4 3 CRT_DDC_CLK_CON_R CRT_DDC_CLK_CON
S
APU_CRT_DDC_CLK
D
2N7002KDWH_SOT363-6 Q38B 1 1
@ C138 C137 @
68P_0402_50V8J 100P_0402_50V8J
2 2
A RP2 A
CRT_DDC_DAT_CON_R 1 8 CRT_DDC_DAT_CON
CRT_DDC_CLK_CON_R 2 7 CRT_DDC_CLK_CON
CRT_VSYNC_1 3 6 CRT_VSYNC_R
CRT_HSYNC_1 4 5 CRT_HSYNC_R
33_0804_8P4R_5% Title
T PN change Idea pad PN SD300003700
Security Classification LC Future Center Secret Data
Issued Date 2013/08/15 Deciphered Date 2013/08/15 CRT
Rev
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN 0.5msˉspecˉ100ms +3VALW_LAN +LAN_VDDREG
Need short
@
JL1 1 2 @ width : 40 mils RL1 1 2
1 2 0_0603_5%
JUMP_43X79
D D
1 1
CL1 CL2
.1U_0402_10V6-K
.1U_0402_10V6-K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K
CL4 CL5 CL6 CL7
2 2
2 2 2 2
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

+3VALW_LAN +3VS
+3VALW_LAN
2
RL4
G
2
10K_0402_5% QL1
RL5 @
10K_0402_5% UL1
1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# OK
<6>
S
1
ACLU1 reserved BDW GPIO27, ACLU5 removed 2N7002KW_SOT323-3

OK <44> LAN_WAKE# RL6 1 @ 2 0_0402_5% PCIE_WAKE#_R
33 0_0402_5% 2 1 RL18
GND
C +3VALW_LAN 32
AVDD33_2 REFCLK_N
16 CLK_PCIE_LAN#
CLK_PCIE_LAN# OK
<7>
@ C
<7>OK
RL8 1 2 RSET 31 15 CLK_PCIE_LAN
RSET REFCLK_P CLK_PCIE_LAN
2.49K_0402_1% +LAN_VDD10 30
AVDD10 HSIN
14 PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_N3 OK
<4>
OK LAN_XTALO 29
CKXTAL2 HSIP
13 PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_P3 OK
<4>
+3VS
LAN_XTALI 28
CKXTAL1 CLKREQB
12 LAN_CLKREQ#_R OK
TL3 @ 1 27
LED0 AVDD33_1
11 +3VALW_LAN OK
TL5 @ 1 26
LED1/GPIO MDIN3
10 LAN_MDI3-
LAN_MDI3- OK
<38>
TL4 @ 1 25
LED2 MDIP3
9 LAN_MDI3+
LAN_MDI3+ OK
<38>
1
OK +LAN_REGOUT 24
REGOUT AVDD10_2
8 +LAN_VDD10
RL9 +LAN_VDDREG 23
VDDREG MDIN2
7 LAN_MDI2-
LAN_MDI2- OK
<38>
1K_0402_1% +LAN_VDD10 22
DVDD10 MDIP2
6 LAN_MDI2+
LAN_MDI2+ OK
<38>
OK PCIE_WAKE#_R 21
LANWAKEB MDIN1
5 LAN_MDI1-
LAN_MDI1- OK
<38>
ISOLATE# 20 4 LAN_MDI1+
LAN_MDI1+ OK
<38>
2
ISOLATEB MDIP1
OK <19,40,6> PLT_RST#
PLT_RST# 19
PERSTB AVDD10_1
3 +LAN_VDD10
OK<4> PCIE_PRX_DTX_N3 CL10 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_N3 18
HSON MDIN0
2 LAN_MDI0-
LAN_MDI0- OK
<38>
ISOLATE# OK<4> PCIE_PRX_DTX_P3 CL11 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_P3 17
HSOP MDIP0
1 LAN_MDI0+
LAN_MDI0+ OK
<38>
CL10 close to Pin18
1
RL11 CL11 close to Pin17
15K_0402_5%
UL1 8106@
2
RTL8111GUL-CG_QFN32_4X4
8111@
RTL8106EUL-CG
B B
SA000060Q00
For RTL8111GUL/ RTL8106EUL (SWR mode)
+LAN_VDD10
+LAN_REGOUT LL1 1 2
2.2UH_NLC252018T-2R2J-N_5%
1 1 1 1 1 1 1 1
CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
4.7U_0603_6.3V6K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
2 2 2 2 2 2 2 @ 2 @
Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
Layout Note: LL1 must be
LAN ROM OK within 200mil to Pin36,
CL15,CL16 must be within
200mil to LL1
LAN_XTALI
+LAN_REGOUT: Width =60mil
YL1 LAN_XTALO
A A
1 4
OSC1 GND2
2 3
GND1 OSC2
1 1 Security Classification LC Future Center Secret Data Title
CL12 25MHZ_10PF_7V25000014 CL13
12P_0402_50V8-J 12P_0402_50V8-J Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_RTL8111GUL/RTL8106EUL
2 2
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
DL1/DL2
1'S PN:SC300003M00
TL1 8111@
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0+ 23 2 LAN_MDO0+
<37> LAN_MDI0+ MX1+ TD1+
DL1
LAN_MDI2- 9 3 LAN_MDI3- LAN_MDI0- 22 3 LAN_MDO0-
I/O4 I/O2 <37> LAN_MDI0- MX1- TD1-
1
2
NC1 10 21 4 MCT RL17
4 NC5 MCT2 TCT2
NC2 75_0603_5%
1
5 11 swap @ 9/13 LAN_MDI1+ 20 5 LAN_MDO1+
+3VALW_LAN VDD GND <37> LAN_MDI1+ MX2+ TD2+ DL3
1
2
6 8 LAN_MDI1- 19 6 LAN_MDO1- BS4200N-C-LV_SMB-F2
NC3 NC4 <37> LAN_MDI1- MX2- TD2-
2
LAN_MDI2+ 7 1 LAN_MDI3+ 18 7 MCT
I/O3 I/O1 MCT3 TCT3
2
AZ3033-04F_DFN2525P10E10 LAN_MDI2+ 17 8 LAN_MDO2+
LAN_MDI2- 16 9 LAN_MDO2-
<37> LAN_MDI2- MX3- TD3-
Place Close to TL1
15 10 MCT
MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL32
DL2 10P_0603_50V8-J CL25
LAN_MDI1- 9 3 LAN_MDI0- 1 LAN_MDI3- 13 12 LAN_MDO3- @ 1000P_1206_2KV7-K
I/O4 I/O2 <37> LAN_MDI3- MX4- TD4- 2 2
2
NC1 10 CL24
C NC5 C
4 0.1U_0402_25V6 BOTH_GST5009 LF
5 NC2 11 2
+3VALW_LAN VDD GND swap @ 9/13
6 8
NC3 NC4
LAN_MDI1+ 7 1 LAN_MDI0+ TL1 8106@
I/O3 I/O1 CHASSIS1_GND
AZ3033-04F_DFN2525P10E10
Place Close to TL2 TST1284C LF LAN

SP050008L00
JRJ1 ME@
12
GND_4
11
GND_3
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
LAN_MDO1+ 3
PR2+ CHASSIS1_GND
LAN_MDO2+ 4
PR3+
OK
LAN_MDO2- 5
PR3-
LAN_MDO1- 6
PR2-
LAN_MDO3+ 7
PR4+
LAN_MDO3- 8
PR4-
SANTA_130460-3
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_Transformer
B
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
Close to U1
SMSC thermal sensor REMOTE1+
Near GPU&VRAM
REMOTE+_R
OK 1
1
C44
1 placed near DIMM C45
100P_0402_50V8J 2
C
Q15
2200P_0402_50V7K @ B MMBT3904WH_SOT323-3
+3VS 2 E PX@
3
2 REMOTE-_R U1 REMOTE1-
1
VDD SCL
8 EC_SMB_CK2
EC_SMB_CK2 <20,44,5> OK
1 REMOTE+_R 2
D+ SDA
7 EC_SMB_DA2
EC_SMB_DA2 <20,44,5> OK
C47 REMOTE-_R 3 6
D- ALERT#
.1U_0402_10V6-K
2 R51 2 @ 1 4 5 REMOTE2+
Near CPU core
+3VS T_CRIT# GND
10K_0402_5% 1
1
NCT7718W_MSOP8 C46 C
100P_0402_50V8J 2 Q16
@ B MMBT3904WH_SOT323-3
2 E UMA@
Address 1001_101xb
3
REMOTE2-
REMOTE1+ R175 1 PX@ 2 0_0402_5%
REMOTE2+ R176 1 UMA@ 2 0_0402_5% REMOTE+_R
C REMOTE2- R177 1 UMA@ 2 0_0402_5% REMOTE-_R C
REMOTE1- R178 1 PX@ 2 0_0402_5%
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

Trace width/space:10/10 mil
Trace length:<8"
FAN Conn
B B
+5VS
@ JFAN1
R52 1 2 0_0603_5% +5VS_FAN 1
1
OK<44> EC_FAN_SPEED 2
2
1 1 OK<44> EC_FAN_PWM 3
3
C50 4
C49 .1U_0402_10V6-K 5 4
10U_0805_10V6K @ 6 GND1
2 2 GND2
ACES_85205-04001
ME@
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN
Custom
NM-A281 0.4

5 4 3 2 1
A B C D E
Mini-Express Card(WLAN/WiMAX) +3VS_WLAN
JWLAN1
1 2
GND1 3.3VAUX1
OK<7> USB20_P6
3
USB_D+ 3.3VAUX2
4
OK<7> USB20_N6
5
USB_D- LED#1
6 1 @ T2
7 8
GND2 NC
9 NC NC 10
11 NC NC 12
13 NC NC 14
15 16 1 @ T3
NC LED#2
17 18
1
19 MLDIR_SENSE GND16 20 1
21 DP_ML3N DP_AUXN 22
23 DP_ML3P DP_AUXP 24
25 GND3 GND13 26
27 DP_ML2N DP_ML1N 28
29 DP_ML2P DP_ML1P 30
31 GND4 GND14 32
33 DP_HPD DP_ML0N 34
OK 35 GND5 DP_ML0P 36
<4> PCIE_PTX_C_DRX_P4
OK<4> 37 PETP0 GND15 38 EC_TX_RSVD R62 1 @ 2 100_0402_1%
PCIE_PTX_C_DRX_N4
39 PETN0 RESERVED1 40 EC_RX_RSVD R63 1 @ 2 100_0402_1%
OK<4> 41 GND6 RESERVED2 42
PCIE_PRX_DTX_P4
OK<4> 43 PERP0 RESERVED3 44 R185 1 2 100_0402_1% OK
PCIE_PRX_DTX_N4 EC_RX <44>
45 PERN0 COEX3 46 If EC have error single , can remove it.
OK<7> 47 GND7 COEX2 48
CLK_PCIE_WLAN
OK<7> 49 REFCLKP0 COEX1 50 SUSCLK_R R55 1 @ 2 0_0402_5% OK
CLK_PCIE_WLAN# SUSCLK <6,9>
51 REFCLKN0 SUSCLK
<19,37,6> OK
52 PLT_RST#
PLT_RST#
OK 53 GND8 PERST0#
<6> OK
WLAN_CLKREQ_Q# 54 BT_OFF# R53 1 2 1K_0402_5%
PCH_BT_OFF#
OK <44> 55 CLKREQ0# RESERVED/W_DISABLE#2
<6>OK
56 WLAN_OFF# R56 1 @ 2 0_0402_5%
WLAN_WAKE# PCH_WLAN_OFF#
57 PEWAKE0# W_DISABLE#1 58 SMB_DATA_S3_R R58 1 @ 2 0_0402_5% OK
SMB_DATA_S3 <14,15,6>
59 GND9 I2C_DATA
<14,15,6>OK
60 SMB_CLK_S3_R R59 1 @ 2 0_0402_5%
SMB_CLK_S3
61 PETP1 I2C_CLK 62 1 @ T4
63 PETN1 I2C_ALERT# 64 EC_TX_R R184 1 2 100_0402_1% OK
EC_TX <44>
65 GND10 RESERVED4 66
+3VALW R125 1 @ 2 10K_0402_5% 67 PERP1 PERST1# 68 +3VS_WLAN
69 PERN1 CLKREQ1# 70 EC_TX_R
+3VS_WLAN R126 1 2 10K_0402_5% 71 GND11 PEWAKE1# 72
73 REFCLKP1 3.3VAUX4 74
1
75 REFCLKN1 3.3VAUX5
GND12 R186
76 77 100K_0402_5%
PEG1 PEG2
JAE_SM3ZS067U410BAR1000
2
ME@
2 2
WLAN_CLKREQ# OK +3VS to +3VS_WLAN (AOAC) OK

+3VS Need short +3VS_WLAN
+3VS J2 @
+3VS_WLAN 1 2
1 2
JUMP_43X79
2
+3VS
RF Solution
2
R60 C83 @ .1U_0402_10V6-K

G
Q18 10K_0402_5% +3VALW LP2301ALT1G_SOT23-3 1 2

AOAC@
D
Q17 3 1 AOAC@ C59 @ .1U_0402_10V6-K
1
<6> WLAN_CLKREQ# AOAC@ 3 1 WLAN_CLKREQ_Q# 1 2

S
1
2N7002KW_SOT323-3 C53 C60 @ .1U_0402_10V6-K
G
2
.1U_0402_10V6-K 1 2
AOAC@
2 C170@ .1U_0402_10V6-K
R61 1 @ 2 0_0402_5% R54 1 AOAC@ 2 1 2
<44> AOAC_ON#
1
100K_0402_5% C54 C172@ .1U_0402_10V6-K
If support AOAC, NC R61; .1U_0402_10V6-K 1 2
AOAC@
if not support AOAC, stuff R61. 2
3 3
4 4
Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN

Custom
NM-A281 0.4

A B C D E
A B C D E
+USB_VCCA
LEFT SIDE USB3.0 PORT X2 C55 1 2
+
220U_6.3V_M
U2 +USB_VCCA C56 1 2
+5VALW @ 1U_0603_25V6M
1 8
GND VOUT3 C57 1 2
1 2 7 @ 470P_0402_50V7K 1
2.2U_0603_10V6-K VIN1 VOUT2
C58 1 2 3 6
VIN2 VOUT1 JUSB1 ME@
<44,45> USB_ON# USB_ON# 4 5 USB_OC1# 1
EN/EN FLAG USB_OC1# <6> VBUS
OK <7> USB20_N2
USB20_N2 R65 1 @ 2 0_0402_5% USB20_N2_R 2
D-
OK AP2820CMMTR-G1_MSOP8
1
C61 OK <7> USB20_P2
USB20_P2 R64 1 @ 2 0_0402_5% USB20_P2_R 3
4 D+ 5
1000P_0402_50V7K GND GND1 6
@ GND2 7
Low Active 2A 2 GND3 8
GND4
C-K_20267-5K11-02
USB20_P2_R
+USB_VCCA
OK USB20_N2_R
AZ5425-01F_DFN1006P2E2
AZ5425-01F_DFN1006P2E2
AZ5425-01F_DFN1006P2E2
1
1
D9 D10 D11
1
2 2
2
@ @ @
2
USB20_P1_R
USB20_N2 1
L8
2 USB20_N2_R
D12
USB30_RX_R_N1 9 10
@
1 1USB30_RX_R_N1
OK USB20_N1_R
1 2
OK
AZ5425-01F_DFN1006P2E2
AZ5425-01F_DFN1006P2E2
OK USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1
1
USB20_P2 4 3 USB20_P2_R D13 D14
4 3 USB30_TX_R_N1 7 7 4 4 USB30_TX_R_N1
1
CMM21T-900M-N_4P
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1
3 3
2
8 @ @
2
AZ1045-04F_DFN2510P10E-10-9
3 3
DLW21SN900HQ2L_4P
For EMC
USB30_RX_P1 2 1 USB30_RX_R_P1
2 1
OK
USB30_RX_N1 3 4 USB30_RX_R_N1
3 4 +USB_VCCA
L9 swap @ 9/13
C62 1 2
@ 1U_0603_25V6M
DLW21SN900HQ2L_4P
USB30_TX_C_P1 2 1 USB30_TX_R_P1 C63 1 2
2 1
OK @ 470P_0402_50V7K
USB30_TX_C_N1 3 4 USB30_TX_R_N1
3 4 JUSB2 ME@
L10 swap @ 9/13 USB30_TX_P1 C64 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R68 1 @ 2 0_0402_5% USB30_TX_R_P1 9
<7> USB30_TX_P1 StdA_SSTX+
L11 OK USB30_TX_N1 C65 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R69 1 @ 2 0_0402_5% USB30_TX_R_N1
1
8 VBUS
<7> USB30_TX_N1 StdA_SSTX-
USB20_P1 1 2 USB20_P1_R USB20_P1 R70 1 @ 2 0_0402_5% USB20_P1_R 3
1 2 <7> USB20_P1 D+
OK OK USB20_N1 R71 1 @ 2 0_0402_5% USB20_N1_R
7
2 GND_DRAIN 10
<7> USB20_N1 D- GND_1
USB20_N1 4 3 USB20_N1_R USB30_RX_P1 R72 1 @ 2 0_0402_5% USB30_RX_R_P1 6 11
4 3 <7> USB30_RX_P1 StdA_SSRX+ GND_2
CMM21T-900M-N_4P OK USB30_RX_N1 R73 1 @ 2 0_0402_5% USB30_RX_R_N1
4
5 GND_5 GND_3
12
13
<7> USB30_RX_N1 StdA_SSRX- GND_4
SUYIN_020053GR009M2736L
4 4
For EMC

Issued Date 2013/08/08 Deciphered Date 2013/08/05 USB2.0/USB3.0 PORT (LEFT)
Rev
Custom
NM-A281 0.4

A B C D E
A B C D E F G H
SATA HDD Conn.

FOR 14"
JHDD1 ME@
1
SATA ODD Conn.
GND_1
OK<7> SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 C66 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2
A+
OK<7> SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 C67 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
A-
4
GND_2
1 OK<7> SATA_PRX_DTX_N0
SATA_PRX_DTX_N0 C68 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5
B-
1
OK<7> SATA_PRX_DTX_P0
SATA_PRX_DTX_P0 C69 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6
B+
JODD1
7 1
GND_3 GND_1
OK
<7> SATA_PTX_DRX_P1 SATA_PTX_DRX_P1 14@ C70 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_14 2
RX+
OK
<7> SATA_PTX_DRX_N1 SATA_PTX_DRX_N1 14@ C71 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_14 3
RX-
8 4
V33_1 GND_2
9
V33_2 OK
<7> SATA_PRX_DTX_N1
SATA_PRX_DTX_N1 14@ C72 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_14 5
TX-
<6> SATA0_DEVSLP SATA0_DEVSLP 10
V33_3 OK
<7> SATA_PRX_DTX_P1
SATA_PRX_DTX_P1 14@ C73 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_14 6
TX+
11 7
Need short +5VS_HDD 12 GND_4
OK
GND_3
J3 @ 13 GND_5 ODD_DETECT#_R 8
GND_6 DP
OK +5VS
1
1 2
2 14
V5_1
9
+5V_1
15
V5_2 OK +5V_ODD 10
+5V_2
JUMP_43X79 16 ODD_DA#_R 11 14
17 V5_3 12 MD GND1 15
18 GND_7 13 GND_4 GND2
19 DAS/DSS GND_5
+5VS_HDD 20 GND_8 SUYIN_127382FB013S255ZL
21 V12_1 ME@
22 V12_2
V12_3
1 1 1 1 1
C74 C75 C76 C77 C78
1000P_0402_50V7K .1U_0402_10V6-K 1U_0603_25V6M 10U_0805_10V6K 10U_0805_10V6K
@ @ @ @
2 2 2 2 2 SUYIN_127043HR022M32QZR_22P-T
FOR 15"
2 2
For EMC
SATA ODD FFC Conn
+5VS to +5V_ODD OK
OK JODD2
Need short OK SATA_PTX_DRX_P1 15@ C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 1
1
SATA_PTX_DRX_N1 15@ C80 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_15 2
2
J4 @ OK 3
3
1
1 2
2 OK SATA_PRX_DTX_N1 15@ C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 4
4
SATA_PRX_DTX_P1 15@ C82 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_15 5
JUMP_43X79 6 5
6
+5VALW +5VS +5V_ODD
OK<6> ODD_DETECT#
R74 1 @ 2 0_0402_5% ODD_DETECT#_R 7
7
8
LP2301ALT1G_SOT23-3 APU S5 GEVENT +5V_ODD 9 8
9
2
APU PH to +3VALW_APU ODD_DA#_R 10
Need check if ODD side only PD to GND. 10
S
3 1 Q19 R161
Otherwise require isloate circuit 0_0402_5% 11
GND_1
1
@
@ @ 12
10U_0805_10V6K
.1U_0402_10V6-K
R75 R76 GND_2
G
1 1
2
1
10K_0402_5% 10K_0402_5% ACES_51524-01001-003
@ @ ME@
2
1
2 2
C86
C85
R78 1 2 ODD_EN# R79 Device Attention/Device Present require GEVENT, but all GEVENT is S5
3
100K_0402_5% 1 470_0603_5% 3
@ C87 @
.01U_0402_16V7-K +3VS +3VS
2
1
Q20 D
1
2 2 Reserve for APU GEVENT S5
<6> ODD_EN
2
G R77
G
1
APU S5 GPIO Q21 D Q22 10K_0402_5%
2
S 2N7002KW_SOT323-3 ODD_EN# 2
3
R81 G 2N7002KW_SOT323-3
2
100K_0402_5% @
S 2N7002KW_SOT323-3
OK <6> ODD_DA#
1 3 ODD_DA#_R
@
S
3
@ APU S0 GPIO
.1U_0402_10V6-K
1
1
AMD Zero PWR ODD R80 1 @ 2 0_0402_5%
C165
4 4

Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD/ODD CONN
Custom
NM-A281 0.4

A B C D E F G H
5 4 3 2 1
+3VS +1.5VS +5VA AVDD_HP

+3VS
.1U_0402_10V6-K
.1U_0402_10V6-K
@
OK
CA11
CA12
RA2 1 2 0_0603_5% +3.3VD RA8 1 @ 2 0_0402_5% 2 2
+3VS RA3 1 @ 2 0_0603_5%
+3VALW
@ RA11 1 2 0_0402_5% DVDD_IO OK 1 1
+5VS +3VL
RA5 1 @ 2 0_0603_5% AVDD_HP OK
ACLU5 use +1.5VS
.1U_0402_10V6-K
@ 2
RA7 1 2 0_0603_5% +5VA CA1 RA25 1 2 0_0603_5%
D @ Close to Pin28 Close to Pin24 D

RA10 1 2 0_0603_5% +5VD 1
Close to Pin3
Close to Pin7
OK DA1
<44> BEEP# 2
.1U_0402_10V6-K
4.7U_0603_10V6-K
.1U_0402_10V6-K CA16 close to Pin18
1 PC_BEEP1 CA2 1 2 PC_BEEP 2 1 CA17 close to Pin2
OK Close to Pin27
1
<6> PCH_BEEP 3
RA14
1 2
CA3
.1U_0402_10V6-K
1U_0402_6.3V6K
BAT54CW_SOT323-3 10K_0402_5%
CA4
CA7
CA8
2.2U_0402_6.3V6M
2 1
.1U_0402_10V6-K
UA1
2
2 1
OK<6>
CA5
HDA_RST_AUDIO# 9 3 FILT_1.8V
HDA_RST_AUDIO# RESET# FILT_1.8V 1 2
OK
CA6
7 DVDD_IO
VDD_IO 2
VDDO_3.3 1 2
OK<6> HDA_BITCLK_AUDIO
HDA_BITCLK_AUDIO 5
BIT_CLK DVDD_3.3
18 +3.3VD OK
OK<6> HDA_SYNC_AUDIO
HDA_SYNC_AUDIO 8
SYNC AVDD_3.3
27 AVDD_3.3
RA16 29 VREF_1.65V
VREF_1.65V
OK<6> HDA_SDIN0
33_0402_5% 1 2 SDATA_IN 6
SDATA_IN AVDD_5V
28 +5VA OK
OK<6>
.1U_0402_10V6-K
1U_0402_6.3V6K
HDA_SDOUT_AUDIO 4
HDA_SDOUT_AUDIO SDATA_OUT
CA10
CA9
MICBIASB
+3.3VD
CX20751-11Z 2 1
LINE_B_R
LINE_B_L
BAT54AWT1G_SOT323-3
OK PC_BEEP 10
PC_BEEP LEFT+
12 SPK_L+ OK
OK SPKR_MUTE# 39
SPKR_MUTE# LEFT-
14 SPK_L- OK
1
1 2
JSENSE 38
JSENSE RIGHT+
17 SPK_R+ OK DA2
2
37
GPIO1/PORTC_R_MIC RIGHT-
15 SPK_R- OK @RA42
@ RA42 RA41@
1
C RA15 0_0402_5% 0_0402_5% C
5.11K_0402_1% 36 35
MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC
OK
<33> DMIC_CLK
33_0402_5% 1 RA18 2 DMIC_CLK_R 40 34 MICBIASB OK RA39 RA40 Close to Pin29
2
DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
OK
<33> DMIC_DATA
RA19 1 @ 2 DMIC_DATA_R 1 100_0402_5% 100_0402_5%
1
2
0_0402_5% DMIC_DAT/GPIO1 33 LINE_B_R
2
PORTB_R_LINE
OK
<45> PLUG_IN
RA17 1 2 JSENSE .1U_0402_10V6-K
PORTB_L_LINE
32 LINE_B_L
39.2K_0402_1% OK +5VD 1 2 11
CLASS-D_REF 1 1
CA13
PORTD_A_MIC
30 PORTD_A_MIC OK
1
RA36 1 2 13
LPWR_5.0 PORTD_B_MIC
31 PORTD_B_MIC OK CA35 CA36
20K_0402_1% 16 RA37 RA38 10U_0603_6.3V6M 10U_0603_6.3V6M
RPWR_5.0 2 2
HGNDA
25 RING2_CONN OK 3K_0402_1% 3K_0402_1%
CA14 1 2 1U_0402_6.3V6K 19
FLY_P HGNDB
26 RING3_CONN OK
20
2
FLY_N
AVDD_HP
24 AVDD_HP OK
CA17 1 2 2.2U_0402_6.3V6M 21
AVEE
PORTA_R
23 HPOUT_R RA20 1 2 75_0402_1%
HP_OUTR OK
<45>
41
GND PORTA_L
22 HPOUT_L RA21 1 2 75_0402_1%
HP_OUTL OK
<45>
+5VD
CX20752-21Z_QFN40_5X5 RA22
PORTD_A_MIC 1 2 100_0402_5% CA20 1 2 2.2U_0402_6.3V6M
RING3_CONN OK
<45>
OK
CA15
CA16
CA18
CA19
4.7U_0603_10V6-K
4.7U_0603_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
PORTD_B_MIC 1 2 100_0402_5% CA21 1 2 2.2U_0402_6.3V6M

RING2_CONN <45>
1 1 2 2
RA1 1 @ 2 0_0402_5% RA23
RA4 1 @ 2 0_0402_5%
2 2 1 1
RA6 1 @ 2 0_0402_5%
RA9 1 @ 2 0_0402_5%
B RA12 1 @ 2 0_0402_5% B
+3.3VD
Close to Pin11,13,16 RA13 1 @ 2 0_0402_5%
RA24 1 @ 2
1
0_0402_5% GND GNDA

RA28
47K_0402_5% Use 250mils wide trace bridging
RB751V-40_SOD323-2
AGND and DGND at codec
OK HDA_RST_AUDIO# DA3 1 2 @
2
SPKR_MUTE# OK
OK RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 JSPK1
<44> EC_MUTE#
HDA_RST_AUDIO# PLUG_IN DMIC_CLK_R SPK_R+ LA1 1 2BLM18PG221SN1D_2P SPK_R+_CONN 1
SPK_R- LA2 1 2BLM18PG221SN1D_2P SPK_R-_CONN 2 1
2
220P_0402_50V7K
100P_0402_50V8J
C43
C15
HDA_SYNC_AUDIO SPK_L+ LA3 1 2BLM18PG221SN1D_2P SPK_L+_CONN 3
SPK_L- LA4 1 2BLM18PG221SN1D_2P SPK_L-_CONN 4 3
1 1 4
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
CA27
CA28
CA29
CA30
RA35 1 @ 2 HDA_SDOUT_AUDIO
0_0402_5% 2 2 2 2 5
GND1
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
1 CA31
1 CA32
1 CA33
1 CA34
RA27 1 @ 2 HDA_BITCLK_AUDIO 6
27_0402_5% 2 2 GND2
HDA_SDIN0 ACES_88231-04001
@1 @1 @1 @1 ME@
CA22
CA23
CA24
CA25
CA26
22P_0402_50V8-J
22P_0402_50V8-J
22P_0402_50V8-J
33P_0402_50V8J
33P_0402_50V8J
2
1 1 1 1 1
2 2 2 2 2
@
A A
For EMI

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Codec_CX20752
Rev
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
@ BORAD ID Config
RE1 1 2 0_0603_5% +3VL +3VALW_R
Vcc 3.3V +/- 5%
RE3 1 2 0_0603_5% +3VALW

RE33 100K +/- 1%
+3VALW_EC Close EC
2
+3VALW_R Board ID
@ RE33
RE34 VAD_BID min V AD_BID typ VAD_BID max Phase
+3VALW_R
LE1 1 2 HCB1608KF-181T20 CE3
1 2 VCOREVCC
10K_0402_5%
@
0 0K +/- 5% 0 V 0 V 0 V SDV
1 1 All capacitors close to EC 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
1
CE4 .1U_0402_10V6-K +3VALW_R
.1U_0402_10V6-K CE5 Board_ID
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
1000P_0402_50V7K
2
2 EC_AGND 2
LE2 1 2 HCB1608KF-181T20
+3VS +3VALW_EC
1
CE6
1
CE7
1
CE8
1
CE9
1
CE10
1
CE11 RE50
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
EC_AGND
+VCCRTC RE4 1 @ 2 0_0402_5%
@
10K_0402_5%
@
4 4.7K +/- 5% 0.141 V 0.148 V 0.155 V
2 2 2 2 2 2
@
5 24K +/- 5% 0.612 V 0.638 V 0.664 V
1
D RE6 1 2 0_0402_5% D
minimum trace width 12 mil
114
121
127
Change RE6 to 0ohm jump
12
11
26
50
92
74
3
UE1
LPC_FRAME# APU S5 PWR PH
VSTBY(PLL)
VBAT
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCORE
VCC
AVCC
+5VS +3VS
<20> WRST#
<45> OK
4 24
+3VALW_R <6> KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED#
<7> SERIRQ
5
SERIRQ/GPM6 PWM1/GPA1
25
BATT_CHG_LED# OK
<45>
2
<7,9> LPC_FRAME#
LPC_FRAME# 6
LFRAME#/GPM5 PWM2/GPA2
28
BATT_LOW_LED# OK
<45>
OK <7> LPC_AD3
7
LAD3/GPM3 PWM3/GPA3
29 VGA_AC_BATT
VGA_AC_BATT <20>
RE52 RE51
DE1 @1 2 OK <7> LPC_AD2
8
LAD2/GPM2 PWM PWM4/GPA4
30 0_0402_5% @ 0_0402_5%
OK <7> LPC_AD1
9
LAD1/GPM1 PWM5/GPA5
31 EC_FAN_PWM
EC_FAN_PWM <39>OK
@
OK <7> LPC_AD0
10 32
BEEP# <43> OK
1
RB751V-40_SOD323-2 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34
<7,9> CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7
RE8 1 2 100K_0402_5% WRST# 14 120
WRST# TMRI0/GPC4 BATT_LEN# <52>
15
ECSMI#/GPD4 TMRI1/GPC6
124 SUSP#
SUSP# OK
<46,55,56,58>
TP_CLK RE12 2 1 4.7K_0402_5%
1 OK
<40> EC_RX
EC_RX 16
PWUREQ#/BBO/SMCLK2ALT/GPC7
CE12
OK
<40> EC_TX
EC_TX 17
LPCPD#/GPE6 ADC0/GPI0
66 NTC_V
NTC_V <51>
TP_DATA RE13 2 1 4.7K_0402_5%
APU_LPC_RST# 22 67 ADC1
1U_0402_6.3V6K<6> APU_LPC_RST#
23 LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP
2 <6> EC_SCI# ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP <52,53>
126 ADC 69 Board_ID
<6> GATEA20 GA20/GPB5 ADC3/GPI3
IT8586E/AX
70 RE53 2 @ 10_0402_5%
ADC4/GPI4 EC_APU_ALWEN <56>
71 ADP_I <53>
ADC5/DCD1#/GPI5 72 VR_IMVP_IMON +3VALW_R
ADC6/DSR1#/GPI6 VR_IMVP_IMON <59>
KSI[0..7]
KSI0
KSI1
58
59 KSI0/STB#
LQFP-128L ADC7/CTS1#/GPI7
73
78
ADAPTER_ID <51>
SUSP# RE18 1 @ 2 100K_0402_5%
<45> KSI[0..7] KSI1/AFD# DAC2/TACH0B/GPJ2 VR_APU_PWRGD <59>
KSI2 60 79
KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON <51,54>
KSI3 61 DAC 80 H_PROCHOT#_EC
<45> KSO[0..17] KSI3/SLIN# DAC4/DCD0#/GPJ4
KSI4 62 81 ENBKL <33>
KSI5 63 KSI4 DAC5/RIG0#/GPJ5
KSI6 64 KSI5 85 REP2
KSI7 65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# <6>
KSO0 36 87 EC_SMB_CK1 1 8
+3VALW_R
KSO1 37 KSO0/PD0 GPF2 88 RE54 2 @ 10_0402_5% EC_SMB_DA1 2 7
KSO1/PD1 Int. K/B PS2 GPF3 APUALW_PWRGD <56>
C KSO2 38
KSO2/PD2 Matrix PS2CLK2/GPF4
89 TP_CLK
TP_CLK <45> OK EC_SMB_CK2 3 6
+3VS
C
KSO3 39
KSO3/PD3 PS2DAT2/GPF5
90 TP_DATA
TP_DATA <45> OK EC_SMB_DA2 4 5
KSO4 40
KSO4/PD4
OK KSO5
KSO6
41
42 KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3
96
97
CAPS_LED# <45>
2.2K_0804_8P4R_5%
KSO6/PD6 GPH4/ID4 EC_VR_ON <59>
KSO7 43 98 REP4
KSO7/PD7 GPH5/ID5 ACOFF <53>
KSO8 44 99
KSO8/ACK# GPH6/ID6 PCH_PWROK can be removed EC_SYS_PWRGD <6>
KSO9 45 EC_FAN_SPEED 1 8 +3VS
KSO10 46 KSO9/BUSY 101 EC_SPI_CS0# USB_ON# 2 7
KSO10/PE NC1 +5VALW
KSO11 51 102 EC_SPI_SI LAN_WAKE# 3 6 +3VALW_R
KSO12 52 KSO11/ERR# NC2 103 EC_SPI_SO 4 5
KSO12/SLCT SPI Flash ROM NC3
KSO13 53 105 EC_SPI_CLK
KSO14 54 KSO13 NC4 10K_0804_8P4R_5%
KSO15 55 KSO14
KSO15
<53> OK
KSO16 56 108
KSO16/SMOSI/GPC3 AC_IN# ACIN#
KSO17 57
KSO17/SMISO/GPC5 UART LID_SW#
109 LID_SW#
LID_SW# OK
<45> +3VS
OK<45> ON/OFF ON/OFF 110

PWRSW# EGAD/GPE1
82 EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
111 SM Bus 83
XLP_OUT EGCS#/GPE2 EC_ON <54>
EC_SMB_CK1 115 84 LPC_FRAME# RE7 1 @ 2 10K_0402_5%
<52,53> EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3 ADAPTER_ID_ON# <51>
Charger, BATT EC_SMB_DA1 116
<52,53> EC_SMB_DA1 SMDAT1/GPC2
<55> VDDQ_PGOOD 117 GPIO 77 PM_SLP_S5# PM_SLP_S5# <6> ENBKL RE9 1 @ 2 100K_0402_5%
SMCLK2/PECI/GPF6 GPJ1 ACLU5
<43> OK
118 100
SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 EC_MUTE#
EC_SMB_CK2 94 106
<20,39,5> EC_SMB_CK2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 PCH_PWR_EN <46,52>
APU,GPU,Thermal Sensor EC_SMB_DA2 95 104 2 @ 1
+3VL<20,39,5> EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 VGA_PWROK <19,58,6> +3VL
<55>OK
107 SYSON RE25 0_0402_5%
DTR1#/SBUSY/GPG1/ID7 SYSON
CRX0/GPC0
119 BKOFF#
BKOFF# <33> OK
<40>OK
Change RE27 to 0ohm jump @ 123 ON/OFF RE35 1 @ 2 10K_0402_5%
CTX0/TMA0/GPB2 AOAC_ON#
RE27 1 2 0_0402_5% 112 18
VSTBY0 RI1#/GPD0 PM_SLP_S3# <6>
OK
<37> LAN_WAKE# 125
GPE4 RI2#/GPD1
21 BKOFF# RE36 1 @ 2 10K_0402_5%
WAKE UP TACH2/GPJ0
76 NOVO# <45> OK
TACH1A/TMA1/GPD7
48
EC_TS_ON# <33> OK LID_SW# RE38 1 2 10K_0402_5%
TACH0A/GPD6
47 EC_FAN_SPEED EC_FAN_SPEED OK
<39>
OK
<41,45> USB_ON#
USB_ON# 33
GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0
19 WLAN_WAKE#
WLAN_WAKE# <40> OK
<52,54,56> ALW_PWRGD
35 GPIO 20
RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# <45>
93
<6> EC_RSMRST# CLKRUN#/GPH0/ID0 SUSP# RE19 1 2 100K_0402_5%
OK
<6> EC_WAKE#
2
CK32KE/GPJ7
SYSON RE21 1 2 100K_0402_5%
OK<6> AC_PRESENT
128
CK32K/GPJ6 Clock
BKOFF# RE40 1 2 10K_0402_5%
B B
ADC1 RE14 1 2 100K_0402_5%
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
IT8586E-AX_LQFP128_14X14
1
27
49
91
113
122
75
EC_AGND
ACIN
+3VL
1
@
RE42 @ EC_SPI_CS0# RE45 2 1 0_0402_5% SPI_CS0#
SPI_CS0# <7>
10K_0402_5%
@
EC_SPI_SI RE47 2 1 0_0402_5% SPI_SI
2
SPI_SI <7>
ACIN# @
EC_SPI_SO RE48 2 1 0_0402_5% SPI_SO
SPI_SO <7>
Mirror Core
+3VL EC_SPI_CLK RE49 2
@
1 0_0402_5% SPI_CLK EMI/ESD Req
SPI_CLK <7>
APU_LPC_RST# SYSON
CLK_PCI_EC RE2 1 @ 2 10_0402_5% +3VS
EC_ON RE55 2 1 100K_0402_5%
A BATT_TEMP @ CE16 1 2 100P_0402_50V8J A
1
1 1
For factory EC flash H_PROCHOT# OK CE2
10P_0402_50V8J CE1 @ @ CE13
ACIN# @ CE17 1 2 100P_0402_50V8J
1
+3VL @ 2 220P_0402_50V7K .1U_0402_10V6-K ON/OFF @ CE18 1 2 1U_0402_6.3V6K CE19 @
2 2 .1U_0402_10V6-K
+3VALW_R EC_SMB_CK1 PAD 1 @ Change RE34 to 0ohm jump
IT1 2
EC_SMB_DA1 PAD 1 @
IT2
EC_MUTE# RE43 2 1 100K_0402_5% PAD 1 @ RE34 1 @ 2 0_0402_5% H_PROCHOT# <5>
IT3 <59> VR_HOT#
PAD 1 @
IT4
RE44 2 @ 1 10K_0402_5% PAD 1 @
IT5
1
QE1 D 1
RE46 2 @ 1 10K_0402_5% H_PROCHOT#_EC 2 CE14 Title
G 47P_0402_50V8J Security Classification LC Future Center Secret Data
KSI7 PAD 1 @ @
when mirror, GPG2 pull high KSI6 PAD 1 @
IT6
IT7
2N7002KW_SOT323-3 S 2 Issued Date 2013/08/08 Deciphered Date 2013/08/05 EC ITE8586LQFP
3
WRST# PAD 1 @
when no mirror, GPG2 pull low IT8 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Rev
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
ON/OFF switch D22 AZ5215-01F_DFN1006P2E2

+3VL +3VALW
K/B Connector +3VS 2 1 14" 15"
2 1
KB_1 KSI1_14 KSO0_15
2
KSI[0..7] OK D23 AZ5215-01F_DFN1006P2E2 OK KB_2 KSI7_14 KSI2_15
R82 R83
KSI[0..7] <44>
14" 15"
1
100K_0402_5% @ 100K_0402_5% KSO[0..17] 2 1 KB_3 KSI6_14 KSI3_15
KSO[0..17] <44> 2 1
JKB2 R84 R90
300_0402_5% 300_0402_5% KB_4 KSO9_14 KSO5_15
1
D15 27 JKB1
GND1
OK <44> NOVO#
NOVO# 2 28
<44> NUM_LED#
NUM_LED# 30 31 KB_5 KSI4_14 KSO1_15
2
CAPS_LED# 26 GND2 PWR_NUM_LED 29 30 GND1 32
<44> CAPS_LED# 26 29 GND2
1 NOVO_BTN# OK PWR_CAPS_LED 25
25
CAPS_LED# 28
28
KB_6 KSI5_14 KSI0_15
@ KSO15 24 PWR_CAPS_LED 27
24 27
OK ON/OFF R85 1 2 0_0402_5% 3 KSO10 23
23
KSO17 26
26 KB_7 KSO0_14 KSO2_15
D KSO11 22 KSO16 25 D
BAT54CW_SOT323-3 KSO14 21 22 KSO15 24 25
21 24 KB_8 KSI2_14 KSO4_15
KSO13 20 KSO10 23
KSO12 19 20 KSO11 22 23
19 22 KB_9 KSI3_14 KSO7_15
KSO3 18 KSO14 21
+3VALW +3VL KSO6 17 18 KSO13 20 21
17 20 KB_10 KSO5_14 KSO8_15
KSO8 16 KSO12 19
@ KSO7 15 16 KSO3 18 19
15 18
KB_11 KSO1_14 KSO6_15
2
SW5 KSO4 14 KSO6 17
1 3 R111 R114 KSO2 13 14 KSO8 16 17
13 16 KB_12 KSI0_14 KSO3_15
100K_0402_5% 100K_0402_5% KSI0 12 KSO7 15
2 4 @ KSO1 11 12 KSO4 14 15
11 14 KB_13 KSO2_14 KSO12_15
KSO5 10 KSO2 13
1
SMT1-05_4P @ KSI3 9 10 KSI0 12 13
KB_14 KSO4_14 KSO13_15
6
5
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF KSI2 8 9 KSO1 11 12

ON/OFF <44> 8 11
OK KSO0 7
7
KSO5 10
10 KB_15 KSO7_14 KSO14_15
KSI5 6 KSI3 9
J5 1 2 @ KSI4 5 6 KSI2 8 9
5 8
KB_16 KSO8_14 KSO11_14
KSO9 4 KSO0 7
SHORT PADS KSI6 3 4 KSI5 6 7
3 6 KB_17 KSO6_14 KSO10_15
KSI7 2 KSI4 5
KSI1 1 2 KSO9 4 5
1 4 KB_18 KSO3_14 KSO15_15
KSI6 3
ACES_88514-02601-071 KSI7 2 3
2 KB_19 KSO12_14 KSO16_15
ME@ KSI1 1
1
KB_20 KSO13_14 KSO17_15
ACES_50504-3041-001
ME@ KB_21 KSO14_14 KB_LED_PWR_15
TP/B Connector
KB_22 KSO11_14 CAPS_LED#_15
KB_23 KSO10_14 VDD_15
KB_24 KSO15_14 NUM_LED#_15
+5VS TP_PWR TP_CLK
C R160 1 @ 2
TP_DATA PWR/B Connector C
USB I/O Connector
2
+3VS 0_0402_5%
JTP1 DT1
R141 1 2 OK 1
1
0_0402_5% TP_CLK 2
<44> TP_CLK 2
TP_DATA 3
.1U_0402_10V6-K
<44> TP_DATA 3
1 OK 4
OK @1 @1 OK TP_P5 5 4
Right Side USB2.0 Port X 1 (USB/B)
100P_0402_50V8J
100P_0402_50V8J
5 D21
OK TP_P6 6
6 GND1
7 @
8
2 GND2
C114
2 1
2 2 2 1
C115
C116
ACES_50503-0060N-001
ME@ @ AZC199-02S.R7G_SOT23-3 +3VL +5VALW U3 +USB_VCCB
1
For EMC AZ5215-01F_DFN1006P2E2 JPWRB1 1 8
GND VOUT3 +USB_VCCB
OK 1
1
2.2U_0603_10V6-K
NOVO_BTN# 2 C119 1 2 2 7
2 VIN1 VOUT2 +3VS ACES_50505-0184N-P01
OK ON/OFFBTN# 3
3
OK TP_LEFT Button OK TP_LEFT Button LID_SW# 4 3 6 18 20
AZ5215-01F_DFN1006P2E2
AZ5215-01F_DFN1006P2E2
AZ5215-01F_DFN1006P2E2
TP_P5 TP_P5 5 4 VIN2 VOUT1 17 18 G2 19
5 17 G1
1
D20 D24 D17 6 7 <41,44> USB_ON# USB_ON# 4 5 USB_OC2# 16
6 GND1 EN/EN FLAG USB_OC2# <6> 16
8 OK <7> OK USB20_P0
USB20_P0 R66 1 @ 20_0402_5% USB20_P0_R 15
1
GND2 15
1 OK <7> OK USB20_N0
USB20_N0 R67 1 @ 20_0402_5% USB20_N0_R 14
14
1
5
AZ5215-01F_DFN1006P2E2
AZ5215-01F_DFN1006P2E2
ACES_50503-0060N-001 AP2820CMMTR-G1_MSOP8 C120 13
13
SW1 SW2 ME@ 1000P_0402_50V7K OK USB20_P3 USB20_P3 R86 1 @ 20_0402_5% USB20_P3_R 12
EVQPLHA15_4P
EVQPLHA15_4P
A
A1
GND2 GND1
A1
GND2 GND1
<7> 12
1
2
DT2 DT3 Low Active 2A 2
@
<7> OK USB20_N3 USB20_N3 R87 1 @ 20_0402_5% USB20_N3_R 11
11
@ 10
For 14" For 15"
1
2
9 10
8 9
LID_SW# <44> 8
1 VDD 1 VDD OK OK<43> HP_OUTR 7
B1
B1
HP_OUTR 7
B
B
2
2
14@ 15@ OK<43> HP_OUTL HP_OUTL 6
6
@ @ 5
3
2
5
OK
<43> RING2_CONN
RING2_CONN 4
4
For EMC 3
2 CLK 2 CLK OK
<43> RING3_CONN
RING3_CONN 2 3
2
PLUG_IN 1
<43> PLUG_IN 1
OK TP_RIGHT Button TP_RIGHT Button OK
3 DAT 3 DAT TP_P6 OK TP_P6 @ JUSB3
L14
1
5
AZ5215-01F_DFN1006P2E2
AZ5215-01F_DFN1006P2E2
B USB20_N0 1 2 USB20_N0_R B
4 GND 4 GND SW3 SW4 1 2
EVQPLHA15_4P
EVQPLHA15_4P
A
A1
GND2 GND1
A1
GND2 GND1
1
DT4 DT5
USB20_P0 4 3 USB20_P0_R
1
4 3
5 TP-L 5 TP-L CMM21T-900M-N_4P
L15
B1
B1
B
B
2
14@ 15@ USB20_P3 1 2 USB20_P3_R

@ @ 1 2
6 TP-R 6 TP-R
3
USB20_N3 4 3 USB20_N3_R
4 3
CMM21T-900M-N_4P
For 14" For 15"
LED
OK <44> PWR_LED# PWR_LED# LED1 1 2 14@ R142 1 2 1.5K_0402_5%

+5VALW
LTW-C193TS5
LED4 1 2 15@
LTW-C193TS5
OK
<44> BATT_LOW_LED# BATT_LOW_LED# LED2 1 2 14@ R143 1 2 470_0402_5% +3VALW
LTST-C193KFKT-LC
A A
LED5 1 2 15@
LTST-C193KFKT-LC
OK
<44> BATT_CHG_LED# BATT_CHG_LED# LED3 1 2 14@ R144 1 2 1.5K_0402_5% +5VALW
LTW-C193TS5
LED6 1 2 15@
Issued Date 2013/08/08 Deciphered Date 2013/08/05 KBD/PWR/IO/LED/TP Conn.
LTW-C193TS5 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
NM-A281 0.4
Date: Friday, February 21, 2014 Sheet 45 of 60

5 4 3 2 1
A B C D E
Load Switch For DisCharge
+5VALW To +5VS OK
+VCCRTC +5VALW
+5VS, C159 ‐‐> 1.5ms
+3VALW To +3VS
1
+3VS, C160 ‐‐> 2.5ms R156 R157 +0.675VS
+3VALW VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm Need Short +3VS

100K_0402_5% 100K_0402_5%
@
1
U13 J11 @
2
1 14 +3VS_LS 1 2 R159
R4 1 @ 2 0_0402_5% 3VSON 2 VIN1_1 VOUT1_2 13 1 2 SUSP 47_0603_5%
VIN1_2 VOUT1_1 JUMP_43X118
1 1
3VSON 3 12 C173 1 2 2200P_0402_25V7-K
2
C178 @ ON1 CT1 C175 @
1U_0402_6.3V6-K +5VALW 4 11 0.1U_0402_10V7-K
VBIAS GND
3
1 2 2 1
Q6A D D Q6B
OK SUSP# R2 1 @ 2 0_0402_5% 5VSON
+5VALW
5VSON 5
ON2 CT2
10 C176 1 2 1000P_0402_50V7K
+5VS
OK<44,55,56,58> SUSP#
2
G G
5 SUSP
6 9 J12 @
7 VIN2_1 VOUT2_2 8 +5VS_LS 1 2 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6
1 1
4
VIN2_2 VOUT2_1 1 2
C180 C179 1 15 JUMP_43X118 1
GPAD
1U_0402_6.3V6-K
2 2
1U_0402_6.3V6-K Need Short
C177 @ TPS22966DPUR_WSON14_2X3 C174 @
1U_0402_6.3V6-K 0.1U_0402_10V7-K
2 2
+1.8VALW to +1.8VS AON6414AL +0.95VALW to +0.95VS AON6414AL

VDS=30V VGS=20V, ID=50A, VDS=30V VGS=20V, ID=50A,
Q39 Q41
+1.8VALW +1.8VS +/- 5% 1.5A Rds=8mohm @ VGS=10V +0.95VALW +0.95VS +/-5% 3.6A Rds=8mohm @ VGS=10V
+/- 2% AON6414AL_DFN8-5 VGS(th)=2.5V Max +/- 1.5% AON6414AL_DFN8-5 VGS(th)=2.5V Max +3VALW
Need Short +3VALW_APU
36m OHM is requried 9m OHM is requried
1 1 J7 @
2 1 1 2 1 1 1 2
5 3 5 3 1 2
1 1
C141 C140 C142 C146 C145 C147
10U_0805_25V6K 10U_0603_6.3V6M 1U_0603_25V6M 10U_0805_25V6K 10U_0603_6.3V6M 1U_0603_25V6M JUMP_43X79
1
@ 2 2 @ 2 2
4
4
2 R213 @ 2 R188 @
470_0603_5% 470_0603_5% LP2301ALT1G_SOT23-3 Id=3.2A
@
D
@ @ Q29 3 1
2
2 2 R210 1 5VS_GATE 2 R206 1 5VS_GATE 2
0_0402_5% Need change to AON6414AL (No symbol) 0_0402_5%
R211 R193
G
2
1.8VS_GATE_R 1 @ 2 R194 2 @ 1 1.8VS_GATE 2 R214 1 +VSB 0.95VS_GATE_R 1 @ 2 R190 2 @ 10.95VS_GATE 2 R189 1 +VSB
0_0402_5% 0_0402_5% 470K_0402_5% 0_0402_5% 0_0402_5% 470K_0402_5%
1
1
1 D Q45 Q46 @ D 1 D Q37 Q40 @ D
R212 2 SUSP 2 R187 2 SUSP 2 PCH_PWR_EN#_R
C143 820K_0402_5% G G C144 820K_0402_5% G G
0.01U_0402_25V7K 0.01U_0402_25V7K 1
2 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 2 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 C131
2
3
.1U_0402_10V6-K
@
2
+5VALW
+3VALW_R
Need check all the EN pin and PWR Sequence.
1
R163 R155
100K_0402_5% 100K_0402_5%
@ @
+1.8VALW to +1.8VGS Reserve for GPU/APU share +1.8V +0.95VALW to +0.95VGS Reserve for GPU/APU share +0.95V
2
PCH_PWR_EN#_R R158 1 @ 2 100K_0402_5% PCH_PWR_EN#
+/- 2% +1.8VALW Q42 PX@ +1.8VGS +/- 1.5% +0.95VALW Q44 PX@ +0.95VGS AON4304
+/- 3% 0.5A +/- 3% 2A
1
AON6414AL_DFN8-5 36m OHM is requried AON6414AL_DFN8-5 VDS=30V VGS=20V, ID=18A, Q30 D
PCH_PWR_EN 2
1 1
Rds=6mohm @ VGS=10V <44,52> PCH_PWR_EN
G
VGS(th)=2.4V Max
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2 1 1 1 2 1 1 1
10U_0603_6.3V6M
1 5 3 1 5 3 7m OHM is requried ??? S 2N7002KW_SOT323-3
3
1
C153 C155 C151 C152 C161 C163 C160 C162
10U_0805_25V6K 1U_0603_25V6M 10U_0805_25V6K 1U_0603_25V6M
PX@ 2 PX@ 2 PX@ 2 PX@ PX@ 2 PX@ 2 PX@ 2 PX@ R162
4
4
2 2 100K_0402_5%
2
3 3
AON6414AL
VDS=30V VGS=20V, ID=50A, AON6414AL
2 R195 1 VDS=30V VGS=20V, ID=50A, 2 R208 1
Rds=8mohm @ VGS=10V +VSB +VSB
PX@
100K_0402_5% Rds=8mohm @ VGS=10V PX@
100K_0402_5%
VGS(th)=2.5V Max
1
VGS(th)=2.5V Max
1
1
1 R196 D Q35 1 D Q36
C154 120K_0402_5% 2 PXS_PWREN# C159 R207 2 PXS_PWREN#
OK .1U_0402_16V7K PX@ G .1U_0402_16V7K 120K_0402_5% G

PX@
OK PX@ PX@
2
2 S 2N7002KW_SOT323-3 2 S 2N7002KW_SOT323-3
3
3
PX@ PX@
OK
+1.8VGS +0.95VGS +VGA_CORE
1
R171 R165 R166

470_0603_5% 470_0603_5% 470_0603_5%
4 @ @ @ 4
1 2
1 2
1 2
Q31 D Q4 D Q5 D
PXS_PWREN# 2 PXS_PWREN# 2 PXS_PWREN# 2
<23> PXS_PWREN# G G G
@ S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3

3

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DC V TO VS INTERFACE
GPU Power Discharger THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Custom
NM-A281 0.4

A B C D E
5 4 3 2 1
Power Sequence Block need to be update! 2 SPOK
V
PU5
D D
VGA_PWRGD
AC A1
MODE VIN 3 +1.1VVALW
V V
A2 A3 B5
VV
A5 2
V
PU401
V
PU301
BATT B2
B+
+3VALW B7 2 V
BATT 4
MODE PU401 EC_RSMRST# VGA_PWRGD
B1
V
V
EC 5 PBTN_OUT#
VS B4
V
V
B3
PM_SLP_S3# FCH
V PM_SLP_S5# 6
V
51_ON#
A5 B7
11 FCH_PWRGD 12 APU_PWRGD
V V
V
EC_ON
PLT_RST# 13 14 APU_RST#
CPU
V
C C
15
A4 B6 KBRST#
V
V
ON/OFF V V
V
PXS_PWREN
PQ1
SYSON 7 PU7
8a
V
+VSYSMEM
+3VGS
V
QV2
V
SUSP#,SUSP 8
U12
V
+1.5VGS
V
+5VS
U14
V
U13 +1.8VGS
10
+3VS PU6
VGATE
B B
V
PU10 +0.95VGS VGA
+1.5VS PU12
V
PU7 VDDCI
+0.75VS PU11 8b
V
U15 +VGA_CORE VGA_PWRGD
V
+1.1VS PU13
PU8
+1.2VS
VR_ON 9 PU14 V
V
+CPU_CORE
A A
PU14
V
+APU_CORE_NB

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power sequence Block
Rev
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol
Size
Document Number Rev
B
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
NH1 NH3 NH4 NH5

HOLEA HOLEA HOLEA HOLEA
1
D D
pad_c2p3d2p3n pad_o2p3x2p8d2p3x2p8n pad_o2p3x2p8d2p3x2p8n pad_c2p3d2p3n
H1 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
H2
HOLEA
1
1
1
pad_sht7p0x6p65b10p66x9p9d2p8 Pad_ct8p0b9p0d2p8 Pad_ct8p0b9p0d2p8 PAD_SHAPET8P8X8P0B9P0D2P8 PAD_SHAPET8P0X8P75B9P0D2P8 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 pad_ct6p0d4p3 Pad_ct6p0b8p0d4p6
PAD_SHAPET5P0X6P0B7P0D2P3
C C
H13 H14 H15 H16 H17 H20 H22 H23 H24 H21
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
1
CHASSIS1_GND
pad_cb8p0d7p0 pad_ct6p0shapeb8p0x6p75d2p3 PAD_CT6P0shapeb10p04x10p0d2p8 pad_ct6p0b7p0d2p3 pad_shapet6p8x8p0cb8p0d2p5 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3
PAD_CT5P5B8P0D2P5
H19 H18
PCB Fedical Mark PAD HOLEA HOLEA
FD1 FD2 FD3 FD4 FD5 FD6

1
B 1 GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8

B
PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2
1
@ @ @ @ @ @ @ @
1
PAD_SHAPET5P0X6P0-D PAD_SHAPET5P0X6P0-U
1
GP9 GP10
+VGA_CORE +3VS PAD_RT2P21X2P99 PAD_RT2P21X2P99 GP11 GP12
@ @ PAD_RT2P45X2P5 PAD_RT2P45X2P5
For EMC
1
1
@ @
FFC CONN GROUND PAD
1
1
1
1 1
C168 C169
.1U_0402_10V6-K .1U_0402_10V6-K
@ @
2 2
A A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole
Size
Document Number Rev
B
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
+5VLP/ 100mA
B+
Silergy
D SY8208CQNC +5VALW/5A
D
Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
+3VLP/ 100mA
Silergy
SY8206BQNC
Converter +3VALW/4A Silergy
SY8868ABC
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
Converter +1.8VALW/2.3A
FOR APU VDDIO
EC_APU_ALWEN EN PGOOD
Richtek +1.35V/11A
RT8231AGQW
C TI SYSON S5 Switch Mode C
+0.675VS/1.3A
BQ24737RGRR SUSP# S3
FOR DDR
Battery Charger PGOOD ANPEC
APL5930KAI-TRG
Switch Mode LDO +1.5VSP/150mA
FOR APU VDDIO

Intersil SUSP# EN PGOOD
ISL62771HRTZ APU Core/20A/25A

Switch Mode
SMBus
FOR APU/NB Core APU Core NB/13A/17A
EC_VR_ON EN PGOOD VR_APU_PWRGD
PGOOD_NB
Battery Silergy
Li-ion SYX198DQNC
B
Converter +0.95VS/7.68A
B
4S1P/41WH FOR APU VDD
EC_APU_ALWEN EN PGOOD APUALW_PWRGD
Interisl
ISL62771HRTZ
Switch Mode +VGA_CORE/20A
VIDs
PXS_PWREN EN FOR GPU VDDC PGOOD VR_VGA_PWRGD
A A
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram

C
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
VIN RTC_VCC +3VL +VCCRTC
2
PF1 PL101
JDCIN1 7A_24VDC_429007.WRML HCB2012KF-121T50_0805 PD1
1 APDIN 1 2 APDIN1 1 2 RB751V-40_SOD323-2
1 2 - +
470P_0402_50V7K
D 2 D
3 ADAPTER_ID PL102 JRTC1
1000P_0402_50V7K
ADAPTER_ID <44>
1
3
470P_0402_50V7K
4
1000P_0402_50V7K
HCB2012KF-121T50_0805 PR417
4
1
PC426
PC427
5 1 2 2 1 1 2 BAT_D 2 1
5
1
PC428
PC429
ACES_50299-00501-003 1K_0603_5% PD2
2
ME@ @
2
@ @ FDK_ML1220-TT28 RB751V-40_SOD323-2
1 2
PR4448
RTC Battery 0_0402_5%
@
C
+3VALW C
PH1 under CPU botten side :
VIN
1
PR419 CPU thermal protection at 92+-3 degree C

750_0603_1%
Recovery at 56 +-3 degree C
1
2
PR420
1M_0402_5%
+5VLP
2
2
+3VALW +3VL
2
D
PR421 2 ADAPTER_ID_ON#_G PC430
1
@ 0_0402_5% G 0.1U_0402_25V6-K
1
1 PR29 PR422
S PQ28A @ 47K_0402_1% 13.7K_0402_1% PR423
1
2N7002KDWH_SOT363-6 @ @ 40.2K_0402_1%
2
ADAPTER_ID
2
1
D
5 ADAPTER_ID_ON# <44> PU403
1
PR424 G 1 8
1M_0402_5% VCC TMSNS1
0.1U_0402_25V6
S PQ28B @ PR426 2 7 OTP_N_002 2 1

2
GND RHYST1
1
1
PC432
2N7002KDWH_SOT363-6 0_0402_5% PR425

B PD6 2 1 OTP_N_003 3 6 499K_0402_1% B
<44,54> MAINPWON OT1 TMSNS2
AZ5425-01F_DFN1006P2E2 @ PH1
2
4 5 100K_0402_1%_NCP15WF104F03RC
OT2 RHYST2
2
2
G718TM1U_SOT23-8
<44> NTC_V
@
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DCIN / RTC
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
VMB2
VMB2 VMB
PF2 PL403 JBATT2
JBATT1 8A_24V_F1206HI8000V024T HCB2012KF-121T50_0805 1
1 1 2 1 2 1 2
1 2
2
2 BATT+ 3
3 EC_SMCA
3 EC_SMCA PR427 1 2 100_0402_1% EC_SMB_CK1 <44,53> PL404 4 EC_SMDA
D 3 4 EC_SMDA PR428 1 2 100_0402_1% HCB2012KF-121T50_0805 4 5 BATT_TEMP_IN D
4 EC_SMB_DA1 <44,53> 5
2
5 1 2 6
5 6 6 7
6 7
1
7 8
7 8 PC433 PC434 GND1 9
GND1 GND2
1
9 1000P_0402_50V7K 0.01U_0402_25V7K
2
GND2 PR429
1
100K_0402_1% SUYIN_200082GR007G232ZR
SUYIN_200082GR007G232ZR 1 2 ME@ PD7
ME@ +3VALW @ AZC199-02S.R7G_SOT23-3
2
For 15
For 14
2
BATT_TEMP_IN 1 2 PD8
BATT_TEMP <44,53>
1
@ AZ5215-01F_DFN1006P2E2
PR430
10K_0402_5%
C C
PR431
@ 0_0603_5% +5VALW
1 2 +3VALW +3VALW
VMB2
100K_0402_1%
PC435
100K_0402_1%
2
2
3 1 0.01U_0402_25V7K
B+ +VSBP
PR432
PR433
2
0.22U_0603_25V7K
1
1
100K_0402_1%
PR434 PR1
1
1
PR435
PC436
280K_0402_1% 10M_0402_5%
1
PC437 1 2
0.1U_0603_25V7-M BATT_OUT <53>
2
2
PR436
2
8
10K_0402_1%
3
PR437 1 2 3 D
P
VSBP_2 1 2 VSBP_3 PQ2 +_1 1 DC_UVP_2 5
2 O1 G
-_1
G
22K_0402_1% TP0610K-T1-E3_SOT23-3 @ PU404A
0.1U_0402_25V6
1
AS393MTR-G1_SO8 PQ3B S
4
1
PC438
PR438 2N7002KDWH_SOT363-6
49.9K_0402_1%
PR439
2
1
@ 0_0402_5% PQ4 D
2
B B
1 2 VSBP_1 2 1 2
<44,54,56> ALW_PWRGD G PR440 +3VL
100K_0402_1%
1
S 2N7002KW_SOT323-3
+3VALW
3
PR441 PC439
2
1 2 1U_0402_6.3V6K PR4449
<44,46> PCH_PWR_EN
2
1K_0402_1% @ 100K_0402_1%
100K_0402_1%
2
PJ409
JUMP_43X39
PR442
1 2
+VSBP +VSB
1
1 2
1
PR443
6
10K_0402_1% D
1 2 2
<44> BATT_LEN# G
PQ3A S
1
2N7002KDWH_SOT363-6
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15 BATTERY CONN/OTP
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
B+
Charge Option() bit[8]=1
VIN P2 P3
PQ6 PQ7
AO4407AL_SO8 SI4483_SO8 PJ2 @ PR53
8 1 1 8 JUMP_43X118 0.01_1206_1% PL905
7 2 2 7 HCB2012KF-121T50_0805
6 3 3 6 1 2 1 4 1 2 PQ8
5 5 1 2 AO4407AL_SO8
2 3 1 8
2
D D
2 7
4
PC22 PC21 PC45 3 6
2200P_0402_50V7K
2200P_0402_50V7K 10U_0805_25V6K 737_ACP 737_ACN 10U_0805_25V6K PC44 5
0.1U_0402_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
PQ9 1 2 @ @ 10U_0805_25V6K 2
1
2
PC20
PC25
PC26
PC27
PC28
PC23 @
4
1
PR54 LTA044EUBFS8TL_UMT3F-3 2 10U_0805_25V6K DISCHG_G
3
200K_0402_5% PR55 @
1
200K_0402_1% 1 PR56
47K_0402_1%
2
2 1 1 2 VIN
2
1P2_G2
Reserve for EMC request
2ACOFF-1
PC24
2
0.1U_0402_25V6-K
PR57
DISCHG_G-1
10K_0402_1%
2
P2-1
1
2 PD3 PR58
1
PQ10 1SS355_SOD323-2 200K_0402_1%
LTC015EUBFS8TL_UMT3F-3 PR59 PC29 PC30
1
P2_G1
20K_0402_1% 0.1U_0402_25V6-K 0.1U_0402_25V6-K

1 2 1 2
P2
3
3
PQ26B D
2
2N7002KDWH_SOT363-6 5 PACIN_N 1 2 PACIN_P
PR61 G
3
6
D D 10_1206_5% PC32 PD4
BQ24737_VDD
1
5 PR60 2 BATT_OUT <52> 2 1 0.1U_0402_25V6-K S 1SS355_SOD323-2
4
G 68K_0402_1% G PR62
PQ30B PC31 1 2 PC34 1M_0402_5%
6
S 2N7002KDWH_SOT363-6 S PQ30A 1U_0603_25V6M 1U_0603_25V6M 2 D
4
1
2N7002KDWH_SOT363-6 2 1 737_VCC 1 2 PC33 2 PACIN
2
0.1U_0402_25V6-K G
VIN
1
P2-2
PD5 S PQ26A
1
RB751V-40_SOD323-2 2N7002KDWH_SOT363-6
1
PR63 2 1
3
5
6
7
8
47K_0402_1% D PQ29B PR64 PQ11
20
14
2
3
C PACIN 1 2 5 2N7002KDWH_SOT363-6 390K_0603_1% C
G AO4466L_SO8
ACP
CMPOUT
VCC
ACN
GND
PACIN_G
PR65 PR66 PC36
2
S 59K_0402_1% 2.2_0603_5% 0.047U_0603_25V7-K
4
1 2 737_ACDET 6 17 BST_CHG 1 2 2 1 4
PC35 ACDET BTST
0.1U_0402_25V6-K
1 2 ACPRN 5 16
ACOK REGN
3
2
1
PR68 PR67 0_0402_5% @ PU4
6
10K_0402_5% D <44,52> EC_SMB_CK1 1 2 737_SCL 9 18 DH_CHG PR70

1 2 ACOFF-1 2 SCL HIDRV PL3 0.01_1206_1%
<44> ACOFF G PR69 0_0402_5% @ BQ24737RGRR_VQFN20_3P5X3P5 4.7UH_PCMB063T-4R7MS_5.5A_20% BATT+
<44,52> EC_SMB_DA1 1 2 737_SDA 8 19 LX_CHG 1 2 CHG 1 4
S SDA PHASE
1
2 3
5
6
7
8
PQ29A ADP_I 7 15 DL_CHG
IOUT LODRV
1
2N7002KDWH_SOT363-6 <44> ADP_I PQ12
CMPIN
PR71
SRN
SRP
BM#
ILIM
2
PC37 21 AO4466L_SO8 2.2_0805_5%
10U_0805_25V6K
10U_0805_25V6K
100P_0402_50V8J PAD
1
4
1
11
10
SRN_1 12
SRP_1 13
2
3
PC38
PC39
D
BATT_OUT 5
2
1
BM#
G PC40
PQ27B PR74 1500P_0402_50V7K
3
2
1
S 2N7002KDWH_SOT363-6 40.2K_0402_1%
4
2
1
@ PR72 737_ILIM 1 2
1
0_0402_5%
1 2 PR77
<44,52> BATT_TEMP
1 2 737_ILIM 10_0603_5%
2
2
PR78 PR76
2
90.9K_0402_1% 6.8_0603_5% PC41
0.1U_0402_25V6-K
2
PC42 1
PR75 0.1U_0402_25V6-K
316K_0402_1% 1 2 737_SRP
B B
+3VL
1
2 737_SRN
+3VALW
1
PC43
PR4447 0.1U_0402_25V6-K
10K_0402_5% 1
2
ACIN# <44>
BQ24737_VDD
PR4446
1
D
1 2 2 PQ906
1
G 2N7002KW_SOT323-3
PR83 10K_0402_1%
1
10K_0402_1% S
3
PR84
47K_0402_1%
2
PACIN
2
PR88
6
D 12K_0402_1%
ACPRN 2
G
2
PQ27A S
1
2N7002KDWH_SOT363-6
A A
Modified for B+ voltage step

PR334
0_0402_5%
ACPRN 1 2 ACIN#
@
Issued Date 2013/08/15 Deciphered Date 2013/08/15 CHARGER

C
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
B+ @ +3VALW
PJ401
1 2
1 2
PU401 TDC :4A
1
JUMP_43X79
10U_0805_25V6K
10U_0805_25V6K
OCP :8A
1
PC401
PC421
PC402 7 2 +3V_PWRGD
0.1U_0402_25V6 PR411 EN2 PG PR444 PC403
2
1M_0402_5% 2.2_0603_5% 0.1U_0603_25V7-M
D
+3VALW D
2
@ 8 6 +3VBS 1 2 1 2
IN BS PL401 @
2.2UH_PCMB063T-2R2MS_8A_20% PJ402
9 10 +3VLX 1 2 +3VALW_P 1 2
PR403 GND LX 1 2
2.2K_0402_5% JUMP_43X79
2200P_0402_25V7-K
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_25V6
2
1
PC440
PC441
EC_ON 1 2 +3VALW_EN 1 4 +3VALW_P @ PR404
EN1 OUT
+3VLP
PC404
PC405
PC406
PC407
4.7_0603_5%
2
1
+3VALW_FB 3 5
FB LDO
1
PD15 PR405
1 1
MAINPWON 1 2 PC408 1M_0402_5%
+3VLP +3VL
1
@ 0.1U_0402_25V6 PC409 PC410
2
RB751V-40_SOD323-2 SY8206BQNC_QFN10_3X3 4.7U_0603_6.3V6K 680P_0402_50V7K
2
@ @ PJ403 @
2
JUMP_43X39
1 2
1 2
1 2 1 2
PC411 PR407
0.01U_0402_25V7K 1K_0402_1%
C C
B+ @
PJ405 +5VALW
1 2
1 2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
TDC :5A
PC412
PC413
JUMP_43X79
PU402
PC414
OCP :11A
2
+5V_VIN 8 2 +5V_PWRGD
IN PG PR4445 PC415
9 6 +5VBS
2.2_0603_5% 0.1U_0603_25V7-M
1 2 1 2
+5VALW
GND BS PL402
PC416 3.3UH_PCMB063T-3R3MS_6.5A_20% PJ406
1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
PR412 VCC LX 2 1
2.2K_0402_5% 1U_0603_25V6M @ JUMP_43X118
2200P_0402_25V7-K
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_25V6
2
1
PC442
PC443
EC_ON 1 2 +5VALW_EN 1 4 +5VALW_P @ PR406
<44> EC_ON EN OUT
+5VLP
PC417
PC418
PC419
PC420
4.7_0603_5%
2
1
+5VFB 3 7
PC422 PR413 FB LDO
1 1
PD16 0.1U_0402_25V6 1M_0402_5%
4.7U_0603_6.3V6K
2
1
MAINPWON 1 2 @ PC424
<44,51> MAINPWON 680P_0402_50V7K
PC423
SY8208CQNC_QFN10_3X3
2
RB751V-40_SOD323-2 @
2
@
B B
1 2 1 2
PC425 PR416
6800P_0402_25V7-K 1K_0402_1%
+3VALW
2
PR408
100K_0402_5%
PR409 0_0402_5%
1
+3V_PWRGD 1 2
ALW_PWRGD <44,52,56>
@
PR410 0_0402_5%
+5V_PWRGD 1 2
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_3VALW/5VALW
Custom
NM-A281 0.4

5 4 3 2 1
A B C D
+1.35VP
10U_0603_6.3V6M
PJ501
B+
PC501
2 1 B+_1.35V
2200P_0402_25V7-K
2 1
+0.675VSP
0.1U_0402_25V6
@ JUMP_43X79
2
10U_0805_25V6-K
10U_0805_25V6-K
TDC :1.3A
1
PC503
PC504
PC505
PC513
1 1
PR511
@ 100K_0402_1%
2
2 1 PR506
+3VALW
1
PR512 237K_0402_1%
100K_0402_1%
1 2 +0.675VSP
+0.675VSP
+1.35VP
10U_0603_6.3V6M
0.1U_0402_10V6-K
2
2
PC507
PC508
5
14
11
13
19
20
1
PGND
VID
CS
VLDOIN
VTT
PR507 21
+1.35V PQ501 PC506 2.2_0603_5% PAD
AON6414AL_DFN 4 1 2 1 2 18 1
BOOT VTTGND
TDC :11A 0.22U_0603_25V7K
DH_1.35V 17 2 +0.675VSP
OCP :14A UGATE VTTSNS
1
2
3
PL501 PU501
0.68UH_PCMB063T-R68MS_16A_+-20% 3
1 2 LX_1.35V 16 RT8231AGQW
GND VTTREF_0.675V
+1.35VP PHASE
4 VTTREF_0.675V
VTTREF
2
2200P_0402_25V7-K
PQ502 PR510
5
0.1U_0402_25V6
1 PR508 AON6414AL_DFN DL_1.35V 15 5.1_0603_5%

LGATE
1
470P_0402_50V7K
330U_2.5V_M
@ 4.7_0603_5% 12 2 1
VDD +5VALW
1
1
PC514
PC515
PC509
PGOOD
1
PC516
5 1 PC511
TON
1
2 VDDQ 0.033U_0402_16V7K 2
FB
S5
S3
2
2
2 PR994 4 PC510
2
2 7.68K_0402_1% 1U_0402_10VA-K
10
1
2
PC512
2 TON_1.35V
@ @ 680P_0402_50V7K
S5_1.35V
S3_1.35V
2
1
2
3
PR503
1
100K_0402_1%
PR995 1 2
10K_0402_1% +3VALW
887K_0402_1%
2
PR504
VDDQ_PGOOD <44>
FB_1.35V
1
B+_1.35V
PJ502
2 1
2 1
@ JUMP_43X118
PR501 0_0402_5%
<44,46,56,58> SUSP# 1 2
2
PJ504
1
@
+1.35VP 2 1 +1.35V
@ JUMP_43X118
3 3
1 2 S3_1.35V
PJ503
PR513 2 1
@ 0_0402_5% +0.675VSP 2 1 +0.675VS
2
PC502 @ JUMP_43X39
0.1U_0402_10V6-K
1
PR505 0_0402_5%
1 2 S5_1.35V
<44> SYSON
2
@
PC517
0.1U_0402_10V6-K
4 4
Issued Date 2013/08/15 Deciphered Date 2013/08/15 1.35VS/+0.675VS

Rev
Custom
NM-A281 0.4

A B C D
A B C D
+3VALW
2
PR601
10K_0402_5% +1.8VALW
PJ601
1_8VS_PG
2 1 1_8VS_PVIN
+3VALW
1
2 1
TDC :2.3A
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_10V6-K
JUMP_43X79
1
@ OCP :3.8A
PC630
PC601
PC602
PL601
9
PU601 1UH_PH041H-1R0MS_3.8A_20% PJ602
1 2 1_8VS_LX 1 2 +1.8VSP 2 1
+1.8VALW
PG
VIN LX1 2 1
5 JUMP_43X79
LX2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_25V6
1 1
1
PR623 6 PR602
LX3
PC631
PC628
PC604
PC629
0_0402_5% 4.7_0603_5%
ALW_PWRGD 1 2 EN_1.8VSP 4 10 @
2
@ EN OUT
1 2
2
PR605 8 7
GND
SS FB
1
PR604 0_0402_5% 1M_0402_5% PC607 PC606
EC_APU_ALWEN 1 2 .1U_0402_10V6-K 680P_0402_50V7K
2
1
@ @
3
SY8868QMC_QFN10_2X2
@ PC663
2
.1U_0402_10V6-K
PR625
200K_0402_1%
1_8VS_FB 1 2
1
PR655
100K_0402_1%
2 1
2
PC603
22P_0402_50V8-J
+5VALW
+1.5VS
TDC :150mA
1
2 2
PC608
1U_0402_6.3V6K PU602
2
APL5930KAI-TRG_SO8
PJ603 @
6
VCNTL VOUT1
3 +1.5VSP 2
2 1
1
+1.5VS
PJ606 @ 5 4
2 1 5332_VIN 9 VIN VOUT2
+3VALW 2 1 TP JUMP_43X39
1
1
1
JUMP_43X79 8
PC609 7 EN 2 PR608 PC610
GND
4.7U_0603_6.3V6K POK FB 21.5K_0402_1% 10U_0603_6.3V6M

2
2
1
2
PR611 5332_FB
1
PR609 0_0402_5% 100K_0402_5%
1
1 2EN_1_5VSP @
<44,46,55,58> SUSP#
PR610
2
24K_0402_1%
@
2
+3VS
2
PC611
0.1U_0402_10V6-K
1
PR622
0_0402_5%
<44,52,54> ALW_PWRGD ALW_PWRGD 1 2
@
PR612 0_0402_5%
<44> EC_APU_ALWEN EC_APU_ALWEN 1 2 0.95VS_EN
1
3
@ PC612 3
.1U_0402_10V6-K
2
@
+0.95VALW
PU603
B+ SYX198DQNC TDC :7.68A
PJ604
2
2 1
1 B+_0.95VS 8
IN EN
1 PR624 PC613 OCP :12A
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0_0603_5% 0.1U_0603_25V7-M
1
JUMP_43X79 6 0.95VS_BS1 2 1 2 PL602

BS
1
PC616
PC614
PC615
@ 0.68UH_PCMB063T-R68MS_16A_+-20%
9 10 0.95VS_LX 1 2
+0.95VALWP
2
GND LX
2
4
FB
1
2200P_0402_25V7-K
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
3
ILMT
PC623
0.1U_0402_25V6
7 PR615
BYP
+3VALW
PC617
PC618
PC620
PC621
1 20.95VS_ILNT 4.7_0603_5%
+3VALW
PC622
@
2
1
PR614 2
1 2
@ 100K_0402_5% PR616 PG 5 0.95VS_LDO PC627

LDO
1
1M_0402_5% PC625 330P_0402_50V8J

+0.95VALWP +0.95VALW
2
1
1
@ 4.7U_0603_6.3V6K PC626
680P_0402_50V7K PR618
2
PC624 @ 20K_0402_1%
2
4.7U_0603_6.3V6K
PJ605
2
PR617 2 1
<44> APUALW_PWRGD 2 1
1K_0402_1%
JUMP_43X118
2
PR620 @
10K_0402_5%
0.95VS_FB
1
+3VALW PR621
34K_0402_1%
2
4 4
Issued Date 2013/08/15 Deciphered Date 2013/08/15 +1.35VS_VGA/+1.5VS

Custom
NM-A281 0.4

A B C D
5 4 3 2 1
D D
C C
B B
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
+VGA_B+
PX@ PL804
HCB2012KF-121T50_0805
1 2
B+
PX@ PL805
D D
HCB2012KF-121T50_0805
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1 2
1
PC801
PC802
PC803
5
2
AON6414AL_DFN
+VGA_CORE
PQ801
PX@
PR801 PX@
PR802 PX@
10K_0402_5%
1
1
TDC :20A
10K_0402_5%
10K_0402_5%
@ VGA_UGATE1 4
1
0_0402_5%
PX@ PX@ PX@
OCP :35A
PR847
PR848
PR849
0_0402_5% PL801
3
2
1
@ PX@ 0.36UH_PCMB063T-R36MS_20A_20%
2
2 1 VGA_PHASE1 1 2
PX@ +VGA_CORE
PR803 PX@
5
2.2_0603_5%
330U_D2_2V_Y
330U_D2_2V_Y
40
39
38
37
36
35
34
33
32
31
1 1
1
PU801 VGA_BOOT1 1 2 BOOT1_R
1 2
PC805
PC806
PR809 + +
AON6554_DFN
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
PC804 PX@ 4.7_0603_5%
PX@
PQ802
0.22U_0603_25V7K @
2
PR805 PX@ 100K_0402_1% VGA_LGATE1 4 2 2
2
1 2 1 30 VGA_BOOT2 PR810 PX@
PR807 PX@ 100K_0402_1% NTC_NB BOOT2 PR806 PX@ PX@
10_0402_1%
1 2 2 29 VGA_UGATE2 10K_0402_1% PR804 PX@
IMON_NB UGATE2
1
PC807 PX@ 3.65K_0402_1%
3
2
1
VSUM- 1
3 28 VGA_PHASE2 680P_0402_50V7K
<20> GPU_SVC
VSUM+ 1
SVC PHASE2 @
2
1
PR811 20_0402_5% VGA_VRHOT_L 4 27 VGA_LGATE2
ISEN1
<20> GPU_VR_HOT# VR_HOT_L LGATE2
@ PR814 0_0402_5%
2
5 26 VGA_VDDP 1 2
PR812
<20> GPU_SVD SVD VDDP PR816 +5VS
10K_0402_1% 6 25 VGA_VDD 1 2 @ +VGA_B+
PR818 PX@ +VDDIO_GPU VDDIO ISL62771HRTZ_TQFN40_5X5 VDD 1_0603_5%
C 20K_0402_1% 7 24 VGA_LGATE1 PX@ C
1
SVT LGATE1
1
PX@
<23,6> PXS_PWREN
2 1 +3VGS VGA_ENABLE 8 23 VGA_PHASE1 PC808 PC809
PR819 0_0402_5% ENABLE PHASE1 1U_0603_25V6M 1U_0603_25V6M
2
1 2 9 22 VGA_UGATE1 PX@ PX@
<19,44,6> VGA_PWROK PWROK UGATE1
2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2 1 10 21 VGA_BOOT1
<44,46,55,56> SUSP# IMON BOOT1
@
1
1
PC811
PC810
PC812
PGOOD
PR820 PC831
ISUMN
ISUMP
2
COMP
ISEN2
ISEN1
VSEN
0_0402_5% .1U_0402_10V6-K
NTC
RTN
@ PX@ PR822 PR824
AON6414AL_DFN
FB
TP
2
1.91K_0402_1% 100K_0402_1%
PQ803
PX@ PX@
11
12
13
14
15
16
17
18
19
20
41
PX@
2 1 VGA_UGATE2 4 PX@ PX@ PX@
+3VGS
1
+3VGS
VGA_ISUMN
VR_VGA_PWRGD <19,6>
VGA_COMP
PR821 PX@
3
2
1
27.4K_0402_1% PL802
VGA_FB
1 2 VGA_NTC 0.36UH_PCMB063T-R36MS_20A_20%
VGA_PHASE2 1 2
PX@
2
5
VGA_NTC_1 1 2 PR823 PR826 PX@
0.1U_0402_25V6
PH801 130K_0402_1% PC813 PX@ VGA_BOOT2 1 2BOOT2_R
1 2
330U_D2_2V_Y
1
470K_0402_3%_NCP15WM474E03RC PX@ 0.1U_0402_25V6-K PR827
2
1
1
PC815
PC816
PX@ 2.2_0603_5% PC814 PX@ 4.7_0603_5% +
AON6554_DFN
1
2
PR825 0.22U_0603_25V7K @
PX@
PQ804
10.7K_0402_1% VGA_NTC VGA_LGATE2 4 PR828
2
PX@ 2
10_0402_1%
+5VS PR829 @
2
2
10K_0402_5% PX@ PX@ PX@
1
1
2 1 PC817 PR830 PX@ PR831 PX@
3
2
1
680P_0402_50V7K 10K_0402_1% 3.65K_0402_1%
VSUM-
@
1
ISEN2
ISEN2
VSUM+
B B
ISEN1
1
PC820 PX@
PR834 2 1 PC818 PC819 0.1U_0402_25V6 PC821 PX@ PR836 PX@ PC822 PX@ PR837 @
10K_0402_5% 0.22U_0402_10V6K 0.22U_0402_10V6K 1 2 PR835 PX@ 100P_0402_50V8J 499_0402_1% 100P_0402_50V8J 32.4K_0402_1%
2
@ PX@ PX@ 1.02K_0402_1% 1 2 VGA_FB_2 1 2 1 2 1 2

330P_0402_50V8J
VSUM- 1 2
PC823 PX@
1
PR841 PX@ PR842 PX@ PC825

PR838 PR840 619_0402_1% 30K_0402_1% 150P_0402_50V8-JPX@
2.61K_0402_1% 10K_0402_5% 1 2 1 2VGA_FB_1 1 2
2
1
PX@ 2 @ 1 1 2
0.033U_0402_16V7K
PR843
2 2
0.033U_0402_16V7K
11K_0402_1% PC824 PR844 PX@ PC827 PX@

PX@ 0.22U_0402_10V6K 2K_0402_1% 680P_0402_50V7K
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PH802 @ 2 1VGA_FB_3 1 2
2
PC826
10K_0402_NTC
PC828
PX@ PX@
2
1
PC1183
PC1182
PC1184
PC1185
1
PX@
2
VSUM+ PR293
10_0402_1%
2 1 @ @ PX@ PX@
PX@ +VGA_CORE
1
PC1255 PR294
330P_0402_50V8J 10_0402_1%
2
PX@ 2 1
PX@
1
PC830
1000P_0402_50V7K
PX@
2
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15 +VGA_CORE
Custom
NM-A281 0.4

5 4 3 2 1
5 4 3 2 1
2 1FB_NB_3 2 1
CPU_B+ PL806
PC901 PR901 HCB2012KF-121T50_0805
680P_0402_50V7K 2K_0402_1% PC902 1 2
PR905 150P_0402_50V8-J B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.01U_0402_25V7K
100_0402_1% 1 2 1 2FB_NB_2
1 2 1 2 1 1 PL807
68U_25V_M
68U_25V_M
<5> APU_VDDNB_SEN_H 1 2 PR902 PR903 HCB2012KF-121T50_0805
2
PC903
PC904
PC906
+
PC910
1.58K_0402_1% 82K_0402_1% PR904 @ PQ901 + 1 2
PC909
PC905
32.4K_0402_1% AON6414AL_DFN
+APU_CORE_NB
1
2 1 1 2FB_NB_1
1 2 1 2 PC908 UGATE_NB 4 2 2
D +APU_CORE_NB PR906 PR907 47P_0402_50V8J D
0_0402_5% PC907 499_0402_1%
@ PC911 100P_0402_50V8J TDC :13A
330P_0402_50V8J
OCP :22A
3
2
1
1 2 PL904
0.36UH 20% PCMB063T-R36MS 20A
PHASE_NB 1 4
+APU_CORE_NB
VSUMP_NB PR909 2 3
1
2.2_0603_5% PQ902 PR911
2
BOOT_NB 1 2 BOOT_NB_R1 2 AON6554_DFN PR910 3.65K_0402_1%
COMP_NB
VSEN_NB
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PR908 PC914 4.7_0603_5%
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1
FB_NB
1 2
2NB_NTCS
2.61K_0402_1% 0.01U_0402_25V7K PC913 @ VSUMP_NB
1
1
1
+
PC1015
+
PC1016
+
PC1017
PC915 0.22U_0603_25V7K
PC1011
PC1012
PC1013
0.1U_0402_25V6 LGATE_NB 4
@
2
1
PR912 PGOOD_NB PC916 VSUMN_NB 1 2 2 2 2
PH901 11K_0402_1% 680P_0402_50V7K
2
10K_0402_NTC LGATE_NB @ PR914 @
3
2
1
2
PR915 10_0402_1%
422_0402_1% PHASE_NB
VSUMN_NB 1 1 2VSUMN_NB_11
UGATE_NB
1 2NB_R_B
2 1
2
BOOT_NB
PC918 PC917 @ PR916 @
0.1U_0402_25V6 0.22U_0402_10V6K 10K_0402_5%
1
PR917
40
39
38
37
36
35
34
33
32
31
27.4K_0402_1% PU901
1 2
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
PR918 PH902
10.7K_0402_1% 470K_0402_3%_NCP15WM474E03RC
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 2 62771NTC_NB_R 1 2 62771NTC_NB 1 30
NTC_NB BOOT2
1
IMON_NB 2 29
IMON_NB UGATE2
PC1014
PC1018
PC1019
PC1020
PC1021
PC1025
PC1026
PR919 0_0402_5% PR920 0_0402_5%
1 2 62771_SVC_A 3 28 1 2
<5> APU_SVC
2
C PR921 0_0402_5%
@ SVC PHASE2 +5VALW C
1000P_0402_50V7K
1 262771_VRHOT_A 4 27 @
<44> VR_HOT# VR_HOT_L LGATE2
133K_0402_1%
PR922
@ 0_0402_5%
1
PC919
1 262771_SVD_A 5 26 APU_VDDP 2 1
<5> APU_SVD SVD VDDP +5VS
2
PR924
PR926 0_0402_5%
@ PR923 @
1 262771_VDDIO_A 6 25 APU_VDD 1 2 0_0402_5%
+1.8VS PR928
@ 0_0402_5% VDDIO ISL62771HRTZ_TQFN40_5X5 VDD PR927
1
1 2 62771_SVT_A 7 24 LGATE1_APU 1_0603_5%

<5> APU_SVT
2
SVT LGATE1
2
PR929 0_0402_5%
@
1 2 62771_EN_A 8 23 PHASE1_APU
<44> EC_VR_ON ENABLE PHASE1
1U_0603_25V6M
1U_0603_25V6M
PR930
@ 0_0402_5%
CPU_B+
1
PC920
PC921
1 262771_PWROK_A 9 22 UGATE1_APU
<5> APU_PWROK PWROK UGATE1
@
PR961 2 1 62771A_IMON 10 21 BOOT1_APU
0_0402_5% PR932 IMON BOOT1
2200P_0402_50V7K
0.01U_0402_25V7K
PGOOD
2 1 62771A_IMON 133K_0402_1%
ISUMN
ISUMP
<44> VR_IMVP_IMON
COMP
ISEN2
ISEN1
VSEN
10U_0805_25V6K
10U_0805_25V6K
NTC
RTN
2
PC923
PC924
1 2
FB
TP
PC922
PC925
5
PC926
11
12
13
14
15
16
17
18
19
20
41
1
0.1U_0402_25V6
PR991 +3VS PQ903
+APU_CORE
62771_VSEN_APU
27.4K_0402_1% AON6414AL_DFN
62771_FB_APU
62771_ISUMN_APU
62771_RTN_APU
1 2 62771NTC_APU
2
UGATE1_APU 4
1
APU_NTC_1 2
PR931 TDC :20A
1.91K_0402_1%
PL903 OCP :30A
PH903 PR956 0_0402_5% 0.36UH_PCMC104T-R36MN1R105_30A_20%
+5VS
3
2
1
2
470K_0402_3%_NCP15WM474E03RC PGOOD_APU 1 2
VR_APU_PWRGD <44>
PR933 @ PHASE1_APU 1 4
10.7K_0402_1% +APU_CORE
1
1
PR957 0_0402_5% PR934 2 3
5
PR940 PGOOD_NB 1 2 2.2_0603_5% PR935
1
0_0402_5% @ 1
BOOT1_APU 2BOOT1_R_A
1 2 4.7_0603_5%
@
PC927
2
2
0.22U_0603_25V7K VSUM+_APU 1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
LGATE1_APU 4 4
LGATE1_APU PR936
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1
ISEN2_APU 3.65K_0402_1%
1
B + B
PC1004
+
PC1005
+
PC1006
PQ904 PQ905 PC935
PC1001
PC1002
PC1003
AON6554_DFN AON6554_DFN 680P_0402_50V7K
ISEN1_APU @ VSUM-_APU 1 2
3
2
1
3
2
1
2
2 2 2
1
PR939
PR941 10_0402_1%
PRE-PWROK METAL VID CODES 10K_0402_5%
PC929
0.1U_0402_25V6
2
SVC SVD Boot Voltage 1 2

330P_0402_50V8J
PR943
499_0402_1% 1 2 APU_FB_2 1 2 1 2 1 2
0 0 1.1V VSUM-_APU 1 2 PC930 PR942 PC931
1
100P_0402_50V8J 499_0402_1% 47P_0402_50V8J PR944 @

0 1 1.0V
1
PC933
PR945 32.4K_0402_1%
2.61K_0402_1% 2 1APU_R_B
1 2
1 0 0.9V @ 1 2 1 2APU_FB_1
1 2
+1.35V
2
1
PR950 PR947 @ PC932 PR948 PR949 PC934

1 1 0.8V(Default)
2APU_NTCS
2
0.1U_0402_25V6
11K_0402_1% 10K_0402_5% 0.22U_0402_10V6K @ 2.37K_0402_1% 267K_0402_1% 150P_0402_50V8-J

0.047U_0402_25V7K
1
PC938
2 1APU_FB_3 1 2
2
PR951
2
1
PH904 2K_0402_1% PC936 PR267 PR268 PR269
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10K_0402_NTC PR952 680P_0402_50V7K @ 1K_0402_1% @ 1K_0402_1%
1K_0402_1%
PC937
10_0402_1%
1
2 1 +APU_CORE
1
PC1007
PC1008
PC1009
PC1010
PC1022
PC1023
PC1024
PC1027
VSUM+_APU
2
PR953 2 1 APU_VDD_SEN_H <5>
0_0402_5%
1
PC940 62771_SVC_A
330P_0402_50V8J PR954 @
@ 0_0402_5% 62771_SVD_A
2
2 1
APU_VDD_SEN_L <5> 62771_SVT_A
1
PC939 PR955 2 1
0.1U_0402_25V6 10_0402_1%
1
A A
2
PR271 PR272 PR273

220_0402_5% @ 220_0402_5%
@ @
220_0402_5%
2
2
Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_CPU Core

Rev
Custom
NM-A281 0.4
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Issued Date 2013/08/15 Deciphered Date 2013/08/15
PROCESSOR DECOUPLING
B
NM-A281 0.4

5 4 3 2 1
www.s-manuals.com

Lenovo G50-45 NM-A281P ACLU5-ACLU6

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Lenovo G50-45 NM-A281P ACLU5-ACLU6

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A B C D E

AMD FT3B Beema SOC with DDRIIIL

Security Classification LC Future Center Secret Data Title

Date: Thursday, February 20, 2014 Sheet 1 of 60

Int. MIC Conn.

Page 33 USB2.0 1x USB Right

SATA HDD SATA Gen3 USB2.0 1x

Codec SPK Conn.

HP&Mic Combo Conn. USB Board NS-A275

Security Classification LC Future Center Secret Data Title

Date: Thursday, February 20, 2014 Sheet 2 of 60

VL +3VALW S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF

6 Blue Tooth 8111GUL LAN Part

Device Address Device Address

Date: Thursday, February 20, 2014 Sheet 3 of 60

Beema (MEM & PCIE I/F)

@ Beema FT3-REV-0P53_BGA769 R103 connection to VDDIO_SUS should

RC5 1 1 1 UC1 UC1 UC1 UC1

RC6 1 2 1K_0402_5% MEM_MA_EVENT#

BEEMA AM6400ITJ44JB 2.4G ZM181103J4470 1.8G ZM151103J4470 1.5G ZM1332M2J2370 1.35G

Security Classification LC Future Center Secret Data Title

Date: Thursday, February 20, 2014 Sheet 4 of 60

NOTE: APU_CRT_HSYNC PU FOR AMD INTERNAL,PD FOR CUSTOMER

OK APU_HDMI_DDC_CLK RC160 1 2 4.7K_0402_5%

2 Lane is OK to support FHD Panel

TC60 @ 1 VDD_095_FB_H AV33 VDD_095_FB_H DP_STEREOSYNC E21 O APU_TEST35_STEREOSYNC RC65 1 @ 2 1K_0402_5%

FT3 REV 0.53

CC5 RC38 3 4 APU_TMS 6 3

UC2 HDT@ 7 8 APU_TDO 1

APU_PWROK 3 4 APU_PWROK_BUF 7 8 CC29

SAMTE_ASP-136446-07-B Zx05 Symbol

Date: Thursday, February 20, 2014 Sheet 5 of 60

Beema (GEVENT/GPIO/SD/AZ) Broad ID OK SMB_CLK_S3 OK

GPIO49/51/71 require external PH or PL, so used for Board ID

1 2 RSMRST#_R GPU_CLKREQ# 10K_0402_5% 2 @ 1 RC174

I PU AN5 LPC_PME_L/GEVENT3_L OK APU_GEVENT22# 10K_0402_5% 1 2 RC216

+3VS 32K_X1 AJ2 X32K_X1

RC223 1 @ 2 10K_0402_5% VR_VGA_PWRGD 32.768KHZ_12.5PF_200458-PG14 @ Beema FT3-REV-0P53_BGA769

RC205 1 UMA@ 2 2K_0402_5% VR_VGA_PWRGD VIL Max is 0.7V

+3VALW_APU Output to GPU Vcore VR SVID EN Pin

APU_GEVENT4# 10K_0402_5% 1 @ 2 RC226 1

Date: Thursday, February 20, 2014 Sheet 6 of 60

Net name changed to same as ACLU1 UC1E

OK RC115 1 2 1K_0402_1% SATA_CALRP AP19 SATA_ZVDD_095 USB_HSD3P AG1 USB20_P2

AC8 GPP_CLK0P USB_HSD8P AB1 USB20_P1

48M_X2 N1 X48M_X2 USB_SS_1RXP W1

OK RC122 1 2 33_0402_5% LPCCLK0 Strap Pin PL AY2 LPCCLK0

FT3 REV 0.53

RC127 1 2 10K_0402_5% SPI_WP#

Security Classification LC Future Center Secret Data Title

Date: Thursday, February 20, 2014 Sheet 7 of 60

Beema (POWER & DECOUPLING)

FT3 REV 0.53

JCOMS1 @ AP2138N-1.5TRG1_SOT23-3 CC114

Security Classification LC Future Center Secret Data Title

Date: Thursday, February 20, 2014 Sheet 8 of 60

Beema (STRAPS & OTHERS)

+3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU

Security Classification LC Future Center Secret Data Title

Date: Thursday, February 20, 2014 Sheet 9 of 60

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Blank

Date: Thursday, February 20, 2014 Sheet 10 of 60

Security Classification LC Future Center Secret Data Title