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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/MDAT.2016.2590982, IEEE Design
Streaming access to ADCs and DACs
for mixed-signal ATPG
Stephen Sunter, J-F Coté,
Mentor Graphics, Ottawa, Canada
Abstract: Analog test buses and serial digital access to ADC
and DAC ports are widely used analog DFT techniques. But
they cannot be described in a standard way to facilitate
automatic test pattern generation, and serial access is typically
too inefficient for periodic sampling. This paper shows that if
a small amount of digital circuitry is added to each ADC/DAC
parallel port, it could be described in IEEE 1687’s instrument
connection language (ICL) to facilitate optimally efficient,
automated streaming access to the parallel ports.
Keywords: mixed-signal DFT, IEEE 1687
PRESENTLY THERE ARE no commercially available
automation tools for general analog design-for-test (DFT) or
automatic test pattern generation (ATPG). It is widely thought
that this is due to the lack of any analog DFT technique that is
as general and widely-used as scan-based DFT is for random
logic.
In fact, analog test buses have been implemented in ICs
for over 30 years [1], and continue to be used in even the latest
production CMOS technologies (e.g., 14 nm at AMD). ICs
often have multiple analog test buses because separate buses
are needed for forcing/driving a voltage (or current) and for
sensing the resulting voltage, and doing this in each voltage
domain of the IC. In the early 1990s, development of the IEEE
1149.4 mixed-signal test bus [2] attempted to standardize
analog test access, but the cost of adding two analog test bus
pins in addition to the IEEE 1149.1 test access port’s four pins
[3] has proven too expensive for most mixed-signal ICs since
they often have fewer than 30 signal pins. Reusing an IC
function’s analog-to-digital converter (ADC) and/or digital-to-
analog converter (DAC) can provide a lower-cost and digital
method to convey analog test bus voltages into and out of pin-
limited designs.
Another DFT technique that is widely used for mixed-
signal functions is serial digital access. Serial shift registers
control CMOS transmission gates connected to analog buses,
and control surrounding digital logic functions, in addition to
providing serial access to the digital ports of ADCs and DACs.
Serial access is often used even for ICs having hundreds of
pins because parallel test access to ADCs and DACs would
require too much chip area, especially if the bus width equals
the number of bits of the highest resolution converter. Serial
access can also be provided via functional interfaces (e.g. I2C)
which are already part of many mixed-signal designs.
When a data register to be accessed captures the output
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and Test
and Jeff Rearick
AMD, Fort Collins, USA
of an N-bit ADC, or updates the input to an N-bit DAC, it is
often necessary to continuously shift the data so that periodic
digital samples of an analog waveform are conveyed. For
instance, when an ADC samples a 1 MHz sine wave, the
signal would usually be sampled at a much higher frequency
than the sine wave’s, for example at 10 MHz. If the ADC has
an 8-bit parallel output, then the 8-bit samples would be
shifted out serially at 80 Mb/s. If the ADC’s register was only
accessible in series with other shift register stages, and all of
the shift register’s bits must be shifted out before capturing a
next sample, then many more clock cycles would be needed to
convey each 8-bit sample, and thus an even higher clock rate
would be needed.
The IEEE 1687 “Standard for Access and Control of
Instrumentation Embedded with a Semiconductor Device” [4]
solves three aspects of this problem. First, it enables serial
shift register reconfiguration so that only the desired register
bits for a given test (e.g., ADC and DAC registers) are
included in the shift register. Second, it allows serial access
through functional interfaces without additional dedicated test
points. Third, it allows ATPG for serial access to registers
within an IC, in a way that allows automated re-targeting of
the patterns when the registers are connected serially in a
different order in a new IC design. However, 1687 was not
developed with periodic sampling in mind.
Parallel/Serial Conversion Schemes
A variety of parallel-to-serial data conversion schemes
has been developed over the years for general access to on-
chip registers, such as the inter-IC bus (I2C) [5], serial
peripheral interface (SPI), and IEEE 1149.1 [3], but these are
not intended for conveying samples of analog signals at a
constant or maximal parallel-sampling rate. For example, I2C
requires 8-bit bytes and an acknowledge bit per byte, and it is
half-duplex; SPI requires a constant length serial register.
1149.1 requires reading/writing an entire test data register
(TDR), which encourages the use of a dedicated TDR for each
ADC and DAC; but if each ADC or DAC is contained in a
different TDR, then interleaving accesses to multiple ADCs
and DACs requires changing the addressed TDR for each
access.
Various serial data communications protocols include
provision for accessing parallel registers. The circuits use
coding, or insert special periodic bit sequences or start bits to
delineate data packet or frame boundaries, which reduces the
number of samples that can be conveyed in a given time
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and Test

interval. In other schemes, data is transferred from multiple

parallel registers only if all the registers have the same number
of parallel bits.
In [6], circuitry is described in which single-bit ADCs
and DACs are connected to a serial shift register in a way that
permits any single ADC or DAC to be accessed serially, based
on the addressing techniques described in IEEE 1687. That
paper provided our motivation to develop a systematic way to
access multiple arbitrarily-sized converters in a single serial
shift register.
The Proposed Circuit
Our primary objective was to define circuitry that could
continuously and simultaneously convey a stream of data
packets to and/or from any number of parallel data registers
connected serially, with any number of intervening or
appended serial shift register stages, in a number of clock
cycles per parallel sample that is simply equal to the sum of
the parallel data registers’ bits.
Briefly stated, the circuit, as shown in Fig. 1,
accomplishes this for conventional serial access by adding a
counter and a packet-size register at each serially connected
N-bit parallel data register. Before serial access begins, the
counter for each DAC register is initialized with an Offset
count equal to the number of shift register clock cycles that
will occur before serial data reaches the DAC register.
Similarly, for ADCs, before serial access begins, the counter Figure 1. Conventional scan access appended with circuitry for
for each ADC data register is initialized with an Offset equal streaming
to the number of clock cycles that must occur before the ADC
output is captured. All Packet-size registers for all data The circuit of Fig. 2 shows details for possible ADC
registers to be accessed simultaneously are initialized with the register circuitry, in a style consistent with IEEE 1687 and
same Packet-size (which sets the periodicity of the update and using its acronyms. The detailed connections for Shift Enable
capture operations). (SE), Test Clock (TCK), and Select (SEL) are specified in
After initialization, clocking continues and each data 1687 so they are omitted here for simplification. Circuitry for
register updates its connected DAC input, or latches its the DAC is similar, so we omit it for brevity.
connected ADC output, when its counter has counted its
Offset number of clock cycles, at which time its counter is re-
initialized with the contents of its Packet-size register (instead
of the Offset) and counting continues; thereafter initialization
occurs every Packet-size number of cycles. This periodic
sequence continues until the needed number of samples has
been conveyed to each DAC and/or from each ADC.
Three-bit converters are shown in the schematic of Fig. 1
for simplicity but they need not be the same size as each other.
The serial shift register shown is constructed of, for example, a
data input pin, any number of prepended shift register stages
(shown as a single bit register in dotted outline), a parallel
input register for the ADC, any number of intervening shift
register stages (dotted outline), a parallel output register for
the DAC, any number of appended shift register stages (dotted
outline), and an output data pin. A signal from the ADC’s
counter controls the multiplexers that select whether the shift
register captures parallel data from the ADC or serial data
originating from the input pin. Similarly, a signal from the
DAC’s counter controls multiplexers that select whether the
DAC receives its 3-bit input from its parallel register or from
digital function circuitry. Figure 2. Simpler ADC access circuitry, consistent with IEEE 1687

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and Test

For these circuits, after the Packet-size and Offset have simply the sum of the bit-widths of the parallel-in-serial-out
been shifted in, an Update occurs that instructs a segment (PISO) registers associated with the respective ADCs. Row 3
insertion bit (SIB) to exclude the Packet-size register and shows that when accessing the DAC, a relatively large offset
counter from the shift register and activate counting (if Packet- is needed, since it is the number of register bits from test data
size > 0). Excluding these ensures they do not respond to in (TDI) to the furthest bit of the DAC serial-in-parallel-out
activity on the Capture Enable (CE), Shift Enable (SE), and (SIPO) register, plus one. The fourth row shows a Packet-size
Update Enable (UE) signals. Initialization of the Packet-size of 14 when the two ADCs and the DAC are accessed, showing
and Offset registers happens once, then they are bypassed by that Packet-size is the sum of ADC and DAC bit-widths when
the SIB and out of the active shift register during the they are all accessed simultaneously.
remainder of the test. The Packet-size register must be large
enough to hold the largest anticipated Packet-size, which we
expect will usually be less than 64, hence 6 bits is sufficient.
The Offset counter must be large enough to hold an
Offset equal to the largest number of clock cycles that could
occur before updates or captures occur. For a DAC, the Offset
is equal to the number of shift register bits preceding the DAC,
plus the DAC’s bits, plus one (since the update pulse occurs
after the bits have arrived in the DAC’s register); a sum which
we expect will usually be less than 1024, hence, 10 bits is
sufficient. For an ADC, the largest Offset would be equal to
the number of scan register bits between the ADC and the
immediately preceding ADC (that would be simultaneously
accessed), or equal to zero if there are none.
Top-level design could ensure that the maximum number
of bits to access any ADC or DAC never exceeds 1024, for
instance, or could adjust the size of parameterized registers
and counters based on the actual size of the ADCs and DACs
included in the design.
The next section discusses an example having multiple
converters and additional shift register bits to illustrate how
packet streaming is programmed and how packets are
assembled on-the-fly as they are shifted by each ADC or DAC
register.
A Realistic Example
The circuit of Fig. 3 shows a simplified schematic in
which three parallel data registers are connected to two ADCs
and one DAC, all of different bit-widths, in a single shift
register.
The shift register includes segments for the Packet-size
and Offset registers that can be selectively bypassed using
SIBs, each of which consists of a single shift-register bit, an
update register bit, and a multiplexer. As shown in the
schematic, the number of bits stored in each Packet-size
register or Offset counter may differ, and the number of
intervening shift-register stages between each parallel register Figure 3. Realistic example circuit with two ADCs and one DAC
may differ.
Table I shows Packet-sizes and Offsets for the circuit TABLE I
that would be initialized for four example configurations of EXAMPLE SETTINGS FOR THE CIRCUIT IN FIG. 3
the streaming shift register. In all these configurations, the
4b 7b 3b
length of the shift register is 24 bits, but the periodic action Row Settings to access … ADC ADC DAC Notes
taken on the bits depends on the values initialized into the 1 4b ADC Packet 4 0 0
Packet-size and Offset registers. Offset 0 - - No offset, since 1st ADC
2 4b and 7b ADCs Packet 11 11 0 11=4+7
The first row of Table I shows a Packet-size of 4 when Offset 0 3 - 3 bits between ADCs
only the 4-bit ADC is accessed via the shift register. The 3 3b DAC Packet 0 0 3
second row shows a Packet-size of 11 when both the 4-bit and Offset - - 24 from TDI to DAC LSB +1
4 Both ADCs and DAC Packet 14 14 14 14=4+7+3
7-bit ADCs are accessed, showing that the Packet-size is Offset 2 5 24 5= 2bits to TDI + 3bits between

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Table II shows bits (as letters, indicating associated for the ADCs. If the order of the parallel registers within the
parallel data register) that would be present in each register bit shift register is changed, or additional shift register bits are
in the circuit of Fig. 3, when the circuit’s Packet-size and inserted before, between, or after the parallel registers, then
Offsets are set according to row 4 of Table I, labeled “Both different initial counts (Offsets) are loaded into the counters.
ADCs and DAC”. All three packet-size registers are set to 14.
The 4-bit ADC’s parallel register is in bit positions 3 to 6, and Using IEEE 1687 Automation
has an initial count (Offset) of 2; the 7-bit ADC’s register is in The circuit connectivity in the preceding figures can be
bit positions 10 to 16, and has an initial count of 5; the 3-bit described in IEEE 1687’s instrument connectivity language
DAC’s register is in bit positions 21 to 23, and has an initial (ICL). As an illustrative example, ICL code for the ADC
count of 24. access circuitry in Fig. 2 is shown next (for a 4-bit ADC):
TABLE II
SHIFT REGISTER CONTENTS FOR THE CIRCUIT IN FIG. 3 Module myADC4 {
AND TABLE I SETTINGS FOR BOTH ADCS AND DAC ScanInPort SI;
ScanOutPort SO {Source DataSample[0];}
ShiftEnPort SE;
UpdateEnPort UE;
SelectPort SEL;
TCKPort TCK;
CaptureEnPort CE;
ScanRegister PacketSize[3:0] {
ScanInSource SI;
}
ScanRegister Offset[3:0] {
ScanInSource PacketSize[0];
}
Instance SIB1 of SIB {
InputPort SI = SI;
InputPort FSO = Offset[0];
}
ScanRegister DataSample[3:0] {
Attribute istream_type = “out”; // “in” for DAC
Attribute istream_packet_size_reg = “PacketSize”;
Attribute istream_packet_offset_reg = “Offset”;
ScanInSource SIB1.SO;
}
}

Generating a test in IEEE 1687’s procedural description

language (PDL) that accesses two of these ADCs and a DAC
simultaneously, for 128 samples, using presently defined PDL
At clock cycle 0, the shift register contents are shown as routines (without streaming) requires code like the following:
blank, meaning they are unknown or don’t care. At the end of
clock cycle 1, the first bit ‘D’ destined for the DAC is in bit for {set i 1} {$i <= 128} {incr i} {
position 1. At the end of clock cycle 2, that bit has moved to iRead myADC4_i1.DataSample
iRead myADC7_i1.DataSample
bit position 2, the second bit ‘D’ for the DAC is in bit position iWrite myDAC3_i1.DataSample $data[$i]
1, and the output of the 4-bit ADC has been captured (since iApply
this clock cycle equals its initial count) in bit positions 3, 4, 5, }
and 6.
At clock cycle 5, all bits of a packet are populated with For the circuit in Fig. 3, the number of clock cycles
valid data bits, 14 in all, comprising the bits previously between parallel samples would equal the total number of bits
captured from the 4-bit ADC, the bits destined for the 3-bit in the shift register, assuming ATPG software would
DAC, and the bits just captured from the 7-bit ADC (since this automatically minimize the access path length by setting the
clock cycle equals the ADC’s Offset). At clock cycle 13, the SIBs to bypass the counters and Packet-size registers. Since
first captured bit arrives at the last stage of the shift register. the length in this case is 24 bits, if a 48 MHz serial clock rate
At clock cycle 16, the second sample of the 4-bit ADC was used, the ADCs and DAC would sample at 2 MHz
output is captured (because 14 cycles have elapsed since the Streaming would increase the parallel sampling rate. To
previous sample at cycle 2). At clock cycle 23, the data arrives achieve this, procedures in PDL would be required for each
into the 3-bit DAC’s register and on cycle 24 the 3-bit DAC is ADC and DAC, using a proposed “iStream” instruction, like
updated with those bits (the DAC’s Offset is set to 24). the following:
In Table II we can see that each ADC and DAC parallel
iProcsForModule myADC4;
data register is accessed every 14 clock cycles, there are no iProc data_from {packet_count} {
start bits or code bits, and data is streamed continuously into iStream DataSample –packets $packet_count
the shift register for the DAC and out from the shift register iApply
}

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and Test
iProcsForModule myADC7;
iProc data_from {packet_count} {
iStream DataSample –packets $packet_count
iApply
}
iProcsForModule myDAC3;
iProc data_to {packet_count data} {
iStream DataSample $data –packets $packet_count
iApply
}
Then, instead of using iRead and iWrite, a test engineer
would use the existing iMerge command (which performs
iCalls in parallel) for simultaneous streaming accesses as
follows:
iMerge –begin
iCall myADC4_i1.data_from 128
iCall myADC7_i1.data_from 128
iCall myDAC3_i1.data_to 128 $data(myDAC3_i1)
iMerge –end
It is important to note that the scan chain would be
shifting continuously (sometimes referred to as overshifting)
during this 128-event test with the scan input data being staged
and scan output data being sampled on every cycle (hence the
term “streaming”).
With streaming, the number of clock cycles between
parallel samples would equal the total number of bits from the
accessed ADCs and DAC, which is 14 in our simple example.
For the same 48 MHz serial shift rate, we get a 70% higher
parallel sampling rate of 3.4286 MHz. Of course, we could set
a slightly larger packet-size, such as 16 bits, so that the
sampling rate is a more convenient value of exactly 3 MHz
(50% higher than our previous value). In a typical IC design,
there may be hundreds of extra bits in the scan path to
converters deeply embedded in the design hierarchy, which
makes streaming much more efficient. Sampling the outputs
from, say, two single-bit sigma-delta modulators (Packet-
size=2) would be extremely inefficient without this streaming.
When software encounters an iMerge that calls PDL
procedures containing iStream (and iApply), the software
would first compute how to access the called module instances
simultaneously, then compute SIB settings, compute the
Offset and Packet size for each DAC’s and ADC’s data
register, fetch the data values to be shifted in and assign them
to appropriate timeslots, and lastly compute timeslots in which
captured data will be shifted out so that it can be latched
serially by ATE for analysis.
Although this technique has been described in the
context of mixed-signal designs with low pin-counts, it can
also provide test time savings for large mostly-digital chips.
For example, high-performance I/O circuitry often includes
DACs used for setting voltage references and impedances.
Recent AMD designs using multi-channel DDR, wide
GDDR5, and multi-lane SerDes interfaces have several
hundred such DACs (often one per I/O pin, plus others for
shared compensation circuitry). The higher bandwidth
provided by the streaming test technique, when appropriately
combined with fast on-chip measurement circuits, can reduce
tests costs associated with sweeping through large numbers of
settings.
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Improvements
The scheme is very general and allows optimization for
many different criteria and diagnostic capabilities.
For the simple case discussed, the Packet-size is equal to
the sum of the ADC and DAC bit-widths that will be accessed
simultaneously, and the ADCs and DACs may be connected in
any sequence in the shift register. For any case in which all the
DACs precede all the ADCs, a smaller Packet-size is possible,
equal to the sum of only the DAC bit-widths, or only the ADC
bit-widths, whichever sum is larger. This is possible because,
after all register bits are delivered to their respective DACs,
the bit positions within each packet of bits being shifted out
can be filled with data from the ADCs.
It is important to test a shift register before using it to
access functions whose output is non-deterministic, like the
output of an ADC, to distinguish between an ADC output bit
that is coincidentally always logic one and a bit that is stuck at
one. Simple circuitry can be added to aid diagnosis. For
example, an extra bit can be programmed per ADC and DAC
(before streaming begins) – when it is logic 1, data delivered
using an iApply could be subsequently read back inverted
using iRead.
While IEEE 1687 allows multiple shift registers, it does
not explicitly allow the shift registers to operate at
independent frequencies – an extension to the standard may be
needed to handle this. This is very important for coherent
sampling of analog signals. In many cases, an ADC and DAC
can both be supplied by data from the same serial shift
register, but when the frequency of the signal of interest is
much higher than the ADC’s sampling rate, undersampling
can be employed. A special case of undersampling, previously
demonstrated for a PLL built-in self-test (BIST) [7], is when
the ADC samples at a frequency slightly offset from being
synchronous to the frequency of the sampled signal – this
facilitates arbitrary time resolution, down to picoseconds.
Future Work
I2C and SPI interfaces can be accommodated by IEEE
1687 ICL using AccessLink descriptions (but they are not yet
standardized), therefore, streaming could eventually be
extended to these interfaces that are so common on mixed-
signal ICs. Describing IEEE 1149.1 and IEEE 1500 interfaces
in IEEE 1687 is already standardized.
We have also developed IEEE 1687 ICL coding that
describes analog test buses and their connections. When
combined with streaming to ADCs and DACs, and iRead and
iWrite for digital registers, this is a very general DFT
infrastructure and description methodology, like scan-based
digital design. Most reported mixed-signal DFT and BIST
schemes can be accommodated to permit general mixed-signal
ATPG, especially when function blocks are reused in new
designs – connections between blocks can be automated and
handcrafted test patterns can be automatically re-targeted
using software originally developed for purely digital designs.
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and Test
Conclusions
This paper showed a new DFT approach that creates a
serial test data bit-stream without any special coding bits, so
that registers can capture/insert arbitrary-sized groups of
contiguous bits to/from the bit-stream at pre-determined
periodic times, at the highest parallel sample-rate possible.
Any number of source registers and destination registers can
be included in a single shift register. The additional circuitry
needed is approximately 16-bits of register/counter per ADC
and DAC.
We showed that, compared to existing 1687-based access
using iRead and iWrite, our iStream approach is 70% faster
for a simple example and much faster for more-complex cases.
In current practice, we expect designers use handcrafted
techniques that maximize access rate, without using 1687, so
our proposal might not offer faster access. But our approach
ensures the fastest serial access possible is achieved
automatically, and it facilitates ATPG for mixed-signal
circuits.
Combining streaming and ICL descriptions of analog test
buses could provide an infrastructure that facilitates efficient,
automated DFT for general analog and mixed-signal ICs. We
are working openly with a half-dozen companies trying to
make this happen [8].
References
[1] P.Fasang, D.Mullins, T.Wong, “Design for Testability for Mixed
Analog/Digital ASICs,” Proc. of the IEEE Custom Integrated Circ.
Conf., May 1988, pp. 16.5.1-5.4
[2] Std. 1149.4-1999, IEEE Standard for a Mixed Signal Test Bus, The
IEEE, Inc., 345 East 47th St., New York, NY
[3] IEEE Std. 1149.1-2013, “IEEE standard test access port and boundary-
scan architecture”, The IEEE, Inc., 345 East 47th St., New York, NY
[4] IEEE 1687 Standard for Access and Control of Instrumentation
Embedded with a Semiconductor Device,” 2014, The IEEE, Inc., 345
East 47th St., New York, NY
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[5] “The I2C-Bus Specification,” version 2.1, Philips Semiconductors,
January 2000
[6] S.Sunter, A.Roy, “A mixed-signal test bus and analog BIST with
‘unlimited’ time and voltage resolution ,” Proc. of European Test Symp.,
May 2011
[7] R. Kinger, S. Narasimhawsamy, S. Sunter, “Experiences with Parametric
BIST for Production Testing PLLs with Picosecond Precision,” Proc. of
Int’l Test Conf. , November 2010
[8] R.Seger (Session Chair), “A Framework for Automation in
Analog/Mixed-signal DfT and Test,” Proc. of European Test Symp.,
May 2015, Sessions 2.2 and 3.2
Stephen Sunter is the engineering director of mixed-
signal DFT at Mentor Graphics. His research interests include
testing, DFT, and BIST for all aspects of ICs beyond logic
ones and zeros. Sunter has a BASc in electrical engineering
from the University of Waterloo, and is a Senior Member of
IEEE.
J.F. Côté is chief architect for Silicon Test Solutions at
Mentor Graphics. His professional interests include design
automation and IC design. He previously worked as an ASIC
system architect and as an IC designer. Côté holds an M.Eng
in electrical engineering from McGill University.
Jeff Rearick is a Senior Fellow at Advanced Micro
Devices. He leads the team responsible for AMD's Design-
For-Testability strategy (which is largely digital but includes
enough pesky analog content to warrant collaboration on next-
generation DFT techniques). Jeff has an MSEE from the
University of Illinois.