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Hardware Specifications of Microprocessor 8086

Intel company released microprocessor 8086 in 1978. It is a 16 bit processor.

It provides 1mb memory space. It supports 20 address lines and 16 data lines.

It works in two modes - minimum or maximum mode. Minimum mode has low performance (single
processor) and maximum mode has high performance (multi- processor). Pin 33 decides whether
the processor is in minimum or maximum mode.

Address and data are multiplexed and sent to processor through pins 16 to 2 and pin 39 (AD0 to
AD15). Address will be available during T1 clock state and data will be available in T2,T3,T4 clock
states.

Pin 38 to 35 (A16 to A19) are used to multiplex address and status signals. T1 contains address and
T2,T3,T4 contain status.

Pin 34 is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device
connected to upper half of the data bus use BHE (Bus High Enable) signal. It is multiplexed with
status signal S7.

Pin 32 is used for read operation and pin 29 is used for write operation.

Pin 28 decides whether the processor is interacting with memory or I/O device.

Pin 27 shows whether the data is being transmitted or received.

If the system bus is having data, pin 26 will be enabled. (DEN means Data Enable)
If the system bus is having addrress, pin 25 will be enabled. (ALE means Address Latch Enable)
Processor gets interrupts. An interrupt is a request from an external device to access the processor.
Processor receives that interrupt and sends an acknowledgement to that external device. Pin 24 is
used to send this acknowledgement.

Processor will be in wait state when pin 23 is enabled.

External device (I/O or Memory) sends Ready signal to Processor thru pin 22, whenever it is ready to
transmit data.

Reset (pin 21) is used to start an activity again from the beginning.

Clock (pin 19) generates timing signals to control the activity of the processor.

Interrupt Request(INTR) (pin 18) is used by an external device to send an interrupt request to the
processor. These are maskable (discardable) interrupts. Processor may attend to them or it may
keep them in queue for latter processing.

Non-Maskable Interrupts are sent to processor via pin 17. Processor must attend to these interrupts.
It cannot discard these interrupts. Emergency interrupts such as power failure, are sent thru pin 17.
External device request system bus thru pin 31 (HOLD)

Processor acknowledges this HOLD request and releases system bus to external device thru pin 32
(HLDA)

S2,S1,S0 (pins 28,27,26) show the status of the processor

QS0,QS1 (pins 25,24) show the status of 6 byte prefetch queue in the Bus Interface Unit of the
processor.

External device requests processor to grant system bus thru RQ/GT1 and RQ/GT0 (pins 30 and 31).
Processor uses the same pins to grant system bus to that external device.

VCC(pin 40) is used to provide power supply to the microprocessor.


Pins 1 and 20 provide ground signals.