Analog Integr Circ Sig Process (2014) 79:73–81
DOI 10.1007/s10470-013-0241-5
A 0.5 V tunable complex filter for Bluetooth and Zigbee using
OTAs
Richa Arya • George Souliotis • Spyros Vlassis •
Costas Psychalinos
Received: 18 June 2013 / Revised: 4 December 2013 / Accepted: 10 December 2013 / Published online: 24 December 2013
Ó Springer Science+Business Media New York 2013
Abstract A 12th-order low voltage tunable differential
complex filter for bluetooth and Zigbee applications is
proposed in this paper. The filter is based on improved
controllable transconductors operating with the ultra-low
supply voltage of 0.5 V. Simulation results using a triple-
well 0.13 lm CMOS technology verify the filter operation
fulfilling all the requirements for the complex filtering
stage in bluetooth or Zigbee receivers. The in-band group
delay variation is 0.79 ls for bluetooth and 0.46 ls for
Zigbee. The image rejection ratio is greater than 71 dB and
the achieved in-band spurious free dynamic range is 42 dB.
Keywords CMOS analog integrated circuits  Ultra-low
voltage filters  Gm-C filters  Complex filters  Bluetooth/
Zigbee filters
1 Introduction
Bluetooth and Zigbee are widely used protocols for short-
range wireless communication between portable devices.
In RF receivers several architectures are used, such as high
intermediate frequency (IF), low-IF or direct conversion [1,
2]. Among them, low-IF architecture seems to be the most
suitable in terms of on-chip integration and performance.
Unfortunately, the high-IF architecture needs an external
filter to satisfy the required high quality factor and the
direct conversion architecture suffers from local oscillator
(LO) leakage and dc offset. Also, the low-IF architecture is
preferable because it needs a relaxed rejection of the image
signal which comes from the down-conversion operation
R. Arya  G. Souliotis (&)  S. Vlassis  C. Psychalinos
Department of Physics, University of Patras, Patras, Greece
e-mail: gsoul@physics.upatras.gr
[2]. The image frequency signal and the IF desired signals
are close to each other and therefore the first must be
removed after the down-conversion and before processing
of the desired signal. Unfortunately, due to their symmetric
response around dc, real filters are unable to remove image
signal. Several techniques, like the Hartley architecture, the
Weaver architecture, passive RC polyphase filters, active
polyphase filters [3, 4], and the complex RD–ADC archi-
tecture [5] are some potential options for on-chip image
rejection, but complex filters seem to be the most prom-
ising solution [6].
Complex filters use the I and Q (quadrature) signals
which are extracted after the down-conversion of the
modulated RF signal, by means of an LO which offers two
phases 0° and 90° of the same frequency xLO [7–9]. The
concept is shown at the block diagram of Fig. 1. The
complex filter rejects the image signal in the frequency of
x = -xIF while applies a selection mask around the fre-
quency x = xIF for the desired signal.
A 12th-order Butterworth complex filter, easily recon-
figurable, for Bluetooth and Zigbee applications is pro-
posed in this paper. The Butterworth approximation is
preferred because it has small group delay variation within
pass-band and all poles have same angular frequency
leading to better matching in cross-coupled OTAs in the
entire filter [6]. The poles of a Butterworth lowpass filter
(LPF) with cut-off frequency xc are evenly spaced around
the circumference of a half-circle of radius xc centered
upon the origin of the s-plane. The proposed filter operates
in ultra-low supply voltage, making it ideal for portable
devices. Low voltage operation is very important in circuits
used in the portable devices [10] helping to reduce their
size, the power consumption and having extended operat-
ing life time without frequent battery recharging. To this
direction, some topologies of complex filters based on
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74
active RC bi-quads [10], current mirrors [11, 12], second
generation current conveyors [13], have been proposed.
Other topologies use quadrature receivers with gm-C filters
[14], gyrator lowpass filters [15], log domain filters [16],
and current feedback operational amplifiers [17].
The proposed filter is based on tunable low-voltage
operational transconductance amplifiers (OTA) [18], it has
no resistors and the center frequency and bandwidth are
orthogonally tunable. Although a gm-C filter based on that
transconductor has been presented in [19], the differential
transconductor used in the proposed realization has been
extensively modified due to the particular requirements for
the complex filter. The most important is that the complex
filters require transconductors with large transconductance
range which must cover all the time-constants variations of
the filter stages. Also, a double-input differential trans-
conductor is required to realize a signal summation. This
filter meets the requirements for a complex filtering stage
in a Bluetooth and Zigbee receiver. The most important
benefit is the operation with the extremely low supply
voltage (VDD) of 0.5 V, although it is designed with a tri-
ple-well 0.13 lm CMOS process that offers relatively high
Fig. 1 Front-end stage block diagram of low-IF receiver using a
complex filter
Fig. 2 Lossy complex
integrator
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Analog Integr Circ Sig Process (2014) 79:73–81
threshold voltage. The paper is organized as follows: in
Section II the concept of the complex filter is presented, in
Section III the employed low voltage OTA is described in
details and in Section IV the analysis of the proposed filter
and the simulated results are given. Also, a performance
comparison with relative published complex filter topolo-
gies is performed.
2 General concept of complex filtering
The block diagram of the front-end of a low IF receiver,
using a complex filtering is shown in Fig. 1. In this
receiver, the RF signal is mixed with the quadrature signal
of LO, in order to produce a complex signal. Complex
bandpass filter acting as a frequency shifted version of a
LPF, passes the desired signal at x = xIF, and attenuates
the image at x = -xIF.
The topologies of complex lossy and lossless integra-
tion/summation blocks based on transconductors are shown
in Figs. 2 and 3, respectively. The differential configura-
tion is preferred for improving the performance in terms of
noise interference rejection.
Considering that xi = (vI1I? - vI1I- ? vI2I? - vI2I–)
? j (vI1Q? - vI1Q–- ? vI2Q? - vI2Q-) and xo = (vOI? -
vOI-) ? j (vOQ? - vOQ-) and after a routine analysis for
the circuit in Fig. 3, it is obtained that,
 
xo xIF
xOI ¼ xII  xO ð1aÞ
s þ xo xo Q
 
xo xIF
xOQ ¼ x IQ þ xO ð1bÞ
s þ xo xo I
where, xo = C/gmo and xIF = xo(gmIF/gmo).
Analog Integr Circ Sig Process (2014) 79:73–81 75

Fig. 3 Lossless complex ITA

integrator

I1 I + In1+
C
I1 I - In1-
O I+
O+
gmo
I2 I + In2+ O-
O I-
C
I2 I - In2-

In+
In-

O+

O-
ITB
ITB gmIF gmIF
ITA

O+
O-

In+

In-
I1 Q + In1+
C
O Q+
I1 Q - In1- O+
gmo
I2 Q + In2+ O-
O Q-
C
I2 Q - In2-

Tuning currents ITA, ITB and ITC in Figs. 2 and 3 are used VDD
to control the transconductance value of each transcon- Vf.p

ductor as given by 2a–2c, vp1

Inv1

gmo ¼ 2ITA = nVt ð2aÞ

Vf.n
gmIF ¼ 2ITB = nVt ð2bÞ io1
VDD von
gmo0 ¼ 2ITC = nVt ð2cÞ Vf.p

where, n is the slope factor and Vt = kT/q is the thermal vp2

Inv2
Vf.p Vf.p
voltage. The bandwidth and the center frequency of the VDD VDD VDD VDD
filter are controlled by gmo and gmIF. Although the trans- Vf.n
Inv6 Inv8
conductance gmo’ has the same value with the value of gmo, Inv5 Inv7
VDD
the ability for independent control through the current ITC Vf.p
can be used for compensation reasons. Inv3
vn1 Vf.n Vf.n

2.1 Low voltage differential transconductor Vf.n

vop
VDD
The 1st-order complex blocks are realized by a modified ultra- Vfp io2
low-voltage differential OTA, based on the principle of Na- Inv4
uta’s transconductor [20]. In the modified configuration [18, vn2 Vf.p Vf.n

19] shown in Fig. 4, the transconductor is bulk-controlled, IT

Control
Vfn
through negative feedback loops incorporated into control circuit

circuit, and it is constructed by inverters operated in weak

inversion region. This offers (a) low-voltage capability,
because cascode devices for tuning purposes are avoided and
(b) linear control of transconductance. The bulk terminals of
the transistors are not constant biased as in conventional cir-
cuit topologies, but they are used to adjust their quiescent
point. Inverters Inv1–Inv4 form the double input differential
transconductor, inverters Inv5, Inv8 form the differential
Fig. 4 The modified transconductor
output load and inverters Inv6, Inv7 form the common mode
(CM) output load. All inverters are controlled through the bulk
voltages Vfp and Vfn which are generated by a suitable control
circuit using a control current IT, as it will be explained later.
Although in the original OTA [18] two different tuning

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76
Fig. 5 Schematic diagram of
the proposed technique
circuits allow better control over frequency and Q tuning, in
this filter only one tuning circuit is used in order to reduce the
power consumption and the area of the filter.
The transconductance control methodology is based on
the master–slave technique using the control circuit which
is shown in Fig. 5. The CMOS inverter which is formed by
Mp.s and Mn.s, is the slave or active transconductor element
in which the input voltage Vin is applied. The CM input
voltage is equal to middle supply (VDD/2) for achieving the
maximum voltage swing. The bulk terminals of both
transistors are modified by the control circuit generating
the voltages Vfp and Vfn which are appropriately adjusted in
order to bias the slave inverter with the desired quiescent
current. Transistors Mp.m–Mn.m and Mp.s–Mn.s are the
master and the slave devices, respectively. The aspect
ratios of the master devices are scaled down m times
compared with the corresponding slave devices to mini-
mize the area and current consumption. Therefore, the
quiescent drain currents IDS,p(n),s of the slave devices are
m times larger (m.IT) than IDS,p(n).m of the master devices
which are both equal to IT.
Eventually, using this approach the transconductances
gm.p.s and gm.n.s of Mp.s and Mn.s, respectively, can be
adjusted by means of the controlling current IT. The feed-
back loops ensure also, that the output CM voltage is kept
constant, equal to VDD/2 and independent from the value of
IT. Concluding using this tuning technique both inverters’s
quiescent current and output dc level are simultaneously
defined.
According to the above considerations and assuming
that all transistors operate in weak-inversion the transcon-
ductance of the slave inverter will be equal to,

The 6th-order passive prototype filter used for the design of the
gm:s ¼ gm:p:s þ gm:n:s ¼ ID;p:s þ ID;n:s =nVt
ð3Þ
¼ 2mIT =nVt
where, gm.p.s, gm.n.s are the transconductances and ID,p.s,
ID,n.s are the quiescent drain currents of the Mp.s and Mn.s,
respectively, shown in Fig. 5. Also, n is the slope factor of
the weak inversion I–V characteristic and Vt is the thermal
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Analog Integr Circ Sig Process (2014) 79:73–81
Fig. 6 Passive 6th-order filter
voltage. Then, the differential output current of the
transconductor in Fig. 4 can be found as,
idif ¼ io1  io2 ¼ vin:dif gm:d
ð4Þ
¼ ðvp1  vn1 þ vp2  vn2 Þgm:s
Details about the differential amplifier employed in
Fig. 5 are presented in [18]. Based on Fig. 5 the constant
voltage of VDD/2 is applied to the inverting inputs of the
differential amplifiers (amp) in the master circuit, while the
feedback loops ensure that the non-inverting inputs of the
differential amplifier will be locked at VDD/2, generating
also, the bias voltages Vfp and Vfn.
For extremely small ratios VDD/VTH, where VTH is the
threshold voltage, MOS devices operate deep in the sub-
threshold region. Therefore, the linearity of the proposed
transconductor is similar to a conventional differential pair
with weak-inverted MOS transistors. On the other hand, the
linearity performance can be improved as the bias current
increases. So, a trade-off between linearity and current
consumption should be fulfilled in order to meet the filter’s
specifications.
3 Filter design and simulation results
complex filter is shown in Fig. 6. The normalized element
values for the 6th-order Butterworth function are C1p = 0.518F,
L2p = 1.414H, C3p = 1.932F, L4p = 1.932H, C5p = 1.414F,
L6p = 0.518H and the transfer function is given by,
1
H ðsÞ ¼
s6 þ 3:86s5 þ 7:46s4 þ 9:14s3 þ 7:46s2 þ 3:86s þ 1
ð5Þ
Analog Integr Circ Sig Process (2014) 79:73–81
The signal flow graph for the complex filter designed
following the leapfrog technique is shown in Fig. 7. The
final 12th-order filter is realized by employing the complex
lossy and lossless integrators of Figs. 2 and 3, as depicted
in Fig. 8. Each transconductor in the filter, takes a suitable
transconductance so that gmo = xLOC and gmIF = xIFC.
To verify the operation of the proposed filter, the circuit
was designed and simulated using a triple well 0.13 lm
CMOS process. The supply voltage was VDD = 0.5 V and
the power consumption 2.77mW. The important point to
this is that transistors with a normal threshold voltage (VTH)
have been used in the simulations and not the recently
offered low VTH transistors. The capacitors of the filter in
Fig. 8 have values C1 = C6 = 0.6C, C2 = 1.6C,
Fig. 7 Signal flow graph of a complex leapfrog filter
Fig. 8 12th-order complex filter
77
C5 = 1.7C, C3 = C4 = 1.9C, where C = 180pF for
Bluetooth and C = 90pF for Zigbee. Although the capac-
itors C2 and C5 should be identical, they are slightly dif-
ferent to compensate internal parasitic capacitances which
affect the response of the filter. Switching from Zigbee to
Bluetooth is easily realized by enabling capacitors through
a suitable capacitor bank.
The tuning current in Figs. 2 and 3 was ITA = 12.7 lA
for the input transconductors and for the feedback trans-
conductor in Fig. 2 was ITC = 12.7 lA. The transconduc-
tors used for cross coupling have three different tuning
currents (ITB) in all six stages. The relationship between the
particular ITB in each stage of the filter, approximately, is
following the ratio of the normalized element values of the
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78 Analog Integr Circ Sig Process (2014) 79:73–81

Fig. 9 Frequency response for signal and image for Bluetooth filter Fig. 11 IIP3 Curve for in-band linearity for Bluetooth filter

Table 1 Performance characteristics of the proposed complex filter

Performance factor Bluetooth Zigbee

Supply voltage VDD (V) 0.5 0.5

Power dissipation (mW) 2.77 2.77
Current consumption (mA) 5.54 5.54
Center frequency fIF (MHz) 1 2
Bandwidth (MHz) 1 2
In-band group delay variation (ls) 0.8 0.46
Spot noise (V/sqrt(Hz) at center frequency 59.7n 55.3n
Output noise (lVrms) 15.96 21.09
IRR (dB) at center frequency 71.90 72.58
1st blocker attenuation (fIF ? Df) (dBc) 35.35 38.88
2nd blocker attenuation (fIF ? 2Df) (dBc) 72.84 74.50
3rd blocker attenuation (fIF ? 3Df) (dBc) 93.92 95.45
Fig. 10 Group delay for Bluetooth filter In-band IIP3 (dBm) -4.4 -4.65
Out-of-band IIP3 (dBm) 9.74 6.15
passive filter. So, the tuning current for the six stages are, In-band SFDR (dB) 43.84 42.26
ITB for the 1st and 6th stage, 3.2ITB for 2nd and 5th stage, Out-of-band SFDR (dB) 53.27 49.36
and 4ITB for 3rd and 4th stage, where ITB = 13.8 lA. CMRR (dB) at center frequency 101.12 101.35
The aspect ratio of transistors of the transconductor in Fig. 4 PSRR (dB) at center frequency -44.34 -44.34
were (W/L)p.s1–4 = 100/0.2 lm, (W/L)n.s.1–4 = 50/0.2 lm for
Inv1–4, (W/L)p.s.5–8 = 100/0.2 lm, (W/L)n.s.5–8 = 50/0.2 lm
for Inv5–8. In Fig. 5, the aspect ratio of the transistors are (W/ process parameters variations and this will be studied in the
L)1–3 = 100/0.5 lm, (W/L)4,5 = 30/0.2 lm for the amplifier. next.
Scale factor was m = 1, the bias current was IB = 1 lA, and The bandwidth and center frequency were 1 and 2 MHz
supply voltage was 0.5 V. for Bluetooth and Zigbee, respectively. The frequency
Simulated results at schematic level have been taken for response for the Bluetooth configuration is shown in Fig. 9.
Bluetooth and Zigbee. Postlayout simulations would pro- The image rejection ratio (IRR) of the filter is better than
vide more realistic information about the effect of parasi- 70 dBc for both filters in their center frequency, and the in-
tics on the filter performance. Taking into account the band group delay variation is 0.8 and 0.46 ls for Bluetooth
absence of the transconductors internal node parasitics and (shown in Fig. 10) and Zigbee, respectively. The filter has
the fact that the filter is electronically tunable, the sche- in-band 3rd-order intercept point (IIP3) -4.4 dBm, as
matic level simulation results provide reasonable infor- shown in Fig. 11, and in-band spurious free dynamic range
mation about the behavior of the filter in a real (SFDR) better than 42 dB. Output integrated noise for
implementation. The most important behavior factor in low Bluetooth is 15.96 and 21.09lVrms for Zigbee. For both
frequencies is the effect of MOS transistors mismatch and Bluetooth and Zigbee, the common-mode rejection ratio

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Analog Integr Circ Sig Process (2014) 79:73–81
Fig. 12 Center frequency tuning for Bluetooth filter
Fig. 13 Bandwidth tuning for Bluetooth filter
Fig. 14 Frequency response variation for Bluetooth filter
(CMRR) is better than 101 dB at center frequency and
power supply rejection ratio (PSRR) is better than
44.43 dB. In Table 1 the filter’s performance characteris-
tics for Bluetooth and Zigbee are summarized.
79
Fig. 15 Bandwidth variation for the Bluetooth filter
The center frequency and the bandwidth of this filter are
orthogonally tunable. The center frequency can be con-
trolled by the current ITB. By changing the current from 10
to 30 lA, the center frequency is varied in the range from
0.84 to 1.22 MHz for Bluetooth as shown in Fig. 12 and
from 1.64 to 2.35 MHz for Zigbee. Also, the bandwidth
can be controlled by the current ITA. The current ITC is kept
equal to ITA to achieve a constant gain response. By
changing the current ITA from 10 to 22 lA, the bandwidth
is varied in the range from 0.78 to 1.72 MHz for Bluetooth
for ITB = 13.8 lA, as shown in Fig. 13. The bandwidth is
varied in the range from 1.56 to 3.72 MHz for Zigbee for
ITB = 13.8 lA.
In order to examine the influence of the process and
mismatch variations on the cutoff frequency of the filter,
Monte Carlo simulation are performed. The mean value is
at 1.002 MHz for Bluetooth and 1.991 MHz for Zigbee,
with a standard deviation r = 17.9 kHz for Bluetooth and
r = 35.4 kHz for Zigbee. The variation of frequency
response for the Bluetooth filter is shown in Fig. 14 and the
deviation of the center frequency in Fig. 15.
The parameters of this filter are compared with recently
published complex filters which are resistorless and operate
in low supply voltage, lower than 1.2 V. The comparison
results are summarized in Table 2. The proposed filter has
the lowest supply voltage of 0.5 V, dissipates significantly
less power and also shows the highest IRR. On the other
hand, SFDR is comparable with other works. The disability
for improving SFDR is probably the cost paid for the low
supply voltage with the good power consumption. Some
other topologies, not shown in the comparison table, may
show improved SFDR but all of them operated under
higher supply voltage. Finally, the improved CMRR make
the proposed filter a good choice for common noise
rejection.
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80 Analog Integr Circ Sig Process (2014) 79:73–81

Table 2 Comparison with recent works

Performance factor This work [14] [16] [17]

Technology CMOS (lm) 0.13 0.09 0.35 0.35

Order 12 6 12 12
Type gm-C gm-C Log-domain Active RC
Supply voltage (V) 0.5 1.2 1.2 1.2
Power consumption (mW) 2.77 3.6 10.9LF/15.4W 5.6
Center frequency (MHz) 1BT/2ZB 2 0.92BT/1.9ZB
Bandwidth (MHz) 0.5–1.5 (and 1–3) (IF band 1–3 MHz) 1.54–2.50LF/1.59–2.40W 0.92BT/1.9ZB
BT ZB
In-band group delay (ls) 0.8 /0.46 – – 1BT/0.5ZB
Input Ref. noise (lVrms) 69BT/90ZB – – 260
BT ZB LF W
Image Rejection ratio (dB) 71.9 /72.6 – [45.7 /[46.1 41BT/40ZB
BT ZB
1st blocker attenuation 35.3 /38.9 – – 37
(fIF ? Df) (dBc)
2nd blocker attenuation 72.8BT/74.5ZB – – 73.5BT/71.5ZB
(fIF ? 2Df) (dBc)
3rd blocker attenuation 93.91BT/95.4ZB – – 94.5BT/91ZB
(fIF ? 3Df) (dBc)
In-band IIP3 (dBm) -4.4BT/-4.65ZB -12.5 (prototype I) – –
-13 (prototype II coil free)
In-band SFDR (dB) 43.84BT/43.67ZB 55.5 (prototype I) 36.9LF/36.7W at 1.950 and 2.050 MHz 45BT/44ZB
54.4 (prototype II coil free)
BT ZB
Out-of-band SFDR (dB) 53.27 /49.36 – 49LF/43.2W 50.2BT/47.6ZB
at 3 and 6 MHz
Independent tuning of center Yes No No No
frequency and BW
BT Bluetooth, ZB Zigbee, LF leapfrog, W wave

4 Conclusion
In this paper a 12th-order differential complex filter which
is suitable for Bluetooth and Zigbee protocol implemen-
tations is described. Employment of an improved low
voltage transconductor allows operation with supply volt-
age as low as 0.5 V. The filter meets the requirements for a
complex filtering stage embedded in Bluetooth or Zigbee
receivers. Also, it has the ability of independent tuning of
center frequency and bandwidth, it shows low power
consumption, and reasonable performance in terms of
noise, image rejection and linearity.
Acknowledgments This research is financially supported by Greek
State Scholarship Foundation (IKY).
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12. Laoudias, C., Psychalinos, C. (2010). Low-voltage Bluetooth/ Researcher with the Department of Physics, University of Patras,
ZigBee complex filter using current mirrors. International Sym- Greece. He is currently a member of the technical staff of the
posium on Circuits and Systems (ISCAS), 1268–1271. Department of Physics, University of Patras, Greece. Dr. Souliotis has
13. Alzaher, H., Tasadduq, N., & Al-Ammari, F. (2013). Optimal low 30 papers in international journal and conferences and holds an
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IEEE Transactions on Circuits and Systems I, 55(11), 3404–3412. M.Sc. degree in Electronic
17. Samiotis P. and Psychalinos, C. (2013). Low-voltage complex Physics in 1996 and the Ph.D.
filters using current feedback operational amplifiers. ISRN Elec- degree in 2000, from Aristotle
tronics. doi:10.1155/2013/915758. University of Thessaloniki,
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fessor with Electronics Laboratory, Department of Physics.
Richa Arya was born in Muzf- University of Patras, Greece. His research interests are in analog and
farnagar, Uttar Pradesh, India in RF integrated circuits and high-speed inter-chip interfaces.
1983. She received her B.Sc.
degree in 2003 and M.Sc. Costas Psychalinos received
degree in 2005, both in Physics, B.Sc. degree in Physics and
from M.J.P. Rohilkhand Uni- Ph.D. degree in Electronics
versity, Bareilly, India. She has from the University of Patras,
worked as a Part-time Lecturer Greece, in 1986 and 1991,
in Vardhman College, India respectively. From 1993 to
from 2005–2007. She had 1995, he worked as Post-Doc-
earned scholarship from State toral Researcher with the VLSI
Scholarship Foundation (IKY) Design Laboratory at the Uni-
for post-graduate studies in versity of Patras. From 1996 to
2009. She is currently a PhD 2000, he was an Adjunct Lec-
candidate in the Electronics turer with the Department of
Laboratory of University of Patras. Her current research interests Computer Engineering and
include VLSI circuits, analog filter design, Complex filters, gm-C Informatics at the University of
filter, Low voltage devices. Patras. From 2000 to 2004 he
was an Assistant Professor with the Electronics Laboratory, Depart-
George Souliotis received the ment of Physics, Aristotle University of Thessaloniki, Greece. From
B.Sc. degree in Physics from the 2004 to 2009 he was an Assistant Professor and currently he is an
University of Ioannina, Greece Associate Professor with the Electronics Laboratory, Department of
in 1993 and the M.Sc. and Ph.D. Physics, University of Patras, Greece. His research area is in the
degrees in Electronics from the continuous and discrete-time analog filtering, including companding
University of Patras, Greece, in filters, current amplifier filters, CCII and CFOA filters, and sampled-
1998 and 2003, respectively. He data filters, and in the development of ultra-low voltage building
has been with international and blocks for biomedical applications. He also serves as a member of the
startup companies, designing Editorial Board of the Analog Integrated Circuits and Signal Pro-
high-speed circuits for elec- cessing Journal and Associate Editor of the Circuits Systems and
tronic systems. From 2002, he Signal Processing Journal.
serves as an part time Adjunct
Lecturer at the Department of
Electrical Engineering, Techno-
logical Educational Institute of
Patras, Greece. From 2004 to 2008 he worked as a Post-Doctoral

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