how many bits this would evaluate tp 8 bit x 8 bit + 8bit > 16 bit

Implement AND gate using only Mux and Inv ( when you are closer to tapeout .. )
About async FIFo , arbriter

1) Convert flip with set input into one with reset input
2) Desing an FSM Vending Machine:
candy bar costs 45 cents
you can input 5 cent, 10 cent, 25 cents
and then give out change at the end
cannot use counter, adder etc - state machine
3) Write verilog code to sum nums 1,2,3,.....100
4) You have 3 FIFO 1 writing at 1MB/s , second one at 2 MB/s and 3rd one 4MB/s
They all need to use the same bus , first come first access , bus throughput is 8 MB/s , each time FIFO is
read 8Bytes
find the depth of each of the FIFO needed to avoid overflow ??

5) Asked to describe the synthesis flow

6) Clock gating
7) CDC Design questions
8) You have a pulse on one clock cycle whose clock is faster
You have to make sure it gets sampled on other clock domain which is slower
Design a logic which can accomplish this.
Also you have req-ack protocol 4-phase ( cant use this , it will not work for edge sensitive signals )

9)

> Write an FSM to find out if 0 to 1 or 1 to 0 transitions are higher in a bit stream of 100101011110000
> Write verilog code to determine an input number is prime number or not
> Say you have a FPGA , its supposed to work at 600 MHz and its working at 300Mhz. What might have
gone wrong ?
>

Explain Glitch free mux schematic

Given 8-bit data bus at 100MHz , Convert it to serial data output at 800MHz.Use Shift register , load
technique.
Parallel in serial out concept
Divide by 5 design

Clock gating cell

Glitch free clock mux
Circuit to sort 4 numbers (use comparators and mux- 5 iterations)
Priority Mux related question to implement a logic given on board

Demets Usage
How to synchronize a bus
Div/3
Generate a pulse for every 4
cycles

How to make Asynchronous reset to synchronous reset in simulations ( remove posedge reset)
Tell which of reset_a ,rest_b is the priority - given a circuit
Bus synchronizer , Do clock gating using enable for power saving
Clock gating , why use negative latch ? whats the width violation if latch is not used ?
a,b,c are 8bit numbers- whats the results of a*b+2c
Probabilty All Heads on coin tossed 10times and Probability of having atleast one tail
For A stick cut at two places, whats the prob that 3 pieces can form a triangle
Perl Script
Ben 0 1 2 5
Jon 4 5 6 8
Ben 6 3 2 1
Implement the script to Add 0 , 3 rd positions of Ben
NAND gate - x is faster than y . which are connected to A,B of NMOS - answer based on critical path

General Readings:
Best article for CDC - https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html

Article for FSM :

http://web.mit.edu/6.111/www/f2007/handouts/L07.pdf
https://inst.eecs.berkeley.edu/~cs150/fa05/Lectures/07-SeqLogicIIIx2.pdf

Good links for Synthesis , Hold times

https://forums.xilinx.com/t5/Synthesis/what-exactly-is-elaborating-a-design/td-p/682043
https://forums.xilinx.com/t5/Timing-Analysis/HOLD-VIOALATION-ON-SIGNAL-GOING-FROM-POSEDGE-
TO-NEGEDGE/td-p/519465
https://solvnet.synopsys.com/dow_retrieve/M-
2017.03/dcolh/Default.htm#dcolh.htm%3FTocPath%3D_____1

CDC .. bus synchronization

Very big question - covers all logic , digital design skills
In the circuit d0 , c0 , d1 , c1 ... d95 , c95 .. z = sum(di*ci) for i = 0 to 95
clock 25M , 50 M ,100M and 200M - num of multipliers required
Max bits of output N , Multiplier , adder
memory architecture if parallelized multipliers are used
4 input nand using 2 input nand gates
verilog code snippet ( <= and = ) difference
Difference btw #5 a = b and b = #5 a

https://courses.edx.org/courses/course-v1:MITx+6.004.2x+3T2015/courseware/c3/c3s1/
TCL practice:
Grab a collection
Set dont_touch using for loop
Why do you need boundary scan registers ?
DFT scan regs working

Clock Leaf Driver Cell Max Cap Limit

Preliminary CTS Jitter
Preliminary Hold Margin
Preliminary Max Transition Release for both CLK and DATA
CTS Jitter
timing sign off corners OCV release
Max CLK Transition
1.1 PDK model correlation derates
pd margin file release
VT Slew Specific Hold Margin
Design Based AOCV and POCV Incremental Release for Clk and Data
Tempus minSA Derates Release

Prior experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks
and/or caches
Good knowledge of PCIE protocol - Gen 3 and above
Experience in micro-architecture and RTL development of complex designs in Verilog
Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS
transistors and circuits is required
Good understanding of ASIC design flow including RTL design, verification, logic synthesis, timing
analysis, floorplanning, ECO, bring-up & lab debug