7 CLK Tree Synthesis PDF

Day 7
Clock Tree Synthesis
Session Speaker
Ajaya Kumar.s
1
PEMP VSD531
Session objective
After completing this session students will be able to:

• Clock Tree General Concepts
• Impact of clock skew
• Clock Skew Types
• CTS in design flow and basic steps
• CTS in real P&G flow
• Set up the design for clock tree synthesis
• Perform clock tree synthesis
• Perform post CTS optimizations
• Analyze timing and clock specifications post CTS
© M.S.Ramaiah School Of Advanced Studies 2

PEMP VSD531
Session Topics
• Clock Tree Synthesis (CTS) goals
• Clock tree attribute
• Clock Distribution schemes
• Clock Skew
• Clock Tree Optimization Techniques
• Effect of clock tree synthesis
• Identify settings of key timing parameters for pre-CTS and post-CTS stages

PEMP VSD531
Design Status, Start of CTS Phase
• Placement - completed
• Power and ground nets – prerouted
• Estimated congestion – acceptable
• Estimated timing – acceptable (~0ns slack)
• Estimated max cap/transition – no violations
• High fanout nets:
• Reset, Scan Enable synthesized with buffers
• Clocks are still not buffered
Why
Whyare
arethere
thereno
nobuffers
bufferson
onclock
clocknets?
nets?

PEMP VSD531
Before CTS
FF FF FF FF FF FF
FF FF FF FF FF FF
Clock
FF FF FF FF FF FF
FF FF FF FF FF FF
All
Allclock
clockpins
pinsare
aredriven
drivenby
byaasingle
singleclock
clocksource.
source.

PEMP VSD531
CTS Goals
Meet logical Design Rule Constraints (DRC):

{ Maximum transition delay
Constraints
Constraints are
are upper
upper bound
bound goals.
goals.
{ Maximum load capacitance If
If constraints
constraints are
are not
not met,
met,
violations
violations will
will be
be reported.
reported.
{ Maximum fanout
{ Maximum buffer levels
Targets
Targets are
are "nice
"nice to
to have"
have" goals.
goals. If
If
Meet the clock tree targets: targets
targets are
are not
not met,
met,
{ Maximum skew no
no violations
violations will
will be
be reported.
reported.
{ Min/Max insertion delay

PEMP VSD531
Clock Tree Synthesis (CTS) (1/2)
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF FF FF FF
Clock
FF FF FF FF FF FF
A
A buffer
buffer tree
tree is
is built
built to
to balance
balance the
the loads
loads and
and minimize
minimize the
the skew.
skew.

PEMP VSD531
Clock Tree Synthesis (CTS) (2/2)
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF FF FF FF
Clock
FF FF FF FF FF FF
A
A “delay
“delay line”
line” is
is added
added to
to meet
meet the
the minimum
minimum insertion
insertion delay.
delay.

PEMP VSD531
Where does the Clock Tree Begin and End?
Clock tree begins at STOP

D
Q
GATED FF
SDC-defined clock source: CLK
{ create_clock D
Q
STOP
Clock tree ends at “sinks”

FF

CLOCK
CLK
Clock sinks are: Start STOP

D
Q
FF
{ Stop / Float pins CLK
{ Exclude pins (aka ignore pins)

PEMP VSD531
Define Clock Root Attributes (1/2)
When the clock root is a primary port of a block

{ Ensure that an appropriate driving cell is defined
set_driving_cell
{ The synthesis constraints may include a weak driving cell
for all inputs, including the clock port
{ Because the clock is ideal during synthesis it has no effect
on design QoR
{ But a weak driver on the clock port affects clock tree
QoR during CTS
Driving Cell
CLK
External driving cell specified for clock port
Clock root defined on primary clock port

PEMP VSD531
Define Clock Root Attributes (2/2)
When the clock root is a primary port, but at the CHIP-

level through an IO-PAD
{ Ensure that an appropriate input transition is defined
set_input_transition
Specify input transition
CLK
IO_PAD
Clock root defined on

primary clock port

PEMP VSD531
Stop, Float and Exclude Pins
Exceptions skew and insertion

delay are optimized
Implicit STOP or FLOAT pins
D
GATED Q
STOP Pins:
FF
{ CTS optimizes for DRC and clock CLOCK
D
Q
tree targets (skew, insertion delay) CLK

FF
FLOAT Pins: IP_CLK
IP
CLK
{ Like Stop pins, but with delays on
clock pin
EXCLUDE Pins: skew and insertion
D
delay are ignored Q
{ CTS optimizes for DRC only
Implicit EXCLUDE pins
CLK_OUT
(ignores clock tree targets) FF
CLK

PEMP VSD531
Generated and Gated Clocks
D Q
FF1
GATED 0.64 CLK
All insertion delays are D Q
matched 0.65
FF2
CLK
D Q
FF3
CLK
CLOCK
D
Q
0.63
D Q
create_clock FFD FF4
CLK CLK
QN
D Q
create_generated_clock FF5
CLK
Skew will be balanced ‘globally’, within each clock domain,

across all clock-pins of both master and generated clock.

PEMP VSD531
User-defined or Explicit Stop Pins
Scenario: If the clock pin inside a

macro cell is correctly defined, CTS CLOCK D
Q
FF3
will treat that pin as an implicit stop CLK
skew and
pin. In this insertion delay
are ignored
example the clock pin is
not defined. What is the problem
here?
IP_CLK D
?
Q
FF
The
The macro’s
macro’s clock
clock pin
pin is
CLKn
is Implicit
exclude pin no clock
marked
marked as
as an
an implicit
implicit pin
definition
exclude
exclude pin
pin –– no
no skew
skew
IP (FRAM)
optimization!
optimization!

PEMP VSD531
Defining an Explicit Stop Pin
Defining an explicit
CLOCK D Q
stop pin allows CTS to 0.42

FF
CLK
optimize for skew and

skew and insertion
insertion delay 0.43 delay are now
targets. optimized
IP_CLK D
CTS has no knowledge 0.17

Q
FF
Explicit stop pin defined
of the IP-internal clock CLKn
delay – it can only “see”

up to the stop pin!
IP
set_clock_tree_exceptions –stop_pins [get_pins IP/IP_CLK]

PEMP VSD531
Defining an Explicit Float Pin
CLOCK D
Exceptions 0.42
Q
FF
CLK
skew and insertion

Defining
Defining anan explicit
explicit float
float 0.27
delay are now optimized
pin
pin allows
allows CTS
CTS toto adjust
adjust
the
the insertion
insertion delays
delays based
based
on IP_CLK
on specification.
specification. D
Q
Explicit float pin defined 0.15

FF
D
Q CLKn
FF
IP CLKn
set_clock_tree_exceptions \
-float_pins IP/IP_CLK \
-float_pin_max_delay_rise 0.15

PEMP VSD531
Clock Tree Optimization
Perform additional Clock Tree Optimization as necessary to further

improve clock skew.
Placed design with clock tree
synthesized that meets
setup/hold, tran/cap
Clock
Clock Analysis
Analysis
CT optimization is run inside
clock_opt, and can be run
independently as well:
Clock
Clock spec
spec No
CTO
CTO
met?
met? optimize_clock_tree
Yes
Routing

PEMP VSD531
Clock Distribution Systems
Style Distribution
Unconstrained tree Automated buffer placements with

unconstrained trees
Balanced tree Multiple levels of balanced tree segments
H-tree is most common
Central spine Central clock driver
Spines with matched branches Multiple central structures with length (or
delay) matched branches
Grid Interconnected (shorted) clock structure
Hybrid distribution Combination of multiple techniques

Common theme is tree + grid or spine + grid

PEMP VSD531
Unconstrained tree
It is commonly used in automatic synthesis flows and usually placed with little or
no restriction on the number of buffer stages and explicit matching between
interconnect delays and the buffer delays

PEMP VSD531
Balanced Tree
• Uses Recursive H structure to distribute

the clock signal
• At each point of a new H in the tree,

the resistance is halved and the
capacitance is doubled
• Larger line width is used for the main

H structure to minimize resistance
• Narrower line width is used at the

branching points along the tree to
minimize capacitance

PEMP VSD531
Balanced Tree Cont….
Balanced H-tree clock topology is a

structural symmetry, a balanced tree
exhibits identical nominal delay and
identical buffer and interconnect segments
from the root of the distribution to all
branches.
Full balanced tree topologies are designed

to span the entire die in both the horizontal
and vertical dimensions. They are capable
of delivering the clock to all regions
of the die.

PEMP VSD531
H structure
Clock Driver
Larger line width

to reduce
resistance
Narrow line to reduce

capacitance

PEMP VSD531
Grid Network
• Gridded clock distribution was

common on earlier DEC Alpha
microprocessors.
• Advantages:
• Clock signals are available everywhere
• Tolerant to process variations
• Usually yields extremely low skew
values
• Disadvantages:
• Huge amounts of wiring & power
• Routing area large
• Wire cap large
PEMP VSD531
Central Spine
A central spine clock distribution is a

specific implementation of a binary
tree. Figure shows an idealized
central spine implementation with the
final branches serving all parts of the
die. The binary tree is shown to have
embedded shorting at all distribution
levels and unconstrained routing to
the local loads at the final branches.
In this configuration, the clock can be transported in a balanced fashion across

one dimension of the die with low structural skew. The unconstrained branches
are simple to implement although there will be residual skew due to asymmetry

PEMP VSD531
Hybrid Distribution
A hybrid clock distribution incorporates a

combination of earlier described topologies.
Common configurations are spines-grid
distribution or tree-grid distribution. It
employs a multilevel H-tree driving a
common grid. Specifically, the multilevel H-
tree delivers the clock from the clock
generator to various regions of the die.
Regional buffers (labeled as level 4 buffers in Fig.) residing at the end of the
multilevel H-tree drive a common grid that includes all local loads

PEMP VSD531
Hybrid Distribution Cont…
Pentium 4 processor clock distribution using centralized spines with delay

matched final branches.

PEMP VSD531
Clock distribution characteristics of commercial

processors
Name Frequency skew Technology Clock Dist.
style
Merom 3,000 18 65 Tree/Grid
Power6 5000 8 65 Sym. H-

Tree/Grid
Xeon processor 3,400 11 65 Tree/Grid
Pentium 4 3,600 16 180

processor Spine/Grid
Itanium 2 1,500 24 130 Asymmetric

processor tree

PEMP VSD531
Clock Distribution Network

PEMP VSD531
Path Length and its Delay Model
S0
L0, W0 R1 S1
N0 S0 R0 C1/2 C1/2
CL1
R2 S2
C0/2 C0/2
L2, W2 L1, W1
CL2
C2/2 C2/2
S1
S2
An equal Path length clock Tree The delay Model

PEMP VSD531
Path Length and its Delay Model Cont….
The skew between S1 and S2 is given by :
rl1 rl 2
ts = C L1 − CL2
w1 w2
The skew variation in terms of wire width variation
∂t1 ∂t 2 rl1C L1 rl 2 C L 2
Δt s = Δw1 + Δw2 = − Δw1 + Δw2
∂w1 ∂w2 w12
w2 2
If Δw = ±0.15w the worst case additional skew is

⎛ rl1C L1 rl 2 C L 2 ⎞
Δt s = 0.15⎜⎜ + ⎟⎟
⎝ w1 w2 ⎠
PEMP VSD531
Buffer Insertion in Clock Tree
Different buffer delays cause phase delay variations on different source to sink paths,
the given tolerable skew of a buffered clock tree ts into two components
Tolerable skew for buffer delays,
ts = t + t b
s
w
s
b
t s
= tolerable skew for buffer delays
w
t s
= wire width variation after buffer insertion
Buffer insertion problem is to find the location on the clock tree to insert intermediate
buffers and and these locations are buffer insertion points (BIP’s)

PEMP VSD531
Clock Skew
• Clock skew is the maximum difference in the arrival time of a clock signal at
two different components.
• Clock skew forces designers to use a large time period between clock pulses.
This makes the system slower.
• So, in addition to other objectives, clock skew should be minimized during
clock routing.

PEMP VSD531
Local Skew
DIN A_OUT DIN A_OUT

A D
FF3
Q
A D Q
FF3
CLK
T3 CLK
(0.4ns)
D Q
CLOCK
D
FF1
Q
B CLOCK FF1
CLK
CLK T1
(0.2ns)
B_OUT
D Q
B_OUT B D
FF2
Q
FF2 CLK
T2
CLK
(0.2ns)
Related path is
minimized for skew
Longer runtime

PEMP VSD531
Global Skew
DIN A_OUT DIN A_OUT

A D
FF3
Q
A D Q
FF3
CLK T3 CLK
(0.38ns)
D Q
CLOCK
D
FF1
Q
B CLOCK FF1
CLK
CLK T1
(0.37ns)
B_OUT
D Q
B_OUT B D
FF2
Q
FF2 CLK
CLK
T2
(0.38ns)
All clock delays are
matched as close as
possible
Global skew is recommended - fastest

PEMP VSD531
Useful Skew
DIN A_OUT
DIN A_OUT A D Q
A D
FF3
Q FF3
CLK
CLK T3
(0.22ns)
D Q
B
CLOCK
D
FF1
Q
B CLOCK FF1
CLK
B_OUT
CLK D Q
T1
FF2
(0.11ns)
CLK
B_OUT
D Q
FF2
T2
CLK
(0.35ns)
Add clock delay to FF2
to help setup time
Use to fix small violations where local or global failed

F F
F F
F F
3X F 3X F
F F
F
F F
F
F F
F F
F
F F
F
4X 4X 2X 4X 3X
F F
F F
F F
F F
4X F
F F
F
5X
F F
F F
After
After
F F
F
F
F
3X F
F
F
F
F
F
F
F
4X 2X
F
F
F
Clock Tree Optimization (1/2)
F
F
F
4X
F
F
Before
© M.S.Ramaiah School Of Advanced Studies

F F
F F
F F
3X F 3X F
F F
F
F F
F
F F
F F
F
F F
F
4X 4X 2X 4X 2X
F F
F F
F F
F F
F
F F
4X 4X F
F F
F F
F F
After
After
36
PEMP VSD531
PEMP VSD531
Clock Tree Optimization (2/2)
F
F
F
F
F
F
F
F
F
F
F
FF
F
F
FF
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
FF
F
F
F
F
F
F
F
F
F
F
F
F
F
F
Before Before
Level Adjustment
F
F
F
F
F
FF
FF
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
FF
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
FF
F
F
F
F
Reconfiguration
After After

PEMP VSD531
Clock Design Problem
• What are the main concerns for clock design?

• Skew
– No. 1 concern for clock networks
– For increased clock frequency, skew may contribute over 10% of the
system cycle time
• Power
– very important, as clock is a major power consumer!
– It switches at every clock cycle!
• Noise
– Clock is often a very strong aggressor
– May need shielding
• Delay
– Not really important
– But slew rate is important (sharp transition)

PEMP VSD531
Effects of Clock Tree Synthesis
Clock buffers added
Congestion may increase
Non clock cells may have

been moved to less ideal
locations
Inserting clock trees can

introduce new timing and max
tran/cap violations

PEMP VSD531
Timing-Driven P&R
optimizes the logic gates, places and routes them to meet all timing constraints
Timing Constraints == Speed Goals
©M.S.Ramaiah School Of Advanced Studies

40
PEMP VSD531
Timing Constraints
Arrival time of inputs

{ Clock period
{ Required arrival time at outputs

41
PEMP VSD531
Timing is Based on Cell and Net Delays
•0.5 ns
•Rnet •Cnet •Cpin
•Cell Delay = ƒ(Input Transition Time, Cnet + Cpin)

•Net Delay = ƒ(Rnet, Cnet + Cpin)
IC Compiler calculates delay for every cell and every net

To calculate delays, needs to know each net’s parasitic Rs and Cs

42
PEMP VSD531
TLU
Layer "METAL1" {
TLU model comes …
unitNomResistance = 6.4e-5
from the vendor and is …
contained in “tech” file }
CapTable "metal1_C_LATERAL_14MIN" {
Contains capacitance wireWidthSize = 5
look-up tables only wireSpacingSize = 16
wireWidth = (0.16, 0.32, 0.48, 0.64, 0.8)
Resistance is calculated from the net wireSpacing = (0.18, 0.36, 0.54, 0.72, …, 2.88)
geometry and capValue = (0.000183764, 9.85682e-05, 6.5029e-05, …
)
a resistance/length (unit resistance) }
value from the tech file
…
CapModel "metal1Config4" {
refLayer = "METAL1"
lateralCapType = "Table"
lateralCapDataMin = "metal1_C_LATERAL_14MIN"
…
}

43
PEMP VSD531
TLU +:
TLU+ models:
Model UDSM process effects
Contain C and R look-up tables
If TLU+ models are available, use them!
UDSM
UDSMProcess
ProcessEffects
Effects
Conformal Dielectric
Conformal Dielectric
TLU+ Astro
Metal
MetalFill
Fill
Shallow
ShallowTrench
TrenchIsolation
Isolation
Copper Dishing:
Copper Dishing:
••Density
DensityAnalysis
Analysis
••Width/Spacing Single
Width/Spacing nxtgrd Star-RCXT
Trapezoid
TrapezoidConductor
Conductor Process File
(ITF)

44
PEMP VSD531
Mapping file
The Mapping File maps the .tf layer/via names to Star-RCXT .itf layer/via
names.
cb13.tf cb13.itf
Layer "METAL" { DIELECTRIC cm_extra3 { THICKNESS=0.06 ER=4.2 }

layerNumber = 14 CONDUCTOR cm { THICKNESS=0.26 WMIN=0.16
…}
maskName = "metal1"
DIELECTRIC diel1d { THICKNESS=0.435 ER=4.2 }
…
…
cb13.map
conducting_layers
poly poly
metal1 cm
metal2 cm2
…

45
PEMP VSD531
Calculating Cell and Net Delay
Now that R and C are known from TLU/TLU+,

the delays can be calculated
For Cell Delays, only Ceff is needed
R3 U2
C3
C4
R2
U1
R1
C2
C1
Calculating Net Delay is done using Delay Calculation algorithms: Elmore,

AWE, Arnoldi

46
PEMP VSD531
PreRoute Delay Calculation Algorithm: Elmore
Virtual Route
Pin-to-pin timing
After placement, but prior to routing, net geometry is estimated based on a

Virtual Route
Since Virtual Routing is only an estimate,
Elmore should be used for all steps up to and including routing

47
PEMP VSD531
PostRoute Delay Calculation Algorithms (Cont…..)
Detailed
Route
After routing, detailed nets are available and extraction will be more
accurate
Use AWE or Arnoldi for postroute optimizations
Arnoldi is preferred when comparing to PrimeTime

48
PEMP VSD531
Timing SetUp parameters
[a] Ignore Interconnect (OFF by default):
When turned “ON”
• ignores any parasitic capacitance and resistance effects of the interconnect
nets (i.e. Rnet = 0; Cnet = 0) during optimization and timing reporting
• The only time this is recommended is when performing a “timing sanity check”
on the starting netlist, before beginning placement. a“timing sanity check” is
performed by running a timing report with all the timing panel settings in pre-
CTS mode, but with Ignore Interconnect” turned “ON”.

49
PEMP VSD531
Timing Setup parameters (Cont…..)
[b] Enable Preset/Clear Arcs (OFF by default):
By default, asynchronous preset and clear timing arcs are not analyzed for timing.
Depending on your design, you may have to enable this setting after CTS. E.g. if
Your design contains a reset network that is asserted asynchronously, will not
analyze for preset/clear violations on the flip-flops unless this setting is enabled

50
PEMP VSD531
Prior to Clock Tree Synthesis (1/3)
Clock Tree not built yet Many more

Clock signal ports are connected directly to FFs D Q
all FF clock ports without a buffer tree
Clock D Q
The SDC should use

set_clock_uncertainty command to model
D Q
an estimate for the Clock Skew that is
going to appear once the Clock Tree is
synthesized Even more Clock skew?
FFs

51
PEMP VSD531
Prior to Clock Tree Synthesis (Cont….)
Load on clock port/driver pre-CTS is tremendous

CTS will buffer the load
Many more FFs

D Q
Clock1 D Q
Pre-CTS,
Pre-CTS, the
the delay
delay to
to the
the FFs
FFs is
is “ideal”.
“ideal”. i.e.
i.e.
the
the delay
delay is
is zero,
zero, unless
unless commands
commands areare used
used to
to
“model”
“model” the
the clock
clock insertion
insertion delay.
delay. example:
example:
set_clock_latency
set_clock_latency
Clock2 D Q
Even more FFs

52
PEMP VSD531
Prior to Clock Tree Synthesis (Cont….)
Clock transition at FF clk ports is unknown until CTS has been

performed
You need to provide an estimate for pre-CTS timing analysis (default
is 0)
D Q
Pre-CTS, use SDC command

?
Clock1 D Q
set_clock_transition to apply a
transition to all FF clock pins
?
Clock2 D Q
?
53
PEMP VSD531
Setup timing check
A setup timing check verifies the timing relationship between the clock and the
data pin of a flip-flop so that the setup requirement is met. In other words, the setup
check ensures that the data is available at the input of the flip-flop before it is
clocked in the flip-flop. The data should be stable for a certain amount of time,
namely the setup time of the flip-flop, before the active edge of the clock arrives at
the flip-flop.

54
PEMP VSD531
Hold Timing Check
A hold timing check ensures that a flip-flop output value that is changing does not
pass through to a capture flip-flop and overwrite its output before the flip-flop has
had a chance to capture its original value. This check is based on the hold
requirement of a flip-flop. The hold specification of a flip-flop requires that the data
being latched should be held stable for a specified amount of time after the active
edge of the clock.

55
PEMP VSD531
Removal timing check
A removal timing check ensures that there is adequate time between an active
clock edge and the release of an asynchronous control signal. The check ensures
that the active clock edge has no effect because the asynchronous control signal
remains active until removal time after the active clock edge. In other words, the
asynchronous control signal is released (becomes inactive) well after the active
clock edge so that the clock edge can have no effect.

56
PEMP VSD531
Recovery Timing Check
A recovery timing check ensures that there is a minimum amount of time between
the asynchronous signal becoming inactive and the next active clock edge. In other
words, this check ensures that after the asynchronous signal becomes inactive, there
is adequate time to recover so that the next active clock edge can be effective.

57
PEMP VSD531
On-Chip Variations
Due to process variations, identical MOS transistors in different portions of the die
may not have similar characteristics . These differences are due to process variations
within the die. Note that the process parameter variations across multiple
manufactured lots can cover the entire span of process models from slow to fast
These differences can arise due to many factors, including:
i. IR drop variation along the die area affecting the local power supply.
ii. Voltage threshold variation of the PMOS or the NMOS device.
iii. Channel length variation of the PMOS or the NMOS device.
iv. Temperature variations due to local hot spots.
v. Interconnect metal etch or thickness variations impacting the interconnect

resistance or capacitance.
58
PEMP VSD531
Derating setup timing check for OCV.

59
PEMP VSD531
Derating Hold timing check for OCV.

60
PEMP VSD531
Data to Data Checks
One important distinction with respect to the setup check of a flip-flop is that the data
to data setup check is performed on the same edge as the launch edge (unlike a
normal setup check of a flip-flop, where the capture clock edge is normally one cycle
away from the launch clock edge). Thus, the data to data setup checks are also
referred to as zero-cycle checks or same-cycle checks.

61
PEMP VSD531
Clock Gating Checks
A clock gating check occurs when a gating signal can control the path of a clock
signal at a logic cell. An example is shown in Figure. The pin of the logic cell
connected to the clock is called the clock pin and the pin where the gating signal is
connected to is the gating pin. The logic cell where the clock gating occurs is also
referred to as the gating cell.

62
PEMP VSD531
Power Gating
Power gating involves gating off the power supply so that the power to the inactive
blocks can be turned off. This procedure is illustrated in Figure, where a footer (or a
header) MOS device is added in series with the power supply. The control signal
SLEEP is configured so that the footer (or header) MOS device is on during normal
operation of the block. Since the power gating MOS device (footer or header) is on
during normal operation, the block is powered and it operates in normal functional
mode.

63
PEMP VSD531
Session Summary
Clock tree synthesis is one of the most important steps of IC design and can
have a significant impact on timing, power, area, etc.
Clock tree synthesis and optimization are an iterative processes and can require
replacement and rerouting various times in order to optimize clock tree
parameters.
CTS importance increases for 90nm and below technologies and especially
when applying low power design techniques as they significantly change the
ratio of gate interconnects as well as manners of building clock trees depending
on their multi-level structures.
Differentiating between TLU/TLU+ models wrt process Foundry rules

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Day 7

Clock Tree Synthesis

After completing this session students will be able to:

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• Clock tree attribute

• Clock Distribution schemes

• Clock Tree Optimization Techniques

• Effect of clock tree synthesis

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Design Status, Start of CTS Phase

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 Meet logical Design Rule Constraints (DRC):

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Clock Tree Synthesis (CTS) (1/2)

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Clock Tree Synthesis (CTS) (2/2)

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Where does the Clock Tree Begin and End?

 Clock tree begins at STOP

SDC-defined clock source: CLK

Clock tree ends at “sinks”

 Clock sinks are: Start STOP

{ Stop / Float pins CLK

{ Exclude pins (aka ignore pins)

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Define Clock Root Attributes (1/2)

 When the clock root is a primary port of a block

Clock root defined on primary clock port

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Define Clock Root Attributes (2/2)

 When the clock root is a primary port, but at the CHIP-

Clock root defined on

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Stop, Float and Exclude Pins

Exceptions skew and insertion

tree targets (skew, insertion delay) CLK

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Generated and Gated Clocks

All insertion delays are D Q

Skew will be balanced ‘globally’, within each clock domain,

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User-defined or Explicit Stop Pins

Scenario: If the clock pin inside a

will treat that pin as an implicit stop CLK

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Defining an Explicit Stop Pin

stop pin allows CTS to 0.42

optimize for skew and

CTS has no knowledge 0.17

delay – it can only “see”

set_clock_tree_exceptions –stop_pins [get_pins IP/IP_CLK]

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Defining an Explicit Float Pin

skew and insertion

Explicit float pin defined 0.15

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Clock Tree Optimization

Perform additional Clock Tree Optimization as necessary to further

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Clock Distribution Systems

Unconstrained tree Automated buffer placements with

Hybrid distribution Combination of multiple techniques

Meet logical Design Rule Constraints (DRC):

Clock tree begins at STOP

Clock sinks are: Start STOP

When the clock root is a primary port of a block

When the clock root is a primary port, but at the CHIP-

IC Compiler calculates delay for every cell and every net