UTKALIKA PANDA

3rd cross B ,Venkateswar Layout, Mahadevpura,Bangalore, Karnataka. India; Contact: +91-7377634601/+91-9538878541

E-Mail: panda.utkalika9@gmail.com(primary)

OBJECTIVES
Seeking a challenging career position within a company, where my professional experience, education and abilities would be an
advantage to the growth of my employer and me.

TECHNICAL SKILLS
 Languages : Verilog, System Verilog, C, C++.
 Methodologies : UVM.
 Tools : Model Sim Simulator (Mentor Graphics), RTL Compiler (Cadence), XilinxISE (Virtex-7),Design
Compiler(Synopsys),Formality(Synopsys),IC Compiler(Synopsys),MATLAB, Virtuoso
(Cadence),VCS(Synopsys),Linting(CadenceHAL),ChipscopePro Analyzer(Xillinx)
 Skills : ASIC verification, Test case creation, Test plan generation, BFMS, Agent development , Checker, Test
bench Development using UVM.

PROFESSIONAL SUMMARY
Overall experience : 3 Years 1 Months Verification Experience
Mirafra Software Technologies Pvt. Ltd.(Feb 2017 - present)
 Project : Worked with Qualcomm: Worked on constrained random verification of the IP that was in submodule
level .Verious coverage closure of the IP such as white box coverage and black box coverage and also test
bench Devlopement of the assigned IP.
PerfectVIPs Techno Solution Pvt. Ltd. (April 2015 – Jan 2017)
 Project : Worked with Synopsys: Stealth mode startup PCIe End point IP verification Project in developing tests to
verify major part of Physical Layer Test cases in PCIe Protocol and improving functional verification. Test
Plan development.Constraint random sequence development for meeting the test plan.
Government Of India sponsored project, Cyber Physical System (CPS), (Aug 2014-Mar 2015 )
 Project : FPGA prototype on Virtex-7 board Low Complexity and Low Power Architecture Design for Reduced 3-
Lead to Standard 12-Lead ECG Signal Reconstruction Architecture for Remote Health Care Monitoring

PAPER PUBLICATIONS
 “Personalized System-on-chip for Standard 12-lead Reconstruction from the Reduced 3-lead System Targeting
Remote Health Care,” 41stAnnual International Scientific Conference on Computing in Cardiology (CinC 2014 Co-
sponsored by IEEE), Cambridge, Massachisetts, USA, 7-10 September, 2014.(This paper has been presented at
Massachusetts Institute of Technology, United States)

EDUCATIONAL CREDENTIALS
Master of Technology (M.Tech) July 2014
Indian Institute of Technology, Hyderabad CGPA: 8.48/10
Specialization:
Microelectronics and VLSI

Bachelor of Technology (B.Tech) July 2010

Krupajal Engineering College, Bhubaneswar CGPA: 7.84/10
Specialization:
Electronics and Telecommunication Engineering

Projects Undertaken
Project1 : Constrained Random Verification and Coverage closure and the test bench Development of the assigned IP
(Feb 2017 – Present)

Environment : System Verilog

Methodology : UVM
Synopsis : Worked on constrained random verification of the IP that was in submodule level. Various coverage closure of
the IP such as white box coverage and black box coverage of the IP assigned. Performed test bench
Development along with test bench modifications of assigned IP.

Project1 : Test case development for Physical Layer of PCI 3.0 (Dec 2015 – Jan 2017)

Environment : System Verilog

Methodology : UVM
Synopsis : Stealth mode startup PCIe End point IP verification Project in developing constrained random tests to verify
major part of Physical Layer Test cases of PCIe Protocol and improving functional coverage.

Project2 : Developed part of the test plan from PCIe 3.0 spec for all PL Layer spec (Sep 2015 – Dec 2015)

Environment : System Verilog

Methodology : UVM
Synopsis : Developed part of the test plan from PCIe 3.0 spec for all PL Layer spec feature and the corresponding
sequences.

Project3 : Design of assertion based APB Protocol and verifying the protocol based on spec (Apr 2015 – Sep 2015)
Environment : System Verilog
Methodology : UVM
Synopsis : Developed the design of APB protocol , the test plan and corresponding constraint random test cases
generation, BFM design, Agent Development for APB protocol.

Project4 : FPGA prototype of the Low Complex and Low Power Design on Virtex -7 for product development which
will give an affordable and wearable solution to that of traditional 10 lead ECG (Aug2014 – Mar 2015)

Technology : FPGA prototyping

Skills/tools : Virtex-7 Xillinx Board.
Synopsis : Proposed and developed a synthesizable RTL code and dumped the code on Virtex-7 Xillinx Board. Functionality
has been checked by the chip-scope pro analyser. The core of Virtex-7 has been take for the PCB Board
implementation for the initial purpose of product validation

Project5 : Design of Low Complexity high speed Architecture and its implementation using 130nm TSMC library(Aug
2013 – July 2014)

Course : M.Tech (Major Project)

Technology : ASIC Implementation
Skills/tools : Design Compiler
Synopsis : Developed a fully synthesizable RTL counter part of an algorithm written in Matlab Code. Implemented the
front end part of the same design on ASIC using 130nm TSMC library. Developed the floor planning of the design
maintaining the power budget and congestion.

Date of Birth : 7th July 1988

Languages Known: English, Hindi & Odia.

Declaration
I hereby declare that the information furnished above is true to the best of my knowledge.
Utkalika Panda