Curriculum Vitae

S. DIVYA BHARATHI Email: divyabharathi.dol@gmail.com

Mobile : +91-9391651515
+91-8309385184

CAREER VISION
To become a key technical resource for an organization, where I am able to explore my full potential, add to my
learning curve, as well as contribute effectively and efficiently to achieve organizational goals.

PROFESSIONAL SUMMARY
 1.1 year of experience in design and development of RTL Code in VHDL for Avionics application projects.
 Developed RTL code for AXI Master Interface for MIG (Memory Interface Generator) to perform data
write to / read from the external DDR3 memory for the Xilinx’s FPGA.
 Developed RTL code using VHDL for ADC, DAC, NVRAM, DPRAM, PCIe to local bridge and External
FIFO Interfaces in FPGA.
 Developed Test benches using VHDL for ADC, DAC, NVRAM, DPRAM, PCIe to local bridge and
External FIFO Interfaces and checked the simulation results in Mentor Graphics QuestaSim.
 Good exposure on Artix7and Spartan6 FPGAs.
 Having user knowledge on Altera’s DE2-115 (Cyclone IV E) evaluation platforms.

EXPERIENCE
 April 2017 to Till Date: Currently working as FPGA Engineer in Dexcel Electronics Designs (P) .Ltd,
Bangalore.
 June 2016 to December 2016: Completed Professional Development Course in VLSI System at UTL
Technologies, Bangalore.
 January 2016 to June 2016 : Done Apprenticeship in BDL (Bharat Dynamics Limited), Hyderabad.

EDUCATIONAL QUALIFICATION

 Bachelor of Engineering in Electrical & Electronics Engineering. with 78.3% from MVSR College of
Engineering, affiliated to Osmania University in 2015.
 Intermediate in MPC with 95% from Narayana Junior College, Hyderabad affiliated to Board of
Intermediate Education, Telangana, in 2011.
 10th(CBSE)with 84.4% from BP DAV School, Hyderabad affiliated to Central Board of Secondary
Education, Telangana, in 2009.

TRAININGS & CERTIFICATIONS

UTL Technologies, Bangalore June 2016 – December 2016.
 Certified in PG diploma course in VLSI System Engineering & Verification from UTL technologies for
the period June 2016 to December 2016.
Maven Silicon, Bangalore November 2016 – December 2016.
 Attended VLSI Chip Designing and Verification Course from Maven Silicon, Bangalore.
TECHNICAL SKILLS

HDL Languages : Verilog, VHDL.

Programming Languages : Basic C.

EDK Tools : Xilinx ISE Design Suite, Xilinx Plan Ahead,
Model Simulator, Questa Simulator, Micro-semi
Libero, Xilinx Vivado.
FPGA Boards : Altera DE2-115.
Operating System : Windows XP, Windows 7, Windows 8. Commented [DB1]:
Commented [DB2]:
Area of Interest
 RTL Coding.
 Development of new IP’s.
 Integration of RTL Designs for different FPGA’s.

PROJECT EXPERIENCE
Project 1: At Dexcel Electronics Designs (P). Ltd

Project Title: DARE DP MSG (Defense Avionics Research Establishment Display Processor Monochrome
Symbol Generator).
Description: The project involved in design and development of a system that displays the symbol data on the
Head Up Display (HUD) based on the control and symbol data coming from the MP Card (Main Processor Card)
through a 208 pin connector via DPRAM. Intel Atom Apollo Lake Processor residing in MSG Card shall send the
control signals as to indicate when to display the symbol on HUD Display. Xilinx Artix 7 FPGA has been used in
the Project.
Role :
 Understanding the requirements and features of the spec.
 RTL coding in VHDL.
 Development of Finite State Machines in VHDL programming.
 Development of unit level test benches for the developed RTL modules.
 Creating design documents and memos.

Project 2: At Dexcel Electronics Designs (P). Ltd

Project Title: VSGO (Video Switching Graphics Overlay Module).

Description: VSGO module contains two Spartan 6 FPGA’s , Overlay FPGA 1 and Overlay FPGA 2. Four Video
outputs from these FPGA’s are connected to the output FPGA for display and post processing operations. Video
switching module, overlay module, graphics processing unit are implemented in the project.
Role :
 Understanding the specifications.
 RTL coding in VHDL, also creating test bench for the corresponding block as per the specifications.
 Development of system level test benches.
 Performing Code coverage analysis, Simulation and Debugging of test cases using Questa simulator.
 Creating design documents and memos.
 Board level debug on different Xilinx FPGA families with Chip Scope analyzer.
Project 3: B.E

Project Title: Power Theft Detection and Indication Using GSM Technology.

Description: Project demonstrates how power theft occurs near Distribution Transformer. Energy meter disc
revolutions of both consumer and distribution transformer are converted to pulses of frequency division
multiplexed. If there’s found any difference in the reading then it is that power theft has occurred which is detected
using a micro controller and indicated using GSM Technology.

POSITIONS & RESPONSIBILITY

 Project leader for the project did in my professional development course.
 Project leader for the project did in my B.E final year.
 Coordinator for 1 year to the technical paper presentations competition for EEE branch conducted in our
college “Samavarthan”.

ACHIEVEMENTS & PARTICIPATION

 Won First Prize in the technical paper presentations given in Princeton college of Engineering. on Paper
Battery.
 Participated in technical paper presentation in BVRIT College on Modern Trends in Power System
Protection.
 Participated in technical paper presentation in JBIET College on Chameleon Chip.

PERSONAL DETAILS
Gender : Female.
Date of Birth : 06-04-1993.
Nationality : Indian.
Marital Status : Single.
Languages Known : Telugu, English, Kannada and Hindi.

DECLARATION
I do here by declare that all the above statements are true to the best of my knowledge and belief.

Place: Bangalore. Signature

Date: S DIVYA BHARATHI