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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO.

6, DECEMBER 1979 1111

[6] H. K. Gummel and H. C. Peon, “An integral charge-cont~ol model


of bipolar transistors,” Belt S’yst. Tech. J., vol. 45, pp. 1327-851,
May, June 1970.
[7] J. J. Ebers and J. L. Moll, “Large-signal behavior of junction tran-
sistors,” Proc. IRE, vol. 42, pp. 1761-1772, Dec. 1954.
[8] H. C. de Graaff, “Two new methods for determining the colfector
series resistance in bipola transistors with lightly doped col-
lectors~’ Philips Res. Rep. 24, pp. 70-81, 1969.

Improvement of the Gain of MOS Amplifiers


(a)
BEDRICH J. HOSTICKA

3
‘DD
~ M2
Abstract–Techniques for improving the gain of MOS amplifiers are
dkcussed. These techniques depend on technology used. Baaed on
some of the design ideas presented, an experimental singfe stage ampli- ‘y-l

fier was realized using CMOS transistor arrays which achieved gain of S4 r
3200. —OUT
@
!-
I. INTRODUCTION

Recent development of all-MOS amplifiers has made it pos-


sible to implement analog functions in MOS/LSI [ 1 ] . But when
the voltage gain is considered, the MOS amplifiers are still in-
ferior to the bipolar ones. The maximum available gain of
MOS stages is generally dependent on device geometries and (b)
processing parameters and is, thus, severely limited [2 I How- Fig. 1.
ever, when proper circuit techniques are employed this gain
can be considerably increased. These techniques will largely
where gd~s is the OFF conductance ,of the switch S3. The ca-
depend on technology used.
pacitor C must be sufficiently large so that ~im < ~cl~~k and
II. STAGE WITH BOOTSTRAPPED LOAD c’>> CS,RAY This means that C would have to be several pico-
farads in large-scale integration.
A. Description

Consider the inverter in Fig. l(a) implemented in single B. Computer Simulation


channel t ethnology using an enhancement load device. The The two gain stages of Fig. 1 have been simulated using the
small signal voltage gain at low frequencies is given by the ratio circuit analysis program SPICE 2 [31, version 2D. 1. The
of transconductance of the stage to total output conductance parameters were: VTO = 1 V, KP = 10-5 A/V23 GAMMA =
0.5 V1[2, PHI = 0.65 V, LAMEDA = 0.02 V-l, CGD = CGS=
gm 1
Av=-ti=- (1) 2 X 10-11 F/cm, CGB = 2 X 10-12 F/cm, CBD = CBS = 2 X
gotot gm2 + gdsl + gds2 10-8 F/cm2, and TOX = 10-s cm. Remaining values were
DEFAULT values. Channel dimensions were WI = 10 roil, L ~ =
where gmi and gdsi are the transconductance and the output
1 mil forlfl, and W2 = 1 roil, L2 = 10 mil fori142. The gain of
conductance of the transistor Mi. Clearly gmz >> gds~ for Ml
the inverter for Fig. 1(a) was 7.7, and the gain of the stage in
in saturation region, and gd~ >> gdsl due to b ackgat e bias ef-
Fig. l(b) was 33.
fect. If such an inverter is used in a switched network with at
least 2-phase nonoverlapping clock then one phase can be used
C. Experimental Results
for bootstrapping the load device lf2 [see Fig. l(b)] [2]. The
MOS capacitor C is precharged to th~ threshold ~oltage of M2 The gain stages of Fig. 1 have been tested experimentally us-
by the leakage current during phase @ (switches @ ON), and it ing CMOS transistor arrays MC 14007B. Since all n-channel
maintains constant gate-to-source voltage on M2 during phase transistors have identical geometry, the gain of the amplifier of
@ (switches @ ON). It can then be derived that for frequency Fig. 1(a) had to be expected less than 1. The measured gain
larger than was 0.5. The same transistors were then used in the circuit in
Fig. 1(b), and the gain increased to 1.5. That means a gain in-
1 + t7m2 /(gdsl + gds2 ) crease by a factor of 3. The switches were CMOS analog
fZim = (2)
2flc(l/gds~ + l/(&J~~ + gdsz )) switches MC 14066B, the power supply voltage was 10 V,
~cIock = 16 kHz, and C = 470 pF.
the gain is given by (during phase ~)
III. CASCODE STAGES
&’m 1
Au=- (3) A. Description
gdsl + gds2 + gds3
Cascode stages in integrated circuits are usually operated at
Manuscript received October 10, 1978; revised February 26, 1979. the same bias current as driver and load transistors. However,
The author is with the Department of Electrical Engineering,, Institute it has already been shown that the driver transconductance can
of Telecommunications, Swiss Federal Institute of Technology, Zurich, be increased by an additional current source [4]. Consider
Switzerland. Fig. 2(a) where the transconductance gm ~ of the driver Ml is

0018 -9200/79/1200-1 111$00.75 @ 1979 IEEE


1112 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979

The loop gain of the feedback circuit is approximately gm3 /


(gd~~ + gd~~ ). The disadvantage of this solution is that, in ad-
dition to the pole at the output, one more pole has been intro-
duced at the node A [see Fig. 2(b)]. The pole is determined
Oul by product of capacitance and resistance at this node. The de-
signer will certainly try to select a small bias current for the
t- cascode transistor lf3 and a load at the output in order to ob-
tain high gain. This will increase the resistance at the node A

q
(which is given mainly by 1/gm3 ) and, consequently, lower
this second pole frequency. The bandwidth of the stage will
be, thus, limited.
A suggested novel circuit is shown in Fig. 2(c). The gate of
T Q v~~ the cascode transistor J43 is now connected to the output of
I the feedback stage lf4, 1145. This has two effects: the resis-
tance at the node ..4 is lowered by the loop gain gm4 /(gd~4 +
LOAD

I-J
gdss ) and the bandwidth increased, and the total output con-
ductance of the amplifier is lowered by the same amount. A
M2 J OUT calculation using equivalent MOSFET circuits yields a total
t- output conductance
&LvDc,B,A,
gds 3
gotot =
A ~+~m3(l+g rn4/(gds4 + gdss )) + gds3

gds 1 + gdsz

gdsl + gds2 gds4 + gds5


= gds3 ‘— (6)
gm 3 gm4 “

It can be seen from this calculation that the original loop gain
which lowered the output conductance of the circuit of Fig.
2(b) is now multiplied by the gain of the stage lf4, M5. The
total transconductance is again given mainly by gm ~

Q LOAD $ M5

OUT
gmtot =
gm3(l
grnl(gm3(l

‘gm4/(gds4
‘gm4/(gds4

‘gds5
‘gds5))

)) ‘gdsl
‘gds3)

‘gds2 ‘gds3
t--t--
‘gm 1. (7)

When the MOS stages of Fig. 2 are loaded the voltage gain can
be calculated as A ~ = ‘gm~o~/(gotor + gload).

B. Computer Simulation
The design ideas described in Section III-A have been verified
using the program s PICE 2. The MOSFET model parameters
were the same as in Section II-B for both n- and p-channel de-
(c)
vices with the exception of VTO = – 1 V for p-channel transis-
Fig. 2, tor. Channel dimensions were W = O.5 mil and L = 1 mil for
all transistors. The actual arrangement used for the computer
set by the current source iW2. This current source could be simulation is shown in Fig. 3. The amplifiers in this figure are
either a depletion load device, or a PMOS device. If a large complementary inverters and incorporate voltage level shifters
transconductance is desired larger bias current must be chosen at the input to insure proper bias voltages for the driver tran-
(because gm ‘Jjz). This will of course increase the total sistors. The current sources were set at 14 PA, and the power
OU@Ut conductance go~o~ = gd~ ~ + g&~, sinCe gd~ a ID. An supply voltages were *7.5 V. Table I shows results of the com-
inserted cascode transistor M3 will lower the total output con- puter simulation of three amplifiers loaded by 1 pF at the out-
ductance [see Fig. 2(b) ] , and the ratio gmfot/gotot will in- put [see Fig. 3(a)–(c)] .
crease. It can be readily shown that the total transconduc- The first amplifier tested can be found in Fig. 3(a). It corre-
tance of the stage in Fig. 2(b) is sponds to the stage of Fig. 2(a), but instead of biasing by a
current source, two complementary drivers are used. The gain
grnl (&7rrr3 +&Tcis3) is
.gmtot = (4)
gm3 ‘gdsl ‘gds2 ‘gds3
Au3a .-— gmtot = _ 2gm driver = _ 28.
(8)
which means gmtof = gm ~ when all devices are in saturation.
go tot 2gdsdriver
The output conductance is lowered by the feedback action of
M3 The second amplifier incorporates a complementary cascode
[see Fig. 3(b) ] similarly to the discussed circuit of Fig. 2(b).
gds 3
gotot = The expected gain can be estimated as follows: the total trans-
1 + (gins +gds3)/(gdsl ‘gds2) conductance is given mainly by gmdnver [see (4)] , and the
total output conductance is given by gd~m~~~de multiplied by
gds 1 + gdsz
‘gals 3 (5) feedback loop gain, as in the case of Fig. 2(b) [see (5)] . Since
&Tm3 “ the small-signal parameters of all transistors are identical
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979 1113

IN IN

(a) (b)

IN IN
I I-’l I---%L
A II

I 1 L

(c) (d)
Fig. 3.

TABLE I
COMPUTERSIMULATION
INVERTING AMP. ,
OPEN LOOP
/Fig.4/

r
DC 3-dB UNITY-GAIN PHASE OUTPUT SLEW SETTLING

I I
GAIN FREQUENCY BANDWIDTH MARGIN SWING RATE TIME /.lk/

(kHz) (MHz) (degrees) (v) (v/us) (IIS)

3a 28 115 3.0 81 f7 25 180

3b 1260 2.4 2.77 65 27 28 160

3C 41300 .074 2.94 63 +7 29 210

=lpF
CLOAD

(gmdriver = gmcascode = gm, etc.), it can be reasoned that this


loop gain is approximately A “3a and, hence,

l~u3bl =: l~u3al = IALJ3.12. (9)

Thus, we would expect


gain is somewhat
The third amplifier,
circuit
[Au3bl ~ 282 = 784.
larger owing to changed operating
illustrated
suggest ed in Fig. 2(c).
The computed
point.
in Fig. 3(c), uses the feedback
Recalling the discussion asso-
ciated with this circuit, we notice an improved unity-gain band-
N*OuT + CLOAD
I
1
width. The gain can be estimated using analogous argument .+
to the one mentioned above [see (6) and (7)] ; the gain will be
multiplied once more by the feedback loop gain. Thus Fig. 4.

IAU3CI = IAU301 IAU3=I = [.4 U3=13 = ‘21952. (lo) C. Experimental Results

Again, the computed gain is larger. The amplifiers of Fig. 3 were experimentally tested using
The slew-rate and settling time (within 0.1 percent of a 1-V CMOS arrays MC 14007B. The current sources were set at
step) have been determined for an inverting amplifier configu- 1 mA, and the power supply voltages were t7.5 V. A sum-
ration (see Fig. 4, R ~ = R z = 10 k$l). All three amplifiers have mary of the measured performance parameters appears in
been again loaded by 1 pF. Table H. The gain increase of the amplifier of Fig. 3(c) is lower
1114 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979

TABLE II
EXPERIMENTALRESULTS
r nDmT
“r b,” rnn~
flu”. ,.
\.JJJ~
= .)
.,
I TNVFRTTNG AMPLIFIER /F IQ.
,., 4/
I I
AMPLIFIER DC 3-dB OUTPUT SLEW SETTLING

TYPE GAIN FREQUENCY SWING ‘RATE TIME /1%/ ‘LOAD

(kHz) (v) (v/!ls) (p,) (PF)

3a 50 130 +7.5 6 2 0

3b

3C
I
]
600

2300
24

5.5
+7

*7
I
1,
4 2.5

7
0

3d 3200 3 +7 4 4 25

than expected; a final limitation on maximum achievable re- ACKNOWLEDGMENT


sistance at the output node is imposed by reverse biased drain The author would like to thank to S. Taylor from the Uni-
junctions and buffer loading (for measurements). The gain can versit y of California, Berkeley, for valuable discussions and
now be increased only by inserting additional current sources suggestions.
that increase the transconductance of the driver transistors.
For our experiment, two current sources (each 1 mA) were in- REFERENCES
serted symmetrically to boost driver transconductances [see
D. A. Hodges, P. R. Gray, and R. W. Brodersen, “Potential of MOS
Fig. 3(d)] . Thus, the drivers were biased at 2 mA and the cas- [1]
technologies for analog integrated circuits,” lEE.E .f. Solid-State
code transistors at 1 mA. Then the gain increased ~ times. Circuits, vol. SC-13, pp. 285-294, June 1978.
While all measurements were carried out without any loading [21 W. N. Carr and J. P. Mize, MOS/LSIDesign and Applications. New
of the amplifiers, the amplifier of Fig. 3(d) became unstable York: McGraw-HiJl, 1972.
when operated as an inverting amplifier (see Fig. 4, R 1 = R z = [3] L. W. Nagel, “SPICE 2: A computer program to simulate semicon-
10 kfl). A load of 25 pF at the output compensated the am- ductor circuits,” College of Eng., Univ. California, Berkeley, CA,
plifier. The settling time was measured within 1 percent of a Memorandum ERL-M520, 1975.
1 V step. [4] B. J. Hosticka, R. W. Brodersen, and P. R. Gray, ‘CMOS sampled
data recursive falters using switched capacitor integrators,” IEEE J
Because the bandwidth of these circuits was larger than the
Solid-State Circuits, vol. SC-12, pp. 600-608, Dec. 1977.
bandwidth of the equipment used (several megahertz), the
[5] Y. A. Tsividis, “Design considerations in single-channel MOS ana-
bandwidth of the amplifiers of Fig. 3(b) and (c) was lowered log integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-13,
by 1 nF at the output. The unity-gain bandwidth was then pp. 383-391, June 1978.
280 and 400 kHz, respectively. It can be reasoned that the
unity-gain bandwidth without any capacitive load would be
larger for Fig. 3(c) than for Fig. 3(b).
Computer-Aided Analysis of MOSFET-Inverter
IV. CONCLUSIONS
Circuits Using Normalized Variables
The advantage of the stage with bootstrapped load [see
Fig. 1(b) ] is that the gain is comparable to stages with depletion J. A. P. HOOGERVORST, J. M. KOOPMANS,
loads. However, the threshold voltage shift is not necessary. T. POORTER, AND A. F. SCHWARZ
Thus, one processing step has been saved, but an additional sil-
icon area is required for the capacitor and switches.
The CMOS a-mplifiers of Fig.-3(c) and (d) require very simple Abstract -A general approach to analysis and design of MOSFET-
phase compensation: a small on-chip capacitor (1-2 pF) be- inverter circuits is presented. This approach includes the use of normal-
tween the high resistance output node and substrate suffices ized variables in conjunction with an accurate MOSFET model in which
to compensate a very high gain integrated amplifier. Hence, important effects, such as body effect and channel shortening, are
the “pole-splitting” compensation technique does not have to taken into account. Design curves of normalized delay parameters and

be used, and the right-half plane zero, typical for MOS analog power-delay product can be used as a design tool and as a means of
amplifiers using this compensation technique, does not occur comparing different static MOSFET-inverter types. The normalization
[5] . A small compensation capacitor would require a small sil- procedure is independent of MOSFET device scaling rules.
icon area and would allow a high slew-rate as well. The disad-
vantage associated with this technique is that, unlike “pole- I. INTRODUCTION
splitting, ” it takes care only of one stage, i.e., the second most
Optimal design of integrated circuits requires the considera-
dominant pole is not broad-banded simultaneously with
tion of the interrelation between device technology and circuit
narrow-banding of the dominant pole.
In order that the effects of processing parameter
The results shown in this work suggest that the gain of MOS behavior”
amplifiers can be improved by using special techniques. It
should be noted that the technology still imposes limits on Manuscript received January 23, 1978; revised July 16, 1979.
J. A. P. Hoogervorst was with the Department of Electrical Engi-
what can be achieved. As the computer simulation indicates,
neering, Delft University of Technology, Delft, The Netherlands. He
the performance of fully integrated amplifiers would be cer-
is now with the Central Engineering Department, KLM RoyaJ Dutch
tainly superior to the experimental results presented. Smaller Airlines, Schipol-Amsterdam, The Netherlands.
parasitic capacitances would allow smaller bias currents and J. M. Koopmans, T. Poorter, and A. F. Schwarz are with the Depart-
different MOS geometries could be used for an optimized ment of Electrical Engineering, Delft University of Technology, Delft,
circuit. The Netherlands.

0018-9200 /79/1200-1 114$00.75 Cl 1979 IEEE

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