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Abstract–Techniques for improving the gain of MOS amplifiers are
dkcussed. These techniques depend on technology used. Baaed on
some of the design ideas presented, an experimental singfe stage ampli- ‘y-l
fier was realized using CMOS transistor arrays which achieved gain of S4 r
3200. —OUT
@
!-
I. INTRODUCTION
q
(which is given mainly by 1/gm3 ) and, consequently, lower
this second pole frequency. The bandwidth of the stage will
be, thus, limited.
A suggested novel circuit is shown in Fig. 2(c). The gate of
T Q v~~ the cascode transistor J43 is now connected to the output of
I the feedback stage lf4, 1145. This has two effects: the resis-
tance at the node ..4 is lowered by the loop gain gm4 /(gd~4 +
LOAD
I-J
gdss ) and the bandwidth increased, and the total output con-
ductance of the amplifier is lowered by the same amount. A
M2 J OUT calculation using equivalent MOSFET circuits yields a total
t- output conductance
&LvDc,B,A,
gds 3
gotot =
A ~+~m3(l+g rn4/(gds4 + gdss )) + gds3
gds 1 + gdsz
It can be seen from this calculation that the original loop gain
which lowered the output conductance of the circuit of Fig.
2(b) is now multiplied by the gain of the stage lf4, M5. The
total transconductance is again given mainly by gm ~
Q LOAD $ M5
OUT
gmtot =
gm3(l
grnl(gm3(l
‘gm4/(gds4
‘gm4/(gds4
‘gds5
‘gds5))
)) ‘gdsl
‘gds3)
‘gds2 ‘gds3
t--t--
‘gm 1. (7)
When the MOS stages of Fig. 2 are loaded the voltage gain can
be calculated as A ~ = ‘gm~o~/(gotor + gload).
B. Computer Simulation
The design ideas described in Section III-A have been verified
using the program s PICE 2. The MOSFET model parameters
were the same as in Section II-B for both n- and p-channel de-
(c)
vices with the exception of VTO = – 1 V for p-channel transis-
Fig. 2, tor. Channel dimensions were W = O.5 mil and L = 1 mil for
all transistors. The actual arrangement used for the computer
set by the current source iW2. This current source could be simulation is shown in Fig. 3. The amplifiers in this figure are
either a depletion load device, or a PMOS device. If a large complementary inverters and incorporate voltage level shifters
transconductance is desired larger bias current must be chosen at the input to insure proper bias voltages for the driver tran-
(because gm ‘Jjz). This will of course increase the total sistors. The current sources were set at 14 PA, and the power
OU@Ut conductance go~o~ = gd~ ~ + g&~, sinCe gd~ a ID. An supply voltages were *7.5 V. Table I shows results of the com-
inserted cascode transistor M3 will lower the total output con- puter simulation of three amplifiers loaded by 1 pF at the out-
ductance [see Fig. 2(b) ] , and the ratio gmfot/gotot will in- put [see Fig. 3(a)–(c)] .
crease. It can be readily shown that the total transconduc- The first amplifier tested can be found in Fig. 3(a). It corre-
tance of the stage in Fig. 2(b) is sponds to the stage of Fig. 2(a), but instead of biasing by a
current source, two complementary drivers are used. The gain
grnl (&7rrr3 +&Tcis3) is
.gmtot = (4)
gm3 ‘gdsl ‘gds2 ‘gds3
Au3a .-— gmtot = _ 2gm driver = _ 28.
(8)
which means gmtof = gm ~ when all devices are in saturation.
go tot 2gdsdriver
The output conductance is lowered by the feedback action of
M3 The second amplifier incorporates a complementary cascode
[see Fig. 3(b) ] similarly to the discussed circuit of Fig. 2(b).
gds 3
gotot = The expected gain can be estimated as follows: the total trans-
1 + (gins +gds3)/(gdsl ‘gds2) conductance is given mainly by gmdnver [see (4)] , and the
total output conductance is given by gd~m~~~de multiplied by
gds 1 + gdsz
‘gals 3 (5) feedback loop gain, as in the case of Fig. 2(b) [see (5)] . Since
&Tm3 “ the small-signal parameters of all transistors are identical
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979 1113
IN IN
(a) (b)
IN IN
I I-’l I---%L
A II
I 1 L
(c) (d)
Fig. 3.
TABLE I
COMPUTERSIMULATION
INVERTING AMP. ,
OPEN LOOP
/Fig.4/
r
DC 3-dB UNITY-GAIN PHASE OUTPUT SLEW SETTLING
I I
GAIN FREQUENCY BANDWIDTH MARGIN SWING RATE TIME /.lk/
=lpF
CLOAD
Again, the computed gain is larger. The amplifiers of Fig. 3 were experimentally tested using
The slew-rate and settling time (within 0.1 percent of a 1-V CMOS arrays MC 14007B. The current sources were set at
step) have been determined for an inverting amplifier configu- 1 mA, and the power supply voltages were t7.5 V. A sum-
ration (see Fig. 4, R ~ = R z = 10 k$l). All three amplifiers have mary of the measured performance parameters appears in
been again loaded by 1 pF. Table H. The gain increase of the amplifier of Fig. 3(c) is lower
1114 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
TABLE II
EXPERIMENTALRESULTS
r nDmT
“r b,” rnn~
flu”. ,.
\.JJJ~
= .)
.,
I TNVFRTTNG AMPLIFIER /F IQ.
,., 4/
I I
AMPLIFIER DC 3-dB OUTPUT SLEW SETTLING
3a 50 130 +7.5 6 2 0
3b
3C
I
]
600
2300
24
5.5
+7
*7
I
1,
4 2.5
7
0
3d 3200 3 +7 4 4 25
be used, and the right-half plane zero, typical for MOS analog power-delay product can be used as a design tool and as a means of
amplifiers using this compensation technique, does not occur comparing different static MOSFET-inverter types. The normalization
[5] . A small compensation capacitor would require a small sil- procedure is independent of MOSFET device scaling rules.
icon area and would allow a high slew-rate as well. The disad-
vantage associated with this technique is that, unlike “pole- I. INTRODUCTION
splitting, ” it takes care only of one stage, i.e., the second most
Optimal design of integrated circuits requires the considera-
dominant pole is not broad-banded simultaneously with
tion of the interrelation between device technology and circuit
narrow-banding of the dominant pole.
In order that the effects of processing parameter
The results shown in this work suggest that the gain of MOS behavior”
amplifiers can be improved by using special techniques. It
should be noted that the technology still imposes limits on Manuscript received January 23, 1978; revised July 16, 1979.
J. A. P. Hoogervorst was with the Department of Electrical Engi-
what can be achieved. As the computer simulation indicates,
neering, Delft University of Technology, Delft, The Netherlands. He
the performance of fully integrated amplifiers would be cer-
is now with the Central Engineering Department, KLM RoyaJ Dutch
tainly superior to the experimental results presented. Smaller Airlines, Schipol-Amsterdam, The Netherlands.
parasitic capacitances would allow smaller bias currents and J. M. Koopmans, T. Poorter, and A. F. Schwarz are with the Depart-
different MOS geometries could be used for an optimized ment of Electrical Engineering, Delft University of Technology, Delft,
circuit. The Netherlands.