® TDA7319

3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR

ONE STEREO INPUT

ONE STEREO OUTPUT
TWO INDEPENDENT VOLUME CONTROL IN
1.0dB STEPS
TREBLE, MIDDLE AND BASS CONTROL IN
1.0dB STEPS
( s )
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS c t
d u DIP20 SO20

DESCRIPTION
r o s )
The TDA7319 is a volume and tone (bass , mid-
dle and treble) processor for quality audio appli-
e P c t ( ORDERING NUMBERS: TDA7319 (DIP20)
cation in car radio and Hi-Fi system.
l e
Control is accomplished by serial I2C bus micro-
t d u TDA7319D (SO20)

processor interface.
s o r o
O b
The AC signal setting is obtained by resistor net-
works and switches combined with operational
e P Thanks to the used BIPOLAR/MOS Technology,
Low Distortion, Low Noise and Low Dc stepping
amplifiers.
- l e t are obtained.

( s ) o
t
BLOCK DIAGRAM AND APPLICATION CIRCUIT

c b s
d u - O R1 R3

r o s )
2.7K 5.6K

e P c t ( C3
5.6nF
C5
15nF
C6
22nF
C9
100nF
C10
100nF

l e t d u
TREBLE(L)
3
MIN(L)
4
MOUT(L)
5 6
BIN(L)
7
BOUT(L)

o o
C1 2.2µF

r
2 1st VOL 2nd VOL

b s P
L TREBLE MIDDLE BASS
8
OUT L

O e
10

t
SCL

o l e SERIAL BUS DECODE & LATCHES

9

11
SDA I2C
BUS

b s C2 2.2µF

R
19
1st VOL 2nd VOL
13
DIGGND

O
TREBLE MIDDLE BASS OUT R

1
VS SUPPLY

12 20 18 17 16 15 14
AGND CREF TREBLE(R) MIN(R) MOUT(R) BIN(L) BOUT(R) D93AU042E

CREF C4 C7 C8 C11 C12

10µF 5.6nF 15nF 22nF 100nF 100nF

R2 R4
2.7K 5.6K

September 2003 1/16

 TDA7319

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VS Operating Supply Voltage 10.5 V
Tamb Operating Ambient Temperature -40 to 85 °C
Tstg Storage Temperature Range -55 to 150 °C

PIN CONNECTION

VS 1 20 CREF
IN L 2
( s ) 19 IN R
TREBLE L 3
c t 18 TREBLE R
M IN L 4
d u 17 M IN R
r o s )
M OUT L

e P 5

c t ( 16 M OUT R
B IN L
B OUT L
l e t 6
7
d u
15
14
B IN R
B OUT R

s o
OUT L r
8 o 13 OUT R

O b SDA
e P 9 12 GND
- l e t
( s ) SCL
o
10 11 DIG GND

c t b s D93AU041A

d u - O
THERMAL DATA
r o s )
Symbol

e P c t ( Parameter DIP20 SO20 Unit

°C/W

l e t
Rth j-amb

d
Thermal Resistance Junction-pins

u
150 150

o r o
QUICK REFERENCE DATA
s
O b Symbol

e P Parameter Min. Typ. Max. Unit

l
VS

e
VCLt Supply Voltage
Max. input signal handling
6
2
9 10.5 V
Vrms

s o
THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 0.08 %

O b S/N
SC
Signal to Noise Ratio
Channel Separation f = 1KHz
1st and 2nd Volume Control 1dB step -47
106
100
0
dB
dB
dB
Bass, Middle and Treble Control 1dB step -14 +14 dB
Mute Attenuation 100 dB

2/16
 TDA7319

ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; f = 1KHz; all control = flat (G = 0); Tamb =
25°C Refer to the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit

INPUT
Rin Input Resistance 35 50 65 KΩ

1st VOLUME CONTROL

CRANGE Control Range 45 47 49 dB
AVMAX Maximum Attenuation 45 47 49 dB
Astep Step Resolution 0.5 1.0 1.5 dB
EA Attenuation Set Error G = 0 to -24dB -1.0 1.0 dB

Et Tracking Error
G = -24 to -47dB
G = 0 to -24dB
( s )-1.5 1.5
1
dB
dB
G = 24 to -47dB
c t 2 dB
Amute
VDC
Mute Attenuation
DC Steps
d u
Adiacent Attenuation Steps
80 100
0 3
dB
mV

r o
From 0dB to AVMAX
s ) 0.5 5 mV
2nd VOLUME CONTROL
e P c t (
CRANGE
AVMAX
Control Range
Maximum Attenuation
l e t d u 45
45
47
47
49
49
dB
dB
Astep Step Resolution
s o r o 0.5 1.0 1.5 dB
EA Attenuation Set Error

O b e P
G = 0 to -24dB
G = -24 to -47dB
-1.0
-1.5
1.0
1.5
dB
dB
Et Tracking Error
- t
G = 0 to -24dB

l e
1 dB

( s ) G = 24 to -47dB
o
2 dB
AMUTE
VDC
Mute Attenuation
DC Steps
c t b s Adiacent Attenuation Steps
80 100
0 3
dB
mV

d u - O From 0dB to AVMAX 0.5 5 mV

BASS
Rb r o s )
Internal Feedback Resistance 32 44 56 KΩ
CRANGE P
Control Range
e c t ( ±11.5 ±14 ±16 dB
Astep

MIDDLE
l e t d u
Step Resolution 0.5 1 1.5 dB

s o
Rb
r o
Internal Feedback Resistance 18 25 32 KΩ

O b CRANGE
P
Control Range

e
±11.5 ±14 ±16 dB
Astep

TREBLE
l e tStep Resolution 0.5 1 1.5 dB

s o
CRANGE Control Range ±13 ±14 ±15 dB

O b Astep

SUPPLY
Step Resolution 0.5 1 1.5 dB

VS Supply Voltage (note1) 6 9 10.5 V

IS Supply Current 4 7 10 mA
SVR Ripple Rejection 60 90 dB

AUDIO OUTPUT
Vclip Clipping Level d = 0.3% 2 2.6 Vrms
ROl Output Load Resistance 2 KΩ
RO Output Impedance 100 180 300 Ω
VDC DC Voltage Level 3.8 V

3/16
 TDA7319

ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

GENERAL
eNO Output Noise All Gains 0dB (B = 20 to 20kHz flat) 5 15 µV
Et Total Tracking Error AV = 0 to -24dB 0 1 dB
AV = -24 to -47dB 0 2 dB
S/N Signal to Noise Ratio All Gains = 0dB; VO = 1Vrms 106 dB
SC Channel Separation 80 100 dB
d Distortion AV = 0; Vin = 1Vrms 0.01 0.08 %

BUS INPUTS

(s)
Vil Input Low Voltage 1 V
Vih Input High Voltage 3 V
Iin Input Current Vin = 0.4V -5
c5t µA
VO Output Voltage SDA
Acknowledge
IO = 1.6mA

d
0.4
u 0.8 V

Note 1: the device is functionally good at Vs = 5V. A step down, on VS, to 4V does’t reset the device.
r o s)
e P c t(
let
APPLICATION SUGGESTIONS The fig.1 refers to basic T Type Bandpass Filter
The first and the last stages are volume control
d
ternal and R2,C1,C2 external) the centre fre-u
starting from the filter component values (R1 in-
blocks. The control range is 0 to -47dB (mute)
with a 1dB step.
s o r o
quency Fc, the gain Av at max. boost and the fil-
The very high resolution allows the implementation
b P
ter Q factor are computed as follows:

e
-O
of systems free from any noisy acoustical effect.
The TDA7319 audioprocessor provides 3 bands
t
FC =
le 2 ⋅ π ⋅√
1

(s)
tones control. 
Ri, R2, C1, C2

s o
Bass, Middle Stages

u
The Bass and the middle cells have the same ct Ob AV =
R2 C2 + R2 C1 + Ri C1
R2 C1 + R2 C2
structure.
o d -
Pr (s)
The Bass cell has an internal resistor Ri = 44KΩ  Ri R2 + C1 C2
√ 
Q=
typical. R2 C1 + R2 C2
t
The Middle cell has an internal resistor Ri = 25KΩ
c
ete
typical.

l d u
Several filter types can be implemented, connect-
Viceversa, once Fc, Av, and Ri internal value are
fixed, the external components values will be:

s o
and OUT pins. o
ing external components to the Bass/Middle IN
r AV − 1 Q2 ⋅ C1

O b e P C1 =
2 ⋅ π ⋅ Ri ⋅ Q
C2 =
AV − 1 Q2
Figure 1.

l et R2 =
AV − 1 − Q2

o 2 ⋅ π ⋅ C1 ⋅ FC ⋅ (AV − 1) ⋅Q

bs
Ri internal
Treble Stage
O IN
C1
OUT
C2
The treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25KΩ
typical) and an external capacitor connected be-
tween treble pins and ground
Typical responses are reported in Figg. 10 to 13.
R2
CREF
D95AU313
The suggested 10µF reference capacitor (CREF)
value can be reduced to 4.7µF if the application
requires faster power ON.
4/16
 TDA7319

Figure 2: Noise vs. volume setting Figure 3: SVRR vs. frequency

( s )
c t
d u
r o s )
Figure 4: THD vs. frequency
P (
Figure 5: THD vs. RLOAD

e c t
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
Figure 6: Channel separation vs. frequency Figure 7: Output clip level vs. Supply voltage

O b e P
l e t
s o
O b

5/16
 TDA7319

Figure 8: Quiescent current vs. supply voltage Figure 9: Quiescent current vs. temperature

( s )
c t
d u
r o s )
Figure 10: Bass response

e P (
Figure 11: Middle response

c t
l e t d uRi = 25kΩ
Ri = 44kΩ

s o
C9 = C10 = 100nF (Bout, Bin)
r o C9 = 15nF (MIN)
C6 - 22nF (MOUT)
R3 = 5.6kΩ

O b e P R1 = 2.7kΩ

- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
Figure 12: Treble response Figure 13: Typical tone response

O b e P
l e t CTREBLE = 5.6nF

s o
O b

6/16
 TDA7319

I2C BUS INTERFACE Acknowledge

Data transmission from microprocessor to the
TDA7319 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.

( s )
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is t
Transmission without Acknowledge
c
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH. u
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simplier transmis-
d
r o s )
sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
Byte Format

e P t (
sends the new data.

c
Every byte transferred to the SDA line must con-

e t
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
l
This approach of course is less protected from
u
misworking and decreases the noise immunity.
d
s o r o
Data Validity on the I2CBUS

O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P
Timing Diagram of I2CBUS
c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
Acknowledge on the I2CBUS

7/16
 TDA7319

SDA, SCL I2CBUS TIMING

Symbol Parameter Min. Typ. Max. Unit
fSCL SCL clock frequency 0 400 kHz
tBUF Bus free time between a STOP and START condition 1.3 µs
tHD:STA Hold time (repeated) START condition. After this period, the first 0.6 µs
clock pulse is generated
tLOW LOW period of the SCL clock 1.3 µs
tHIGH HIGH period of the SCL clock 0.6 µs
tSU:STA Set-up time for a repeated START condition 0.6 µs
tHD:DA Data hold time 0.300 µs
tSU:DAT Data set-up time

( s ) 100 ns
tR
tF
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
c t 20
20
300
300
ns (*)
ns (*)
tSU:STO Set-up time for STOP condition
d u 0.6 µs

All values referred to VIH min. and VIL max. levels

r o s )
(*) Must be guaranteed by the I2C BUS master.

e P c t (
l e t d u
Definition of timing on the I2C-bus
s o r o
O b e P
- l e t
( s ) o
SDA

c t b s
tBUF

d u - O tR tF tHIGH tSU;STO

r o s )
tHD;STA tSP

SCL

e P c t (
l e t d u tLOW tF tSU;STA

o
tHD;DAT

s r o tHD;STA tSU;DAT

O b e P
P
P = STOP
S Sr
D95AU314
P

l e t S = START

s o
O b

8/16
 TDA7319

SOFTWARE SPECIFICATION address (the 8th bit of the byte must be 0). The
TDA7319 must always acknowledge at the end
Interface Protocol of each transmitted byte.
The interface protocol comprises: A sequence of data (N-bytes + acknowledge)
A start condition (s)
A stop condition (P)
A chip address byte, containing the TDA7319

TDA7319 ADDRESS

( s )
MSB first byte LSB MSB

c t LSB MSB LSB

S 1 0 0 0 0 1 A 0 ACK

d u DATA ACK DATA ACK P

r o s )
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge

e P c t (
S = Start
P = Stop
l e t d u
MAX CLOCK SPEED 400kbits/s

s o r o
O b e P
- l e t
SOFTWARE SPECIFICATION

( s ) o
Chip address

c t b s
1
MSB
0 0

d u 0

- O0 1 1 0
LSB

r o s )
e P c t (
l e t
FUNCTION CODES

d u
s o r o
1st VOLUME
MSB
0
F6
F6
F5
F5
F4
F4
F3
F3
F2
F2
F1
F1
LSB
0

O b e P
2nd VOLUME 0 F6 F5 F4 F3 F2 F1 1

l e t TREBLE
MIDDLE
1
1
0
0
0
1
F4
F4
F3
F3
F2
F2
F1
F1
F0
F0

s o BASS 1 1 0 F4 F3 F2 F1 F0

O b MUTMUX 1 1 1 F4 F3 F2 F1 F0

POWER ON RESET:
1st volume = 2nd volume = Mute
Treble = Middle = Bass = -14dB
Mutmux = Active Input

9/16
 TDA7319

1st VOLUME CODES

MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
0 0 step 1dB
0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB
0 0 step 8dB

( s )
0
0
0
0
0
1
c t
0dB
-8dB
0 1 0
d u-16dB
0
1
1
0
1
0
r o -24dB
-32dB
s )
1 0 1

e P t
-40dB
c (
1 1 1

l e t d uMUTE

s o r o
O b e P
2nd VOLUME CODES
- l e t
( s ) o
MSB
0
F6 F5 F4

c t
F3 F2

b s F1 LSB
1
FUNCTION
step 1dB

d u 0

- O
0 0 0dB

r o 0
0
s )
0
1
1
0
-1dB
-2dB

e P c t (0 1 1 -3dB

l e t d u
1
1
0
0
0
1
-4dB
-5dB

s o r o 1 1 0 -6dB

O b 0
e P 1 1 1
1
-7dB
step 8dB

l e t
0
0
0
0
0
1
0dB
-8dB

s o 0 1 0 -16dB

O b 0
1
1
0
1
0
-24dB
-32dB
1 0 1 -40dB
1 1 1 MUTE

10/16
 TDA7319

TREBLE CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
1 0 0 TREBLE BOOST
0 0 0 0 0 0dB
0 0 0 0 1 1dB
0 0 0 1 0 2dB
0 0 0 1 1 3dB
0 0 1 0 0 4dB
0 0 1 0 1 5dB
0 0 1 1 0 6dB
0 0 1 1 1 7dB
0 1 0 0 0 8dB

( s )
0
0
1
1
0
0
0
1
1
0
c t
9dB
10dB
0 1 0 1 1
d u 11dB
0
0
1
1
1
1
0
0
0
1
r o 12dB
13dB
s )
0 1 1 1 0

e P t
14dB
c (
1 0 0
0 1 1 1

l e t1

d u 14dB
TREBLE CUT
1 0 0
s o0 0
r o 0dB
1
1
0
0
0

O
0 b 0
1
1
0
e P -1dB
-2dB
1 0
- 0 1
l e t1 -3dB
1

(
0
s ) 1
o0 0 -4dB
1
1
c t 0
0
1
1
b s 0
1
1
0
-5dB
-6dB

d u1 0
- O
1 1 1 -7dB

r o 1 1

s ) 0 0 0 -8dB

e P 1
1
c t (
1
1
0
0
0
1
1
0
-9dB
-10dB

l e t d u1
1
1
1
0
1
1
0
1
0
-11dB
-12dB

s o r o 1 1 1 0 1 -13dB

O b e P 1 1 1 1 0 -14dB

t
1 1 1 1 1 -14dB

o l e
b s
O

11/16
 TDA7319

MIDDLE CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
1 0 1 MIDDLE BOOST
0 0 0 0 0 0dB
0 0 0 0 1 1dB
0 0 0 1 0 2dB
0 0 0 1 1 3dB
0 0 1 0 0 4dB
0 0 1 0 1 5dB
0 0 1 1 0 6dB
0 0 1 1 1 7dB
0 1 0 0 0 8dB

( s )
0
0
1
1
0
0
0
1
1
0
c t
9dB
10dB
0 1 0 1 1
d u 11dB
0
0
1
1
1
1
0
0
0
1
r o 12dB
13dB
s )
0 1 1 1 0

e P t
14dB
c (
1 0 1
0 1 1 1

l e t1

d u 14dB
MIDDLE CUT
1 0 0
s o0 0
r o 0dB
1
1
0
0
0

O
0 b 0
1
1
0
e P -1dB
-2dB
1 0
- 0 1
l e t1 -3dB
1

(
0
s ) 1
o0 0 -4dB
1
1
c t 0
0
1
1
b s 0
1
1
0
-5dB
-6dB

d u1 0
- O
1 1 1 -7dB

r o 1 1

s ) 0 0 0 -8dB

e P 1
1
c t (
1
1
0
0
0
1
1
0
-9dB
-10dB

l e t d u1
1
1
1
0
1
1
0
1
0
-11dB
-12dB

s o r o 1 1 1 0 1 -13dB

O b e P 1 1 1 1 0 -14dB

t
1 1 1 1 1 -14dB

o l e
b s
O

12/16
 TDA7319

BASS CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
1 1 0 BASS BOOST
0 0 0 0 0 0dB
0 0 0 0 1 1dB
0 0 0 1 0 2dB
0 0 0 1 1 3dB
0 0 1 0 0 4dB
0 0 1 0 1 5dB
0 0 1 1 0 6dB
0 0 1 1 1 7dB
0 1 0 0 0 8dB

( s )
0
0
1
1
0
0
0
1
1
0
c t
9dB
10dB
0 1 0 1 1
d u11dB
0
0
1
1
1
1
0
0
0
1
r o 12dB
13dB
s )
0 1 1 1 0

e P t
14dB
c (
1 1 0
0 1 1 1

l e t1

d u14dB
BASS CUT
1 0 0
s o0 0
r o 0dB
1
1
0
0
0

O
0 b 0
1
1
0
e P -1dB
-2dB
1 0
- 0 1
l e t1 -3dB
1

(
0
s ) 1
o0 0 -4dB
1
1
c t 0
0
1
1
b s 0
1
1
0
-5dB
-6dB

d u1 0
- O
1 1 1 -7dB

r o 1 1

s ) 0 0 0 -8dB

e P 1
1
c t (
1
1
0
0
0
1
1
0
-9dB
-10dB

l e t d u1
1
1
1
0
1
1
0
1
0
-11dB
-12dB

s o r o 1 1 1 0 1 -13dB

O b e P 1 1 1 1 0 -14dB

t
1 1 1 1 1 -14dB

o l e
s
MUTMUX CODES
b
O MSB
1
F6
1
F5
1
F4 F3 F2 F1 LSB FUNCTION
INPUTS
X X X 0 0 NOT ALLOWED
X X X 0 1 NOT ALLOWED
X X X 1 0 NOT ALLOWED
X 1 1 1 1 IN

13/16
 TDA7319

mm inch
DIM. OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

( s )
E 7.4 7.6 0.291 0.299
c t
d u
e 1.27 0.050

r o s )
H 10 10.65 0.394

e P 0.419

c t (
h 0.25 0.75 0.010

l e t 0.030

d u
L 0.4 1.27 0.016
s o SO20 r o
0.050

K
O b
0˚ (min.)8˚ (max.)
e P
- l e t
( s ) o
c t b s
d u - O L
h x 45˚

r o s )
e P c t ( A

l e
B
t d u e K A1 C

s o r o H

O b e P
l e t D

s o
O b 20 11

1 0
1

SO20MEC

14/16
 TDA7319

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

( s )
E 8.5 0.335

c t
e 2.54 0.100

d u
e3 22.86 0.900
r o s )
F 7.1 P
0.280

e c t (
I 3.93
l e t 0.155
d u
L 3.3
s o DIP20
0.130
r o
Z 1.34
O b e P
0.053

- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

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 TDA7319

( s )
c t
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

O b
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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