A B C D E

LCFC Confidential
1 1

BMWQ1/Q2 M/B Schematics Document

Intel Skylake U22 with DDRIIIL + AMD Exo-Pro-S3 GPU
2 2

2015-06-02

REV:0.3

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Tuesday, June 02, 2015 Sheet 1 of 60
A B C D E
 A B C D E

LCFC confidential
AMD Exo-Pro 64bit
Package:S3 PCI-Express
Page 18~24 PCIe Port1
4x Gen3 Memory BUS (DDR3L)
Dual Channel DDR3L-SO-DIMM X2
Page 14,15
VRAM:256*16/128*16
1 1.35V DDR3L 1600 MT/s 1
DDR3L*8 4GB/2GB UP TO 8G x 2
Page 25~26

HDMI (DDI0) USB3.0 Left CONN1

HDMI Conn. USB 3.0 1x
Page 34 USB 2.0 1x USB 3.0 Port1
USB 2.0 Port1
Page 41

DP to VGA DPx2 Lane (DDI1)

VGA Conn.
Page 36 Page 35 IT6515FN Intel MCP
eDP x2 Lane USB2.0 2x USB2.0 Right CONN
eDP Conn
SKL-U22 15W USB2.0 Port2, Port3
USB2.0 1x USB Board
Int. Camera
USB2.0 Port6
BGA-1356
2 Int. MIC Conn. 42mm*24mm USB 2.0 1x Touch Screen 2

(optionanl)
Page 33 USB2.0 Port5 Page 33

SATA HDD SATA Gen3

Page 42 SATA Port0
USB2.0 1x
Cardreader Realtek SD/MMC Conn.
SATA ODD SATA Gen1 RTS5170
USB2.0 Port4 Page 30
Page 42 SATA Port1A

USB 2.0 1x NGFF slot WLAN&BT

RJ45 Conn. LAN Realtek PCIe 1x PCIe 1x USB2.0 Port7
Page 38 RTL8111H_CG PCIe Port6 Page 40
Sub-board ( for 14")
Page 37 PCIe Port5

3 HD Audio SPI BUS SPI ROM POWER BOARD 3

Page 3~13
8MB Page 07

LCP BUS USB Board

Codec SPI ROM 4MB
SPK Conn. for reserve
Conexant_CX11802_33Z Page 07
Page 43
Page 43

EC TPM (reserved) Sub-board ( for 15")

ITE IT8586E-LQFP Z32H320TC
Page 44
POWER BOARD
HP&Mic Combo Conn.
USB Board

Touch Pad Int.KBD Thermal Sensor

Page 45 Page 45 NCT7718W ODD Board
Page 39

4 4

www.vinafix.com Security Classification

Issued Date 2014/12/11
LC Future Center Secret Data
Deciphered Date 2015/12/11
Title

Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 2 of 60
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Power Plane Full ON HIGH HIGH HIGH ON ON ON ON

+5VS
+3VALW +1.35V S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+3VS
1 +5VALW +VCCST +VCCIO S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF 1

+VCCSTG
+3VALW_PCH S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+VCCSA
B+ +1.8VALW +VCC_GT
+CPU_CORE
+1.0VALW
+0.675VS
State
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 CONN left @ Not stuff
2 NC 14@ For 14" part
3 NC 15@ For 15" part
USB3.0 4 NC For 14" or 15" part
14or15@
S0 O O O O 5 NC 14or17@ For 14" or 17" part
6 NC AOAC@ AOAC support part
1 USB3.0 CONN Left
S3 O O O X 2 USB2.0 CONN1 Right Cannonlake@ For Cannonlake part
2
3 USB2.0 CONN2 Right CD@ For C cost down 2

4 Camera DUALMIC@ For Dual MIC part

S3
Battery only O O O X USB2.0 5 Cardreader EMC@ For EMC part
6 Touch Panel EMC_15@ For EMC 15" part
7 BT EMC_NS@ For EMC nu-stuff part

S5 S4/AC Only O O X X 8 NC EMC_PX@ For EMC PX part

9 NC EMC_PXNS@ For EMC PX nu-stuff part
10 NC ES@ For ES CPU
S5 S4 X 1 NC EXO@ For EXO GPU
Battery only O X X 2 NC GCLK@ For GreenCLK part
3 NC ME@ For ME part
S5 S4 4 NC NTS@ For nu-touch part
AC & Battery X X X X 5 LAN PCH_SDIO@ For PCH SDIO part
don't exist PCIE 6 WLAN
7 used as SATA
8 used as SATA PX@ For PX part
SMBUS Control Table
3 RANKA@ For VRAM rank A part 3

WLAN Thermal PCH TP X4 PCIE RANKB@ For VRAM rank B part

SOURCE BATT IT8586E SODIMM WiMAX Sensor Module charger DGPU DGPU
(9-12) Realtek_SD@ For Realtek SD part
SINGLEMIC@ For single MIC part
EC_SMB_CK1 IT8586E V 0 HDD SINGLERANK@ For single VRAN rank part
+3VALW V +3VALW X X X X X V X 1A ODD DUALRANK@ For dual VRAN rank part
EC_SMB_DA1 SATA 1B used as PCIE TS@ For touch screen part
EC_SMB_CK2 IT8586E V 2 used as PCIE TPM@ For TPM part
X X V V X X V
EC_SMB_DA2 +3VS X +3VS +3VS +3VALW_PCH UMA@ For UMA part
+3VGS

PCH_SMB_CLK PCH
PCH_SMB_DATA +3VALW_PCH X X V V X V X X X
+3VS +3VS +3VALW_PCH

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address

Device Address
Device Device Address DDR DIMMA 1010 000Xb
4 4

Smart Battery 0X16 Thermal Sensor NCT7718W 1001_100xb DDR DIMMB 1010 010Xb
Charger 0001 0010 b PCH need to update Wlan Rsvd
DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 3 of 60
A B C D E
 5 4 3 2 1

SKL_ULT ?
UC1A

HDMI_TX2- E55 C47 CPU_EDP_TX0-

34 HDMI_TX2- DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0- 33
HDMI D2 HDMI_TX2+ F55 C46 CPU_EDP_TX0+ confirmed with ITE, the HPD
D 34 HDMI_TX2+ DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX0+ 33 D
HDMI_TX1- E58 D46 CPU_EDP_TX1- pull down resistor should follow
34 HDMI_TX1- DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1- 33
HDMI D1 HDMI_TX1+ F58 C45 CPU_EDP_TX1+
34 HDMI_TX1+
HDMI_TX0- F53 DDI1_TXP[1] EDP_TXP[1] A45
CPU_EDP_TX1+ 33 ITE recommended resistor 4.7k~10Kohm
34 HDMI_TX0- DDI1_TXN[2] EDP_TXN[2]
HDMI D0 HDMI_TX0+ G53 B45
34 HDMI_TX0+ DDI1_TXP[2] EDP_TXP[2]
HDMI_CLK- F56 A47
34 HDMI_CLK- DDI1_TXN[3] EDP_TXN[3]
HDMI CLK HDMI_CLK+ G56 B47
34 HDMI_CLK+ DDI1_TXP[3] EDP_TXP[3] +3VS
VGA_TX0- C50 E45 CPU_EDP_AUX#
35 VGA_TX0- DDI2_TXN[0] DDI EDP EDP_AUXN CPU_EDP_AUX# 33
VGA_TX0+ D50 F45 CPU_EDP_AUX
35 VGA_TX0+ DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX 33
DP TO VGA Converter VGA_TX1- C52
35 VGA_TX1- DDI2_TXN[1]
VGA_TX1+ D52 B52 GPP_E15 RC1601 1 @ 2 10K_0402_5%
35 VGA_TX1+ DDI2_TXP[1] EDP_DISP_UTIL
A50
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50
DDI2_TXN[3] DDI1_AUXP

2
C51 E48 VGA_AUX#
DDI2_TXP[3] DDI2_AUXN VGA_AUX# 35
F48 VGA_AUX RC37
DDI2_AUXP G46 VGA_AUX 35
DDI3_AUXN 4.7K_0402_5%
DISPLAY SIDEBANDS F46
DDPB_CLK L13 DDI3_AUXP

1
34 DDPB_CLK DDPB_DATA L12 GPP_E18/DDPB_CTRLCLK L9 HDMI_HPD
34 DDPB_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 HDMI_HPD 34
L7 DP_VGA_HPD
GPP_E14/DDPC_HPD1 DP_VGA_HPD 35
DDPC_CLK N7 L6 GPP_E15 RC181 1 2 0_0402_5%
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# 8,44
DDPC_DATA N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD 33
N11
GPP_E22/DDPD_CTRLCLK

1
+VCCIO N12 R12 PCH_ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_ENBKL 33
R11 PCH_EDP_PWM RC13
RC4 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 PCH_ENVDD PCH_EDP_PWM 33 100K_0402_5%
EDP_RCOMP EDP_VDDEN PCH_ENVDD 33
1 OF 20
+VCCIO&EDP_COMP : SKYLAKE-U_BGA1356

2
Trace Width: 20mil REV = 1 ?
+VCCST_CPU
Isolation Spacing: 25mil @
C C
Max length: 100mil

1
+VCCSTG
RC1625
@ 49.9_0402_1%
1

RC19 UC1D SKL_ULT ?

2
1K_0402_5% XDP_TCK RC15461 2 0_0402_5% JTAGX RC1551 1 2 51_0402_5%
check PROCHOT# circuit with PWR CATERR# D63
H_PECI A54 CATERR# XDP_TDO RC1547 1 2 0_0402_5% PCH_JTAG_TDO RC1543 1 2 51_0402_5%
44 H_PECI +VCCSTG
2

RC20 1 2 499 +-1% 0402 H_PROCHOT#_R C65 PECI

44 H_PROCHOT# PROCHOT# JTAG
H_THRMTRIP# C63
A65 THERMTRIP# B61 XDP_TCK 1 PAD @ XDP_TDI RC1548 1 2 0_0402_5% PCH_JTAG_TDI
SKTOCC# PROC_TCK TC15
CPU MISC D60 XDP_TDI 1 PAD @
PROC_TDI TC16
1

PAD @ TC11 1 XDP_BPM0# C55 A61 XDP_TDO 1 PAD @ XDP_TMS RC1549 1 2 0_0402_5% PCH_JTAG_TMS
BPM#[0] PROC_TDO TC17
RC143 PAD @ TC12 1 XDP_BPM1# D55 C60 XDP_TMS 1 PAD @
BPM#[1] PROC_TMS TC18
1K_0402_5% PAD @ TC13 1 XDP_BPM2# B54 B59 XDP_TRST# 1 PAD @ XDP_TRST# RC1550 1 2 0_0402_5% PCH_JTAG_TRST#
BPM#[2] PROC_TRST# TC27
PAD @ TC14 1 XDP_BPM3# C56
BPM#[3] B56 PCH_JTAG_TCK 1 PAD @
TC29
2

PAD @ TC162 1 GPP_E3 A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI 1 PAD @

GPP_E3/CPU_GP0 PCH_JTAG_TDI TC31 check JTAG circuit?
+VCCST_CPU PAD @ TC163 1 GPP_E7 A7 A56 PCH_JTAG_TDO 1 PAD @
GPP_E7/CPU_GP1 PCH_JTAG_TDO TC35
PAD @ TC164 1 GPP_B3 BA5 C59 PCH_JTAG_TMS 1 PAD @
GPP_B3/CPU_GP2 PCH_JTAG_TMS TC36
check H_THRMTRIP# if need to connector to EC PAD @ TC165 1 GPP_B4 AY5 C61 PCH_JTAG_TRST# 1 PAD @
GPP_B4/CPU_GP3 PCH_TRST# TC42
A59 JTAGX 1 PAD @
JTAGX TC43
RC155 1 2 49.9_0402_1% PROC_OPI_RCOMP AT16
RC156 1 2 49.9_0402_1% PCH_OPI_RCOMP AU16 PROC_POPIRCOMP
RC157 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC170 1 2 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
@
@
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
B B
@

check DDPC_CLK pull high or not?

+3VS

RPC19
8 1 DDPC_CLK
7 2 DDPC_DATA
6 3 DDPB_CLK
5 4 DDPB_DATA

2.2K_0804_8P4R_5%

DDP*_CTRLDATA strapping sampled on the rising edge of PWROK

Port Strap Enable Disable

Pull up to 3.3 V
Port 1 DDPB_CTRLDATA with 2.2Kohm NC
Pull up to 3.3 V
Port 2 DDPC_CTRLDATA with 2.2Kohm NC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1B

AU53
17 DDRA_DQ[0..63] DDR0_CKN[0] DDRA_CLK0# 17
DDRA_DQ0 AL71 AT53
AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDRA_CLK0 17
DDRA_DQ1
DDR0_DQ[1] DDR0_CKN[1] DDRA_CLK1# 17
DDRA_DQ2 AN68 AT55
DDR0_DQ[2] DDR0_CKP[1] DDRA_CLK1 17
DDRA_DQ3 AN69
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE0 17
DDRA_DQ5 AL69 BB56
DDR0_DQ[5] DDR0_CKE[1] DDRA_CKE1 17
DDRA_DQ6 AN70 AW56
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
D DDRA_DQ9 AR68 DDR0_DQ[8] AU45 D
DDR0_DQ[9] DDR0_CS#[0] DDRA_CS0# 17
DDRA_DQ10 AU71 AU43
AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDRA_CS1# 17
DDRA_DQ11
AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDRA_ODT0 17
DDRA_DQ12
DDR0_DQ[12] DDR0_ODT[1] DDRA_ODT1 17
DDRA_DQ13 AR69
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDRA_MA5 17
DDRA_DQ15 AU69 BB54
BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDRA_MA9 17
DDRA_DQ16
AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDRA_MA6 17
DDRA_DQ17
AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDRA_MA8 17
DDRA_DQ18
AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDRA_MA7 17
DDRA_DQ19
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDRA_BS2# 17
DDRA_DQ20 BA65 AW54
AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDRA_MA12 17
DDRA_DQ21
BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDRA_MA11 17
DDRA_DQ22
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDRA_MA15 17
DDRA_DQ23 BB63 AY54
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDRA_MA14 17
DDRA_DQ24 BA61
DDRA_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46
BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDRA_MA13 17
DDRA_DQ26
AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDRA_CAS# 17
DDRA_DQ27
DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDRA_WE# 17
DDRA_DQ28 BB61 AU50
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDRA_RAS# 17
DDRA_DQ29 AY61 AU52
DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDRA_BS0# 17
DDRA_DQ30 BA59 AY51
AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDRA_MA2 17
DDRA_DQ31
AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDRA_BS1# 17
DDRA_DQ32
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_MA10 17
DDRA_DQ33 AW39 BB50
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_MA1 17
DDRA_DQ34 AY37 AY50
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDRA_MA0 17
DDRA_DQ35 AW37 BA50
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDRA_MA3 17
DDRA_DQ36 BB39 BB52
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 17
DDRA_DQ37 BA39
DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1 DDRA_DQS#[0..7]
C DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] DDRA_DQS#[0..7] 17 C
DDRA_DQ41 AW35 AT70 DDRA_DQS1
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2 DDRA_DQS[0..7]
DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] CHECK DDRA_DQS[0..7] 17
DDRA_DQ43 AW33 AY64 DDRA_DQS2
DDRA_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDRA_DQS#3
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3
DDRA_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRA_DQS#4
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5
DDRA_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRA_DQS5
DDRA_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRA_DQS#6
DDRA_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRA_DQS6
DDRA_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRA_DQS#7
DDRA_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRA_DQS7
DDRA_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_DQ[54]/DDR1_DQ[38] SMVREF
DDRA_DQ55 BB29 AW50 WIDTH:20MIL
DDRA_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52
DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR SPACING: 20MIL
DDRA_DQ57 AW27
DDRA_DQ58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA DDR_SM_VREFCA 17
DDRA_DQ59 AW25 AY68
DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ DDR_SA_VREFDQ 17
DDRA_DQ60 BB27 DDR CH - A BA67
DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR_SB_VREFDQ 18
DDRA_DQ61 BA27
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20

SKYLAKE-U_BGA1356
REV = 1 ?
@

B B

+3VALW

RC30
100K_0402_5%
2

CPU_DRAMPG_CNTL 55
+1.35V
1

C
RC3 1 2 2 QC18
1K_0402_5% B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC29
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (DDR3LA)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1C
18 DDRB_DQ[0..63]

DDRB_DQ0 AF65 AN45

DDRB_DQ1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDRB_CLK0# 18
DDRB_DQ2 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDRB_CLK1# 18
DDRB_DQ3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDRB_CLK0 18
AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDRB_CLK1 18
DDRB_DQ4
D DDRB_DQ5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
DDRB_DQ6 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDRB_CKE0 18
DDRB_DQ7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDRB_CKE1 18
DDRB_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRB_DQ9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDRB_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDRB_DQ11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDRB_CS0# 18
DDRB_DQ12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDRB_CS1# 18
DDRB_DQ13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDRB_ODT0 18
AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1 18
DDRB_DQ14
DDRB_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
DDRB_DQ16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDRB_MA5 18
DDRB_DQ17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDRB_MA9 18
AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDRB_MA6 18
DDRB_DQ18
DDRB_DQ19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDRB_MA8 18
AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDRB_MA7 18
DDRB_DQ20
DDRB_DQ21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDRB_BS2# 18
DDRB_DQ22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDRB_MA12 18
AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDRB_MA11 18
DDRB_DQ23
DDRB_DQ24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDRB_MA15 18
AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_MA14 18
DDRB_DQ25
DDRB_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
DDRB_DQ27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDRB_MA13 18
DDRB_DQ28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDRB_CAS# 18
DDRB_DQ29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDRB_WE# 18
AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDRB_RAS# 18
DDRB_DQ30
DDRB_DQ31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDRB_BS0# 18
DDRB_DQ32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDRB_MA2 18
AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDRB_BS1# 18
DDRB_DQ33
AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDRB_MA10 18
DDRB_DQ34
DDRB_DQ35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDRB_MA1 18
DDRB_DQ36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDRB_MA0 18
C DDRB_DQ37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDRB_MA3 18 C
DDRB_DQ38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDRB_MA4 18
DDRB_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDRB_DQS#0
DDRB_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDRB_DQS0
DDRB_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDRB_DQS#1
DDRB_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDRB_DQS1
DDRB_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDRB_DQS#2
DDRB_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDRB_DQS2
DDRB_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDRB_DQS#3 DDRB_DQS#[0..7]
DDRB_DQ46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDRB_DQS3 DDRB_DQS#[0..7] 18
DDRB_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDRB_DQS#4 DDRB_DQS[0..7]
AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDRB_DQS[0..7] 18
DDRB_DQ48 DDRB_DQS4
DDRB_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDRB_DQS#5
DDRB_DQ50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDRB_DQS5
DDRB_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDRB_DQS#6
DDRB_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDRB_DQS6
DDRB_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDRB_DQS#7
DDRB_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDRB_DQS7
DDRB_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRB_DQ56 AT22 DDR1_DQ[55] AN43
DDRB_DQ57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43
DDRB_DQ58 AU21 DDR1_DQ[57] DDR1_PAR AT13 CPU_DRAMRST#_R
DDRB_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
DDRB_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
DDRB_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
DDRB_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRB_DQ63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
B @ B

Need to check the resistor value

+1.35V

1
RC22
2 470_0402_5%

RC23 1 2 0_0402_5% CPU_DRAMRST#_R

17,18 CPU_DRAMRST#

1
EMC_NS@
CC1
0.01U_0402_25V7K
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (DDR3LB)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1E
+3VALW_PCH +3VS +3VS
SPI - FLASH
SMBUS, SMLINK
SPI_CLK RC1539 1 2 15_0402_5% SPI_CLK_R SPI_CLK_R AV2 R7 PCH_SMB_CLK
44 SPI_CLK SPI0_CLK GPP_C0/SMBCLK
SPI_CLK_1 RC1538 1 @ 2 33_0402_5% SPI_SO_R AW3 R8 PCH_SMB_DATA DIMM1, DIMM2, NGFF
SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
SPI0_MOSI GPP_C2/SMBALERT#

3
4

4
3
SPI_WP#_R AW2 RPC20
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 SPI0_IO2 R9 SML0_CLK RPC24
44 SPI_SO SPI0_IO3 GPP_C3/SML0CLK

2
SPI_SO_1 RC177 1 @ 2 33_0402_5% SPI_CS0#_R AU3 W2 SML0_DATA 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
D SPI_CS1#_R AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SML0_ALERT# D
AU1 SPI0_CS1# GPP_C5/SML0ALERT#

2
1

1
2
SPI0_CS2# W3 PCH_SML1_CLK
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R GPP_C6/SML1CLK V3 PCH_SML1_DAT PCH_SMB_CLK QC2A 6 1
44 SPI_SI GPU, EC, Thermal Sensor SMB_CLK_S3 17,18,40

S
SPI_SI_1 RC175 1 @ 2 33_0402_5% SPI - TOUCH GPP_C7/SML1DATA AM7 SML1_ALERT#

D
M2 GPP_B23/SML1ALERT#/PCHHOT# 2N7002KDWH_SOT363-6
GPP_D1/SPI1_CLK

5
M3

G
J4 GPP_D2/SPI1_MISO
SPI_CS0# RC51 1 2 0_0402_5% SPI_CS0#_R V1 GPP_D3/SPI1_MOSI
44 SPI_CS0# GPP_D21/SPI1_IO2
SPI_CS1# RC174 1 @ 2 0_0402_5% SPI_CS1#_R V2
BOARD_ID4 M1 GPP_D22/SPI1_IO3 AY13 PCH_SMB_DATA QC2B 3 4
8 BOARD_ID4 LPC LPC_AD0 32,44 SMB_DATA_S3 17,18,40

S
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 BA13

D
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 32,44
BB13 2N7002KDWH_SOT363-6
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_AD2 32,44
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 32,44
G3 BA12
CL_CLK GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# 32,44
G2 BA11 SUS_STAT# 1
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC81@
CL_RST#
AW9 CLK_PCI_EC_R RC173 2 1 22_0402_5% +3VALW_PCH
+3V_SPI GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_EC 44
KBRST# AW13 AY9 CLK_PCI_TPM_R RC1541 2 1 22_0402_5%
44 KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 CLK_PCI_TPM 32
AW11 PM_CLKRUN# TPM@
SERIRQ AY11 GPP_A8/CLKRUN# SMB_ALERT# 2.2K_0402_5% 2 1 RC1562
32,44 SERIRQ GPP_A6/SERIRQ

1 OF 20
1

SKYLAKE-U_BGA1356
RC60 RC61 REV = 1
?
1K_0402_5% 1K_0402_5%
Check with BIOS, SPI is Dual mode or quad mode @
2

SPI_WP#_R RC54 1 2 15_0402_5% SPI_WP#

+3VALW_PCH
C @ +3V_SPI check CLKRUN# / SUS_STAT# signal if need to connect +3VS C
SPI_HOLD#_R RC55 1 2 15_0402_5% SPI_HOLD# RPC23
+3VS +3VALW_PCH SML0_CLK 4 1
@ SML0_DATA 3 2
RC171 1 2 0_0402_5% PM_CLKRUN# RC11 1 2 8.2K_0402_5%
2.2K_0404_4P2R_5%
RC172 1 @ 2
0_0402_5% SERIRQ RC12 1 2 10K_0402_5%
+3V_SPI
+3V_SPI
* +3VALW_PCH
1. If support DS3, connect to +3VS and don't support EC mirror code; KBRST# RC10 1 2 10K_0402_5%
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
@
1

SML0_ALERT# RC1564 2 1 2.2K_0402_5%

RC179 RC180
1K_0402_5% 1K_0402_5% KBRST# CC1255 1 2 EMC_NS@ 1000P_0402_50V7K
@ @ This signal has a weak internal pull-down.
0 = LPC Is selected for EC. (Default)
2

RC176 1 @ 2 33_0402_5%
1 = eSPI Is selected for EC.
SPI_WP#_R SPI_WP#_1
Notes:
1. The internal pull-down is disabled after RSMRST#
SPI_HOLD#_R RC178 1 @ 2 33_0402_5% SPI_HOLD#_1 de-asserts.
2. This signal is in the primary wel
+3V_SPI Rising edge of RSMRST#
+3VALW_PCH
UC3
SPI_CS0# 1 8
CS# VCC SML1_ALERT# RC1569 1 2150K_0402_5%
SPI_SO 2 7 SPI_HOLD# 1
DO HOLD# CC8
+3VALW_PCH Follow CRB, need to check the strap ? SPI_WP# 3 6 SPI_CLK .1U_0402_10V6-K
B WP# CLK B
@ 4 5 SPI_SI 2
RC1568 2 1 20K_0402_5% SPI_SO_R GND DI +3VALW_PCH +3VS To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
@ added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.
RC1565 2 1 20K_0402_5% SPI_SI_R W25Q64FVSSIQ_SO8
@
(Refer to WW52_MOW)
RC1578 2 1 20K_0402_5% SPI_WP#_R

4
3
@
RC1580 2 1 20K_0402_5% SPI_HOLD#_R RPC25

2
+3V_SPI 2.2K_0404_4P2R_5%

G
@
UC6

1
2
SPI_CS1# 1 8
SPI_SO_1 2 CS# VCC 7 SPI_HOLD#_1 PCH_SML1_CLK QC10A 6 1

S
DO HOLD# EC_SMB_CK2 21,39,44
SPI_WP#_1 3 6 SPI_CLK_1

D
WP# CLK 1
Follow CRB, need to check the strap ? 4 5 SPI_SI_1 CC97 2N7002KDWH_SOT363-6
GND DI

5
.1U_0402_10V6-K

G
@ W25Q32FVSSIQ_SO8 @ @
RC1567 2 1 4.7K_0402_5% SPI_SO_R 2
@
@
RC1566 2 1 4.7K_0402_5% SPI_SI_R PCH_SML1_DAT QC10B 3 4

S
EC_SMB_DA2 21,39,44
@

D
RC1581 2 1 4.7K_0402_5% SPI_WP#_R 2N7002KDWH_SOT363-6

RC64 1 2 1K_0402_5% SPI_HOLD#_R

ES@

Based on WW36 SKL U&Y WOM, RC64 populated,

and RC61 de-populated for SKL U ES sample.
In this case, customers must ensure that the
A SPI flash device on the platform A
has HOLD functionality disabled by default.

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MPC (MISC,JTAG,SPI,LPC,SMB)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VS RC1561 1 @ 2 2.2K_0402_5% GPP_B18

DUALRANK@ DUALMIC@
+3VS SKL_ULT ?
UC1F

1 RC1615 2

1 RC1613 2

1 RC1611 2

1 RC1609 2

1 RC1606 2
RC1602 1 @ 2 10K_0402_5% EC_SCI#_R 17@ 15@ TS@ PX@

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2

LPSS ISH

RC1608
RC1559
10K_0402_5% AN8 P2 BOARD_ID0
PX@ RC1563 1 @ 2 2.2K_0402_5% GPP_B22 AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1

1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
1

PXS_PWREN_R GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3 BOARD_ID0

GPP_B18/GSPI0_MOSI GPP_D12 BOARD_ID1
D AM5 M4 BOARD_ID2 D
GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA 9 BOARD_ID2
CMOS_ON# AN7 N3 BOARD_ID5 BOARD_ID3
33 CMOS_ON# GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
RC183 1 @ 2 0_0402_5% EC_SCI#_R AP5 BOARD_ID4
4,44 EC_SCI# GPP_B21/GSPI1_MISO 7 BOARD_ID4
RC1557 1 PX@ 2 10K_0402_5% PXS_RST#_R GPP_B22 AN5 N1 BOARD_ID5
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
AB1 GPP_D8/ISH_I2C1_SCL
40 UART_RX_DEBUG GPP_C8/UART0_RXD
AB2 AD11 SINGLERANK@SINGLEMIC@

10K_0402_5%
40 UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA

1 RC1616 2

1 RC1614 2

1 RC1612 2

1 RC1610 2

1 RC1607 2

1 RC123 2
RC1558 1 UMA@ 2 10K_0402_5% VGA_PWRGD W4 AD12 14or15@ 14or17@ NTS@ UMA@

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS#
PXS_PWREN RC7 1 PX@ 2 1K_0402_5% PXS_PWREN_R AD1 U1
24,57,58 PXS_PWREN GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
PXS_RST# RC8 1 PX@ 2 0_0402_5% PXS_RST#_R AD2 U2
20 PXS_RST# GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
VGA_PWRGD AD3 U3
20,58 VGA_PWRGD GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS#
AD4 U4
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1
ODD_EN U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
+3VALW_PCH GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
PCH_WLAN_OFF# U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
40 PCH_WLAN_OFF# GPP_C18/I2C1_SDA
PCH_BT_OFF# U9 AY8
40 PCH_BT_OFF# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0
@ BA8
RC1593 2 1 10K_0402_5% ODD_EN AH9 GPP_A19/ISH_GP1 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7
+3VS AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 GPP_A12 1 TC82 @
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
AF11 check GPP_A12
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
Board ID Description Stuff R
@ 00 14" RC1616 RC1614
C RC1595 2 1 10K_0402_5% CMOS_ON# 1 OF 20 C
SKYLAKE-U_BGA1356
RC1596 2 1 10K_0402_5% PCH_WLAN_OFF# REV = 1 ? Board_ID[0:1] 01 15" RC1616 RC1613
RC1597 2 1 10K_0402_5% PCH_BT_OFF#
@ UC1G SKL_ULT ?
10 17" RC1615 RC1614
double check if need the pull up resisor
AUDIO 11 Reserved
RC43 1 2 33_0402_5% HDA_SYNC BA22 Board_ID2 0 Non-touch RC1612
43 HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM
RC42 1 2 33_0402_5% HDA_BCLK AY22
+3VALW_PCH +3VS 43 HDA_BITCLK_AUDIO HDA_BLK/I2S0_SCLK
HDA_SDOUT BB22 SDIO/SDXC 1 Touch RC1611
HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
43 HDA_SDIN0 HDA_SDI0/I2S0_RXD
RC1600 1 @ 2 1K_0402_5% AY21 AB11 SD_CMD_PCH Board_ID3 0 UMA RC1610
HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD SD_CMD_PCH 30
RC44 1 2 33_0402_5% HDA_RST# AW22 AB13 SD_D0_PCH
43 HDA_RST_AUDIO# HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 SD_D0_PCH 30
RC47 1 @ 2 1K_0402_5% HDA_SDOUT J5 AB12 SD_D1_PCH 1 DIS RC1609
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 SD_D1_PCH 30
AY20 W12 SD_D2_PCH
* AW20 I2S1_SFRM
I2S1_TXD
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
W11 SD_D3_PCH
SD_D2_PCH
SD_D3_PCH
30
30 Board_ID4 0 SingleRankRC1607
HDA_SDO This signal has a weak internal pull-down. W10 SD_CD#_PCH
GPP_G5/SD_CD# SD_CD#_PCH 30
0 = Enable security measures defined in the Flash Descriptor. AK7 W8 SD_CLK_PCH 1 DualRank RC1608
GPP_F1/I2S2_SFRM GPP_G6/SD_CLK SD_CLK_PCH 30
AK6 W7 SD_WP_PCH
1 = Disable Flash Descriptor Security(override). This strap AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP SD_WP_PCH 30
should only be asserted high during external pull-up in GPP_F2/I2S2_TXD Board_ID5 0 SingleMIC RC123
AK10 BA9 SD_PWR_EN#
manufacturing/debug environments ONLY. GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 SD_PWR_EN# 44
BB9 SD_1P8_SEL 1 DualMIC RC1606
GPP_A16/SD_1P8_SEL SD_1P8_SEL 30
H5 AB7 SD_RCOMP RC49 1 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
For EMI D8 AF13
HDA_SDIN0 C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
PCH_BEEP AW5
43 PCH_BEEP GPP_B14/SPKR
1
EMC_NS@
B CC7 B
10P_0402_50V8J 1 OF 20
2 SKYLAKE-U_BGA1356
REV = 1 ?
@

+3VS
RC45 1 2 33_0402_5% HDA_SDOUT
43 HDA_SDOUT_AUDIO +3VALW_PCH
RC46 1 2 0_0402_5% @
44 ME_FLASH
RC14 1 2 2.2K_0402_5% PCH_BEEP

PCH_SDIO@
SD_PWR_EN# RC1603 1 2 49.9K_0402_1%
Default When
Pin Name Strap Description Configuration Value Sampled
Internal PD
0 = Disable “Top Swap”
SPKR / Top Swap 0 Rising edge
GPP_B14 Override
mode. (Default)
1 = Enable “Top Swap”
* of PCH_PWROK
mode.
Internal PD
0 = Disable “No Reboot”
GSPI0_MOSINo Reboot
A
/GPP_B18
mode. (Default)
1 = Enable “No Reboot”
* 0 Rising edge A

mode of PCH_PWROK

Internal PD
0 = SPI (Default) Security Classification LC Future Center Secret Data Title
GSPI1_MOSIBoot BIOS Rising edge
/GPP_B22 Strap Bit
1 = LPC * 0 of PCH_PWROK Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (LPSS,ISH,AUDIO,SDIO)
BBS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

PCIE1
D D

SKL_ULT
?
UC1H

SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN G8 USB30_RX_P1 USB30_RX_N1 41
H13 USB3_1_RXP C13 USB30_TX_N1 USB30_RX_P1 41 LEFT USB (3.0)
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB30_TX_N1 41
USB30_TX_P1
B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 41
A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6
G11 USB3_2_RXP/SSIC_1_RXP B13
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
H16 USB3_3_RXP/SSIC_2_RXP B15
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 AB10 USB20_P1 USB20_N1 41
PCIE_PRX_DTX_N5 F16 USB2P_1 USB20_P1 41 LEFT USB (3.0)
37 PCIE_PRX_DTX_N5 PCIE5_RXN
PCIE_PRX_DTX_P5 E16 AD6 USB20_N2
LAN PCIE5
37 PCIE_PRX_DTX_P5
CC22 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N5 C19 PCIE5_RXP USB2N_2 AD7 USB20_P2 USB20_N2 45 RIGHT USB (2.0)
37 PCIE_PTX_C_DRX_N5 PCIE5_TXN USB2P_2 USB20_P2 45
CC23 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P5 D19
C 37 PCIE_PTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3 C
PCIE_PRX_DTX_N6 G18 USB2N_3 AJ3 USB20_P3 USB20_N3 45
40 PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6 F18 PCIE6_RXN USB2P_3 USB20_P3 45 RIGHT USB (2.0)
40 PCIE_PRX_DTX_P6 PCIE6_RXP
WLAN PCIE6 CC24 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N6 D20 AD9 USB20_N4
40 PCIE_PTX_C_DRX_N6 PCIE6_TXN USB2N_4 USB20_N4 33
CC25 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P6 C20 AD10 USB20_P4
40 PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 33 Camera
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
42 SATA_PRX_DTX_N0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_N5 30
SATA_PRX_DTX_P0 USB20_P5
42 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 30 Card reader
42 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
42 SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_P6 USB20_N6 33 Touch panel
G21 USB2P_6 USB20_P6 33
SATA_PRX_DTX_N1
42 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
42 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_P7 USB20_N7 40 BT
42 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 40
42 SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
PCIE_CRX_GTX_N0 E22 USB2N_8 AF9
PCIE_CRX_GTX_P0 E23 PCIE9_RXN USB2P_8
PCIE_CTX_C_GRX_N0 0.22U_0402_10V6K PX@ 1 2 CC16 PCIE_CTX_GRX_N0 B23 PCIE9_RXP AG1
PCIE_CTX_C_GRX_P0 0.22U_0402_10V6K PX@ 1 2 CC14 PCIE_CTX_GRX_P0 A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
PCIE_CRX_GTX_N1 F25 AH7
PCIE_CRX_GTX_P1 E25 PCIE10_RXN USB2N_10 AH8
PCIE_CTX_C_GRX_N1 0.22U_0402_10V6K PX@ 1 2 CC15 PCIE_CTX_GRX_N1 D23 PCIE10_RXP USB2P_10
third-part dGPU PCIEP9 PCIE10_TXN
PCIE_CTX_C_GRX_P1 0.22U_0402_10V6K PX@ 1 2 CC17 PCIE_CTX_GRX_P1 C23 AB6 USB2_COMP RC118 2 1 113_0402_1% USBRBIAS
PCIE10_TXP USB2_COMP AG3 USB2_ID RC1626 1 2 0_0402_5%
USB2_ID
Width 20Mil
PCIE_RCOMPN and PCIE_RCOMPP RC119 1 2 100_0402_1% PCIE_RCOMPN F5 AG4 USB2_VBUSSENSE RC1627 1 2 1K_0402_5% Space 15Mil
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
Trace Width: 12-15mil PCIE_RCOMPP A9
Length 500Mil
USB_OC0#
Differential between RCOMPP/RCOMPN PAD @ TC20 1 XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
1 XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2# USB_OC1# 41
PAD @ TC19
PIRQA# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# USB_OC2# 45
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
PCIE_CRX_GTX_N2 E28 J1 GPP_E4 RC1628 1 @ 2 0_0402_5%
PCIE_CRX_GTX_P2 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 GPP_E5 1 EC_SMI# 44
PCIE_CTX_C_GRX_N2 0.22U_0402_10V6K PX@ 1 2 CC18 PCIE_CTX_GRX_N2 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 @ PAD TC202
PCIE_CTX_C_GRX_P2 0.22U_0402_10V6K PX@ 1 2 CC19 PCIE_CTX_GRX_P2 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
PCIE_CRX_GTX_N3 E30 PCIE11_TXP/SATA1B_TXP H2 SATA0GP
PCIE_CRX_GTX_P3 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 ODD_DETECT#
PCIE_CTX_C_GRX_N3 0.22U_0402_10V6K PX@ 1 2 CC20 PCIE_CTX_GRX_N3 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 SATA2GP
PCIE_CTX_C_GRX_P3 0.22U_0402_10V6K PX@ 1 2 CC21 PCIE_CTX_GRX_P3 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1 BOARD_ID2
GPP_E8/SATALED# BOARD_ID2 8

1 OF 20 +3VS
SKYLAKE-U_BGA1356
REV = 1 ?
@
@
GPP_E4 RC1617 2 1 10K_0402_5%
+3VALW_PCH

20 PCIE_CRX_GTX_N[0..3] +3VS
RPC2 RPC17
1 8 ODD_DETECT# USB_OC0# 8 1
20 PCIE_CRX_GTX_P[0..3]
2 7 SATA0GP USB_OC1# 7 2
3 6 SATA2GP USB_OC3# 6 3
20 PCIE_CTX_C_GRX_N[0..3] 4 5 5 4
PIRQA# USB_OC2#
20 PCIE_CTX_C_GRX_P[0..3]
10K_0804_8P4R_5% 10K_0804_8P4R_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (PCIE,SATA,USB3,USB2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D D36 CSI2_DN2 CSI2_CLKN2 D29 D
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC73 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
check the Pull up resistor CSI2_DN6
B31 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
+3VS B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
RPC3 @ A29 GPP_F16/EMMC_DATA3 AN1
1 8 PCIE_CLKREQ2# B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
2 7 PCIE_CLKREQ3# C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
3 6 PCIE_CLKREQ1# D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
4 5 A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
10K_0804_8P4R_5% C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
RPC4 D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
1 8 GPU_CLKREQ# CSI2_DP11 GPP_F12/EMMC_CMD
2 7 LAN_CLKREQ# AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
3 6 EMMC_RCOMP
4 5 WLAN_CLKREQ# 1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
10K_0804_8P4R_5%
@

SUSCLK RC95 1 @ 2 1K_0402_5%

UC1J SKL_ULT ?

C CLOCK SIGNALS C

CLK_PCIE_GPU# D42
20 CLK_PCIE_GPU# C42 CLKOUT_PCIE_N0
PCIE CLK0 GPU CLK_PCIE_GPU
20 CLK_PCIE_GPU GPU_CLKREQ# AR10 CLKOUT_PCIE_P0
21 GPU_CLKREQ# GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDP# 1 TC85 @
PCIE_CLKREQ1# AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_PCIE_XDP 1 TC87 @
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17 SUSCLK
C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 40
PCIE_CLKREQ2# AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT +VCCCLK5
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1% RC1555
PCIE_CLKREQ3# AT10 CLKOUT_PCIE_P3 XCLK_BIASREF DIFFCLK_BIASREF 1 2 60.4_0402_1%
GPP_B8/SRCCLKREQ3# AM18 RTC_X1 Cannonlake@
CLK_PCIE_LAN# B40 RTCX1 AM20 RTC_X2
37 CLK_PCIE_LAN# CLK_PCIE_LAN A40 CLKOUT_PCIE_N4 RTCX2
PCIE CLK5 LAN 37 CLK_PCIE_LAN CLKOUT_PCIE_P4
LAN_CLKREQ# AU8 AN18 SRTC_RST#
37 LAN_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# AM16 RTC_RST#
CLK_PCIE_WLAN# E40 RTCRST#
40 CLK_PCIE_WLAN# E38 CLKOUT_PCIE_N5
PCIE CLK6 WLAN CLK_PCIE_WLAN
40 CLK_PCIE_WLAN WLAN_CLKREQ# AU7 CLKOUT_PCIE_P5
40 WLAN_CLKREQ# GPP_B10/SRCCLKREQ5#
1
CC3
VCCRTC 1U_0402_10V6K
1 OF 20
SKYLAKE-U_BGA1356 2
REV = 1 ?
RC33 1 2 20K_0402_1% SRTC_RST#
B @ RC34 1 2 20K_0402_1% RTC_RST# RC16241 2 0_0402_5% B
EC_RTC_RST# 44
1 @

1
CC6 JCMOS1
1U_0402_10V6K SHORT PADS
@

2
2

check if need to change to 1M_0402_1% follow PDG, RTC_X1

RC71 2 1 1M_0402_5%
CRB is 1M_0402_5%
YC2 RC32 2 1 10M_0402_5% RTC_X2

2 3 XTAL24_OUT YC1
GND1 OSC2 1 2
XTAL24_IN 1 4
OSC1 GND2 32.768KHZ_9PF_X1A0001410002
2 2
1
1 24MHZ_6PF_X1E000021088000 CC4 CC5
CC12 CC11 8P_0402_50V8J 9P_0402_50V8J
2.7P_0402_50V9-B 2.7P_0402_50V9-B 1 1
2
2 when single end external clock generator used,
this pin should be grounded
need to use 38.4MHz (30ohm) for Cannonlake-u

GCLK@
31 RTC_CLK RC121 1 2 0_0402_5% RTC_X1
A GCLK@ A

31 24M_CLK RC122 1 2 0_0402_5% XTAL24_IN

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CSI2,EMMC,CLOCK)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
?
UC1K
SYSTEM POWER MANAGEMENT
check if need one buffer
AT11 PM_SLP_S0# 1 TC204 PAD @
GPP_B12/SLP_S0# AP15 PM_SLP_S3#_R RC96 1 @ 2 0_0402_5%
1 2 0_0402_5% PLT_RST#_R AN10 GPD4/SLP_S3# BA16 PM_SLP_S4#_R 1 2 0_0402_5% PM_SLP_S3# 11,13,44
RC84 RC97 @
20,32,37,40,44 PLT_RST# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S4# 44
SYS_RESET# PM_SLP_S5#
D 1 2 0_0402_5% SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# 44 D
RC85 PCH_RSMRST#_R AY17
44 EC_RSMRST# RSMRST# AN15 PM_SLP_SUS#_R 1 2 0_0402_5%
RC89 @
1 CPU_PROCPWRGD A68 SLP_SUS# AW15 1 PM_SLP_SUS# 44
PAD @ TC21
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 1 TC40 PAD @ Reserve for DS3
VCCST_PWRGD GPD9/SLP_WLAN# AN16 1 TC41 PAD @
RC139 1 2 0_0402_5% SYS_PWROK_R B6 GPD6/SLP_A# TC44 PAD @
44 SYS_PWROK 1 2 0_0402_5% PCH_PWROK_R BA20 SYS_PWROK BA15 PBTN_OUT#_R 1 2 0_0402_5% PBTN_OUT# 44
RC126 RC87 @
44 PCH_PWROK PCH_DPWROK_R BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT_R
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
RC86 1 @ 2 0_0402_5% SUSWARN#_R AR13 GPD0/BATLOW#
44 SUSWARN# 1 2 0_0402_5% SUSACK#_R AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
RC79 @ VCCRTC
44 SUSACK# Reserve for DS3 GPP_A15/SUSACK# AU11 PME# 1 TC89 @
RC91 1 @ 2 0_0402_5% WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
37,40,44 PCIE_WAKE# PCH_LAN_WAKE# AM15 WAKE# INTRUDER#
PAD @ TC203 1 GPD11 AW17 GPD2/LAN_WAKE# AM10 1 TC93 @
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 1 TC96 @
GPD7/RSVD GPP_B2/VRALERT#

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
+3VALW +3VS

RC74 1 2 10K_0402_5% AC_PRESENT_R RC80 1 2 10K_0402_5% SYS_RESET#

RC88 1 @ 2 0_0402_5% AC_PRESENT_R
1 2 8.2K_0402_5% BATLOW# 44 AC_PRESENT
RC75

RC76 2 1 1K_0402_5% WAKE# Follow CRB change to 1kohm

1
RC90 1 2 10K_0402_5% PCH_LAN_WAKE# D @
C 2 QC8 C
44 ACIN# G 2N7002KW_SOT323-3

3
+3VALW_PCH

RC78 @1 2 10K_0402_5% SUSWARN#_R +VCCST_CPU +VCCSTG

CC1254 EMC_NS@

2
1 2 PCH_RSMRST#_R @
1000P_0402_50V7K +3VALW RC137 RC1554
CC104 EMC_NS@ 1K_0402_5% 1K_0402_5%
1 2 PCH_PWROK

2
1000P_0402_50V7K

1
CC103 EMC_NS@ RC136
1 2 PCH_DPWROK_R 10K_0402_5% VCCST_PWRGD_R
1000P_0402_50V7K

3
EMC_NS@ D

1
CC1011 2 SYS_PWROK 5 QC6B 2
@ G
1000P_0402_50V7K
2N7002KDWH_SOT363-6 CC140

6
D S 1000P_0402_50V7K

4
RC138 1 @ 2 0_0402_5% 2 QC6A 1
44 EC_VCCST_PWRGD @ EMC_NS@
G
1 2N7002KDWH_SOT363-6
RPC21 CC46 S

1
1 8 PCH_RSMRST#_R 0.01U_0402_16V7K
2 7 PCH_PWROK @
EMC_NS@
3 6 SYS_PWROK 2
B 4 5 B

10K_0804_8P4R_5%

RC1599 1 2 0_0402_5%

DC4 1 2 @ RC182 1 2 0_0402_5% EC_RSMRST#

11,13,44 PM_SLP_S3#
RB751V-40_SOD323-2 Reserve for DS3
PCH_DPWROK_R RC81 1 @ 2 0_0402_5%
DPWROK_EC 44

100K_0402_5% 2 1 RC92 PLT_RST#_R

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE ? +CPU_CORE +VCC_GT

SKL_ULT SKL_ULT ?
UC1L +VCC_GT UC1M
CPU POWER 1 OF 4
CPU POWER 2 OF 4
A30 G32 +CPU_CORE +VCC_GT N70
A34 VCC_A30 VCC_G32 G33 A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 VCORE_VCC_SEN RC77 1 2 100_0402_1% VCCGT_VCC_SEN RC83 1 2 100_0402_1% A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
D VCC_AL40 VCC_K33 VCCGT_AA70 VCCGT_T62 D
AM32 K35 AA71 U65
AM33 VCC_AM32 VCC_K35 K37 AC64 VCCGT_AA71 VCCGT_U65 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
@ VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
TC90 1 K32 E32 VCORE_VCC_SEN AC70 VCCGT_AC69 VCCGT_W66 W67
RSVD_K32 VCC_SENSE E33 VCORE_VCC_SEN 59 AC71 VCCGT_AC70 VCCGT_W67 W68
VCORE_VSS_SEN SVID
1 AK32 VSS_SENSE VCORE_VSS_SEN 59 J43 VCCGT_AC71 VCCGT_W68 W69
TC91 +VCCST_CPU
@ RSVD_AK32 B63 CPU_SVID_ALERT#_R J45 VCCGT_J43 VCCGT_W69 W70
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
TC92 1 +V_EDRAM_VR V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62
@ VCCOPC_V62 G20 J52 VCCGT_J50
VCCSTG_G20 +VCCSTG VCCGT_J52
H63 @ J53 AK42 1 TC135 @

.1U_0402_10V6-K
VCC_OPC_1P8_H63 VCCGT_J53 VCCGTX_AK42

1
J55 AK43
TC94 1 +V1.8S_EDRAM G61 J56 VCCGT_J55 VCCGTX_AK43 AK45

CC42
2

1
@ VCC_OPC_1P8_G61 J58 VCCGT_J56 VCCGTX_AK45 AK46

56_0402_5%

100_0402_1%

100_0402_1%

2
TC95 1 AC63 J60 VCCGT_J58 VCCGTX_AK46 AK48

RC131

RC132
RC1544
TC97
@ 1 AE63 VCCOPC_SENSE K48 VCCGT_J60 VCCGTX_AK48 AK50
@ VSSOPC_SENSE K50 VCCGT_K48 VCCGTX_AK50 AK52
AE62 K52 VCCGT_K50 VCCGTX_AK52 AK53

2
TC99 1 +VCCEOPIO AG62 VCCEOPIO_AE62 @ K53 VCCGT_K52 VCCGTX_AK53 AK55
@ VCCEOPIO_AG62 K55 VCCGT_K53 VCCGTX_AK55 AK56
TC100 1 AL63 K56 VCCGT_K55 VCCGTX_AK56 AK58
TC101
@ 1 AJ62 VCCEOPIO_SENSE K58 VCCGT_K56 VCCGTX_AK58 AK60
@ VSSEOPIO_SENSE RC133 1 2 220_0402_1% CPU_SVID_ALERT#_R K60 VCCGT_K58 VCCGTX_AK60 AK70
59 VR_SVID_ALRT# VCCGT_K60 VCCGTX_AK70
L62 AL43
1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
SKYLAKE-U_BGA1356 ? VCCGT_L63 VCCGTX_AL46
REV = 1 RC134 1 2 0_0402_5% CPU_SVID_CLK_R L64 AL50
59 VR_SVID_CLK VCCGT_L64 VCCGTX_AL50
@ L65 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
RC1545 1 2 0_0402_5% CPU_SVID_DAT_R L67 VCCGT_L66 VCCGTX_AL56 AL60
59 VR_SVID_DAT L68 VCCGT_L67 VCCGTX_AL60 AM48
L69 VCCGT_L68 VCCGTX_AM48 AM50
L70 VCCGT_L69 VCCGTX_AM50 AM52
C VCCGT_L70 VCCGTX_AM52 C
L71 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
1, Alert# Route Between CLK and Data VCCGT_M62 VCCGTX_AM56
N63 AM58
N64 VCCGT_N63 VCCGTX_AM58 AU58
N66 VCCGT_N64 VCCGTX_AU58 AU63
N67 VCCGT_N66 VCCGTX_AU63 BB57
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66 TC133
TC134
VCCGT_VCC_SEN J70 AK62 VCCGTX_SENSE 1
59 VCCGT_VCC_SEN VCCGT_SENSE VCCGTX_SENSE
VCCGT_VSS_SEN J69 AL61 VSSGTX_SENSE 1
59 VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE
@
1 OF 20 @
SKYLAKE-U_BGA1356
REV = 1 ?
@

+CPU_CORE

13x10uF 0402, SIT update to 0603 package +VCC_GT Backside Cap 8x10uF 0402, SIT update
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0402_6.3V6-M

10U_0402_6.3V6-M

1 1 1 1 1 1 1 1 1 1

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M
CC1086

CC1085

CC1080

CC1236

CC1237

CC1093

CC1092

CC1091

CC1089

CC1238

1 1 1 1 1 1 1 1

CC1122

CC1123

CC1124

CC1125

CC1126

CC1127

CC1128

CC1129
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
B B
@
@ @ @ @

+VCC_GT
Backside Cap 12x1uF 0201, SIT update
+CPU_CORE
15x1uF 0201, SIT update to 0402 package

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1

CC1111

CC1114

CC1115

CC1116

CC1118

CC1119

CC1240

CC1241
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2
CC1095

CC1096

CC1097

CC1098

CC1099

CC1100

CC1101

CC1102

CC1104

CC1105

CC1108

CC1109

2 2 2 2 2 2 2 2 2 2 2 2

@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CPU PWR1)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCIO
3.1A 2x10uF, 4x1uF
+1.35V Need short +1.35V_CPU

JC1 @

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K
10U_0402_6.3V6-M

10U_0402_6.3V6-M

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
1 2 +VCCIO

CC1218

CC1230

CC1231

@ CC1232
1 2 1 1 1 1 1 1 1 1 1 1
@ +1.35V_CPU

CC1152

CC1153

CC1158

CC1159

CC1160

CC1161
1 ?
UC1N SKL_ULT
JUMP_43X79
CC1170 CPU POWER 3 OF 4
0.1u_0201_10V6K 2 2 2 2 2 2 2 2 2 2
2 AU23 AK28
AU28 VDDQ_AU23 VCCIO_AK28 AK30
+1.35V_CPU AU35 VDDQ_AU28 VCCIO_AK30 AL30 @ @ @ @
2A , 3x22uF, 6x10uF, 4x1uF, SIT update VDDQ_AU35 VCCIO_AL30
AU42 AL42
BB23 VDDQ_AU42 VCCIO_AL42 AM28
BB32 VDDQ_BB23 VCCIO_AM28 AM30 +VCCSA
BB41 VDDQ_BB32 VCCIO_AM30 AM42
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
BB47 VDDQ_BB41 VCCIO_AM42
D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDQ_BB47 D
BB51 AK23 +VCCSA
CC1256

CC1257

CC1258

CC1168

CC1169

CC1171

CC1222

CC1223

CC1243

CC1244

CC1224

CC1225

CC1226

CC1227
VDDQ_BB51 VCCSA_AK23 AK25
@ @ VCCSA_AK25 G23
2 2 2 2 2 2 2 2 2 2 2 2 2 2 VCCSA_G23
4.5A 10x10uF, 7x1uF, SIT update
+VDDQ_CPU_CLK
AM40 G25
VDDQC VCCSA_G25 G27
A18 VCCSA_G27 G28

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M
@ @ +VCCST_CPU VCCST VCCSA_G28 J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A22 VCCSA_J22 J23

CC1133

CC1134

CC1135

CC1136

CC1137

CC1251

CC1252

CC1253

CC1139

CC1140

CC1142

CC1145

CC1141

CC1143

CC1144
+VCCSTG VCCSTG_A22 VCCSA_J23 J27

CC1132
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27
K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30 @ @ @ @
+VCCSTG +VCCST_CPU VCCSA_K30
+VDDQ_CPU_CLK AM23 VCCIO_SENSE 1 TC136 @
VCCIO_SENSE AM22 VSSIO_SENSE 1 TC137 @
120mA VSSIO_SENSE
1
RC1497 2 0_0402_5% RC103 1 2 0_0402_5% H21 VCCSA_VSS_SEN

1U_0402_10V6K
+1.35V_CPU +VCCIO VSSSA_SENSE VCCSA_VSS_SEN 59
1 H20 VCCSA_VCC_SEN
10U_0402_6.3V6-M
1U_0201_6.3V6-K

RC1604 1 2 0_0402_5% VCCSA_SENSE VCCSA_VCC_SEN 59

1@

CC86
1U_0402_10V6K
1 +VCCST_CPU
CC1229

CC1228

1
1 OF 20

CC87
@ SKYLAKE-U_BGA1356
2 REV =1 ?
2 2 @
2 +VCCSA

Reserved for VCCST/VCCSTG/VCCPLL power optimized

+VCCSFR_OC

VCCSA_VCC_SEN RC101 1 2 100_0402_1%

+VCCPLL_CPU
RC104 1 2 0_0402_5%
VCCSA_VSS_SEN RC102 1 2 100_0402_1%
1U_0201_6.3V6-K

1 120mA
1 2 0_0402_5%
CC85

C +VCCST_CPU RC105 C
+1.0VALW +VCCST_CPU

1U_0402_10V6K
0.1U_0402_10V7K
2 1 1
@

CC84
CC1249
RC1605 1 2 0_0402_5%
2 2
Reserved for VCCST/VCCSTG/VCCPLL power optimized

+1.0VALW +VCCST_CPU_R +VCCST_CPU

+1.0VALW +VCCIO_R +VCCIO
need to open UC7 @
JC2 @ 2 6 RC1592 1 2 0_0402_5%
1 2 VIN VOUT
UC8 1 2 EC_VCCST_EN 1 3
EN VBIAS +5VALW
2 6

1U_0402_10V6K
VIN VOUT JUMP_43X79
5 4 1
DC3 GATE GND
VCCIO_EN 1 3 RC1590

CC1246
EN VBIAS +5VALW
1 2 2 1 M5938CTB1U_SOT23-6

1U_0402_10V6K
5 4 1 40.2K_0402_1% 2
DC2 GATE GND 2
RC1591 SDM10U45LP-7_DFN1006-2-2

CC1248
1 2 2 1 M5938CTB1U_SOT23-6 CC1245
40.2K_0402_1% 2 0.01U_0402_25V7K
SDM10U45LP-7_DFN1006-2-2 2 1
CC1247
0.01U_0402_25V7K
1
Reserved for +VCCST_CPU switch

Reserved for +VCCIO switch +1.0VALW +VCCST_CPU

QC19
AO3402_SOT-23-3
B B

+1.0VALW AON7408L_DFN8-5 +VCCIO 1 3

D S
QC11
CC79

10U_0603_6.3V6M

10U_0603_6.3V6M
G

1
1 1
1 @ RC135

CC80
2
5 S1 2 470_0603_5%
D S2 3
10U_0603_6.3V6M
22U_0603_6.3V6-M

@ S3 2 2 @
1 1
10U_0603_6.3V6M

22U_0603_6.3V6-M

2
G
CC72
CC71

1 1

1
CC1250

C1102
4

RC124
2 2 @ 470_0603_5%

1
2 2 D
@ +20VSB VCCST_EN# 2 QC14

2
G 2N7002KW_SOT323-3
+3VALW
+20VSB 1 2 RC142 S

3
100K_0402_5% @

1
+3VALW D

0.01U_0402_25V7K

2
RC1621 2 1 100K_0402_5% VCCIO_EN# 2 QC13

100K_0402_5%
1

6
G 2N7002KW_SOT323-3

CC81

RC1584
D
RC141 1 2 VCCST_EN# 2 QC16A
0.01U_0402_25V7K

1 S 47K_0402_5% G 2N7002KDWH_SOT363-6
3
6

2
CC77

D RC125 @

1
RC128 1 2VCCIO_EN# 2 QC12A 470K_0402_5% S

1
47K_0402_5% G 2N7002KDWH_SOT363-6
2

@ 2
2

3
RC1575 S D
1

47K_0402_5% EC_VCCST_EN 5 QC16B

44 EC_VCCST_EN G 2N7002KDWH_SOT363-6
1

4
+VCCST_CPU switch
3

D
RC1577 1 2 VCCIO_EN 5 QC12B
44 EC_VCCIO_EN G
A 0_0402_5% 2N7002KDWH_SOT363-6 A
DC1 1 2 @
11,44 PM_SLP_S3# S
4

RB751V-40_SOD323-2

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CPU PWR2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCPGPPG

+1.0VALW 0_0603_5% 1 2 RC1503

+VCCAMPHY

+3VALW_PCH RC1622 1 2 0_0402_5%

+1.0VALW 0_0603_5% 1 2 RC1504 +VCCAPLL_1P0

+VCCPGPPG_SDIO RC1623 1 2 0_0402_5%

D +VCCHDA D
@
+3VS RC1585 1 2 0_0402_5% @

+3VALW_PCH RC1586 1 2 0_0402_5%

+1.0VALW RC1620 1 2 0_0402_5% VCCMPHYON_1P0_L1

1U_0402_10V6K
@
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW

1U_0402_10V6K
Near AB19
1

CC141

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K
@ @ @ @ @
22mA 2.574A +VCCPGPPG
+1.0VALW +1.0VALW ? 1 1 1 1 1

CC156

CC164

CC172

CC173

CC174
22U_0603_6.3V6-M

1U_0402_10V6K
1 1 2 SKL_ULT

CC158
UC1O

CC153
CPU POWER 4 OF 4 2 2 2 2 2
+VCCDSW_1P0 2 2 AB19

1U_0402_10V6K

1U_0402_10V6K
@
AB20 VCCPRIM_1P0_AB19 AK15 20mA
1 VCCPRIM_1P0_AB20 VCCPGPPA
Near Y15 1 +3VALW_PCH

CC145
P18 AG15

CC175

1U_0402_10V6K
4mA @
1.5A VCCPRIM_1P0_P18 VCCPGPPB Y16 6mA
+1.0VALW Near AF18 VCCPGPPC 1
AF18 Y15

CC176
@ 8mA
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA 2
VCCPRIM_CORE_AF19 VCCPGPPE +1.8VALW
V20 AF16
47U_0805_4V6-M

1U_0402_10V6K
161mA
1U_0201_6.3V6-K

C C
VCCPRIM_CORE_V20 VCCPGPPF +1.8VALW 2
1 1 PCH Internal VRM V21 AD15 61mA 1
VCCPRIM_CORE_V21 VCCPGPPG
CC148

CC147

CC142
@ +3VALW_PCH
AL1 V19

1U_0402_10V6K
Near N15

.1U_0402_10V6-K
DCPDSW_1P0 VCCPRIM_3P3_V19
2 2 2 1 1
K17 T1

CC143
+1.0VALW CC149
88mA VCCMPHYON_1P0_L1 L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1
+VCCAMPHY VCCMPHYAON_1P0_L1 AA1 6mA
N15 VCCATS_1P8 2 2
1U_0402_10V6K
22U_0603_6.3V6-M

@ N16 VCCMPHYGT_1P0_N15 AK17 1mA

1 1 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
C1096

CC151

N17
P15 VCCMPHYGT_1P0_N17 AK19 1mA
VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC
P16 BB14

1U_0402_10V6K
.1U_0402_10V6-K
Near K15 VCCMPHYGT_1P0_P16 VCCRTC_BB14
2 2
1 1
K15 BB10

CC1242
VCCRTCEXT CC146
L15 VCCAMPHYPLL_1P0_K15 DCPRTC

0.1U_0402_10V7K
VCCAMPHYPLL_1P0_L15 A14 35mA
VCCCLK1 +1.0VALW 2 2
V15
1U_0402_10V6K

22mA 1
+VCCAPLL_1P0 VCCAPLL_1P0 K19 0_0603_5% 1 2 RC1587 +1.0VALW

CC55
1U_0402_10V6K
1 29mA
AB17 VCCCLK2
CC154
22U_0603_6.3V6-M

+1.0VALW VCCPRIM_1P0_AB17 1
Y18 L21

CC56

22U_0603_6.3V6-M
@ 1 24mA
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 2
C1097

+VCCHDA @ 1
2

C1098
AD17 N20
1U_0402_10V6K

1 0.118A 33mA
+3VALW VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4 2
CC165

AD18
2 @ AJ17 VCCDSW_3P3_AD18 L19 4mA
VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5 2
2 68mA AJ19 A10 10mA
VCCHDA VCCCLK6 +1.0VALW

1U_0402_10V6K
+3VALW_PCH
11mA AJ16 AN11 1 TC179 @ PAD 1
VCCSPI GPP_B0/CORE_VID0 AN13 1

CC57
TC180 @ PAD
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
AF21
1U_0402_10V6K

1 VCCSRAM_1P0_AF21 2
CC159

Near AF20 T19

T20 VCCSRAM_1P0_T19
VCCSRAM_1P0_T20
2 75mA AJ21
+3VALW_PCH VCCPRIM_3P3_AJ21
1U_0402_10V6K

1
CC171

AK20
+1.0VALW VCCPRIM_1P0_AK20
N18 0_0603_5% 1 2 RC1588
B 2 VCCAPLLEBB +VCCCLK4 +1.0VALW B
1U_0402_10V6K

1
CC169

22U_0603_6.3V6-M
1 OF 20 @
SKYLAKE-U_BGA1356 1

C1099
2 REV = 1 ?
@
2
33mA
+1.0VALW
Near A18
+VCCCLK5 0_0603_5% 1 2 RC1589
+1.0VALW

22U_0603_6.3V6-M
@ 1

C1100
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (PCH PWR)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1Q ?
SKL_ULT
UC1P ?
SKL_ULT ?
GND 2 OF 3 UC1R
GND 1 OF 3
AT63 BA49 GND 3 OF 3
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53 F8 L18
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57 G10 VSS_F8 VSS_L18 L2
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6 G22 VSS_G10 VSS_L2 L20
D AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62 G43 VSS_G22 VSS_L20 L4 D
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66 G45 VSS_G43 VSS_L4 L8
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71 G48 VSS_G45 VSS_L8 N10
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18 G5 VSS_G48 VSS_N10 N13
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26 G52 VSS_G5 VSS_N13 N19
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30 G55 VSS_G52 VSS_N19 N21
AB18 VSS_AB16 VSS_AM46 AM55 AV69 VSS_AV68 VSS_BB30 BB34 G58 VSS_G55 VSS_N21 N6
AB21 VSS_AB18 VSS_AM55 AM60 AV70 VSS_AV69 VSS_BB34 BB38 G6 VSS_G58 VSS_N6 N65
AB8 VSS_AB21 VSS_AM60 AM61 AV71 VSS_AV70 VSS_BB38 BB43 G60 VSS_G6 VSS_N65 N68
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55 G63 VSS_G60 VSS_N68 P17
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 G66 VSS_G63 VSS_P17 P19
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 H15 VSS_G66 VSS_P19 P20
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 H18 VSS_H15 VSS_P20 P21
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 H71 VSS_H18 VSS_P21 R13
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 J11 VSS_H71 VSS_R13 R6
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 J13 VSS_J11 VSS_R6 T15
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 J25 VSS_J13 VSS_T15 T17
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 J28 VSS_J25 VSS_T17 T18
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 J32 VSS_J28 VSS_T18 T2
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 J35 VSS_J32 VSS_T2 T21
AE68 VSS_AE67 VSS_AN37 AN38 AW34 VSS_AW32 VSS_D11 D14 J38 VSS_J35 VSS_T21 T4
AE69 VSS_AE68 VSS_AN38 AN40 AW36 VSS_AW34 VSS_D14 D18 J42 VSS_J38 VSS_T4 U10
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 J8 VSS_J42 VSS_U10 U63
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 K16 VSS_J8 VSS_U63 U64
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 K18 VSS_K16 VSS_U64 U66
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 K22 VSS_K18 VSS_U66 U67
AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 K61 VSS_K22 VSS_U67 U69
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 K63 VSS_K61 VSS_U69 U70
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 K64 VSS_K63 VSS_U70 V16
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 K65 VSS_K64 VSS_V16 V17
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 K66 VSS_K65 VSS_V17 V18
AG18 VSS_AG17 VSS_AP32 AP35 AW57 VSS_AW55 VSS_D47 D48 K67 VSS_K66 VSS_V18 W13
C AG19 VSS_AG18 VSS_AP35 AP38 AW6 VSS_AW57 VSS_D48 D53 K68 VSS_K67 VSS_W13 W6 C
AG20 VSS_AG19 VSS_AP38 AP42 AW60 VSS_AW6 VSS_D53 D58 K70 VSS_K68 VSS_W6 W9
AG21 VSS_AG20 VSS_AP42 AP58 AW62 VSS_AW60 VSS_D58 D6 K71 VSS_K70 VSS_W9 Y17
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 L11 VSS_K71 VSS_Y17 Y19
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 L16 VSS_L11 VSS_Y19 Y20
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 L17 VSS_L16 VSS_Y20 Y21
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 VSS_L17 VSS_Y21
AH64 VSS_AH63 VSS_AR11 AR15 B10 VSS_AY66 VSS_E11 E15
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 1 OF 20
AJ20 VSS_AJ18 VSS_AR23 AR28 B30 VSS_B22 VSS_E46 E50 SKYLAKE-U_BGA1356
VSS_AJ20 VSS_AR28 VSS_B30 VSS_E50 REV = 1 ?
AJ4 AR35 B34 E53
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56 @
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8 VSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33
AL35 VSS_AL32 VSS_AR8 AT2 BA23 VSS_BA2 VSS_F33 F35
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
AL45 VSS_AL4 VSS_AT23 AT28 BA36 VSS_BA32 VSS_F38 F4
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
B AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41 B
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
1 OF 20

1 OF 20 SKYLAKE-U_BGA1356
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ?
@
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1S

RESERVED SIGNALS-1

CPU_CFG0 E68 BB68 1 TC173 @ PAD

D PAD @ TC142 1 CPU_CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 1 TC174 @ PAD D
PAD @ TC143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
PAD @ TC144 1 XDP_CPU_CFG3 D67 CFG[2] AK13 1 TC175 @ PAD
CFG[3] RSVD_TP_AK13
2

CPU_CFG4 E70 AK12 1 TC176 @ PAD

RC1618 PAD @ TC146 1 CPU_CFG5 C68 CFG[4] RSVD_TP_AK12 +VCCST_CPU
1K_0402_5% PAD @ TC147 1 CPU_CFG6 D68 CFG[5] BB2 1 TC196 @ PAD UC1T SKL_ULT ?
PAD @ TC148 1 CPU_CFG7 C67 CFG[6] RSVD_BB2 BA3 1 TC200 @ PAD
CFG[7] RSVD_BA3

2
PAD @ TC153 1 CPU_CFG8 F71 SPARE
1

RC106 PAD @ TC150 1 CPU_CFG9 G69 CFG[8] +1.8VALW

@ CFG[9]

1
1K_0402_5% PAD @ TC151 1 CPU_CFG10 F70 AU5 AW 69 F6
PAD @ TC152 1 CPU_CFG11 G68 CFG[10] TP5 AT5 AW 68 RSVD_AW 69 RSVD_F6 E3 RC1619
PAD @ TC157 1 CPU_CFG12 H70 CFG[11] TP6 AU56 RSVD_AW 68 RSVD_E3 C11 150_0402_5%
1

PAD @ TC154 1 CPU_CFG13 G71 CFG[12] AW 48 RSVD_AU56 RSVD_C11 B11 @

PAD @ TC155 1 CPU_CFG14 H69 CFG[13] D5 Cannonlake@ C7 RSVD_AW 48 RSVD_B11 A11

2
PAD @ TC156 1 CPU_CFG15 G70 CFG[14] RSVD_D5 D4 RC1582 2 1 0_0402_5% RSVD_U12 U12 RSVD_C7 RSVD_A11 D12
CFG[15] RSVD_D4 B2 1 TC183 @ PAD RC1583 2 1 0_0402_5% RSVD_U11 U11 RSVD_U12 RSVD_D12 C12
PAD @ TC159 1 CPU_CFG16 E63 RSVD_B2 C2 1 TC185 @ PAD Cannonlake@ H11 RSVD_U11 RSVD_C12 F52 RSVD_F52
PAD @ TC158 1 CPU_CFG17 F63 CFG[16] RSVD_C2 RSVD_H11 RSVD_F52
CFG[17] B3 1 TC184 @ PAD
PAD @ TC161 1 CPU_CFG18 E66 RSVD_B3 A3 1 TC181 @ PAD
CFG[18] RSVD_A3 1 OF 20
PAD @ TC160 1 CPU_CFG19 F66
CFG[19] AW 1 1 SKYLAKE-U_BGA1356
TC194 @ PAD REV = 1 ?
C CFG_RCOMP E60 RSVD_AW 1 C
CFG_RCOMP @
E1 1 TC187 @ PAD
PAD @ TC166 1 XDP_ITP_PMODE E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
2

RC162 PAD @ TC201 1 AY2 BA4

PAD @ TC195 1 AY1 RSVD_AY2 RSVD_BA4 BB4 1 TC198 @ PAD
49.9_0402_1% RSVD_AY1 RSVD_BB4
PAD @ TC186 1 D1 A4 1 TC182 @ PAD
1

D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5 1 TC199 @ PAD
K45 RSVD_K46 TP4
RSVD_K45 A69 1 TC188 @ PAD
AL25 RSVD_A69 B69 1 TC193 @ PAD
AL27 RSVD_AL25 RSVD_B69 need to check with Intel
RSVD_AL27 AY3 RSVD_AY3
PAD @ TC189 1 C71 RSVD_AY3
RSVD_C71

2
PAD @ TC191 1 B70 D71 1 TC190 @ PAD
RSVD_B70 RSVD_D71 C70 1 TC192 @ PAD RC107
F60 RSVD_C70
RSVD_F60 0_0402_5%
C54
A52 RSVD_C54 D54

1
B RSVD_A52 RSVD_D54 B
PAD @ TC171 1 BA70 AY4
PAD @ TC172 1 BA68 RSVD_TP_BA70 TP1 BB3 1 TC197 @ PAD
RSVD_TP_BA68 TP2 need to check with Intel
J71 AY71 VSS_AY71
J68 RSVD_J71 VSS_AY71 AR56 1 TC167 @ PAD
RSVD_J68 ZVM#

2
PAD @ TC169 1 F65 AW 71 1 TC177 @ PAD
PAD @ TC170 1 G65 VSS_F65 RSVD_TP_AW 71 AW 70 1 TC178 @ PAD RC108
VSS_G65 RSVD_TP_AW 70
0_0402_5%
F61 AP56 1 TC168 @ PAD
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 2
+VCCST_CPU

1
RSVD_E61 PROC_SELECT# R22 100K_0402_5%
Cannonlake@
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
Default
Pin Name Strap Description Configuration Value

A A
CFG[4] Display Port —1 = eDP Disabled 1
Presence strap —0 = eDP Enabled Title
* Security Classification LC Future Center Secret Data
Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CFG,RESERVED)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

Swap Table
Pin Pin
DDR_SA_VREFDQ 5
DDR3 SO-DIMM A DDRA_DQ[0..63] 5
Number Pin Name Net Name Number Pin Name Net Name
DDRA_DQS[0..7] 5
5 DQ0 DDRA_DQ1 5 DQ32 DDRA_DQ33
+1.35V 7 DQ1 DDRA_DQ5 7 DQ33 DDRA_DQ36
DDRA_DQS#[0..7] 5
+1.35V +1.35V
15 DQ2 DDRA_DQ6 15 DQ34 DDRA_DQ39
DDRA_MA[0..15] 5 17 DQ3 DDRA_DQ7 17 DQ35 DDRA_DQ38
1
RD5 4 DQ4 DDRA_DQ0 4 DQ36 DDRA_DQ37
1.82K_0402_1% 3A@1.5V 6 DQ5 DDRA_DQ4 6 DQ37 DDRA_DQ32
RD6 For RF 16 DQ6 DDRA_DQ2 16 DQ38 DDRA_DQ34
JDDR1 18 DQ7 DDRA_DQ3 18 DQ39 DDRA_DQ35
2

1 2 +VREF_DQ_DIMMA 1 2
D 2_0402_5% 3 VREF_DQ VSS_2 4 DDRA_DQ0 10 DQS#0 DDRA_DQS#0 10 DQS#4 DDRA_DQS#4 D
VSS_1 DQ4
1

12 DQS0 DDRA_DQS0 12 DQS4 DDRA_DQS4

0.022U_0402_16V7-K

1.82K_0402_1%

2.2U_0603_6.3V6K

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRA_DQ1 5 6 DDRA_DQ4
DDRA_DQ5 7 DQ0 DQ5 8
1 1 DQ1 VSS_4 1 1 1
RD7

CD5

CD6

CD7
1 CD4 CD2 9 10 DDRA_DQS#0 21 DQ8 DDRA_DQ12 21 DQ40 DDRA_DQ44
VSS_3 DQS0#
CD3

11 12 DDRA_DQS0 23 DQ9 DDRA_DQ9 23 DQ41 DDRA_DQ41

13 DM0 DQS0 14
33 DQ10 DDRA_DQ14 33 DQ42 DDRA_DQ46
2

CD@2 2 DDRA_DQ6 15 VSS_5 VSS_6 16 DDRA_DQ2 2 2 2

2 DDRA_DQ7 17 DQ2 DQ6 18 DDRA_DQ3 35 DQ11 DDRA_DQ10 35 DQ43 DDRA_DQ47
19 DQ3 DQ7 20 22 DQ12 DDRA_DQ13 22 DQ44 DDRA_DQ45
21 VSS_7 VSS_8 22
DDRA_DQ12
DQ8 DQ12
DDRA_DQ13 24 DQ13 DDRA_DQ8 24 DQ45 DDRA_DQ40
1

DDRA_DQ9 23 24 DDRA_DQ8 34 DQ14 DDRA_DQ11 34 DQ46 DDRA_DQ43

RD8 25 DQ9 DQ13 26
24.9_0402_1% DDRA_DQS#1 27 VSS_9 VSS_10 28
36 DQ15 DDRA_DQ15 36 DQ47 DDRA_DQ42
DDRA_DQS1 29 DQS1# DM1 30 CPU_DRAMRST# 27 DQS#1 DDRA_DQS#1 27 DQS#5 DDRA_DQS#5
31 DQS1 RESET# 32 CPU_DRAMRST# 6,18 29 DQS1 DDRA_DQS1 29 DQS5 DDRA_DQS5
2

VSS_11 VSS_12

.1U_0402_10V6-K
DDRA_DQ14 33 34 DDRA_DQ11
DDRA_DQ10 35 DQ10 DQ14 36 DDRA_DQ15
DQ11 DQ15
39 DQ16 DDRA_DQ20 39 DQ48 DDRA_DQ48
37 38 @ 1 41 DQ17 DDRA_DQ21 41 DQ49 DDRA_DQ53
VSS_13 VSS_14

CD70
DDRA_DQ20 39 40 DDRA_DQ17 Layout Note:
DDRA_DQ21 41 DQ16 DQ20 42 DDRA_DQ16
51 DQ18 DDRA_DQ18 51 DQ50 DDRA_DQ55
43 DQ17 DQ21 44 Place near DIMM (10uF_0603_6.3V)*8 53 DQ19 DDRA_DQ23 53 DQ51 DDRA_DQ54
DDRA_DQS#2 45 VSS_15 VSS_16 46 2 40 DQ20 DDRA_DQ17 40 DQ52 DDRA_DQ52
DDRA_DQS2 47 DQS2# DM2 48 (1U_0402_6.3V)*8 42 DQ21 DDRA_DQ16 42 DQ53 DDRA_DQ49
49 DQS2 VSS_18 50 DDRA_DQ22
VSS_17 DQ22 50 DQ22 DDRA_DQ22 50 DQ54 DDRA_DQ51
DDRA_DQ18 51 52 DDRA_DQ19
DDRA_DQ23 53 DQ18 DQ23 54
52 DQ23 DDRA_DQ19 52 DQ55 DDRA_DQ50
55 DQ19 VSS_20 56 DDRA_DQ24 45 DQS#2 DDRA_DQS#2 45 DQS#6 DDRA_DQS#6
DDRA_DQ29 57 VSS_19 DQ28 58 DDRA_DQ28 +1.35V 47 DQS2 DDRA_DQS2 47 DQS6 DDRA_DQS6
DDRA_DQ25 59 DQ24 DQ29 60
61 DQ25 VSS_22 62 DDRA_DQS#3
VSS_21 DQS3#
57 DQ24 DDRA_DQ29 57 DQ56 DDRA_DQ61

CD8

CD9

CD10

CD11

CD12

CD13

CD14

CD15
63 64 DDRA_DQS3 59 DQ25 DDRA_DQ25 59 DQ57 DDRA_DQ60
65 DM3 DQS3 66
VSS_23 VSS_24 67 DQ26 DDRA_DQ26 67 DQ58 DDRA_DQ59

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
C DDRA_DQ26 67 68 DDRA_DQ31 C
DDRA_DQ30 69 DQ26 DQ30 70 DDRA_DQ27 69 DQ27 DDRA_DQ30 69 DQ59 DDRA_DQ63
DQ27 DQ31 1 1 1 1 1 1 1 1
71 72 56 DQ28 DDRA_DQ24 56 DQ60 DDRA_DQ56
VSS_25 VSS_26
58 DQ29 DDRA_DQ28 58 DQ61 DDRA_DQ57
2 2 2 2 2 2 2 2
68 DQ30 DDRA_DQ31 68 DQ62 DDRA_DQ62
DDRA_CKE0 73 74 DDRA_CKE1
5 DDRA_CKE0
75 CKE0 CKE1 76 DDRA_CKE1 5 70 DQ31 DDRA_DQ27 70 DQ63 DDRA_DQ58
77 VDD_1 VDD_2 78 DDRA_MA15 62 DQS#3 DDRA_DQS#3 62 DQS#7 DDRA_DQS#7
DDRA_BS2# 79 NC_1 A15 80 DDRA_MA14 64 DQS3 DDRA_DQS3 64 DQS7 DDRA_DQS7
5 DDRA_BS2# BA2 A14
81 82 CD@ CD@
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
VDD_5 VDD_6

CD16

CD17

CD18

CD19

CD56

CD57

CD58

CD59
DDRA_MA8 89 90 DDRA_MA6
DDRA_MA5 91 A8 A6 92 DDRA_MA4
A5 A4

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
93 94
DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2
A3 A2 1 1 1 1 1 1 1 1
DDRA_MA1 97 98 DDRA_MA0
99 A1 A0 100
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
5 DDRA_CLK0 CK0 CK1 DDRA_CLK1 5 2 2 2 2 2 2 2 2
DDRA_CLK0# 103 104 DDRA_CLK1#
5 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 5
105 106
DDRA_MA10 107 VDD_11 VDD_12 108 DDRA_BS1#
109 A10/AP BA1 110 DDRA_BS1# 5
5 DDRA_BS0# DDRA_BS0# DDRA_RAS#
111 BA0 RAS# 112 DDRA_RAS# 5
DDRA_WE# 113 VDD_13 VDD_14 114 DDRA_CS0# CD@ CD@ CD@ CD@
5 DDRA_WE# WE# S0# DDRA_CS0# 5
DDRA_CAS# 115 116 DDRA_ODT0
5 DDRA_CAS# CAS# ODT0 DDRA_ODT0 5
117 118
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1
DDRA_CS1# 121 A13 ODT1 122 DDRA_ODT1 5
5 DDRA_CS1# S1# NC_2
123 124
125 VDD_17 VDD_18 126 +VREF_CA_DIMMA RD22 1 @ 2 0_0402_5% +VREF_CA
B 127 TEST VREF_CA 128 B
VSS_27 VSS_28
.1U_0402_10V6-K

DDRA_DQ33 129 130 DDRA_DQ37

DDRA_DQ36 131 DQ32 DQ36 132 DDRA_DQ32
DQ33 DQ37 1 1
CD22

133 134 CD23

DDRA_DQS#4 135 VSS_29 VSS_30 136 2.2U_0603_6.3V6K
DDRA_DQS4 137 DQS4# DM4 138
139 DQS4 VSS_32 140 DDRA_DQ34 2 2
DDRA_DQ39 141 VSS_31 DQ38 142 DDRA_DQ35
DDRA_DQ38 143 DQ34 DQ39 144
145 DQ35 VSS_34 146 DDRA_DQ45
DDRA_DQ44 147 VSS_33 DQ44 148 DDRA_DQ40
DQ40 DQ45 Layout Note: (10U_0603_6.3V)*2
DDRA_DQ41 149 150
151 DQ41 VSS_35 152 DDRA_DQS#5 Place near DIMM
153 VSS_36 DQS5# 154 DDRA_DQS5 (.1U_0402_10V)*4
155 DM5 DQS5 156
DDRA_DQ46 157 VSS_37 VSS_38 158 DDRA_DQ43 +1.35V
DDRA_DQ47 159 DQ42 DQ46 160 DDRA_DQ42
161 DQ43 DQ47 162
Note:
VSS_39 VSS_40 VREF trace width:20 mils at least

1
DDRA_DQ48 163 164 DDRA_DQ52 +0.675VS
DDRA_DQ53 165 DQ48 DQ52 166 DDRA_DQ49 RD9 Spacing:20mils to other signal/planes
167 DQ49 DQ53 168
VSS_41 VSS_42 Trace width:20 mils 1.82K_0402_1% Place near DIMM scoket
CD24

CD25

CD26

CD27

CD64

CD65
DDRA_DQS#6 169 170
DDRA_DQS6 171 DQS6# DM6 172 Space:20mils

2
DQS6 VSS_44
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
173 174 DDRA_DQ51
DDRA_DQ55 175 VSS_43 DQ54 176 DDRA_DQ50 +VREF_CA RD10 1 2 2_0402_5%
DQ50 DQ55 1 1 1 1 1 1 18 +VREF_CA DDR_SM_VREFCA 5
DDRA_DQ54 177 178 1
179 DQ51 VSS_46 180 DDRA_DQ56 CD21
VSS_45 DQ60

1
DDRA_DQ61 181 182 DDRA_DQ57 0.022U_0402_16V7-K
DDRA_DQ60 183 DQ56 DQ61 184 2 2 2 2 2 2 RD11
185 DQ57 VSS_48 186 DDRA_DQS#7 1.82K_0402_1% 2
VSS_47 DQS7#

1
187 188 DDRA_DQS7
189 DM7 DQS7 190 CD@ CD@ CD@

2
A DDRA_DQ59 191 VSS_49 VSS_50 192 DDRA_DQ62 RD12 A
DDRA_DQ63 193 DQ58 DQ62 194 DDRA_DQ58 24.9_0402_1%
195 DQ59 DQ63 196

2
1 @ 2 0_0402_5%197 VSS_51 VSS_52 198
RD13 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS 201 VDDSPD SDA 202 SMB_CLK_S3 SMB_DATA_S3 7,18,40
203 SA1 SCL 204 SMB_CLK_S3 7,18,40
1 1 VTT_1 VTT_2 +0.675VS
1

@ Security Classification LC Future Center Secret Data Title

CD28 CD29 205
GND1 GND2
206 1 0.65A@0.75V
2.2U_0603_6.3V6K .1U_0402_10V6-K 0_0402_5% 207 208 CD68
@ 2 2 RD14 BOSS1 BOSS2 33P_0402_50V8J
Issued Date 2014/12/11 Deciphered Date 2015/12/11 DDRIII SO-DIMM A
2

2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCN_DAN06-K4406-0103 Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
ME@ For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

DDR_SB_VREFDQ 5

+1.35V
DDR3 SO-DIMM B Swap Table
Pin
+1.35V +1.35V Pin Name Net Name
Number

1
DDRB_DQ[0..63] 6
RD15 5 DQ0 DDRB_DQ12
1.82K_0402_1% 3A@1.5V 7 DQ1 DDRB_DQ8
DDRB_DQS[0..7] 6
RD16 For RF 15 DQ2 DDRB_DQ10
JDDR2

2
1 2 +VREF_DQ_DIMMB 1 2 DDRB_DQS#[0..7] 6 17 DQ3 DDRB_DQ11
2_0402_5% 3 VREF_DQ VSS1 4 DDRB_DQ9 4 DQ4 DDRB_DQ9
VSS2 DQ4 DDRB_MA[0..15] 6

1.82K_0402_1%

CD30

2.2U_0603_6.3V6K

CD31

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRB_DQ12 5 6 DDRB_DQ13 6 DQ5 DDRB_DQ13
DQ0 DQ5
1
0.022U_0402_16V7-K

1 1 DDRB_DQ8 7 8 1 1 1 16 DQ6 DDRB_DQ14

DQ1 VSS3

RD17

CD33

CD34

CD35
D 9 10 DDRB_DQS#1 D
11 VSS4 DQS#0 12 DDRB_DQS1
18 DQ7 DDRB_DQ15
1 DM0 DQS0 10 DQS#0 DDRB_DQS#1
CD32

13 14
2 2 DDRB_DQ10 15 VSS5 VSS6 16 DDRB_DQ14 2 2 2 12 DQS0 DDRB_DQS1
2

DDRB_DQ11 17 DQ2 DQ6 18 DDRB_DQ15

2 19 DQ3 DQ7 20
VSS7 VSS8
21 DQ8 DDRB_DQ4
CD@ DDRB_DQ4 21 22 DDRB_DQ1 23 DQ9 DDRB_DQ5
DDRB_DQ5 23 DQ8 DQ12 24 DDRB_DQ0
DQ9 DQ13 33 DQ10 DDRB_DQ7
1

25 26
RD18 DDRB_DQS#0 27 VSS9 VSS10 28 35 DQ11 DDRB_DQ3
24.9_0402_1% DDRB_DQS0 29 DQS#1 DM1 30 CPU_DRAMRST# 22 DQ12 DDRB_DQ1
31 DQS1 RESET# 32 CPU_DRAMRST# 6,17
VSS11 VSS12
24 DQ13 DDRB_DQ0

.1U_0402_10V6-K
DDRB_DQ7 33 34 DDRB_DQ6 34 DQ14 DDRB_DQ6
2

DDRB_DQ3 35 DQ10 DQ14 36 DDRB_DQ2

37 DQ11 DQ15 38 @ 1 Layout Note: (10uF_0603_6.3V)*8 36 DQ15 DDRB_DQ2
VSS13 VSS14 27 DQS#1 DDRB_DQS#0

CD71
DDRB_DQ16 39 40 DDRB_DQ20
DDRB_DQ18 41 DQ16 DQ20 42 DDRB_DQ21 Place near DIMM (1U_0402_6.3V)*8 29 DQS1 DDRB_DQS0
43 DQ17 DQ21 44
DDRB_DQS#2 45 VSS15 VSS16 46 2
DQS#2 DM2
39 DQ16 DDRB_DQ16
DDRB_DQS2 47 48 41 DQ17 DDRB_DQ18
49 DQS2 VSS17 50 DDRB_DQ17
DDRB_DQ19 51 VSS18 DQ22 52 DDRB_DQ22
51 DQ18 DDRB_DQ19
DDRB_DQ23 53 DQ18 DQ23 54 53 DQ19 DDRB_DQ23
55 DQ19 VSS19 56 DDRB_DQ27 +1.35V 40 DQ20 DDRB_DQ20
57 VSS20 DQ28 58
DDRB_DQ29
DQ24 DQ29
DDRB_DQ28 42 DQ21 DDRB_DQ21
DDRB_DQ24 59 60 50 DQ22 DDRB_DQ17
DQ25 VSS21

CD36

CD37

CD38

CD39

CD40

CD41

CD42

CD43
61 62 DDRB_DQS#3
63 VSS22 DQS#3 64 DDRB_DQS3
52 DQ23 DDRB_DQ22
DM3 DQS3 45 DQS#2 DDRB_DQS#2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
65 66
DDRB_DQ31 67 VSS23 VSS24 68 DDRB_DQ25 47 DQS2 DDRB_DQS2
DQ26 DQ30 1 1 1 1 1 1 1 1
DDRB_DQ30 69 70 DDRB_DQ26
71 DQ27 DQ31 72
VSS25 VSS26
57 DQ24 DDRB_DQ29
C C
2 2 2 2 2 2 2 2 59 DQ25 DDRB_DQ24
67 DQ26 DDRB_DQ31
DDRB_CKE0 73 74 DDRB_CKE1 69 DQ27 DDRB_DQ30
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6
75 76 56 DQ28 DDRB_DQ27
77 VDD1 VDD2 78 DDRB_MA15
NC1 A15
CD@ CD@ 58 DQ29 DDRB_DQ28
DDRB_BS2# 79 80 DDRB_MA14 68 DQ30 DDRB_DQ25
6 DDRB_BS2# BA2 A14
81 82
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
70 DQ31 DDRB_DQ26
A12/BC# A11 62 DQS#3 DDRB_DQS#3

CD44

CD45

CD46

CD47

CD60

CD61

CD62

CD63
DDRB_MA9 85 86 DDRB_MA7
87 A9 A7 88 64 DQS3 DDRB_DQS3
VDD5 VDD6

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDRB_MA8 89 90 DDRB_MA6
DDRB_MA5 91 A8 A6 92 DDRB_MA4
A5 A4 1 1 1 1 1 1 1 1 129 DQ32 DDRB_DQ36
93 94 131 DQ33 DDRB_DQ37
DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0
141 DQ34 DDRB_DQ38
99 A1 A0 100 2 2 2 2 2 2 2 2 143 DQ35 DDRB_DQ39
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1 130 DQ36 DDRB_DQ33
6 DDRB_CLK0 CK0 CK1 DDRB_CLK1 6
DDRB_CLK0# 103 104 DDRB_CLK1# CD@ CD@ CD@ CD@ 132 DQ37 DDRB_DQ32
6 DDRB_CLK0# CK0# CK1# DDRB_CLK1# 6
105 106 140 DQ38 DDRB_DQ35
DDRB_MA10 107 VDD11 VDD12 108 DDRB_BS1#
DDRB_BS0# 109 A10/AP BA1 110 DDRB_RAS#
DDRB_BS1# 6 142 DQ39 DDRB_DQ34
6 DDRB_BS0# BA0 RAS# DDRB_RAS# 6 135 DQS#4 DDRB_DQS#4
111 112
DDRB_WE# 113 VDD13 VDD14 114 DDRB_CS0# 137 DQS4 DDRB_DQS4
6 DDRB_WE# WE# S0# DDRB_CS0# 6
DDRB_CAS# 115 116 DDRB_ODT0
6 DDRB_CAS# CAS# ODT0 DDRB_ODT0 6
117 118 147 DQ40 DDRB_DQ44
DDRB_MA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 6 149 DQ41 DDRB_DQ45
DDRB_CS1# 121 122
6 DDRB_CS1#
123 S1# NC2 124
157 DQ42 DDRB_DQ47
125 VDD17 VDD18 126 +VREF_CA_DIMMB RD19 1 @ 2 0_0402_5% 159 DQ43 DDRB_DQ46
127 NCTEST VREF_CA 128 +VREF_CA 17 146 DQ44 DDRB_DQ41
VSS27 VSS28
.1U_0402_10V6-K
DDRB_DQ36 129 130 DDRB_DQ33 148 DQ45 DDRB_DQ40
B DDRB_DQ37 131 DQ32 DQ36 132 DDRB_DQ32 B
DQ33 DQ37 1 1 158 DQ46 DDRB_DQ42
133 134 CD48 CD49
DDRB_DQS#4 135 VSS29 VSS30 136 2.2U_0603_6.3V6K
160 DQ47 DDRB_DQ43
DDRB_DQS4 137 DQS#4 DM4 138 152 DQS#5 DDRB_DQS#5
139 DQS4 VSS31 140 DDRB_DQ35 2 2 154 DQS5 DDRB_DQS5
DDRB_DQ38 141 VSS32 DQ38 142 DDRB_DQ34
DDRB_DQ39 143 DQ34 DQ39 144
DQ35 VSS33
163 DQ48 DDRB_DQ52
145 146 DDRB_DQ41 165 DQ49 DDRB_DQ53
DDRB_DQ44 147 VSS34 DQ44 148 DDRB_DQ40
DQ40 DQ45 Layout Note: (10U_0603_6.3V)*2 175 DQ50 DDRB_DQ54
DDRB_DQ45 149 150
151 DQ41 VSS35 152 DDRB_DQS#5 Place near DIMM 177 DQ51 DDRB_DQ51
153 VSS36 DQS#5 154 DDRB_DQS5 (.1U_0402_10V)*4 164 DQ52 DDRB_DQ49
155 DM5 DQS5 156 166 DQ53 DDRB_DQ48
DDRB_DQ47 157 VSS37 VSS38 158 DDRB_DQ42
DQ42 DQ46 174 DQ54 DDRB_DQ50
DDRB_DQ46 159 160 DDRB_DQ43
161 DQ43 DQ47 162
176 DQ55 DDRB_DQ55
DDRB_DQ52 163 VSS39 VSS40 164 DDRB_DQ49 +0.675VS 169 DQS#6 DDRB_DQS#6
DDRB_DQ53 165 DQ48 DQ52 166 DDRB_DQ48 171 DQS6 DDRB_DQS6
167 DQ49 DQ53 168
VSS41 VSS42
CD50

CD51

CD52

CD53

CD66

CD67
DDRB_DQS#6 169 170 181 DQ56 DDRB_DQ57
DDRB_DQS6 171 DQS#6 DM6 172
DQS6 VSS43 183 DQ57 DDRB_DQ60
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
173 174 DDRB_DQ50
DDRB_DQ54 175 VSS44 DQ54 176 DDRB_DQ55
191 DQ58 DDRB_DQ58
DQ50 DQ55 1 1 1 1 1 1 193 DQ59 DDRB_DQ59
DDRB_DQ51 177 178
179 DQ51 VSS45 180 DDRB_DQ56 180 DQ60 DDRB_DQ56
DDRB_DQ57 181 VSS46 DQ60 182 DDRB_DQ61 182 DQ61 DDRB_DQ61
DDRB_DQ60 183 DQ56 DQ61 184 2 2 2 2 2 2
DQ57 VSS47 192 DQ62 DDRB_DQ62
185 186 DDRB_DQS#7 CD@
187 VSS48 DQS#7 188 DDRB_DQS7
194 DQ63 DDRB_DQ63
189 DM7 DQS7 190 CD@ CD@ 186 DQS#7 DDRB_DQS#7
DDRB_DQ58 191 VSS49 VSS50 192 DDRB_DQ62 188 DQS7 DDRB_DQS7
DDRB_DQ59 193 DQ58 DQ62 194 DDRB_DQ63
A 195 DQ59 DQ63 196 A
RD20 1 2 @ 197 VSS51 VSS52 198
0_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
1 2 201 VDDSPD SDA 202 SMB_CLK_S3 SMB_DATA_S3 7,17,40
+3VS 203 SA1 SCL 204 SMB_CLK_S3 7,17,40
RD21 10K_0402_5% +0.675VS
VTT1 VTT2
1 1 0.65A@0.75V
205 206 1
CD54 CD55 G1 G2 CD69
Security Classification LC Future Center Secret Data Title
2.2U_0603_6.3V6K .1U_0402_10V6-K LCN_DAN06-K4406-0102 33P_0402_50V8J
@ 2 2
ME@ 2 Issued Date 2014/12/11 Deciphered Date 2015/12/11 DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
Power-Up/Down Sequence
MLPS Bit Strap Name Description RECOMMENDED
"Topaz" has the following requirements with regards to power-supply sequencing to SETTINGS
avoid damaging the ASIC: PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
PS_0[3] ROM_CONFIG[2] X
All the ASIC supplies must reach their respective nominal voltages within 20 ms 100 = 256MB

D of the start of the ramp-up sequence, though a shorter ramp-up duration is PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1 D

preferred. The maximum slew rate on all rails is 50 mV/µs. AUD_PORT_CONN_
It is recommended that the 3.3-V rail ramp up first. PS_0[5] PINSTRAP[0]
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 µs
before VDDC, VDDCI, and VMEMIO start to ramp up. PS_1[1] STRAP_BIF_GEN3_EN_A
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example PS_1[2] STRAP_BIF_CLK_PM_EN
The LSB (least significant bit) of the strap option that
indicates the number of audio-capable display outputs. 1
1 = PCIe GEN3 is supported.
0 = PCIe GEN3 is not supported. 1= support X
0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled 0

AMD PowerXpress idle state), all the power rails are removed from the dGPU. PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/µs). STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
For power down, reversing the ramp-up sequence is recommended. PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1

0 = Tx deemphasis disabled.
PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X

PS_2[1] N/A Reserved. 0

PS_2[2] N/A Reserved. 0

0 ~ 20ms
0 = Disable the external BIOS ROM device.
PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X

VDDR3(+3VGS) 0 = VGA controller capacity enabled.

1 = The device will not be recognized as the system’s VGA controller.
0 ~ 20ms PS_2[4] STRAP_BIF_VGA_DIS 1

PS_2[5] N/A Reserved 1

C
VDD_CT(+1.8VGS) Board configuration related strapping, such as for memory ID
C
PS_3[1] BOARD_CONFIG[0] 000 = Hynix 256M*16 001 = Hynix 128M*16 X
PS_3[2] BOARD_CONFIG[1] 100 = Samsung 256M*16 011 = Samsung 128M*16
PS_3[3] BOARD_CONFIG[2] 010 = Micron 256M*16 111 = Micron 128M*16

PCIE_VDDC(+0.95VGS) Determines the maximum number of digital display audio endpoints

that will be presented to the OS and user.(Combine with PS_0[5])
10us min. 111 = No usable endpoints.
AUD_PORT_CONN_ 110 = One usable endpoint.
PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
VDDR1(+1.35VGS) PS_3[5] AUD_PORT_CONN_
100 = Three usable endpoints.
011 = Four usable endpoints.
11
PINSTRAP[2] 010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.
VDDC/VDDCI(+VGA_CORE) 100ms min.

100us min. VRAM ID config

PERSTb(GPU_RST#)
VRAM ID PU resistor PD resistor
Memory Type
REFCLK(CLK_PCIE_VGA) PS_3[3:1] RV33 RV36

Hynix
100 4.53K 4.99K
H5TC2G63FFR-11C
B B
128Mx16 Micron
111 4.75K NC
MT41J128M16JT-093G

Samsung
110 3.4K 10K
K4W2G1646Q-BC1A

Hynix
000 NC 4.75K
H5TC4G63CFR-N0C (New)

Micron
256Mx16 010 4.53K 2K
MT41J256M16HA-093G

Samsung
001 8.45K 2K
K4W4G1646E-BC1A (New no AVL)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0]
9 PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0] 9
UV1A
PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0]
9 PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0] 9

PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0

0.22U_0402_10V6K PX@ 1 2 CV1 PCIE_CRX_GTX_P0
PCIE_CTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0
0.22U_0402_10V6K PX@ 1 2 CV2 PCIE_CRX_GTX_N0
PCIE_RX0N PCIE_TX0N

D PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1

0.22U_0402_10V6K PX@ 1 2 CV3 PCIE_CRX_GTX_P1 D
PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1
0.22U_0402_10V6K PX@ 1 2 CV4 PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N

PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2

0.22U_0402_10V6K PX@ 1 2 CV5 PCIE_CRX_GTX_P2
PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2
0.22U_0402_10V6K PX@ 1 2 CV6 PCIE_CRX_GTX_N2
PCIE_RX2N PCIE_TX2N

PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3

0.22U_0402_10V6K PX@ 1 2 CV7 PCIE_CRX_GTX_P3
PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3
0.22U_0402_10V6K PX@ 1 2 CV8 PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N

V30 W24
C U31 NC#V30 NC#W24 W23 C
NC#U31 NC#W23

U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23

N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23

L29 M27
K30 NC#L29 NC#M27 N26
B NC#K30 NC#N26 B

CLOCK
CLK_PCIE_GPU AK30
10 CLK_PCIE_GPU PCIE_REFCLKP
CLK_PCIE_GPU# AK32
10 CLK_PCIE_GPU# PCIE_REFCLKN
+0.95VGS
CALIBRATION
Y22 RV3 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX

GPU_RST# AL27
21 GPU_RST# PERSTB
1

JET-S3-LE_FCBGA631
RV6 @ RV27 1 @ 2 0_0402_5%
100K_0402_5%
PX@
2

RV7 1 @ 2 0_0402_5% DV3 PX@

GPU_RST# 2
1 GPU_PW ROK
GPU_PW ROK 58
+3VGS VGA_PW RGD 3
8,58 VGA_PW RGD
BAT54AW _SOT323-3
5

A UV2 A
VCC

1
8 PXS_RST# IN1 4 GPU_RST#
2 OUT
GND

11,32,37,40,44 PLT_RST# IN2

Security Classification LC Future Center Secret Data Title

MC74VHC1G08DFT2G_SC70-5
3

PX@ Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_PCIE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

+3VGS UV1B RECOMMENDED SETTINGS

+1.8VGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
+3VGS 1 = INSTALL 10K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
.1U_0402_10V6-K .1U_0402_10V6-K AF2 GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
NC#AF2

2
1 2 CV222 1 2 CV223 AF4
RV235 RV236 @ @ NC#AF4
10K_0402_5% 10K_0402_5% N9 AG3 MLPS Bit Strap Name Description RECOMMENDED
@ UV11 @ L9 DBG_DATA16 NC#AG3 AG5 SETTINGS
@ DBG_DATA15 NC#AG5
AE9 DPA PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,

1
1 8 Y11 DBG_DATA14 AH3 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
VCC(A) VCC(B) AE8 DBG_DATA13 NC#AH3 AH1 PS_0[3] ROM_CONFIG[2] X
GPU_VID3 RV121 1 @ 2 2 7 RV239 1 @ 2 GPU_SVD AD9 DBG_DATA12 NC#AH1 100 = 256MB
33_0402_5% 1A 1B 33_0402_5% AC10 DBG_DATA11 AK3
GPU_VID4 RV122 1 @ 2 3 6 RV240 1 @ 2 GPU_SVC AD7 DBG_DATA10 NC#AK3 AK1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
33_0402_5% 2A 2B 33_0402_5% AC8 DBG_DATA9 NC#AK1
DVO
5 4 AC7 DBG_DATA8 AK5 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
DIR GND DBG_DATA7 NC#AK5
2

2
AB9 AM3 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
RV237 RV238 AB8 DBG_DATA6 NC#AM3
10K_0402_5% 74AVCH2T45GD_XSON8_3X2 AB7 DBG_DATA5 AK6 1 = PCIe GEN3 is supported.
10K_0402_5% DBG_DATA4 NC#AK6
@ @ AB4 AM5 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 1= GEN3 is supported X
AB2 DBG_DATA3 NC#AM5
DPB
1

Y8 DBG_DATA2 AJ7 0 = The CLKREQB power management capability is disabled

D
RV241 2 @ 1 Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
D
+3VGS DBG_DATA0 NC#AH6
10K_0402_5%
AK8 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0

10U_0603_6.3V6M
NC#AK8
.1U_0402_10V6-K
2 1 AL7
NC#AL7 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
CV236 CV31 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
@ @ W6
1 2 V6 NC#W6 0 = Tx deemphasis disabled.
NC#V6 V4 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
AC6 NC#V4 U5
AC5 NC#AC6 NC#U5 PS_2[1] N/A Reserved. 0
NC#AC5 W3 VGA_VSSI_SEN 1 TV10 PAD @
Reserve NC#W3
AA5 V2 PS_2[2] N/A Reserved. 0
AA6 NC#AA5 NC#V2
DPC
+3VGS +1.8VGS NC#AA6 Y4 0 = Disable the external BIOS ROM device.
NC#Y4 W5 PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X
NC#W5
10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 RV93 1 2 TOPAZ@ BP_0 U1 AA3 PLL_ANALOG_OUT RV94 1 @ 2 0 = VGA controller capacity enabled.
4.7K_0402_5% TV11 @ 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2 16.2K_0402_1% PS_2[4] STRAP_BIF_VGA_DIS 1 = The device will not be recognized as the system’s VGA controller. 1
RV95 1 2 TOPAZ@ PAD BP_1 U3 NC#W1 NC#Y2
4.7K_0402_5% Y6 NC#U3 J8 PS_2[5] N/A Reserved 1
NC#Y6 NC#J8 Reserve for Topaz
10K_0402_5% 1 @ 2 RV9 GPU_GPIO0 TV12 @ 1 PLL_ANALOG_IN AA1
10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 PAD NC#AA1 Board configuration related strapping, such as for memory ID
10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 PS_3[1] BOARD_CONFIG[0] 000 = Hynix 256M*16 001 = Hynix 128M*16 X
10K_0402_5% 1 @ 2 RV14 GPU_GPIO10 PS_3[2] BOARD_CONFIG[1] 100 = Samsung 256M*16 011 = Samsung 128M*16
10K_0402_5% 1 @ 2 RV15 GPU_GPIO11 PS_3[3] BOARD_CONFIG[2] 010 = Micron 256M*16 111 = Micron 128M*16
10K_0402_5% 1 @ 2 RV96 GPU_GPIO12 I2C
10K_0402_5% 1 @ 2 RV17 GPU_GPIO13 Determines the maximum number of digital display audio endpoints
10K_0402_5% 1 @ 2 RV18 GPU_GPIO22 R1 that will be presented to the OS and user.(Combine with PS_0[5])
10K_0402_5% 1 @ 2 RV97 GPU_VID1 R3 SCL 111 = No usable endpoints.
10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 SDA TOPAZ@ AUD_PORT_CONN_ 110 = One usable endpoint.
10K_0402_5% 1 @ 2 RV99 GPU_VID5 AM26 DIECRACKMON RV117 1 2 PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
10K_0402_5% 1 @ 2 RV106 GPU_VID2 NC_R AK26 10K_0402_5% 100 = Three usable endpoints. 11
GPU_GPIO0 U6 GENERAL PURPOSE I/O NC_AVSSN#AK26 PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
+VGA_CORE_GPIO1 U10 GPIO_0 AL25 PINSTRAP[2] 010 = Five usable endpoints.
Reserve NC_GPIO_1 NC_G 001 = Six usable endpoints.
+VGA_CORE_GPIO2 T10 AJ25
U8 NC_GPIO_2 NC_AVSSN#AJ25 000 = All endpoints are usable.
VGA_SMB_DATA
RB751V-40_SOD323-2 VGA_SMB_CLK U7 SMBDATA AH24
DV1 1 2 @ GPU_GPIO5 T9 SMBCLK NC_B AG25
44 VGA_AC_DET GPIO_5_AC_BATT NC_AVSSN#AG25
GPU_VID5 T8
T7 GPIO_6 DAC1 AH26
GPU_GPIO8 P10 NC_GPIO_7 NC_HSYNC AJ27 4.7K_0402_5% 1 TOPAZ@ 2 RV20 +3VGS +VDDIO_GPU +1.8VGS
+VGA_CORE GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC
GPU_GPIO10 P2 GPIO_9_ROMSI
GPIO_10_ROMSCK SVC SVD Output Voltage (V)
RV100 1 2 0_0402_5% +VGA_CORE_GPIO1 GPU_GPIO11 N6 AD22 Pull down for none OBFF design RV234 1 EXO@ 2 RV203 1 TOPAZ@ 2
TOPAZ@ @ PAD TV3 1 GPU_GPIO12 N5 NC_GPIO_11 NC_RSET 0 0 1.1 0_0402_5% 0_0402_5%
RV101 1 2 0_0402_5% +VGA_CORE_GPIO2 GPU_GPIO13 N3 NC_GPIO_12 AG24
TOPAZ@ +VGA_CORE_GPIO14 Y9 NC_GPIO_13 NC_AVDD AE22 0 1 1.0
RV102 1 2 0_0402_5% +VGA_CORE_GPIO14 GPU_SVD 0_0402_5% 1 EXO@ 2 RV103 GPU_VID3 N1 NC_GPIO_14
GPIO_15_PWRCNTL_0
NC_AVSSQ *
C TOPAZ@ 10K_0402_5% 1 @ 2 RV22 GPU_GPIO16 M4 AE23 1 0 0.9 C
GPIO_16 NC_VDD1DI

2
RV104 1 2 0_0402_5% +VGA_CORE_GPIO18 0_0402_5% 1 PX@ 2 RV247 GPU_HOT#_R R6 AD23
58 GPU_HOT# GPIO_17_THERMAL_INT NC_VSS1DI
TOPAZ@ +VGA_CORE_GPIO18 W10 1 1 0.8 RV205 RV204 RV208
10K_0402_5% 1 PX@ 2 RV23 GPIO_19_CTF M2 NC_GPIO_18 10K_0402_5% 10K_0402_5% 10K_0402_5%
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
GPU_SVC 0_0402_5% 1 EXO@ 2 RV105 GPU_VID4 P8 AM12 CEC_1 1 @ TV5 PX@ @ @
GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1 PAD

1
GPU_GPIO22 N8 GPIO_21 GPU_SVD
GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R RV107 1TOPAZ@ 2 0_0402_5% GPU_SVC
GPIO_29 NC_SVI2#AK12 GPU_SVD 58
GPU_VID1 AM10 AL11 GPU_SVT_R RV108 1TOPAZ@ 2 0_0402_5% GPU_SVT
1 2 RV124 N7 GPIO_30 NC_SVI2#AL11 AJ11 GPU_SVT 58
0_0402_5% @ GPU_CLKREQ#_R GPU_SVC_R RV109 1TOPAZ@ 2 0_0402_5%
10 GPU_CLKREQ# CLKREQB NC_SVI2#AJ11 GPU_SVC 58

2
2

2
JTAG_TRSTB L6 RV209
+3VGS JTAG_TDI L5 JTAG_TRSTB RV206 RV207 10K_0402_5%
JTAG_TCK L3 JTAG_TDI 10K_0402_5% 10K_0402_5% @
PAD JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1 TV1 PAD @ @ PX@

1
10K_0402_5% 1 @ 2 RV37 JTAG_TRSTB TV7 @ 1JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13 GENLK_VSYNC 1 TV2 PAD @

1
10K_0402_5% 1 @ 2 RV38 JTAG_TDI RV34 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
10K_0402_5% 1 @ 2 RV39 JTAG_TMS 1K_0402_5% AF24 TESTEN
NC#AF24 AG13
10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12
0_0402_5% 1 2 RV110 AB13 NC_SWAPLOCKB
+VGA_CORE NC_GENERICA
TOPAZ@ W8 +1.8VGS +1.8VGS
0_0402_5% 1 2 RV111 W9 NC_GENERICB
TOPAZ@ W7 NC_GENERICC AC19 PS_0
NC_GENERICD PS_0

1
GCLK@ 0_0402_5% 1 2 RV112 AD10
RV212 1 2 0_0402_5% XTALIN TOPAZ@ AJ9 NC_GENERICE_HPD4 AD19 PS_1 RV25 RV26
31 27M_CLK NC#AJ9 PS_1
AL9 8.45K_0402_1% 8.45K_0402_1%
DBG_CNTL0 AE17 PS_2 PX@ PX@
AC14 PS_2

2
PAD TV6 @ 1 PX_EN AB16 NC_HPD1 AE20 PS_3 PS_0 PS_1
PX_EN PS_3

1
4.7K_0402_5% 1 @ 2 RV31 1 1
PX@ 2 1 CV25 XTALIN AE19 RV28 CV15 RV29 CV16
AC16 TS_A 2K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
9P_0402_50V8-B NC_DBG_VREFG PX@ @ PX@ @
If need stuff RV31. use 0ohm resistor. 2 2

2
DDC/AUX
2

AE6
27MHZ_10PF_X1E000021015300

YV1 PLL/CLOCK NC_DDC1CLK AE5

GND1

OSC1

PX@ NC_DDC1DATA +1.8VGS +1.8VGS

1

AD2 +VGA_CORE
NC_AUX1P
1
RV46 AD4
NC_AUX1N

1
1M_0402_5% RV19
GND2
OSC2

PX@ AC11 RV113 1 TOPAZ@ 2 0_0402_5% 100_0402_1% RV32 RV33

NC_DDC2CLK AC13 RV114 1 2 0_0402_5% @ 10K_0402_5% 8.45K_0402_1%
2

NC_DDC2DATA TOPAZ@ @ @
2

XTALIN AM28 AD13

3

2
XTALOUT AK28 XTALIN NC_AUX2P AD11 PS_2 PS_3
XTALOUT NC_AUX2N
B B

1
10K_0402_5% 1 PX@ 2 RV45 XO_IN AC22 AD20 VGA_VSS_SEN_R RV125 1 TOPAZ@ 2 0_0402_5% 1 1
XO_IN NC#AD20 VGA_VSS_SEN 58
10K_0402_5% 1 PX@ 2 RV50 XO_IN2 AB22 AC20 VGA_CORE_SEN_R RV126 1 2 0_0402_5% RV35 CV18 RV36 CV19
XO_IN2 NC#AC20 VGA_CORE_SEN 58
TOPAZ@ 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
PX@ 2 1 CV32 XTALOUT AE16 PX@ @ @ @
NC#AE16 AD16 2 2

2
9P_0402_50V8-B NC#AD16
1

SEYMOUR/FutureASIC AC1
PAD TV13 @ 1 GPU_DPLUS T4 NC_DDCVGACLK AC3 RV16
PAD TV14 @ 1 GPU_DMINUS T2 DPLUS THERMAL NC_DDCVGADATA 100_0402_1%
DMINUS @
2

+3VS RV41 1 @ 2 GPIO_28_FDO R5

10K_0402_5% LV3 1 2 PX@ +TSVDD AD17 GPIO28_FDO
+1.8VGS TSVDD Capacitor Value (nF) Bits [5:4] R_pu (Ω) R_pd (Ω) Bits [3:1]
0_0402_5% AC17
TSVSS +VGA_CORE 680 00 NC 4750 000
CV21
1U_0402_6.3V6K
2

(1.8V@13mA TSVDD) 1
RV42 82 01 8450 2000 001
10K_0402_5% JET-S3-LE_FCBGA631
EXO@ @ For Topaz, RV16/RV19 stuff 100ohm 10 10 4530 2000 010
2
PX@

for Jet, RV16/RV19 stuff 0hm.

1

NC 11 6980 4990 011

4530 4990 100

For Jet: Connect GPIO_28 to 10K pull
down to enable MLPS. 3240 5620 101
For Topaz: default is MLPS mode
3400 10000 110
+3VGS
4750 NC 111

Note: 0402 1% resistors are required.

1

RV127 RV21 1 @ 2 0_0402_5%

WRST# 44
20K_0402_5%
@
2
3

E
QV12 2
B Internal VGA Thermal Sensor
MMBT3906_SOT23-3 +3VGS
@
C +3VGS
1

C
RV128 1 @ 2 2 QV13
1

2.2K_0402_5% B MMBT3904WH_SOT323-3
CV215

.1U_0402_10V6-K

E @ RV43 RV44
3
1

45.3K_0402_1% 45.3K_0402_1%
G

1
RV129 RV130 RV131 PX@ PX@
GPU_RST# @ 1 2 DV2 20K_0402_5% 20K_0402_5% 100K_0402_5%
20 GPU_RST#
2

FOR ONE TIME CTF USE 47K @ @ @

A SDM10U45LP-7_DFN1006-2-2 FOR RESETABLE CTF USE 2K 2 VGA_SMB_CLK QV4A 1 6 PX@ A
S

EC_SMB_CK2 7,39,44
2

1 2

C 2N7002KDWH_SOT363-6
G

GPIO_19_CTF 1 @ 2 RV132 RV133 1 @ 2 2

47K_0402_5% 47K_0402_5% B
CV216

.01U_0402_16V7-K

E
3
1

QV14 VGA_SMB_DATA QV4B 4 3 PX@

S

1 EC_SMB_DA2 7,39,44
D

RV134 MMBT3904_SOT23-3
100K_0402_5% @ 2N7002KDWH_SOT363-6
@
2
@
2

RV135 1 @ 2 0_0402_5%
Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_Main_MSIC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

UV1F
+VGA_CORE

D D
AB11 RV115 1 2 0_0402_5% TOPAZ@
NC_VARY_BL AB12 RV116 1 2 0_0402_5% TOPAZ@
NC_DIGON

AL15
NC_UPHYAB_TMDPA_TX0N AK14
NC_UPHYAB_TMDPA_TX0P
AH16
NC_UPHYAB_TMDPA_TX1N AJ15
NC_UPHYAB_TMDPA_TX1P
AL17
NC_UPHYAB_TMDPA_TX2N AK16
NC_UPHYAB_TMDPA_TX2P
AH18
NC_UPHYAB_TMDPA_TX3N AJ17
NC_UPHYAB_TMDPA_TX3P
AL19
NC_TXOUT_L3P AK18
NC_TXOUT_L3N
C C
TMDP

AH20
NC_UPHYAB_TMDPB_TX0N AJ19
NC_UPHYAB_TMDPB_TX0P
AL21
NC_UPHYAB_TMDPB_TX1N AK20
NC_UPHYAB_TMDPB_TX1P
AH22
NC_UPHYAB_TMDPB_TX2N AJ21
NC_UPHYAB_TMDPB_TX2P
AL23
NC_UPHYAB_TMDPB_TX3N AK22
NC_UPHYAB_TMDPB_TX3P
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N

JET-S3-LE_FCBGA631
B @ B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_TMDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

+1.8VGS (1.8V@40mA DP_VDDR)

0_0603_5%
1 2 RV48 +DP_VDDR
UV1G UV1E

PX@

PX@
PX@
NC/DP POWER

10U_0603_6.3V6M

1U_0402_6.3V6K
DP POWER
1 1
AG15 AE11 AA27 A3
AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
D D
AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
2 2 AG17 NC_DP_VDDR#AF16 NC#AE13 AF13 AC24 GND_3 GND_67 AA16

CV39

CV40
AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
AE27 GND_8 GND_72 AD6
+0.95VGS AF32 GND_9 GND_73 AD8
(0.95V@32mA DP_VDDC) GND_10 GND_74
0_0603_5% AG27 AE7
1 2 RV47 +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
AG21 NC_DP_VDDC#AG20 NC#AF6 AF7 K28 GND_12 GND_76 AH10

CV38

CV37
AF22 NC_DP_VDDC#AG21 NC#AF7 AF8 K32 GND_13 GND_77 AH28
PX@
AG22 NC_DP_VDDC#AF22 NC#AF8 AF9 L27 GND_14 GND_78 B10

1U_0402_6.3V6K

.1U_0402_16V7K
AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
1 1 DP_VDDC#AD14 GND_16 GND_80
N25 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
2 2 AG14 AE1 P32 GND_19 GND_83 B20
NC_DP_VSSR_1 NC#AE1 GND_20 GND_84
PX@

PX@
AH14 AE3 R27 B22
AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
AG23 NC_DP_VSSR_6 NC#AF10 AG9 V32 GND_25 GND_89 C1
C
AM20 NC_DP_VSSR_7 NC#AG9 AH8 W25 GND_26 GND_90 C32 C
AM22 NC_DP_VSSR_8 NC#AH8 AM6 W26 GND_27 GND_91 E28
AM24 NC_DP_VSSR_9 NC#AM6 AM8 W27 GND_28 GND_92 F10
AF19 NC_DP_VSSR_10 NC#AM8 AG7 Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
DP_VSSR_13 GND_96 F18
GND_97 F2
GND_98 F20
RV49 1 @ 2 AF17 AE10 M6 GND_99 F22
150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24
N16 GND_33 GND_101 F26
N18 GND_34 GND_102 F6
JET-S3-LE_FCBGA631 N21 GND_35 GND
GND_103 F8
@ P6 GND_36 GND_104 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
B B
U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2
U20 GND_49 GND_117 K22
U9 GND_50 GND_118 K6
V13 GND_51 GND_119
V16 GND_52
V18 GND_53
Y10 GND_54
Y15 GND_55
Y17 GND_56
Y20 GND_57
R11 GND_58 A32
T11 GND_59 VSS_MECH_1 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
N11 GND_62
V11 GND_63
GND_64

JET-S3-LE_FCBGA631
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_DP Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

+1.35VGS
For DDR3/GDDR5, 2A@1.35V

CV48

CV51

CV52

CV53

CV54

CV55

CV56

CV217
10U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

.1U_0402_16V7K

.01U_0402_16V7-K
1 1 1 1 1 1 1 1 UV1D +1.8VGS
(1.8V@100mA PCIE_PVDD)
AM30
PCIE_PVDD

PCIE
MEM I/O

CV46

CV47
2 2 2 2 2 2 2 2

PX@
H13 AB23

10U_0603_6.3V6M
1U_0402_6.3V6K
VDDR1_1 NC#AB23

PX@

PX@

PX@

PX@

PX@
@

@
H16 AC23 1 1
H19 VDDR1_2 NC#AC23 AD24
J10 VDDR1_3 NC#AD24 AE24
J23 VDDR1_4 NC#AE24 AE25
VDDR1_5 NC#AE25 2 2

PX@

PX@
J24 AE26
J9 VDDR1_6 NC#AE26 AF25
D K10 VDDR1_7 NC#AF25 AG26 D
+1.8VGS +VDD_CT K23 VDDR1_8 NC#AG26 +0.95VGS
(1.8V@13mA VDD_CT) VDDR1_9
K24 (0.95V@1A PCIE_VDDC)
LV7 1 @ 2 0_0402_5% K9 VDDR1_10 L23
VDDR1_11 PCIE_VDDC_1

CV90
L11 L24
VDDR1_12 PCIE_VDDC_2

CV64

CV65

CV66

CV67

CV68

CV69

CV71
L12 L25

1U_0402_6.3V6K
L13 VDDR1_13 PCIE_VDDC_3 L26

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 VDDR1_14 PCIE_VDDC_4
L20 M22 1 1 1 1 1 1 1
L21 VDDR1_15 PCIE_VDDC_5 N22
L22 VDDR1_16 PCIE_VDDC_6 N23
2 VDDR1_17 PCIE_VDDC_7

PX@
N24
PCIE_VDDC_8 2 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@
R22

CD@

CD@
PCIE_VDDC_9 T22
LEVEL PCIE_VDDC_10 U22
TRANSLATION PCIE_VDDC_11 V22
AA20 PCIE_VDDC_12 +VGA_CORE
AA21 VDD_CT_1
AB20 VDD_CT_2 AA15
+3VGS AB21 VDD_CT_3 CORE VDDC_1 N15
(3.3V@25mA VDDR3) VDD_CT_4 VDDC_2

CV9

CV73

CV74

CV75

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87
N17

CV100
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
LV8 1 @ 2 0_0402_5% +VDDR3 VDDC_3 R13

33P_0402_50V8J
I/O VDDC_4 R16

CV93
VDDC_5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AA17 R18

1U_0402_6.3V6K
AA18 VDDR3_1 VDDC_6 Y21
1 VDDR3_2 VDDC_7
AB17 T12
VDDR3_3 VDDC_8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
AB18 T15
VDDR3_4 VDDC_9

@
T17
2 VDDC_10

PX@
V12 T20
Y12 NC_VDDR4_1 VDDC_11 U13
+1.8VGS U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13 For RF
(1.8V@90mA MPLL_PVDD) U18
VDDC_14 V21
LV4 1 2 PX@ +MPLL_PVDD VDDC_15 V15
VDDC_16
CV26

CV34

CV27

CV88
V17

CV101

CV102

CV103

CV104

CV105
0_0603_5%
VDDC_17
CV24

V20

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VDDC_18

POWER
Y13
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

VDDC_19 1 1 1 1 1 1
Y16
.1U_0402_16V7K

1 1 1 VDDC_20
1 Y18
EMC_NS@ VDDC_21 AA12
VDDC_22 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@

PX@
M11
2 2 2 VDDC_23 N12
2 VDDC_24 U11
For EMC VDDC_25
PX@

PX@

PX@

C C

PLL
+0.95VGS

(0.95V@0.8A BIF_VDDC) +VGA_CORE

+1.8VGS R21
BIF_VDDC_1 U21
(1.8V@75mA SPLL_PVDD)

1
BIF_VDDC_2
1
LV5 1 2 PX@ +SPLL_PVDD +MPLL_PVDD L8 CV41 RV244
MPLL_PVDD
CV29

CV30

0_0402_5% +VGA_CORE 1U_0402_6.3V6K 470_0603_5%

CV28

ISOLATED PX@ @
2
10U_0603_6.3V6M

1U_0402_6.3V6K

CORE I/O

1 2
M13
.1U_0402_16V7K

1 1 VDDCI_1
1 EMC_NS@ +SPLL_PVDD H7 M15 QV21 D
SPLL_PVDD VDDCI_2 M16 PXS_PWREN# 2
+0.95VGS VDDCI_3

CV10
M17

CV218

CV219

CV114

CV115

CV116

CV117
G
For EMC 2 2 VDDCI_4 M18

CV220
33P_0402_50V8J
(0.95V@100mA SPLL_VDDC)

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 VDDCI_5 M20 @ S 2N7002KW_SOT323-3
1 1 1 1 1 1 1 1

3
VDDCI_6
PX@

PX@

LV6 1 2 PX@ +SPLL_VDDC H8 M21

SPLL_VDDC VDDCI_7 N20
CV35

CV36

0_0402_5%
VDDCI_8
CV33

J7 VGA_CORE dischange
SPLL_PVSS 2 2 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@

PX@

PX@
1U_0402_6.3V6K

.1U_0402_16V7K

@
.1U_0402_16V7K

1 1
1
JET-S3-LE_FCBGA631
For EMC @
2 2
2
For RF
EMC_NS@
PX@

PX@

+1.0VALW +0.95VGS
AON7408L_DFN8-5
+1.0VALW TO +0.95VGS QV16

Can change to low cost and

1
small size MOS.Rdson<22mohm 5 S1 2
+1.8VALW TO +1.8VGS Reserve for GPU support +0.95VS /2A
D S2 3
+1.8VALW +1.8VGS S3

1U_0603_25V6M
Can change to low cost and small

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1

1
QV22 PXS_PWREN#_H 1 PX@ 2 RV245
B AO3402_SOT-23-3 size MOS. AO3402 B

CV240

CV238

CV239
15K_0402_5%

4
PX@ +1.8VGS /0.5A Rdson<65mohm RV243
PX@ 2 PX@ 2 PX@ 2 PX@
1 3 @ 470_0603_5%
D S 1 @ 2 RV120
1U_0603_25V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

+20VSB

1 2
100K_0402_5%
G

D QV20
1

1
470_0603_5%

1 1 1 1 2 PXS_PWREN#
2

1
RV242

D RV119 CV221 G
2
CV242

CV241 CV243 PXS_PWREN# QV15 120K_0402_5% 0.1U_0402_16V4Z

@ G @ PX@ S @

3
+20VSB 2 PX@ 2@ 2@ 2 2N7002KW_SOT323-3
1 2

2
@ S

3
1 PX@ 2 RV202 PXS_PWREN#_H D QV19 2N7002KW_SOT323-3
100K_0402_5% 2 PXS_PWREN#
1

1 G
RV123 CV237
1

D 120K_0402_5% 0.1U_0402_16V4Z S @ +1.35V +1.35VGS

3

PXS_PWREN# 2 QV17 PX@ PX@ 2N7002KW_SOT323-3

G 2
2

PX@ S
3

2N7002KW_SOT323-3

CV214 CV210 CV211 CV212

+1.35V TO +1.35VGS CV208 CV209 AON6414AL_DFN8-5

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K
330U_D2_2V_Y
1

1
1 1 1 1 1
1 + RV91
2 470_0603_5%
5 3 @
2 2 @ 2 2 2 2

PX@

PX@

PX@

PX@
@
+3VS +3VGS

1 2
+3.3VS TO +3VGS QV9 PX@ D QV10

4
+3.3VGS /25mA 2 PXS_PWREN#
G
S

QV6 3 1 PX@
LP2301ALT1G_SOT23-3 S 2N7002KW_SOT323-3

3
CV118 CV119 PXS_PWREN#_H RV246 1 PX@ 2 47K_0402_5% @
10U_0603_6.3V6M

1U_0402_10V6K

1
G

1 1
2

RV51
470_0603_5%
+5VALW @ 1 @ 2 RV92
2 2 +20VSB
PX@

PX@

499K_0402_1%
2

A RV52 1 PX@ 2 PXS_PWREN# 2 PX@ 1 RV53 A

1
20K_0402_5% 15K_0402_5% 1
1

1 D QV7 D RV118 CV213

CV120 2 PXS_PWREN# PXS_PWREN# 2 QV11 499K_0402_1% 0.1U_0402_16V4Z
1

D 0.1U_0402_16V4Z G G @ PX@
PXS_PWREN 2 QV8 PX@ 2
8,57,58 PXS_PWREN

2
G 2 S 2N7002KW_SOT323-3 @ S
3

@ 2N7002KW_SOT323-3
PX@ S
3

2N7002KW_SOT323-3

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 24 of 60
5 4 3 2 1
 5 4 3 2 1

UV1C
DQA0_[31..0]
DQA0_[31..0] 26,27 GDDR5/DDR3 GDDR5/DDR3
DQA1_[31..0] DQA0_0 K27 K17 MAA0
DQA1_[31..0] 26,27 J29 DQA0_0 MAA0_0/MAA_0 J20
DQA0_1 MAA1
DQA0_2 H30 DQA0_1 MAA0_1/MAA_1 H23 MAA2
MAA[15..0] DQA0_3 H32 DQA0_2 MAA0_2/MAA_2 G23 MAA3
MAA[15..0] 26,27 G29 DQA0_3 MAA0_3/MAA_3 G24
DQA0_4 MAA4
A_BA[2..0] DQA0_5 F28 DQA0_4 MAA0_4/MAA_4 H24 MAA5
A_BA[2..0] 26,27 DQA0_5 MAA0_5/MAA_5
D DQA0_6 F32 J19 MAA6 D
DQA0_7 F30 DQA0_6 MAA0_6/MAA_6 K19 MAA7
DQA0_8 C30 DQA0_7 MAA0_7/MAA_7 G20 MAA13
DQA0_9 F27 DQA0_8 MAA0_8/MAA_13 L17 MAA15
DQA0_10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_11 C28 DQA0_10 J14 MAA8
DQA0_12 E27 DQA0_11 MAA1_0/MAA_8 K14 MAA9
DQA0_13 G26 DQA0_12 MAA1_1/MAA_9 J11 MAA10
DQA0_14 D26 DQA0_13 MAA1_2/MAA_10 J13 MAA11
DQA0_15 F25 DQA0_14 MAA1_3/MAA_11 H11 MAA12
DQA0_16 A25 DQA0_15 MAA1_4/MAA_12 G11 A_BA2
DQA0_17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 A_BA0
DQA0_18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 A_BA1
DQA0_19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 MAA14
DQA0_20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
DQA0_21 F23 DQA0_20 MAA1_9/RSVD
DQA0_21 DQMA#[7..0] 26,27
DQA0_22 D22 E32 DQMA#0
DQA0_23 F21 DQA0_22 W CKA0_0/DQMA0_0 E30 DQMA#1
DQA0_24 E21 DQA0_23 W CKA0B_0/DQMA0_1 A21 DQMA#2
DQA0_25 D20 DQA0_24 W CKA0_1/DQMA0_2 C21 DQMA#3 +1.35VGS
DQA0_26 F19 DQA0_25 W CKA0B_1/DQMA0_3 E13 DQMA#4
DQA0_27 A19 DQA0_26 W CKA1_0/DQMA1_0 D12 DQMA#5
DQA0_28 D18 DQA0_27 W CKA1B_0/DQMA1_1 E3 DQMA#6 RV136 1 PX@ 2 100_0402_1% MAA0 100_0402_1% 1 PX@ 2 RV137
DQA0_29 F17 DQA0_28 W CKA1_1/DQMA1_2 F4 DQMA#7 RV138 1 PX@ 2 100_0402_1% MAA1 100_0402_1% 1 PX@ 2 RV139
DQA0_30 A17 DQA0_29 W CKA1B_1/DQMA1_3 RV140 1 PX@ 2 100_0402_1% MAA2 100_0402_1% 1 PX@ 2 RV141
C17 DQA0_30 H28 QSA[7..0] 26,27 1 2 1 2
DQA0_31 QSA0 RV142 PX@ 100_0402_1% MAA3 100_0402_1% PX@ RV143
DQA1_0 E17 DQA0_31 EDCA0_0/QSA0_0 C27 QSA1 RV144 1 PX@ 2 100_0402_1% MAA4 100_0402_1% 1 PX@ 2 RV145
DQA1_1 D16 DQA1_0 EDCA0_1/QSA0_1 A23 QSA2 RV146 1 PX@ 2 100_0402_1% MAA5 100_0402_1% 1 PX@ 2 RV147
C DQA1_1 EDCA0_2/QSA0_2 C
+1.35VGS DQA1_2 F15 E19 QSA3 RV148 1 PX@ 2 100_0402_1% MAA6 100_0402_1% 1 PX@ 2 RV149
DQA1_3 A15 DQA1_2 EDCA0_3/QSA0_3 E15 QSA4 RV150 1 PX@ 2 100_0402_1% MAA7 100_0402_1% 1 PX@ 2 RV151
DQA1_4 D14 DQA1_3 EDCA1_0/QSA1_0 D10 QSA5 RV152 1 PX@ 2 100_0402_1% MAA8 100_0402_1% 1 PX@ 2 RV153
DQA1_4 EDCA1_1/QSA1_1
1

DQA1_5 F13 D6 QSA6 RV154 1 PX@ 2 100_0402_1% MAA9 100_0402_1% 1 PX@ 2 RV155
RV61 DQA1_6 A13 DQA1_5 EDCA1_2/QSA1_2 G5 QSA7 RV156 1 PX@ 2 100_0402_1% MAA10 100_0402_1% 1 PX@ 2 RV157
40.2_0402_1% DQA1_7 C13 DQA1_6 EDCA1_3/QSA1_3 RV158 1 PX@ 2 100_0402_1% MAA11 100_0402_1% 1 PX@ 2 RV159
E11 DQA1_7 H27 QSA#[7..0] 26,27 1 2 1 2
PX@ DQA1_8 QSA#0 RV160 PX@ 100_0402_1% MAA12 100_0402_1% PX@ RV161
DQA1_9 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 QSA#1 RV162 1 PX@ 2 100_0402_1% MAA13 100_0402_1% 1 PX@ 2 RV163
2

+VDD_MEM15_REFDA DQA1_10 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 QSA#2 RV164 1 PX@ 2 100_0402_1% MAA14 100_0402_1% 1 PX@ 2 RV165
DQA1_11 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 QSA#3 RV166 1 PX@ 2 100_0402_1% MAA15 100_0402_1% 1 PX@ 2 RV167
DQA1_11 DDBIA0_3/QSA0_3B
1

1 DQA1_12 A9 C15 QSA#4

RV65 CV124 DQA1_13 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 QSA#5
100_0402_1% 1U_0402_6.3V6K DQA1_14 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 QSA#6 RV168 1 PX@ 2 100_0402_1% A_BA0 100_0402_1% 1 PX@ 2 RV169
PX@ PX@ DQA1_15 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 QSA#7 RV170 1 PX@ 2 100_0402_1% A_BA1 100_0402_1% 1 PX@ 2 RV171
2 DQA1_16 E7 DQA1_15 DDBIA1_3/QSA1_3B RV172 1 PX@ 2 100_0402_1% A_BA2 100_0402_1% 1 PX@ 2 RV173
2

DQA1_17 A7 DQA1_16 L18 ODTA0

C7 DQA1_17 ADBIA0/ODTA0 K16 ODTA0 26,27
DQA1_18 ODTA1
F7 DQA1_18 ADBIA1/ODTA1 ODTA1 26,27 1
DQA1_19 RV174 PX@ 2 100_0201_1% ODTA0 100_0201_1% 1 PX@ 2 RV175
DQA1_20 A5 DQA1_19 H26 CLKA0 RV176 1 PX@ 2 100_0201_1% ODTA1 100_0201_1% 1 PX@ 2 RV177
E5 DQA1_20 CLKA0 H25 CLKA0 26,27
DQA1_21 CLKA0#
C3 DQA1_21 CLKA0B CLKA0# 26,27
DQA1_22
DQA1_23 E1 DQA1_22 G9 CLKA1 RV178 1 PX@ 2 100_0201_1% RASA0# 100_0201_1% 1 PX@ 2 RV179
DQA1_23 CLKA1 CLKA1 26,27
DQA1_24 G7 H9 CLKA1# RV180 1 PX@ 2 100_0201_1% RASA1# 100_0201_1% 1 PX@ 2 RV181
DQA1_24 CLKA1B CLKA1# 26,27
+1.35VGS DQA1_25 G6
DQA1_26 G1 DQA1_25 G22 RASA0#
DQA1_26 RASA0B RASA0# 26,27
DQA1_27 G3 G17 RASA1# RV182 1 PX@ 2 100_0201_1% CASA0# 100_0201_1% 1 PX@ 2 RV183
DQA1_27 RASA1B RASA1# 26,27
1

B DQA1_28 J6 RV184 1 PX@ 2 100_0201_1% CASA1# 100_0201_1% 1 PX@ 2 RV185 B

RV62 DQA1_29 J1 DQA1_28 G19 CASA0#
DQA1_29 CASA0B CASA0# 26,27
40.2_0402_1% DQA1_30 J3 G16 CASA1#
DQA1_31 J5 DQA1_30 CASA1B CASA1# 26,27 1 RANKA@2 100_0201_1% CSA0#_0 1 RANKA@2 RV187
PX@ RV186 100_0201_1%
DQA1_31 H22 CSA0#_0 RV190 1 RANKA@2 100_0201_1% CSA1#_0 100_0201_1% 1 RANKA@2 RV191
2

K26 CSA0B_0 J22 CSA0#_0 26

+VDD_MEM15_REFSA +VDD_MEM15_REFDA CSA0#_1
MVREFDA CSA0B_1 CSA0#_1 27
+VDD_MEM15_REFSA J26
MVREFSA
1

1 G13 CSA1#_0 RV188 1 RANKB@2 100_0201_1% CSA0#_1 100_0201_1% 1 RANKB@2 RV189

J25 CSA1B_0 K13 CSA1#_0 26 1 RANKB@2 100_0201_1% 1 RANKB@2 RV193
RV66 CV125 CSA1#_1 RV192 CSA1#_1 100_0201_1%
NC#J25 CSA1B_1 CSA1#_1 27
100_0402_1% 1U_0402_6.3V6K RV55 1 2 PX@ K25
PX@ PX@ 120_0402_1% MEM_CALRP0 K20 CKEA0
2 CKEA0 CKEA0 26,27
J17 CKEA1 RV194 1 PX@ 2 100_0201_1% CKEA0 100_0201_1% 1 PX@ 2 RV195
CKEA1 26,27
2

CKEA1 RV196 1 PX@ 2 100_0201_1% CKEA1 100_0201_1% 1 PX@ 2 RV197

G25 WEA0#
W EA0B WEA0# 26,27
DRAMRST L10 H10 WEA1#
DRAM_RST W EA1B WEA1# 26,27 1
RV198 PX@ 2 100_0201_1% WEA0# 100_0201_1% 1 PX@ 2 RV199
PAD @ TV8 1 CLKTESTA K8 RV200 1 PX@ 2 100_0201_1% WEA1# 100_0201_1% 1 PX@ 2 RV201
PAD @ TV9 1 CLKTESTB L7 CLKTESTA
CLKTESTB

JET-S3-LE_FCBGA631
@

DRAMRST RV56 1 PX@ 2 RV57 1 2 PX@

DRAM_RST# 26,27
10_0402_5% 51.1_0402_1%
1

RV58 1
A 4.99K_0402_1% CV121 A
PX@ 120P_0402_50V8-J
PX@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_MEM IF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

UV3 UV4 UV5 UV6

VREF_UV3_4 M8 E3 DQA0_19 VREF_UV3_4 M8 E3 DQA0_14 VREF_UV5_6 M8 E3 DQA1_9 VREF_UV5_6 M8 E3 DQA1_26

H1 VREFCA DQL0 F7 DQA0_21 H1 VREFCA DQL0 F7 DQA0_9 H1 VREFCA DQL0 F7 DQA1_14 H1 VREFCA DQL0 F7 DQA1_31
VREFDQ DQL1 F2 DQA0_18 VREFDQ DQL1 F2 DQA0_15 VREFDQ DQL1 F2 DQA1_11 VREFDQ DQL1 F2 DQA1_27
MAA0 N3 DQL2 F8 DQA0_22 MAA0 N3 DQL2 F8 DQA0_10 MAA0 N3 DQL2 F8 DQA1_12 MAA0 N3 DQL2 F8 DQA1_29
DQA0_[31..0] MAA1 P7 A0 DQL3 H3 DQA0_17 MAA1 P7 A0 DQL3 H3 DQA0_12 MAA1 P7 A0 DQL3 H3 DQA1_8 MAA1 P7 A0 DQL3 H3 DQA1_25
25,27 DQA0_[31..0] A1 DQL4 Group2 A1 DQL4 Group1 A1 DQL4 Group5 A1 DQL4 Group7
MAA2 P3 H8 DQA0_23 MAA2 P3 H8 DQA0_11 MAA2 P3 H8 DQA1_13 MAA2 P3 H8 DQA1_30
DQA1_[31..0] MAA3 N2 A2 DQL5 G2 DQA0_16 MAA3 N2 A2 DQL5 G2 DQA0_13 MAA3 N2 A2 DQL5 G2 DQA1_10 MAA3 N2 A2 DQL5 G2 DQA1_24
25,27 DQA1_[31..0] P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7
MAA4 DQA0_20 MAA4 DQA0_8 MAA4 DQA1_15 MAA4 DQA1_28
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA[15..0] MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
25,27 MAA[15..0] R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
MAA7 DQA0_4 MAA7 DQA0_26 MAA7 DQA1_7 MAA7 DQA1_23
QSA[7..0] MAA8 T8 A7 DQU0 C3 DQA0_2 MAA8 T8 A7 DQU0 C3 DQA0_28 MAA8 T8 A7 DQU0 C3 DQA1_3 MAA8 T8 A7 DQU0 C3 DQA1_20
25,27 QSA[7..0] R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8
D MAA9 DQA0_7 MAA9 DQA0_27 MAA9 DQA1_6 MAA9 DQA1_19 D
QSA#[7..0] MAA10 L7 A9 DQU2 C2 DQA0_0 MAA10 L7 A9 DQU2 C2 DQA0_31 MAA10 L7 A9 DQU2 C2 DQA1_0 MAA10 L7 A9 DQU2 C2 DQA1_18
25,27 QSA#[7..0] R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7
MAA11 DQA0_5 Group0 MAA11 DQA0_25 Group3 MAA11 DQA1_5 Group4 MAA11 DQA1_21 Group6
DQMA#[7..0] MAA12 N7 A11 DQU4 A2 DQA0_1 MAA12 N7 A11 DQU4 A2 DQA0_29 MAA12 N7 A11 DQU4 A2 DQA1_1 MAA12 N7 A11 DQU4 A2 DQA1_17
25,27 DQMA#[7..0] T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8
MAA13 DQA0_6 MAA13 DQA0_24 MAA13 DQA1_4 MAA13 DQA1_22
A13 DQU6 A3 DQA0_3 A13 DQU6 A3 DQA0_30 A13 DQU6 A3 DQA1_2 A13 DQU6 A3 DQA1_16
DQU7 DQU7 DQU7 DQU7
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

25,27 A_BA0 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9
A_BA1 A_BA1 A_BA1
25,27 A_BA1 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7
A_BA2 A_BA2 A_BA2
25,27 A_BA2 BA2 VDD_3 K2 BA2 VDD_3 K2 BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 K8 VDD_4 K8 VDD_4 K8 VDD_4 K8
VDD_5 N1 VDD_5 N1 VDD_5 N1 VDD_5 N1
J7 VDD_6 N9 CLKA0 J7 VDD_6 N9 J7 VDD_6 N9 CLKA1 J7 VDD_6 N9
25,27 CLKA0 K7 CK VDD_7 R1 K7 CK VDD_7 R1 25,27 CLKA1 K7 CK VDD_7 R1 K7 CK VDD_7 R1
CLKA0# CLKA1#
25,27 CLKA0# K9 CK VDD_8 R9 K9 CK VDD_8 R9 25,27 CLKA1# K9 CK VDD_8 R9 K9 CK VDD_8 R9
CKEA0 CKEA1
25,27 CKEA0 CKE VDD_9 CKE VDD_9 25,27 CKEA1 CKE VDD_9 CKE VDD_9
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
25,27 ODTA0 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8 25,27 ODTA1 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
CSA0#_0 CSA1#_0
25 CSA0#_0 J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1 25 CSA1#_0 J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1
RASA0# RASA1#
25,27 RASA0# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9 25,27 RASA1# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9
CASA0# CASA1#
25,27 CASA0# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2 25,27 CASA1# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
WEA0# WEA1#
25,27 WEA0# WE VDDQ_5 E9 WE VDDQ_5 E9 25,27 WEA1# WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1 VDDQ_6 F1 VDDQ_6 F1
QSA2 F3 VDDQ_7 H2 QSA1 F3 VDDQ_7 H2 QSA5 F3 VDDQ_7 H2 QSA7 F3 VDDQ_7 H2
QSA0 C7 DQSL VDDQ_8 H9 QSA3 C7 DQSL VDDQ_8 H9 QSA4 C7 DQSL VDDQ_8 H9 QSA6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 DQSU VDDQ_9 DQSU VDDQ_9

DQMA#2 E7 A9 DQMA#1 E7 A9 DQMA#5 E7 A9 DQMA#7 E7 A9

DQMA#0 D3 DML VSS_1 B3 DQMA#3 D3 DML VSS_1 B3 DQMA#4 D3 DML VSS_1 B3 DQMA#6 D3 DML VSS_1 B3
DMU VSS_2 E1 DMU VSS_2 E1 DMU VSS_2 E1 DMU VSS_2 E1
VSS_3 G8 VSS_3 G8 VSS_3 G8 VSS_3 G8
QSA#2 G3 VSS_4 J2 QSA#1 G3 VSS_4 J2 QSA#5 G3 VSS_4 J2 QSA#7 G3 VSS_4 J2
QSA#0 B7 DQSL VSS_5 J8 QSA#3 B7 DQSL VSS_5 J8 QSA#4 B7 DQSL VSS_5 J8 QSA#6 B7 DQSL VSS_5 J8
DQSU VSS_6 M1 DQSU VSS_6 M1 DQSU VSS_6 M1 DQSU VSS_6 M1
C VSS_7 VSS_7 VSS_7 VSS_7 C
M9 M9 M9 M9
VSS_8 P1 VSS_8 P1 VSS_8 P1 VSS_8 P1
T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9
25,27 DRAM_RST# RESET VSS_10 T1 RESET VSS_10 T1 RESET VSS_10 T1 RESET VSS_10 T1
L8 VSS_11 T9 L8 VSS_11 T9 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 ZQ VSS_12 ZQ VSS_12
1

1
J1 B1 J1 B1 J1 B1 J1 B1
RV67 L1 NC1 VSSQ_1 B9 RV68 L1 NC1 VSSQ_1 B9 RV69 L1 NC1 VSSQ_1 B9 RV70 L1 NC1 VSSQ_1 B9
243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
RANKA@ L9 NC3 VSSQ_3 D8 RANKA@ L9 NC3 VSSQ_3 D8 RANKA@ L9 NC3 VSSQ_3 D8 RANKA@ L9 NC3 VSSQ_3 D8
MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2
2

2
MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8
NC6 VSSQ_6 F9 NC6 VSSQ_6 F9 NC6 VSSQ_6 F9 NC6 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1 VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 G9 VSSQ_8 G9 VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 VSSQ_9 VSSQ_9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96
@ @ @ @

+1.35VGS +1.35VGS

CV126

CV127

CV128

CV129

CV130

CV131

CV132

CV133

CV134

CV135

CV136

CV137

CV138

CV139

CV140

CV141

CV142
+1.35VGS

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
+1.35VGS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

B B
1
1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKA@

RANKA@

RANKA@

RANKA@
CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@
RV210
RV73 4.99K_0402_1%
4.99K_0402_1% RANKA@
RANKA@
2
2

VREF_UV5_6
VREF_UV3_4 +1.35VGS +1.35VGS
1

1
1

1 RV211 CV224
RV77 CV144 4.99K_0402_1% 0.1U_0402_10V7K
CV146

CV147

CV148

CV149

CV150

CV151

CV152

CV153

CV154

CV155

CV156

CV157

CV158

CV159

CV160

CV161

CV162

CV163

CV164

CV165
4.99K_0402_1% 0.1U_0402_10V7K RANKA@ RANKA@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
RANKA@ RANKA@ 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2

2
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@
ACLU1: (10U_0603_6.3V6M)*4 CRB: 10uF *4
+1.35VGS (1U_0402_6.3V6K)*20 1uF *32
(.1U_0402_10V6-K)*13 .1uF *32
CV11

CV12

CV13

CV14
33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

1 1 1 1

2 2 2 2
A A
@

CLKA0 RV71 1 2 @ CLKA1 RV75 1 2 @

40.2_0402_1% 40.2_0402_1%

CLKA0# RV72 1 2 @ CLKA1# RV76 1 2 @

40.2_0402_1% 40.2_0402_1% For RF
1 1
CV143 CV166
.01U_0402_16V7-K .01U_0402_16V7-K Title
RANKA@ RANKA@ Security Classification LC Future Center Secret Data
2 2
Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_VRAM_A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
For Single-Rank: RV71,RV72,RV75,RV76 use 40.2_0402_1% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.3
For Dual-Rank: RV71,RV72,RV75,RV76 use 80.6_0402_1% DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

UV7 UV8 UV9 UV10

VREF_UV7_8 M8 E3 DQA0_21 VREF_UV7_8 M8 E3 DQA0_9 VREF_UV9_10 M8 E3 DQA1_12 VREF_UV9_10 M8 E3 DQA1_31

H1 VREFCA DQL0 F7 DQA0_19 H1 VREFCA DQL0 F7 DQA0_14 H1 VREFCA DQL0 F7 DQA1_9 H1 VREFCA DQL0 F7 DQA1_26
VREFDQ DQL1 F2 DQA0_22 VREFDQ DQL1 F2 DQA0_10 VREFDQ DQL1 F2 DQA1_13 VREFDQ DQL1 F2 DQA1_29
MAA0 N3 DQL2 F8 DQA0_18 MAA0 N3 DQL2 F8 DQA0_15 MAA0 N3 DQL2 F8 DQA1_11 MAA0 N3 DQL2 F8 DQA1_27
DQA0_[31..0] MAA1 P7 A0 DQL3 H3 DQA0_20 MAA1 P7 A0 DQL3 H3 DQA0_11 MAA1 P7 A0 DQL3 H3 DQA1_15 MAA1 P7 A0 DQL3 H3 DQA1_28
25,26 DQA0_[31..0] A1 DQL4 Group2 A1 DQL4 Group1 A1 DQL4 Group5 A1 DQL4 Group7
MAA2 P3 H8 DQA0_16 MAA2 P3 H8 DQA0_12 MAA2 P3 H8 DQA1_10 MAA2 P3 H8 DQA1_24
DQA1_[31..0] MAA3 N2 A2 DQL5 G2 DQA0_23 MAA3 N2 A2 DQL5 G2 DQA0_8 MAA3 N2 A2 DQL5 G2 DQA1_14 MAA3 N2 A2 DQL5 G2 DQA1_30
25,26 DQA1_[31..0] P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7
MAA4 DQA0_17 MAA4 DQA0_13 MAA4 DQA1_8 MAA4 DQA1_25
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA[15..0] MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
25,26 MAA[15..0] R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
MAA7 DQA0_2 MAA7 DQA0_28 MAA7 DQA1_3 MAA7 DQA1_20
QSA[7..0] MAA8 T8 A7 DQU0 C3 DQA0_4 MAA8 T8 A7 DQU0 C3 DQA0_26 MAA8 T8 A7 DQU0 C3 DQA1_5 MAA8 T8 A7 DQU0 C3 DQA1_23
25,26 QSA[7..0] R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8
D MAA9 DQA0_0 MAA9 DQA0_31 MAA9 DQA1_0 MAA9 DQA1_18 D
QSA#[7..0] MAA10 L7 A9 DQU2 C2 DQA0_7 MAA10 L7 A9 DQU2 C2 DQA0_27 MAA10 L7 A9 DQU2 C2 DQA1_7 MAA10 L7 A9 DQU2 C2 DQA1_19
25,26 QSA#[7..0] R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7
MAA11 DQA0_3 Group0 MAA11 DQA0_30 Group3 MAA11 DQA1_2 Group4 MAA11 DQA1_16 Group6
DQMA#[7..0] MAA12 N7 A11 DQU4 A2 DQA0_6 MAA12 N7 A11 DQU4 A2 DQA0_24 MAA12 N7 A11 DQU4 A2 DQA1_6 MAA12 N7 A11 DQU4 A2 DQA1_22
25,26 DQMA#[7..0] T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8
MAA13 DQA0_1 MAA13 DQA0_29 MAA13 DQA1_1 MAA13 DQA1_17
A13 DQU6 A3 DQA0_5 A13 DQU6 A3 DQA0_25 A13 DQU6 A3 DQA1_4 A13 DQU6 A3 DQA1_21
DQU7 DQU7 DQU7 DQU7
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

25,26 A_BA0 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9
A_BA1 A_BA1 A_BA1
25,26 A_BA1 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7
A_BA2 A_BA2 A_BA2
25,26 A_BA2 BA2 VDD_3 K2 BA2 VDD_3 K2 BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 K8 VDD_4 K8 VDD_4 K8 VDD_4 K8
VDD_5 N1 VDD_5 N1 VDD_5 N1 VDD_5 N1
J7 VDD_6 N9 CLKA0 J7 VDD_6 N9 J7 VDD_6 N9 CLKA1 J7 VDD_6 N9
25,26 CLKA0 K7 CK VDD_7 R1 K7 CK VDD_7 R1 25,26 CLKA1 K7 CK VDD_7 R1 K7 CK VDD_7 R1
CLKA0# CLKA1#
25,26 CLKA0# K9 CK VDD_8 R9 K9 CK VDD_8 R9 25,26 CLKA1# K9 CK VDD_8 R9 K9 CK VDD_8 R9
CKEA0 CKEA1
25,26 CKEA0 CKE VDD_9 CKE VDD_9 25,26 CKEA1 CKE VDD_9 CKE VDD_9
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
25,26 ODTA0 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8 25,26 ODTA1 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
CSA0#_1 CSA1#_1
25 CSA0#_1 J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1 25 CSA1#_1 J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1
RASA0# RASA1#
25,26 RASA0# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9 25,26 RASA1# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9
CASA0# CASA1#
25,26 CASA0# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2 25,26 CASA1# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
WEA0# WEA1#
25,26 WEA0# WE VDDQ_5 E9 WE VDDQ_5 E9 25,26 WEA1# WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1 VDDQ_6 F1 VDDQ_6 F1
QSA2 F3 VDDQ_7 H2 QSA1 F3 VDDQ_7 H2 QSA5 F3 VDDQ_7 H2 QSA7 F3 VDDQ_7 H2
QSA0 C7 DQSL VDDQ_8 H9 QSA3 C7 DQSL VDDQ_8 H9 QSA4 C7 DQSL VDDQ_8 H9 QSA6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 DQSU VDDQ_9 DQSU VDDQ_9

DQMA#2 E7 A9 DQMA#1 E7 A9 DQMA#5 E7 A9 DQMA#7 E7 A9

DQMA#0 D3 DML VSS_1 B3 DQMA#3 D3 DML VSS_1 B3 DQMA#4 D3 DML VSS_1 B3 DQMA#6 D3 DML VSS_1 B3
DMU VSS_2 E1 DMU VSS_2 E1 DMU VSS_2 E1 DMU VSS_2 E1
VSS_3 G8 VSS_3 G8 VSS_3 G8 VSS_3 G8
QSA#2 G3 VSS_4 J2 QSA#1 G3 VSS_4 J2 QSA#5 G3 VSS_4 J2 QSA#7 G3 VSS_4 J2
QSA#0 B7 DQSL VSS_5 J8 QSA#3 B7 DQSL VSS_5 J8 QSA#4 B7 DQSL VSS_5 J8 QSA#6 B7 DQSL VSS_5 J8
DQSU VSS_6 M1 DQSU VSS_6 M1 DQSU VSS_6 M1 DQSU VSS_6 M1
C VSS_7 VSS_7 VSS_7 VSS_7 C
M9 M9 M9 M9
VSS_8 P1 VSS_8 P1 VSS_8 P1 VSS_8 P1
T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9
25,26 DRAM_RST# RESET VSS_10 T1 RESET VSS_10 T1 RESET VSS_10 T1 RESET VSS_10 T1
L8 VSS_11 T9 L8 VSS_11 T9 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 ZQ VSS_12 ZQ VSS_12
1

1
J1 B1 J1 B1 J1 B1 J1 B1
RV79 L1 NC1 VSSQ_1 B9 RV80 L1 NC1 VSSQ_1 B9 RV81 L1 NC1 VSSQ_1 B9 RV82 L1 NC1 VSSQ_1 B9
243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
RANKB@ L9 NC3 VSSQ_3 D8 RANKB@ L9 NC3 VSSQ_3 D8 RANKB@ L9 NC3 VSSQ_3 D8 RANKB@ L9 NC3 VSSQ_3 D8
MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2
2

2
MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8
NC6 VSSQ_6 F9 NC6 VSSQ_6 F9 NC6 VSSQ_6 F9 NC6 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1 VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 G9 VSSQ_8 G9 VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 VSSQ_9 VSSQ_9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96
@ @ @ @

+1.35VGS +1.35VGS +1.35VGS +1.35VGS

1

CV167

CV168

CV169

CV170

CV171

CV172

CV173

CV174

CV175

CV176

CV177

CV178

CV179

CV180

CV181

CV182

CV184
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
RV85 RV223 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1%
RANKB@ RANKB@
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKB@

RANKB@

RANKB@

RANKB@
CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@
B VREF_UV7_8 VREF_UV9_10 B
1

1 1
RV88 CV185 RV222 CV230
4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K
RANKB@ RANKB@ RANKB@ RANKB@ +1.35VGS +1.35VGS
2 2
2

CV188

CV189

CV190

CV191

CV192

CV193

CV194

CV195

CV196

CV197

CV198

CV199

CV200

CV201

CV202

CV203

CV204

CV205

CV206

CV207
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@
ACLU1: (10U_0603_6.3V6M)*4 CRB: 10uF *4
+1.35VGS (1U_0402_6.3V6K)*20 1uF *32
(.1U_0402_10V6-K)*13 .1uF *32
CV17

CV20

CV23

CV22
33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

1 1 1 1

2 2 2 2
@

A A

CLKA0 RV83 1 2 @ CLKA1 RV87 1 2 @

80.6_0402_1% 80.6_0402_1% For RF
CLKA0# RV84 1 2 @ CLKA1# RV90 1 2 @
80.6_0402_1% 80.6_0402_1%
1 1
CV183 CV187
.01U_0402_16V7-K .01U_0402_16V7-K Title
RANKB@ RANKB@ Security Classification LC Future Center Secret Data
2 2
Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_VRAM_B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 28 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

FOR ESD Close to Connector

LW1 UW1
USB20_N5 1 2 USB20_N5_R
1 2 Realtek_SD@ CARD_3V3 SD_CD# SD_CMD
RW2 1 2 6.2K_0402_1% RREF 1 24 VDD18 1U_0402_6.3V6K 2 1 CW1
USB20_P5 4 3 USB20_P5_R USB20_N5 RW9 1Realtek_SD@
2 0_0402_5% USB20_N5_R 2 RREF V18 23

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
4 3 9 USB20_N5 DM XD_D7

1
USB20_P5 RW10 1 2 0_0402_5% USB20_P5_R 3 22 Realtek_SD@ DW1 DW2 DW3
9 USB20_P5 4 DP SP14 21
EXC24CH900U_4P Realtek_SD@ SD_D2_R

1
+3VS 3V3_IN SP13
FOR EMI EMC_NS@ CARD_3V3_R 5 20 SD_D3_R
SDREG 6 CARD_3V3 SP12 19

0.1U_0402_10V7K
4.7U_0603_6.3V6K
7 SDREG SP11 18 SD_CMD_R
1 1 XD_CD# SP10
CW2 CW3 SD_WP_R 8 17

1U_0402_6.3V6K
SP1 GPIO0

2
Realtek_SD@ 1 9 16
Realtek_SD@ CW4 SD_D1_R 10 SP2 SP9 15 SD_CLK_R

2
2 2 SD_D0_R 11 SP3 SP8 14 EMC_NS@ EMC_NS@ EMC_NS@
12 SP4 SP7 13 SD_CD#_R
2 SP5 SP6
D D
Realtek_SD@ 25 CARD_3V3
GND

RTS5170-GRT_QFN24_4X4 CARD_3V3_R RW28 1 2 0_0603_5%

Realtek_SD@
Realtek_SD@

JREAD1 ME@
CARD_3V3_PCH F2 1 2 @ 4
VDD

.1U_0402_10V6-K
4.7U_0603_6.3V6K
0.5A_8V_KMC3S050RY 1 1 SD_D0 7
+VCCPGPPG_SDIO_PU SD_D1 8 DAT0
CW9 CW17 SD_D2 9 DAT1
SD_D3 1 DAT2
2 2 CD/DAT3
SD_D0 RW30 1 @ 2 49.9K_0402_1% SD_CD# 11
SD_WP 10 C/D
SD_D1 RW31 1 @ 2 49.9K_0402_1% W/P
Close to Connector SD_CMD 2
SD_D2 RW32 1 @ 2 49.9K_0402_1% SD_CLK 5 CMD
CLK
SD_D3 RW33 1 @ 2 49.9K_0402_1% 3 12
Realtek_SD@ 6 VSS1 GND_1 13
SD_D0_R RW3 1 2 0_0402_5% SD_D0 SD_CMD RW34 1 @ 2 49.9K_0402_1% VSS2 GND_2
CW5 1 2 5.6P_0402_50V8-D DEREN_404232501111RHF_NR
SD_D0_PCH_R3 RW19 1 @ 2 0_0402_5% SD_WP RW38 1 @ 2 49.9K_0402_1%
EMC@
+VCCPGPPG_SDIO
Realtek_SD@
SD_D1_R RW4 1 2 0_0402_5% SD_D1
CW6 1 2 5.6P_0402_50V8-D
SD / MMC
SD_D1_PCH_R3 RW18 1 @ 2 0_0402_5% SD_CD#_PCH RW132 1 @ 2 49.9K_0402_1%
EMC@

Realtek_SD@
SD_D2_R RW5 1 2 0_0402_5% SD_D2 SD_WP pull-up or pull-down reserved
C CW7 1 2 5.6P_0402_50V8-D C
SD_D2_PCH_R3 RW21 1 @ 2 0_0402_5% SD_CLK RW35 1 @ 2 49.9K_0402_1%
EMC@ SD_WP RW39 1 @ 2 49.9K_0402_1%

Realtek_SD@
SD_D3_R RW6 1 2 0_0402_5% SD_D3
CW8 1 2 5.6P_0402_50V8-D
SD_D3_PCH_R3 RW20 1 @ 2 0_0402_5%
EMC@
+3VALW +3VS CARD_3V3_PCH +VCCPGPPG_SDIO +VCCPGPPG_SDIO_PU
Realtek_SD@
SD_CMD_R RW7 1 2 0_0402_5% SD_CMD
CW11 1 2 5.6P_0402_50V8-D PCH_SDIO@ PCH_SDIO@
SD_CMD_PCH_R3 RW23 1 @ 2 0_0402_5%

D
EMC@ QW1 3 1 QW15 3 1

2
1 LP2301ALT1G_SOT23-3

1
Realtek_SD@ RW133 LP2301ALT1G_SOT23-3 CW24 CW23
SD_CLK_R RW8 1 2 0_0402_5% SD_CLK 10K_0402_5% 10U_0603_6.3V6M 1U_0402_6.3V6K

G
2

2
CW12 1 2 5.6P_0402_50V8-D PCH_SDIO@ @ PCH_SDIO@

2
SD_CLK_PCH_R3 RW22 1 @ 2 0_0402_5% 2

1
EMC@

Realtek_SD@
SD_CD#_R RW25 1 2 0_0402_5% SD_CD# 44 EC_SD_PWR_EN# EC_SD_PWR_EN# EC_SD_PWR_EN#
1 1
SD_CD#_PCH RW27 1 @ 2 0_0402_5% CW19 CW22
8 SD_CD#_PCH
0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCH_SDIO@ PCH_SDIO@
Realtek_SD@ 2 2
SD_WP_R RW24 1 2 0_0402_5% SD_WP

SD_WP_PCH RW26 1 @ 2 0_0402_5%

8 SD_WP_PCH

+3VALW
B B
+3VALW

2
+3VALW
RW128
10K_0402_5%
PCH_SDIO@

1
2

3
S
SD_D0_PCH RW40 1 @ 2 0_0201_5% SD_D0_PCH_R1 RW47 1 @ 2 0_0201_5% SD_D0_PCH_R3 QW14
8 SD_D0_PCH G
RW127 SD_1P8_SEL_3.3V_EN RW130 2 1 10K_0402_5% 2 LP2301ALT1G_SOT23-3
RW46 1 2 0_0201_5% SD_D0_PCH_R2 RW48 1 2 0_0201_5% 10K_0402_5% PCH_SDIO@ PCH_SDIO@
PCH_SDIO@ PCH_SDIO@ PCH_SDIO@ 1
D

1
CW21

1
0.1U_0402_10V7K

D2 3
SD_D1_PCH RW49 1 @ 2 0_0201_5% SD_D1_PCH_R1 RW51 1 @ 2 0_0201_5% SD_D1_PCH_R3 PCH_SDIO@
8 SD_D1_PCH 2
QW12B
RW50 1 2 0_0201_5% SD_D1_PCH_R2 RW52 1 2 0_0201_5% SD_1P8_SEL_1.8V_EN 5 G2 PJT138K_SOT363-6
PCH_SDIO@ PCH_SDIO@ PCH_SDIO@ +VCCPGPPG_SDIO

4 S2
1 2 0_0201_5% 1 2 0_0201_5%

D1 6
SD_D2_PCH RW53 @ SD_D2_PCH_R1 RW55 @ SD_D2_PCH_R3
8 SD_D2_PCH
QW12A
RW54 1 2 0_0201_5% SD_D2_PCH_R2 RW56 1 2 0_0201_5% SD_1P8_SEL 2 G1 PJT138K_SOT363-6
8 SD_1P8_SEL
PCH_SDIO@ PCH_SDIO@ PCH_SDIO@

1 S1
1

3
S
SD_D3_PCH RW57 1 @ 2 0_0201_5% SD_D3_PCH_R1 RW59 1 @ 2 0_0201_5% SD_D3_PCH_R3 RW131 QW2
8 SD_D3_PCH G
49.9K_0402_1% SD_1P8_SEL_1.8V_EN RW129 2 1 10K_0402_5% 2 LP2301ALT1G_SOT23-3
RW58 1 2 0_0201_5% SD_D3_PCH_R2 RW60 1 2 0_0201_5% PCH_SDIO@ PCH_SDIO@ PCH_SDIO@
PCH_SDIO@ PCH_SDIO@ 1
D
2

1
CW20
0.1U_0402_10V7K
SD_CMD_PCH RW61 1 @ 2 0_0201_5% SD_CMD_PCH_R1 RW63 1 @ 2 0_0201_5% SD_CMD_PCH_R3 @
8 SD_CMD_PCH 2
RW62 1 2 0_0201_5% SD_CMD_PCH_R2 RW64 1 2 0_0201_5%
A PCH_SDIO@ PCH_SDIO@ A

+1.8VALW
SD_CLK_PCH RW65 1 @ 2 0_0201_5% SD_CLK_PCH_R1 RW67 1 @ 2 0_0201_5% SD_CLK_PCH_R3
8 SD_CLK_PCH
RW66 1 2 0_0201_5% SD_CLK_PCH_R2 RW68 1 2 0_0201_5%
PCH_SDIO@ PCH_SDIO@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Cardreader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 30 of 60
5 4 3 2 1
 5 4 3 2 1

VCCRTC

1
CG16
390_0402_5%
D GCLK@ D
UG1

2
10 14 CG3 1 2 GCLK@
VRTC VOUT
15 2.2U_0402_6.3V6M
+3VL V3.3A
1
2
+3VALW VDD
CG9 9
32.768K RTC_CLK 10
22U_0603_6.3V6-M
2
GCLK@ 11 12 1 2 33_0402_5%
+1.8VGS CLK_27M RG5
VIOE_27M 27M 27M_CLK 21
GCLK@
8 6 CLK_25M RG3 1 2 33_0402_5%
+3VALW_LAN VIO_25M 25M 25M_CLK 37
GCLK@
VIOE_24 3 5 CLK_24M RG4 1 2 33_0402_5%
VIOE_24M 24M 24M_CLK 10
GCLK@
GCLK_XTALI 1
+1.0VALW GCLK_XTALO 16 X1
1 X2

GND1
GND2
GND3

GND4
CG8
.1U_0402_10V6-K
C 2 C

4
7
13

17
GCLK@ SLG3NB3377VTR_TQFN16_2X3
1

GCLK@
RG7
0_0402_5%
2

GCLK@
VIOE_24

+3VL

1
CG5 GCLK_XTALI
EMC_NS@
.1U_0402_10V6-K
2 YG1 GCLK@ GCLK_XTALO CLK_27M CG12 1 2 6P_0402_50V8D
B GCLK@ B
3 2
OSC2 GND1 EMC_NS@
4 1 CLK_25M CG13 1 2 6P_0402_50V8D
GND2 OSC1
1 1
CG1 25MHZ_10PF_X1E000021013300 CG2
15P_0402_50V8J 15P_0402_50V8J
GCLK@ GCLK@
+3VALW +3VALW_LAN +1.8VGS 2 2 EMC_NS@
CLK_24M CG15 1 2 6P_0402_50V8D

1 1 1
For EMC
CG4 CG6 CG10
.1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K
2 2 2
GCLK@ GCLK@ GCLK@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Greenclk
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

D D

+3VS
+3VS_TPM
1A RTPM11 TPM@ 2 0_0603_5%
1 1
1 CTPM3
CTPM4 CTPM1 .1U_0402_10V6-K
TPM .1U_0402_10V6-K 10U_0603_6.3V6M TPM@
TPM@ 2 TPM@ 2
2

+3VS_TPM
UTPM1 TPM@
1 24
2 NC_1 VDD3 10
C 3 NC_2 VDD1 C
7 NC_3 28 RTPM2 1 TPM@ 2 4.7K_0402_5%
PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
6 SERIRQ 26 SERIRQ 7,44
LPC_AD0_TPM RTPM6 1 TPM@ 2 0_0402_5%
9 NC_4 LAD0 23 LPC_AD0 7,44
LPC_AD1_TPM RTPM7 1 TPM@ 2 0_0402_5%
NC_7 LAD1 22 LPC_AD1 7,44
LPC_FRAME#_TPM RTPM8 1 TPM@ 2 0_0402_5%
LFRAME# LPC_FRAME# 7,44
4 20 LPC_AD2_TPM RTPM9 1 TPM@ 2 0_0402_5%
11 GND_1 LAD2 17 LPC_AD2 7,44
LPC_AD3_TPM RTPM10 1 TPM@ 2 0_0402_5%
+3VS_TPM 18 GND_2 LAD3 LPC_AD3 7,44
GND_3 25 +3VS_TPM
5 GND_4 21
8 NC_5 LCLK 19 CLK_PCI_TPM 7
12 NC_6 VDD2 15 RTPM4 1 TPM@ 2 0_0402_5%
13 NC_8 CLK_RUN#
14 NC_9 16
NC_10 LRESET# PLT_RST# 11,20,37,40,44

Z32H320TC_TSSOP28

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 32 of 60
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+3VS +3VS Need short +3VS_CMOS_R
+LCDVDD +LCDVDD_CON J1 @
1 2
U5 0_0805_5% 1 2
5 1 2 1 R263 W=60mils JUMP_43X39
IN OUT +3VS_CMOS

33P_0402_50V8J
.1U_0402_10V6-K
C121

C122

C123
4.7U_0603_6.3V6K
1 2
GND LP2301ALT1G_SOT23-3
1 1 1
C1 PCH_ENVDD 4 3 W=40 mils W=40mils
EN FLG

D
.1U_0402_10V6-K Q7 3 1 R3 1 @ 2
2

.01U_0402_16V7-K
D 0_0603_5% D

EMC_NS@
2 2 2

C6
AP22802AW5-7_SOT25-5 @ 1 1
C3 C4

G
1 1

2
U5 EN PIN VIH MIN 1.5V @
C5
.1U_0402_10V6-K
.1U_0402_10V6-K
CD@
10U_0603_6.3V6M
@
@ 2 2
2 @2

PCH_ENVDD For RF R5 1 @ 2
4 PCH_ENVDD 8 CMOS_ON#
100K_0402_5%

1
1 1
R1 C9 C10
100K_0402_5% 0.01U_0402_25V7K For EMI .1U_0402_10V6-K
EMC_NS@ Close to R5 @
2 2

2
+3VS

+3VS
EMI request

2
R8 R9
2

100K_0402_1% 100K_0402_1% DMIC_CLK DISPOFF# INVT_PWM

470P_0402_50V7K
R10

470P_0402_50V7K
100P_0402_50V8J
C11

C12

C13
PCH_ENBKL R11 1 @ 2 4.7K_0402_5% @ @

1
0_0402_5% @ 1 1 1
EMC_NS@ EMC_NS@
1

EDP_AUX EMC@
R12 1 @ 2 0_0402_5% DISPOFF# B+ +LEDVDD EDP_AUX#
44 BKOFF# 2 2 2
2A 80 mil 0_0805_5% 2A 80 mil

2
R14 1 @ 2 0_0402_5% ENBKL 2 1 R17
4 PCH_ENBKL ENBKL 44

4.7U_0805_25V6-K
C14 R13 R15
1

C C

0.1U_0402_25V6
1 1 100K_0402_1% 100K_0402_1%
R16 C15
100K_0402_5% AO3401A_SOT23-3 EMC@ @ @

1
2 2

D
Q33 3 1 @
2

EMI Request JEDP1

+LEDVDD 1
CD@ 2 1

G
2
3 2
+3VS R179 1 @ 2 LEDVDD_EN# 4 3
B+ 4
100K_0402_5% CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 5
4 CPU_EDP_TX0+ 5
CPU_EDP_TX0- C16 1 2 .1U_0402_10V6-K EDP_TX0- 6
4 CPU_EDP_TX0- 6
2

1
7
R18 R180 CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 8 7
4 CPU_EDP_TX1+ 8
1K_0402_5% 100K_0402_5% CPU_EDP_TX1- C18 1 2 .1U_0402_10V6-K EDP_TX1- 9
4 CPU_EDP_TX1- 9
@ @ 10
CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 11 10
4 CPU_EDP_AUX
1

1 2
CPU_EDP_AUX# C21 1 2 .1U_0402_10V6-K EDP_AUX# 12 11
4 CPU_EDP_AUX# 12
R19 1 @ 2 0_0402_5% INVT_PWM Q34 D 13
4 PCH_EDP_PWM 13
PCH_ENVDD R181 1 @ 2 2 DISPOFF# 14
0_0402_5% G 15 14
15
1

1 INVT_PWM 16
R20 C132 @ S 17 16
3

100K_0402_5% .1U_0402_10V6-K 2N7002KW_SOT323-3 +3VS 18 17

@ 19 18
2 4 CPU_EDP_HPD 19
R21 1 @ 2 20
2

0_0402_5% 21 20
1 +LCDVDD_CON 21
W=60mils 22
EMC_NS@ C22 23 22
Reserve for power consumption test +3VS 23
680P_0402_50V7K 43 DMIC_DATA 24
2 25 24
43 DMIC_CLK 25
26 31
27 26 G1 32
R182 1 2 0_0402_5% USB20_P4_R 28 27 G2 33
9 USB20_P4 28 G3
B R183 1 2 0_0402_5% USB20_N4_R 29 34 B
9 USB20_N4 29 G4
+3VS_CMOS 30 35
30 G5
2
Touch Screen C24
W=40mils ACES_50406-03071-001
ME@
0.047U_0402_16V7K
EMC_NS@1

+3VS +3VS_TS

R26 1 TS@ 2 0_0402_5%

EMI request
JTS1
1
C25 1
.1U_0402_10V6-K R28 2 TS@ 1 0_0402_5% TS_RS 2 1 7
44 EC_TS_ON# 2 GND1
TS@ 3
2 R23 1 TS@ 2 0_0402_5% USB20_N6_CONN 4 3 8
9 USB20_N6 4 GND2
R24 1 TS@ 2 0_0402_5% USB20_P6_CONN 5
9 USB20_P6 5
6
6 For EMI
CVILU_CI1806M2HR0-NH L12 EMC_NS@
USB20_P6_CONN USB20_P4 1 2 USB20_P4_R
ME@ 1 2
+3VS_TS USB20_N6_CONN Touch Screen USB20_N4 4 3 USB20_N4_R
4 3
3

EXC24CH900U_4P
1

EMC_NS@
D2
1

For EMI
L15 D1
2

USB20_P6 1 2 USB20_P6_CONN AZC199-02S.R7G_SOT23-3

A 1 2 EMC_NS@ A
2

AZ5215-01F_DFN1006P2E2
USB20_N6 4 3 USB20_N6_CONN
1

4 3
EXC24CH900U_4P For EMI
EMC_NS@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 eDP/ CMOS/Touch screen

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

L2 EMC@ EMC_NS@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2 C26 3.3P_0402_50V8-C
EMC_NS@
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
EXC24CH900U_4P
+3VS
D L3 EMC@ EMC_NS@ D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2
1 2 C28 3.3P_0402_50V8-C
EMC_NS@
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2
4 3 C29 3.3P_0402_50V8-C

5
EXC24CH900U_4P

G
Q1B D3
L4 EMC@ EMC_NS@ HDMI_DET 1 1 10 9 HDMI_DET
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2
1 2 4 3 2 2
C30 3.3P_0402_50V8-C HDMICLK_R HDMIDAT_R 9 8 HDMIDAT_R

S
4 DDPB_CLK

D
EMC_NS@
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 2N7002KDWH_SOT363-6 HDMICLK_R 4 4 7 7 HDMICLK_R
4 3

2
C31 3.3P_0402_50V8-C

G
EXC24CH900U_4P Q1A +5VS_HDMI 5 5 6 6 +5VS_HDMI

L5 EMC@ EMC_NS@ 3 3
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 1 6 HDMIDAT_R

S
1 2 4 DDPB_DATA

D
C32 3.3P_0402_50V8-C 8
EMC_NS@ 2N7002KDWH_SOT363-6
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 C33 3.3P_0402_50V8-C AZ1045-04F_DFN2510P10E-10-9
EXC24CH900U_4P EMC_NS@

For EMC
For EMC

C C
HDMI_CLK-_C R29 1 2 470_0402_5% +5VS +5VS_HDMI_F +5VS_HDMI
D5
HDMI_CLK+_C R30 1 2 470_0402_5% +5VS 2 F1
+3VS 1 1 2
HDMI_TX0-_C R31 1 2 470_0402_5% 3

2
D4 RB491D_SOT23-3 0.5A_8V_KMC3S050RY
HDMI_TX0+_C R32 1 2 470_0402_5% @

HDMI_TX1-_C R33 1 2 470_0402_5% @ LP2301ALT1G_SOT23-3

2
HDMI_TX1+_C R34 1 2 470_0402_5% BAT54S-7-F_SOT23-3 1 3 Q22

S
R35

1
2
Q12 D4

G
1M_0402_5%
HDMI_TX2-_C R37 1 2 470_0402_5% 1
C34

G
1

2
HDMI_TX2+_C R38 1 2 470_0402_5% .1U_0402_10V6-K

2
3 1
4 HDMI_HPD 46 SUSP 2

D
R39 R40
1

D Q13 2N7002KW_SOT323-3 2.2K_0402_5% 2.2K_0402_5%

2
2
+3VS
G 2N7002KW_SOT323-3 R41

1
20K_0402_5%
S JHDMI1
3

HDMI_DET 19

1
R42 1 @ 2 18 HP_DET
17 +5V
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
4 HDMI_CLK- CK- GND1
11 21
B HDMI_CLK+ C36 2 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 B
4 HDMI_CLK+ CK+
HDMI_TX0- C37 2 1 .1U_0402_10V6-K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 22
4 HDMI_TX0- D0- GND3
8 23
HDMI_TX0+ C38 2 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield GND4
4 HDMI_TX0+ D0+
HDMI_TX1- C39 2 1 .1U_0402_10V6-K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6
4 HDMI_TX1- D1-
5
HDMI_TX1+ C40 2 1 .1U_0402_10V6-K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
4 HDMI_TX1+ D1+
HDMI_TX2- C41 2 1 .1U_0402_10V6-K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3
4 HDMI_TX2- D2-
2
HDMI_TX2+ C42 2 1 .1U_0402_10V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
4 HDMI_TX2+ D2+
FOX_QJ111A1-RC0AH1-8H
ME@

Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

A A
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 34 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS +DP_3V3

+IVDDO +RX_AVCC
RVG16 1 2 0_0603_5%
Change to SA000072B10 IT6515FN/BX-0051
1 LVG2 1 2

.1U_0402_10V6-K
BLM15PD600SN1D_2P
CVG8 +DP_3V3+DP_3V3 +IVDDO +RX_IVDD
1 1

CVG15
10U_0805_10V6K
D 2 CVG10 D

10U_0603_6.3V6M
2 2

10
40

29
30

32

11
20
37
39
UVG1 +DDCP

IVDDO
OVDD_1
OVDD_2

IVDD33_1
IVDD33_2

IVDD_1
IVDD_2
IVDD_3
IVDD_4
DP_VGA_HPD 33
4 DP_VGA_HPD HPD
38 +IVDDO +RX_IVDD
CVG3 1 2 .1U_0402_10V6-K DRX0P 22 MCUVDDH
4 VGA_TX0+ RX0P
CVG2 1 2 .1U_0402_10V6-K DRX0N 23
4 VGA_TX0- RX0N RVG19 1 2 0_0603_5%

.1U_0402_10V6-K
CVG4 1 2 .1U_0402_10V6-K DRX1P 25
4 VGA_TX1+ RX1P
CVG5 1 2 .1U_0402_10V6-K DRX1N 26 1
4 VGA_TX1- RX1N

CVG16
24 @1 TVG1
URDBG
12 2
ISPSCL 13
CVG6 1 2 .1U_0402_10V6-K AUXP 19 ISPSDA
4 VGA_AUX RXAUXP
CVG7 1 2 .1U_0402_10V6-K AUXN 18 17
4 VGA_AUX# RXAUXN VGADDCCLK 16 CRT_DDC_CLK 36
+DP_3V3 VGADDCSDA CRT_DDC_DAT 36
15 1 VGA_VS
14 DCAUXP VSYNC 2 VGA_HS VGA_VS 36
DCAUXN HSYNC VGA_HS 36
+IVDDO +DAC_VDDC
+DAC_VDDC
+RX_AVCC
LVG4 1 2

4.7U_0805_25V6-K
C C

.1U_0402_10V6-K
21 6 BLM15PD600SN1D_2P CVG11
27 AVCC_1 VDDC
AVCC_2 1 1

CVG17
IT6515FN 2 2
9 CRT_R
IORP CRT_R 36

8 CRT_G
IOGP CRT_G 36

7 CRT_B
IOBP CRT_B 36
34
NC_2
3 RVG3 1 2 200_0402_1%
28 RSET +DAC_VDDC
ASPVCC RVG3 closed to pin3
5
VDDA
+DDCP
RPVG1 4
3 2 36 NC_1
4 1 35 PCSDA
+DP_3V3 +CRT_VCC_CON PCSCL

2.2K_0404_4P2R_5%

PWD

GND
RVG1 1 2 0_0402_5% +DDCP
IT6515FN-BX-0051_QFN40_5X5 CRT_R

31

41
B B
RVG2 1 2 0_0402_5% 1
@ CRT_G

TVG2 CRT_B
@

1
RVG25 RVG26 RVG27
+DP_3V3 75_0402_1% 75_0402_1% 75_0402_1%

2
2
1

RPVG2 CLOSE TO UVG1

2.2K_0404_4P2R_5%
CD@
3
4

CRT_DDC_CLK

CRT_DDC_DAT

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 DP to CRT Convert(IT6515FN)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 35 of 60
5 4 3 2 1
 5 4 3 2 1

+DP_3V3 +CRT_VCC_CON

CRT Connector

5
G

2
1
QVG1B +CRT_VCC_CON +5VS_HDMI
RPVG3
+5VS @
2.2K_0404_4P2R_5% +CRT_VCC
CRT_DDC_CLK 4 3 CRT_DDC_CLK_R RVG39 1 2 0_0603_5%

S
35 CRT_DDC_CLK

D
CD@ DVG1

3
4
2N7002KDWH_SOT363-6 CRT_DDC_CLK_R @ 2 FVG1

2
1 1 2 @ +CRT_VCC_CON

G
QVG1A 3 1
D CRT_DDC_DAT_R PMEG2010ET_SOT23-3 0.5A_8V_KMC3S050RY D

1
CVG34
CRT_DDC_DAT 1 6 CRT_DDC_DAT_R .1U_0402_10V6-K DVG2
W=40mils

S
1 1

1
35 CRT_DDC_DAT 2

D
CD@ AZ5425-01F_DFN1006P2E2
2N7002KDWH_SOT363-6 CVG43 CVG44 CD@
100P_0402_50V8J 68P_0402_50V8J EMC_NS@
CRT_DDC_CLK RVG5 1 2 0_0402_5% CRT_DDC_CLK_R @ 2 2 @

2
2
CRT_DDC_DAT RVG4 1 2 0_0402_5% CRT_DDC_DAT_R JCRT1
6
11
LVG6 1 2 EMC@ CRT_R_CON 1
35 CRT_R 7
BLM15BA220SN1D_2P For EMC
CRT_DDC_DAT_R 12
LVG7 1 2 EMC@ CRT_G_CON 2
35 CRT_G 8
BLM15BA220SN1D_2P
HSYNC_CON 13
LVG8 1 2 EMC@ CRT_B_CON 3
35 CRT_B 9
BLM15BA220SN1D_2P
VSYNC_CON 14

15P_0402_50V8J
CVG35

15P_0402_50V8J
CVG36

15P_0402_50V8J
CVG37

15P_0402_50V8J
CVG38

15P_0402_50V8J
CVG39

15P_0402_50V8J
CVG40
1 1 1 1 1 1 4
10 G 16
CRT_DDC_CLK_R 15 G 17
5
2 2 2 2 2 2
1
CVG41 SUYIN_070546HR015M25KZR
100P_0402_50V8J ME@
EMC@ EMC@ EMC@ EMC@ EMC@ EMC@ @
2

C C

VGA_HS RVG32 1 2 33_0402_5% HSYNC_CON

35 VGA_HS

1
CVG42
10P_0402_50V8-J
2

B B

VGA_VS RVG33 1 2 33_0402_5% VSYNC_CON

35 VGA_VS
1
CVG45
10P_0402_50V8-J
2

DVG3 DVG4
CRT_B_CON 1 1 10 9 CRT_B_CON VSYNC_CON 1 1 10 9 VSYNC_CON

CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON

CRT_R_CON 4 4 7 7 CRT_R_CON CRT_DDC_CLK_R 4 4 7 7 CRT_DDC_CLK_R

5 5 6 6 CRT_DDC_DAT_R 5 5 6 6 CRT_DDC_DAT_R

3 3 3 3
A A
8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@
For EMC
Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 CRT_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 36 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms＜
＜ spec＜
＜ 100ms +3VALW_LAN +LAN_VDDREG
Need short
RL1 @
JL1 1 2 @ width : 40 mils 1 2
1 2
JUMP_43X79 0_0603_5%
D D
1 1
+3VALW

.1U_0402_10V6-K

.1U_0402_10V6-K
LP2301ALT1G_SOT23-3 CL1 CL2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K

D
3 1 @

.1U_0402_10V6-K

.01U_0402_16V7-K
Q14 CL4 CL5 CL6 CL7

1
2 2
@
RL2 1 1
100K_0402_5% CL8 CL9 @ 2 @ 2 2 2 CD@

G
2
@
2

2 2
RL3 1 @ 2 @ @
44 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
@

2
RL4

G
2
RL5
manual change the Codec PN to RTL8111H-CG QFN 10K_0402_5% QL1

10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 10

S
1
2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
11,40,44 PCIE_WAKE#
40,44 LAN_WAKE# RL6 1 2 0_0402_5%
33 RL18 1 @ 2 0_0402_5%
C +3VALW_LAN 32 GND 16 CLK_PCIE_LAN# C
1 2 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN# 10
RL8 RSET CLK_PCIE_LAN
RSET REFCLK_P CLK_PCIE_LAN 10
2.49K_0402_1% +LAN_VDD10 30 14 PCIE_PTX_C_DRX_N5
29 AVDD10 HSIN 13 PCIE_PTX_C_DRX_N5 9
LAN_XTALO PCIE_PTX_C_DRX_P5
CKXTAL2 HSIP PCIE_PTX_C_DRX_P5 9
LAN_XTALI 28 12 LAN_CLKREQ#_R
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
@ LED0 AVDD33_1
LAN_PWR_ON# RL121 2 LAN_DISABLE# 26 10 LAN_MDI3-
LED1/GPIO MDIN3 LAN_MDI3- 38
0_0402_5% TL4 @ 1 25 9 LAN_MDI3+
LED2 MDIP3 LAN_MDI3+ 38
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
22 VDDREG MDIN2 6 LAN_MDI2- 38
1K_0402_1% +LAN_VDD10 LAN_MDI2+
21 DVDD10 MDIP2 5 LAN_MDI2+ 38
PCIE_WAKE#_R LAN_MDI1-
LANW AKEB MDIN1 LAN_MDI1- 38
ISOLATE# 20 4 LAN_MDI1+
2

19 ISOLATEB MDIP1 3 LAN_MDI1+ 38

PLT_RST# +LAN_VDD10
11,20,32,40,44 PLT_RST# PERSTB AVDD10_1
9 PCIE_PRX_DTX_N5 CL10 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_N5 18 2 LAN_MDI0-
HSON MDIN0 LAN_MDI0- 38
ISOLATE# RL10 1 @ 2 LAN_PWR_ON#
9 PCIE_PRX_DTX_P5 CL11 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_P5 17 1 LAN_MDI0+
HSOP MDIP0 LAN_MDI0+ 38
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17

15K_0402_5%
@
2

RTL8111H-CG QFN 32P

B B

LAN_XTALI
For RTL8111GUL(SWR mode, reserved)
LAN_XTALO_R 1 2 LAN_XTALO For RTL8111H (LDO mode)
+LAN_VDD10
YL1 RL21 1K_0402_5% LL1 1 2 @
2.2UH_NLC252018T-2R2J-N_5%
1 4
OSC1 GND2 +LAN_REGOUT RL20 1 2 0_0805_5%
2 3
GND1 OSC2
1 1 1 1 1 1 1 1
1 1
CL12 25MHZ_10PF_X1E000021013300 CL13 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
15P_0402_50V8J 15P_0402_50V8J 4.7U_0603_6.3V6K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
2 2 2 2 2 2 2 @ 2 @
2 2 @ @ CD@

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

Layout Note: LL1 must be
GCLK@ within 200mil to Pin24,
31 25M_CLK RL19 1 2 0_0402_5% LAN_XTALI CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 LAN_RTL8111H_CG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00
TL1
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0+ 23 2 LAN_MDO0+
37 LAN_MDI0+ MX1+ TD1+
DL1
LAN_MDI2+ 1 10 LAN_MDI2+ LAN_MDI0- 22 3 LAN_MDO0-
Tx1+In Tx1+Out 37 LAN_MDI0- MX1- TD1-

1
LAN_MDI2- 2 9 LAN_MDI2- EMC@
Tx1-In Tx1-Out 21 4 MCT RL17
3 8 MCT2 TCT2 20_0603_5%
GND1 GND2

1
LAN_MDI1+ 20 5 LAN_MDO1+
37 LAN_MDI1+ MX2+ TD2+
LAN_MDI3+ 4 7 LAN_MDI3+ DL3

1
2
LAN_MDI3- 5 Tx2+In Tx2+Out 6 LAN_MDI3- LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
Tx2-In Tx2-Out 37 LAN_MDI1- MX2- TD2- EMC@

2
11 18 7 MCT EMC
GND3 12 MCT3 TCT3

2
GND4 13 LAN_MDI2+ 17 8 LAN_MDO2+
GND5 37 LAN_MDI2+ MX3+ TD3+
RCLAMP3374N.TCT_SLP3020N10-10 LAN_MDI2- 16 9 LAN_MDO2-
37 LAN_MDI2- MX3- TD3-
EMC_SKU2@
15 10 MCT
MCT4 TCT4
1 1
DL2 LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25
37 LAN_MDI3+ MX4+ TD4+
LAN_MDI1- 1 10 LAN_MDI1- 0.022U_0603_50V7K 1000P_1206_2KV7-K
LAN_MDI1+ 2 Tx1+In Tx1+Out 9 LAN_MDI1+ LAN_MDI3- 13 12 LAN_MDO3- EMC@ EMC@
Tx1-In Tx1-Out 1 37 LAN_MDI3- MX4- TD4- 2 2
EMC
3 8 CL24
C GND1 GND2 C
0.01UF_0402_25V7-K BOTH_GST5009 LF
LAN_MDI0- 4 7 LAN_MDI0- 2
5 Tx2+In Tx2+Out 6 EMC@
LAN_MDI0+ LAN_MDI0+ EMC
Tx2-In Tx2-Out
11
GND3 12
GND4 13 CHASSIS1_GND
GND5
RCLAMP3374N.TCT_SLP3020N10-10
EMC_SKU2@

Place Close to TL1

EMC

JRJ1 ME@
12
GND_4
11
GND_3
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
LAN_MDO1+ 3
PR2+ CHASSIS1_GND
RL14 1 EMC_NS@
2 0_0603_5% LAN_MDO2+ 4
PR3+
RL15 1 EMC_NS@
2 0_0603_5% LAN_MDO2- 5
PR3-
RL16 1 EMC_NS@
2 0_0603_5% LAN_MDO1- 6
PR2-
EMC LAN_MDO3+ 7
PR4+
LAN_MDO3- 8
CHASSIS1_GND PR4-

SANTA_130460-3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 38 of 60
5 4 3 2 1
 5 4 3 2 1

R175 1 @ 2 0_0402_5% REMOTE1+

REMOTE2+
Close to U1 REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+
Near GPU&VRAM Near CPU core
1

1
REMOTE+_R 1 C46 C

1
1 C45 C 100P_0402_50V8J 2 Q16
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 100P_0402_50V8J 2 Q15 @ B MMBT3904WH_SOT323-3
2200P_0402_50V7K @ B MMBT3904WH_SOT323-3 2 E @

3
@ 2 E @ REMOTE2-

3
2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- REMOTE1-

+3VALW
D REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW D

Trace width/space:10/10 mil Near CPU

Trace length:<8"

1
R36
13.7K_0402_1% R25
SMSC thermal sensor PX@ 13.7K_0402_1%

placed near DIMM

2
NTC_V1

2
NTC_V2

1
+3VS

1
U1 PH2
1 8 EC_SMB_CK2 100K_0402_1%_NCP15WF104F03RC PH3
VDD SCL EC_SMB_CK2 7,21,44
PX@ 100K_0402_1%_NCP15WF104F03RC
1 REMOTE+_R 2 7 EC_SMB_DA2
EC_SMB_DA2 7,21,44

2
D+ SDA
C47

2
.1U_0402_10V6-K REMOTE-_R 3 6
D- ALERT#

2
@
2 R51 2 @ 1 4 5 R184 R185
+3VS T_CRIT# GND
10K_0402_5% 0_0402_5% 0_0402_5%
NCT7718W_MSOP8 @ PX@ @
Address 1001_101xb

1
EC_AGND

+5VLP +5VLP for layout optimized, change the EC_AGND to GND

C +5VLP C

HW thermal sensor

2
C7 R252 R253
1

0.1U_0402_25V6 21.5K_0402_1% 21.5K_0402_1%

@ @
@
2

1
@
U4
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 44
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
54 EC_ON_R OT1 TMSNS2 NTC_V2 44
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

over temperature threshold:

RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C
B B

FAN Conn
+5VS

JFAN1
R52 1 2 0_0603_5% +5VS_FAN 1
2 1
44 EC_FAN_SPEED 2
3
.1U_0402_10V6-K

4 3
1 1 44 EC_FAN_ANTI 4
C49 @ 44 EC_FAN_PWM 5
5
C50

10U_0805_10V6K 6
7 GND1
2 2 GND2
ACES_50273-0050N-001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Thermal sensor/FAN CONN/TPM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 39 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3VS
+3VS_W LAN

JW LAN1
1 1

1
1 2
3 GND1 3.3VAUX1 4 R258 R259
9 USB20_P7 USB_D+ 3.3VAUX2
5 6 1 @ T2 49.9K_0402_1% 49.9K_0402_1%
9 USB20_N7 USB_D- LED#1
7 8
9 GND2 PCM_CLK 10

2
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0 PCM_OUT 16 1 @ T3
17 SDIO_DAT1 LED#2 18
19 SDIO_DAT2 GND11 20
21 SDIO_DAT3 UART_WAKE 22 UART_RX_DEBUG_R R256 1 2 0_0402_5%
SDIO_WAKE UART_RX UART_RX_DEBUG 8
23
SDIO_RESET

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32 UART_TX_DEBUG_R R257 1 2 0_0402_5%

GND3 UART_TX UART_TX_DEBUG 8
35 34
9 PCIE_PTX_C_DRX_P6 PETP0 UART_CTS
37 36
9 PCIE_PTX_C_DRX_N6 PETN0 UART_RTS
39 38 EC_TX_RSVD R62 1 @ 2 0_0402_5%
41 GND4 RSRVD10 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
9 PCIE_PRX_DTX_P6 PERP0 RSRVD11
43 42
9 PCIE_PRX_DTX_N6 PERN0 RSRVD9
45 44 R88 1 2 0_0402_5%
GND5 COEX3 EC_RX 44
47 46
10 CLK_PCIE_W LAN REFCLKP0 COEX2
49 48
10 CLK_PCIE_W LAN# REFCLKN0 COEX1
2 51 50 SUSCLK_R R55 1 2 0_0402_5% 2
GND6 SUSCLK SUSCLK 10
W LAN_CLKREQ_Q# 53 52 PLT_RST#
CLKEQ0# PERSTO# PLT_RST# 11,20,32,37,44
R262 1 @ 2 0_0402_5% PCIE_W AKE#_W LAN 55 54 BT_OFF# R53 1 2 1K_0402_5%
11,37,44 PCIE_W AKE# PEWAKE0# RSRVD/W_DISABLE#2 PCH_BT_OFF# 8
57 56 W LAN_OFF# R56 1 @ 2 0_0402_5%
GND7 W_DISABLE#1 PCH_W LAN_OFF# 8
R57 1 @ 2 0_0402_5%
37,44 LAN_W AKE#
59 58 W LAN_SMB_DATA R58 1 @ 2 0_0402_5%
RSRVD/PETP1 I2C_DATA SMB_DATA_S3 7,17,18
61 60 W LAN_SMB_CLK R59 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK SMB_CLK_S3 7,17,18
63 62
65 GND8 ALERT 64 EC_TX_R R89 1 2 0_0402_5%
RSRVD/PERP1 RSRVD6 EC_TX 44
67 66
69 RERVD/PERN1 RSRVD7 68 +3VS_W LAN

1
71 GND9 RSRVD8 70
73 RSRVD1 RSRVD12 72 R186
75 RSRVD2 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76

2
GND15 GND14

LCN_DAN05-67406-0102
ME@

3 3

+3VS +3VS Need short +3VS_W LAN

+3VS_W LAN J2 @
1 2
1 2
2

JUMP_43X79
2

R60
G

Q18 10K_0402_5%
AOAC@ +3VALW LP2301ALT1G_SOT23-3
1

D
10 W LAN_CLKREQ# AOAC@ 3 1 W LAN_CLKREQ_Q# Q17 3 1 AOAC@
S

.01U_0402_16V7-K
2N7002KW _SOT323-3 1 1 1
C51 C52 C53

G
2
.1U_0402_10V6-K @ .1U_0402_10V6-K
@ AOAC@
R61 1 @ 2 0_0402_5% 2 2 2
R54 1 AOAC@ 2
44 AOAC_ON#
1
If support AOAC, NC R61; 100K_0402_5% C54
.1U_0402_10V6-K
if not support AOAC, stuff R61. AOAC@
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 40 of 60
A B C D E
 A B C D E

+USB_VCCA

C55 1 2

+
220U_6.3V_M
C125 1 2
@ 1U_0603_25V6M

C127 1 2
@ 1U_0603_25V6M
1 LEFT SIDE USB3.0 PORT x1 JUSB1 ME@
1

USB30_TX_P1 C126 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9

9 USB30_TX_P1 1 StdA_SSTX+
USB30_TX_N1 C124 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
9 USB30_TX_N1 1 2 0_0402_5% 3 StdA_SSTX-
USB20_P1 R97 @ USB20_P1_R
9 USB20_P1 7 D+
+5VALW +USB_VCCA USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
9 USB20_N1 USB30_RX_P1 1 2 0_0402_5% USB30_RX_R_P1 6 D- GND_1 11
U2 R94 @
5 1 9 USB30_RX_P1 4 StdA_SSRX+ GND_2 12
IN OUT USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
1 9 USB30_RX_N1 StdA_SSRX- GND_4
C128 2
1U_0402_6.3V6K GND SUYIN_020053GR009M2736L
4 3 USB_OC1#
2 44,45 USB_ON# ENB OCB USB_OC1# 9
SY6288D20AAC_SOT23-5 1
C140
1000P_0402_50V7K
Low Active 2A EMC_NS@
2

2 2

L13 EMC@
USB30_RX_P1 1 2 USB30_RX_R_P1
1 2

USB30_RX_N1 4 3 USB30_RX_R_N1
4 3
EXC24CH900U_4P

+USB_VCCA D12 EMC_NS@ USB20_P1_R

L16 EMC@ USB30_RX_R_N1 9 10 1 1 USB30_RX_R_N1
USB30_TX_C_P1 1 2 USB30_TX_R_P1 USB20_N1_R

AZ5425-01F_DFN1006P2E2
1 2 USB30_RX_R_P1 8 2 USB30_RX_R_P1
9 2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1
D11

1
USB30_TX_C_N1 4 3 USB30_TX_R_N1 USB30_TX_R_N1 7 7 4 4 USB30_TX_R_N1 D13 D14

1
4 3

EMC_NS@

1
EMC_NS@

EMC_NS@
EXC24CH900U_4P USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

L8 EMC@ 3 3

2
USB20_P1 1 2 USB20_P1_R
1 2

2
8

2
USB20_N1 4 3 USB20_N1_R AZ1045-04F_DFN2510P10E-10-9
3 4 3 3
EXC24CH900U_4P

EMC EMC

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 P32-USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 41 of 60
A B C D E
 A B C D E F G H

SATA HDD Conn.

FOR 14"
JHDD1 ME@

1
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND_1
9 SATA_PTX_DRX_P0 A+
9 SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 C67 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
4 A-
1 SATA_PRX_DTX_N0 C68 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND_2 1
9 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B- JODD1
9 SATA_PRX_DTX_P0 7 B+ 1
GND_3 SATA_PTX_DRX_P1 14@ C70 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_14 2 GND_1
9 SATA_PTX_DRX_P1 RX+
9 SATA_PTX_DRX_N1 SATA_PTX_DRX_N1 14@ C71 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_14 3
8 4 RX-
9 V33_1 SATA_PRX_DTX_N1 14@ C72 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_14 5 GND_2
10 V33_2 9 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_14 6 TX-
+5VS +5VS_HDD 11 V33_3 9 SATA_PRX_DTX_P1 7 TX+
Need short 12 GND_4 GND_3
J3 @ 13 GND_5 8
1 2 14 GND_6 9 DP
1 2 15 V5_1 +5V_ODD 10 +5V_1
JUMP_43X79 16 V5_2 11 +5V_2 14
17 V5_3 12 MD GND1 15
18 GND_7 13 GND_4 GND2
19 DAS/DSS GND_5
+5VS_HDD 20 GND_8 SUYIN_127382FB013S255ZL
21 V12_1 24 ME@
22 V12_2 GND_10 23
V12_3 GND_9
1 1 1 1 1
@ @ C75 C77 C78 HIGHS_SA2S0226-1511H
C74 C76 .1U_0402_10V6-K 10U_0805_10V6K 10U_0805_10V6K
33P_0402_50V8J 33P_0402_50V8J @
2 2 2 2 2

FOR 15"
2 2

For EMC SATA ODD FFC Conn

JODD2
1
SATA_PTX_DRX_P1 15@ C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 2 1
SATA_PTX_DRX_N1 15@ C80 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_15 3 2
4 3
SATA_PRX_DTX_N1 15@ C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 5 4
SATA_PRX_DTX_P1 15@ C82 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_15 6 5
7 6
+5V_ODD 8 7
9 8
10 GND_1
GND_2
ACES_51524-00801-001
ME@

+5VS +5V_ODD
3
Need Short 3
J4 @
1 2
1 2
JUMP_43X79
10U_0805_10V6K

1 1 .1U_0402_10V6-K

2 2
C86
C85

CD@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 HDD/ODD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 42 of 60
A B C D E F G H
 5 4 3 2 1

+3VS

+3VS +3VALW_PCH RA3 1 @ 2 0_0603_5%

+3VALW +5VA AVDD_HP
RA2 1 2 0_0603_5% +3.3VD RA44 1 2 0_0402_5%

.1U_0402_10V6-K

.1U_0402_10V6-K
+3VS

CA11

CA12
RA5 1 @ 2 0_0603_5% AVDD_HP 2 2
+3VL
RA11 1 2 0_0402_5% DVDD_IO
RA43 1 2 0_0603_5%
+5VS @ 1 1

.1U_0402_10V6-K
2
RA7 1 2 0_0603_5% +5VA CA1

RA10 1 2 0_0603_5% +5VD 1 Close to Pin28 Close to Pin24

D Close to Pin3 D

Close to Pin7
DA1
44 BEEP#
2
.1U_0402_10V6-K CA16 close to Pin18

.1U_0402_10V6-K

4.7U_0603_10V6-K
1 PC_BEEP1 CA2 1 2 PC_BEEP 2 1 CA17 close to Pin2
Close to Pin27

1
8 PCH_BEEP
3
RA14
1 2

CA3
BAT54CW_SOT323-3 10K_0402_5%

.1U_0402_10V6-K

1U_0402_6.3V6K
change the Codec PN to CX11802-33Z,, symbol check ok

CA4

CA7

CA8
2 1
UA1

.1U_0402_10V6-K

2.2U_0603_6.3V6K
2

2 1

CA5

CA6
HDA_RST_AUDIO# 9 3 FILT_1.8V
8 HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO CD@ 1 2
VDD_IO 2
HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 1 2
8 HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
HDA_SYNC_AUDIO 8 27 AVDD_3.3
8 HDA_SYNC_AUDIO RA16 SYNC AVDD_3.3 29 VREF_1.65V
33_0402_5% 1 2 SDATA_IN 6 VREF_1.65V 28 +5VA
8 HDA_SDIN0 4 SDATA_IN AVDD_5V
HDA_SDOUT_AUDIO

.1U_0402_10V6-K

1U_0402_6.3V6K
8 HDA_SDOUT_AUDIO SDATA_OUT

CA9

CA10
MICBIASB
+3.3VD

PC_BEEP 10
PC_BEEP
CX20751-11Z LEFT+
12 SPK_L+
2 1
SPKR_MUTE# 39 14 SPK_L-
SPKR_MUTE# LEFT- DA2

4LINE_B_R
3LINE_B_L
JSENSE 38 17 SPK_R+ BAT54AW_SOT323-3 1 2
JSENSE RIGHT+
2

1
37 15 SPK_R- @ RA41
GPIO1/PORTC_R_MIC RIGHT-

2
RA15 RA42 0_0402_5%
5.11K_0402_1% 36 35
33_0402_5% 1 RA18 2 DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 MICBIASB 0_0402_5%
33 DMIC_CLK DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
Close to Pin29
0_0402_5% 1 RA19 2 DMIC_DATA_R 1 RPA2
1

33 DMIC_DATA DMIC_DAT/GPIO1 33 LINE_B_R 100_0404_4P2R_1%

1
RA17 1 2 JSENSE .1U_0402_10V6-K PORTB_R_LINE 32 LINE_B_L
45 PLUG_IN PORTB_L_LINE
39.2K_0402_1% +5VD 1 2 11

1
2
CA13 CLASS-D_REF 30 PORTD_A_MIC
C PORTD_A_MIC C
RA36 1 2 13 31 PORTD_B_MIC
20K_0402_1% 16 LPWR_5.0 PORTD_B_MIC
RPWR_5.0

1
3K_0402_1%

3K_0402_1%
25 RING2_CONN 1 1
HGNDA

RA37

RA38
CA14 1 2 1U_0402_6.3V6K 19 26 RING3_CONN
20 FLY_P HGNDB CA35 CA36
FLY_N 24 AVDD_HP 4.7U_0603_10V6-K 4.7U_0603_10V6-K
CA17 1 2 2.2U_0603_6.3V6K 21 AVDD_HP 2 2 RPA3

2
AVEE 23 HPOUT_R 1 4
41 PORTA_R 22 2 3 HP_OUTR 45
HPOUT_L
GND PORTA_L HP_OUTL 45
82.5_0404_4P2R_1%

CD@ CD@ +5VD CX11802-33Z QFN LOW POWER CODEC

RPA1
PORTD_A_MIC 2 3 CA39 1 2 2.2U_0603_6.3V6K
RING3_CONN 45
CA15

CA16

CA18

CA19

PORTD_B_MIC 1 4 CA40 1 2 2.2U_0603_6.3V6K

4.7U_0603_10V6-K

4.7U_0603_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1 2 0_0402_5% RING2_CONN 45
1 1 2 2 RA1 @
100_0404_4P2R_1%
RA4 1 @ 2 0_0402_5%
2 2 1 1 RA6 1 @ 2 0_0402_5%

RA9 1 @ 2 0_0402_5%
JSPK1
RA12 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA25 SPK_R+ RA26 EMC@1 2 PBY160808T-221Y-N_2P SPK_R+_CONN 1
15_0402_5% 1 CD@ 2 RA29 SPK_R- RA31 EMC@1 2 PBY160808T-221Y-N_2P SPK_R-_CONN 2 1
RA13 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA32 SPK_L+ RA30 EMC@1 2 PBY160808T-221Y-N_2P SPK_L+_CONN 3 2
15_0402_5% 1 CD@ 2 RA33 SPK_L- RA34 EMC@1 2 PBY160808T-221Y-N_2P SPK_L-_CONN 4 3
Close to Pin11,13,16 4
5
6 GND1
GND GNDA GND2

CA27

CA28

CA29

CA30
220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
+3.3VD

Use 250mils wide trace bridging 2 2 2 2 1 1 1 1 ACES_88231-04001

CA31

CA32

CA33

CA34
AGND and DGND at codec ME@

RA24 1 @ 2 1 1 1 1 2 2 2 2
B B
1

0_0402_5%
RA28
47K_0402_5% HDA_RST_AUDIO# EMC@ EMC@ EMC@ EMC@
RB751V-40_SOD323-2 @
HDA_RST_AUDIO# DA3 1 2 @ HDA_SYNC_AUDIO
2

CD@ CD@ CD@ CD@

SPKR_MUTE# HDA_SDOUT_AUDIO
RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 @ RA27 1 EMC@ 2 HDA_BITCLK_AUDIO
44 EC_MUTE#
27_0402_5%
HDA_SDIN0
CA23

CA24

CA25

CA26

EMC@
RA35 1 @ 2
68P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

33P_0402_50V8J

33P_0402_50V8J

0_0402_5% 1 1 1 1 1
CA22

2 2 2 2 2
EMC@
EMC_NS@

EMC_NS@

EMC_NS@

For EMI

DMIC_CLK

DMIC_DATA
CA37

CA38
100P_0402_50V8J

100P_0402_50V8J

1 1
A A

2 2
EMC_NS@ EMC_NS@

For EMI
Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Codec_CX11802 & Audio jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 43 of 60
5 4 3 2 1
 5 4 3 2 1

For EMI RE1 1 2 0_0603_5%

For ESD EMC_NS@
+3VL B+
PLT_RST# CLK_PCI_EC RE2 1 2 10_0402_5%

1
RE3 1 @ 2 0_0603_5%
1 1 Close EC +3VALW
RE261
CE1 CE2 +3VL_EC_R @ 470K_0402_5%
220P_0402_50V7K 10P_0402_50V8J CE3 +3VL_EC +3VL_EC
2 EMC@ EMC_NS@ 2 1 2 VCOREVCC

2
LE1 1 @ 2 0_0603_5% B+_Track
.1U_0402_10V6-K +3VL_EC All capacitors close to EC

1
1 1
CE4 +3VL_EC R260

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
1 1 1 1 1 1 .1U_0402_10V6-K CE5 @ 47K_0402_5%
+3VS +3VL_EC_R CE6 CE7 CE8 CE9 CE10 CE11 1000P_0402_50V7K
LE2 1 @ 2 0_0603_5% 2 EC_AGND 2

2
1
D D
@ @
2 2 2 2 2 2 RE5
RE6 1 @ 2 0_0402_5% EC_AGND 10K_0402_5%

CD@

2
LAN_WAKE#
minimum trace width 12 mil LAN_WAKE# 37,40

114
121
127
Change RE6 to 0ohm jump

12

11

26
50
92

74
3
UE1
+3VS

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VBAT

VSTBY(PLL)
VCORE
EC_FAN_SPEED RE10 1 2 10K_0402_5%

21 WRST# EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

RE56 2 @ 1 0_0402_5% 4 24 PWR_LED#
7 KBRST# 2 1 0_0402_5% 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 45 1 2 10K_0402_5%
RE59 @ LPC_FRAME# RE7 @
+3VL_EC 7,32 SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# 45
RE60 2 1 0_0402_5% LPC_FRAME#_EC 6 28
7,32 LPC_FRAME# 2 1 0_0402_5% 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# 45 1 2 100K_0402_5%
RE61 LPC_AD3_EC EC_VCCST_PWRGD ENBKL RE9 @
7,32 LPC_AD3 LAD3/GPM3 PWM3/GPA3 EC_VCCST_PWRGD 11
DE1 1 2 @ RE62 2 1 0_0402_5% LPC_AD2_EC 8 PWM 30
7,32 LPC_AD2 LAD2/GPM2 PWM4/GPA4 SYS_PWROK 11
RE63 2 1 0_0402_5% LPC_AD1_EC 9 31 EC_FAN_PWM CPU_VR_READY RE270 1 2 10K_0402_5%
7,32 LPC_AD1 2 1 0_0402_5% 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 39
RB751V-40_SOD323-2 RE64 LPC_AD0_EC
7,32 LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# 43
CLK_PCI_EC 13 LPC 34 EC_VCCST_EN_R RE54 2 1 0_0402_5% EC_VCCST_EN
1 2 7 CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 EC_VCCST_EN 13
WRST# LAN_WAKE#
RE8 15 WRST# TMRI0/GPC4 124 SUSP# +5VS +3VS
1 9 EC_SMI# ECSMI#/GPD4 TMRI1/GPC6 SUSP# 46,55
100K_0402_5% EC_RX 16
CE12 40 EC_RX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66
EC_TX NTC_V1 39
40 EC_TX LPCPD#/GPE6 ADC0/GPI0

2
1U_0402_6.3V6K PLT_RST# 22 67
2 11,20,32,37,40 PLT_RST# LPCRST#/GPD2 ADC1/GPI1 NTC_V2 39
23 68 BATT_TEMP RE52 RE51
4,8 EC_SCI# ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP 52,53
EC_RTCRST#_ON 126 ADC 69 RE264 2 1 0_0402_5% SD_PWR_EN# 0_0402_5% 0_0402_5%
GA20/GPB5 ADC3/GPI3 SD_PWR_EN# 8
70 @ @
IT8586E/AX ADC4/GPI4 71 CPU_VR_READY
ADP_I 53
59

1
ADC5/DCD1#/GPI5 72 B+_Track +3VL_EC
ADC6/DSR1#/GPI6

45 KSI[0..7]
KSI[0..7] KSI0 58 LQFP-128L ADC7/CTS1#/GPI7
73
ADAPTER_ID 51,53
TP_CLK RE12 2 1 4.7K_0402_5%

1
KSI1 59 KSI0/STB# 78
KSO[0..17] KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# 11
KSI2 60 79 RE65 TP_DATA RE13 2 1 4.7K_0402_5%
45 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON 54
C KSI3 61 DAC 80 H_PROCHOT#_EC 100K_0402_5% C
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81
KSI4 DAC5/RIG0#/GPJ5 ENBKL 33
KSI5 63

2
+3VL_EC KSI6 64 KSI5 85 EC_ON_GPIO RE57 2 1 0_0402_5% +5VALW
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 EC_ON 54
KSI7
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# 11
KSO0 36 87
1 37 KSO0/PD0 GPF2 88 PM_SLP_SUS# 11
RPE2 EC_SMB_CK1 PAD @ KSO1 Int. K/B PS2 USB_ON# RE15 1 2 100K_0402_5%
IT1 KSO1/PD1 GPF3 SUSACK# 11
2 3 EC_SMB_CK1 EC_SMB_DA1 PAD 1 @ KSO2 38 89 TP_CLK
1 4 EC_SMB_DA1 1
IT2
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA
TP_CLK 45
PAD @
1 IT3 40 KSO3/PD3 PS2DAT2/GPF5 TP_DATA 45
PAD @ KSO4
IT4 KSO4/PD4
2.2K_0404_4P2R_5% PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96 +3VL_EC
IT5 42 KSO5/PD5 GPH3/ID3 97 CAPS_LED# 45
KSO6
KSO6/PD6 GPH4/ID4 PCH_PWR_EN 46,56
KSO7 43 98
KSO7/PD7 GPH5/ID5 ACOFF 53
KSO8 44 99
+3VS 1 45 KSO8/ACK# GPH6/ID6 PCH_PWROK 11
KSI7 PAD @ KSO9 SUSP# RE18 1 @ 2 100K_0402_5%
IT6 KSO9/BUSY
KSI6 PAD 1 @ KSO10 46 101 EC_SPI_CS0#
1 IT7 51 KSO10/PE NC1 102
RPE3 WRST# PAD @ KSO11 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
IT8 KSO11/ERR# NC2
1 4 EC_SMB_CK2 KSO12 52 SPI Flash ROM 103 EC_SPI_SO RE266 PCH_SDIO@
2 3 EC_SMB_DA2 KSO13 53 KSO12/SLCT NC3 105 EC_SPI_CLK SD_PWR_EN# 2 1 EC_SD_PWR_EN# SYSON_R RE21 1 2 100K_0402_5%
KSO14 54 KSO13 NC4 0_0402_5%
For factory EC flash KSO14
2.2K_0404_4P2R_5% KSO15 55 EC_VCCST_EN RE269 1 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN#
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# EC_VCCIO_EN RE268 1 @ 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 45
@
@ 45 ON/OFF ON/OFF 110 82 EC_FAN_ANTI_R RE53 2 1 0_0402_5% EC_FAN_ANTI 39
EC_ON RE58 2 1 0_0402_5% 111 PWRSW# EGAD/GPE1 83
XLP_OUT SM Bus EGCS#/GPE2 VDDQ_PGOOD 55
EC_SMB_CK1 115 84 ADAPTER_ID_ON# 53 RE265 2 1 0_0402_5%
EC_SD_PWR_EN#
52,53 EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3 EC_SD_PWR_EN# 30
EC_SMB_DA1 116 @
52,53 EC_SMB_DA1 SMDAT1/GPC2
4 H_PECI RE24 1 2 43_0402_5% PECI_EC 117 GPIO 77 RE25 2 @ 1 0_0402_5% PM_SLP_S4# CE50 1 2 EMC_NS@ 1000P_0402_50V7K
SMCLK2/PECI/GPF6 GPJ1 PM_SLP_S5# 11
118 100 GPG2
37 LAN_PWR_ON# 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106
EC_SMB_CK2
7,21,39 EC_SMB_CK2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 EC_MUTE# 43
EC_SMB_DA2 95 104 PM_SLP_S5# CE49 1 2 EMC_NS@ 1000P_0402_50V7K
+3VL 7,21,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH 8
107 SYSON_R RE271 2 1 0_0402_5% SYSON
DTR1#/SBUSY/GPG1/ID7 119 SYSON 55
BKOFF#
CRX0/GPC0 BKOFF# 33
123 RE263 2 @ 1 0_0402_5% PM_SLP_S3# CE21 1 2 EMC_NS@ 1000P_0402_50V7K
1 2 0_0402_5% 112 CTX0/TMA0/GPB2 18 AOAC_ON# 40
RE27 @
VSTBY0 RI1#/GPD0 PM_SLP_S3# 11,13,44
RE272 2 1 0_0402_5% 125 21 PM_SLP_S4# 11,44 RE55 2 @ 1 0_0402_5% EC_VCCIO_EN
B 59 EC_VR_ON GPE4 RI2#/GPD1 EC_VCCIO_EN 13 B
WAKE UP 76 NOVO# 45 SYSON CE13 1 2 EMC_NS@ 1000P_0402_50V7K
DE2 1 2 TACH2/GPJ0 48
11,13,44 PM_SLP_S3# TACH1A/TMA1/GPD7 EC_TS_ON# 33
@ RB751V-40_SOD323-2 47 EC_FAN_SPEED EC_FAN_SPEED 39
USB_ON# 33 TACH0A/GPD6 19 VGA_AC_DET
41,45 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 VGA_AC_DET 21 EMC Request

2
35 GPIO 20
11 DPWROK_EC RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 45
93
11 EC_RSMRST# CLKRUN#/GPH0/ID0 Reserve for VGA_AC_DET
PCIE_WAKE# 2 DE3
11,37,40 PCIE_WAKE#

1
128 CK32KE/GPJ7 RB751V-40_SOD323-2
11 AC_PRESENT CK32K/GPJ6 Clock
+3VL @
11,44 PM_SLP_S4#

RE34 2 1 0_0402_5% H_PROCHOT# 4

53,59 VR_HOT#
AVSS

RE35 1 2 10K_0402_5% ON/OFF

VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

@
EC_RTC_RST# 10

1
RE36 1 @ 2 10K_0402_5% BKOFF# 1
IT8586E-AX_LQFP128_14X14 RE267 CE14
1

27
49
91
113
122

75

RE38 1 2 10K_0402_5% LID_SW# 100_0402_5% 47P_0402_50V8J

EMC_NS@

1
2 QE3 D

1 2
EC_RTCRST#_ON 2
RE40 1 2 10K_0402_5% BKOFF# QE1 D G
EC_AGND H_PROCHOT#_EC 2 +3VL
G @ S 2N7002KW_SOT323-3

3
1
2N7002KW_SOT323-3 S RE50
for EC version update to EX, manual modify PN to FX

2
100K_0402_5%
RE42 @
100K_0402_5%

2
PECI_EC EMC_NS@
CE15 1 2 47P_0402_50V8J

1
+3VL BATT_TEMP EMC_NS@
CE16 1 2 100P_0402_50V8J +3VS ACIN# RE262 2 1 0_0402_5%
11 ACIN#
+3VL_EC ACIN# EMC_NS@
CE17 1 2 100P_0402_50V8J

1
1 D QE2
A GPG2 RE43 2 @ 1 10K_0402_5% ON/OFF @ CE18 1 2 1U_0402_6.3V6K CE19 2 A
.1U_0402_10V6-K G ACIN 53
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 2 @ 1 0_0402_5% SPI_CS0#
SPI_CS0# 7 NOVO# 2 2N7002KW_SOT323-3 S

3
GPG2 RE46 2 @ 1 10K_0402_5% EMC_NS@
@
EC_SPI_SI RE47 2 @ 1 0_0402_5% SPI_SI Check if can save the mos
SPI_SI 7
.01U_0402_16V7-K

when mirror, GPG2 pull high

CE48

when no mirror, GPG2 pull low EC_SPI_SO RE48 2 @ 1 0_0402_5% SPI_SO

SPI_SO 7 1

Security Classification LC Future Center Secret Data Title

EC_SPI_CLK RE49 2 @ 1 0_0402_5% SPI_CLK
SPI_CLK 7 2
Issued Date 2014/12/11 Deciphered Date 2015/12/11 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 44 of 60
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch +3VL +3VALW

K/B Connector

2
+3VS
R82 R83
100K_0402_5% @ 100K_0402_5%
@ KSI[0..7]
R261 1 2
KSI[0..7] 44
EMC_NS@ 14" 15"

1
0_0402_5% KSO[0..17]
KSO[0..17] 44 1 2 100P_0402_50V8J
PWR_CAPS_LED C133 JKB2 R84 R90
300_0402_5% 300_0402_5%
D15 PWR_NUM_LED C134 1 2 100P_0402_50V8J 27 15@ JKB1
NOVO# 2 GND1 28 NUM_LED# 30 31
44 NOVO# 44 NUM_LED#

2
EMC_NS@ CAPS_LED# 26 GND2 PWR_NUM_LED 29 30 GND1 32
1 44 CAPS_LED# 25 26 28 29 GND2
NOVO_BTN# PWR_CAPS_LED CAPS_LED#
KSO15 24 25 PWR_CAPS_LED 27 28
ON/OFF R85 1 @ 2 0_0402_5% 3 KSO10 23 24 KSO17 26 27
KSO11 22 23 KSO16 25 26
D D
BAT54CW_SOT323-3 KSO14 21 22 KSO15 24 25
KSO13 20 21 KSO10 23 24
EMC@ KSO12 19 20 KSO11 22 23
CAPS_LED# C117 1 2 100P_0402_50V8J KSO3 18 19 CAPS_LED# NUM_LED# KSO14 21 22
+3VALW +3VL KSO6 17 18 KSO13 20 21
NUM_LED# C118 1 2 100P_0402_50V8J KSO8 16 17 KSO12 19 20
KSO7 15 16 KSO3 18 19
15 18

2
EMC_15@ KSO4 14 KSO6 17

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
14 17

1
R111 R114 KSO2 13 KSO8 16
100K_0402_5% 100K_0402_5% KSI0 12 13 D22 D23 KSO7 15 16

1
@ KSO1 11 12 KSO4 14 15
KSO5 10 11 KSO2 13 14

1
KSI3 9 10 KSI0 12 13
9 12

2
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF KSI2 8 KSO1 11
ON/OFF 44 7 8 10 11
KSO0 EMC@ EMC_15@ KSO5

2
KSI5 6 7 KSI3 9 10
J5 1 2 @ KSI4 5 6 KSI2 8 9
KSO9 4 5 KSO0 7 8
SHORT PADS KSI6 3 4 KSI5 6 7
3 For EMC 6
KSI7 2 KSI4 5
J6 1 2 @ KSI1 1 2 KSO9 4 5
1 KSI6 3 4
SHORT PADS ACES_88514-02601-071 KSI7 2 3
KSI1 1 2
ME@ 1
ACES_50504-3041-001
ME@

+5VS TP_PWR TP_CLK

C R160 1 @ 2
TP/B Connector TP_DATA PWR/B Connector USB I/O Connector C

2
+3VS 0_0402_5%
JTP1 DT1
R141 1 2 1
0_0402_5% TP_CLK 2 1 EMC_NS@
44 TP_CLK 2
TP_DATA 3
44 TP_DATA 3
.1U_0402_10V6-K

1 4
1 1 TP_P5 5 4
5
Right Side USB2.0 Port X 2 (USB/B)
100P_0402_50V8J

100P_0402_50V8J

TP_P6 6 7
EMC_NS@

EMC_NS@

6 GND1 8
2 GND2
C114

2 2 ACES_50503-0060N-001
C115

C116

ME@ AZC199-02S.R7G_SOT23-3 +3VL

1
For EMC
JPWRB1
1 +5VALW +USB_VCCB +USB_VCCB
NOVO_BTN# 2 1 U3
ON/OFFBTN# 3 2 5 1 JUSB3
LID_SW# 4 3 IN OUT 18 20
TP_LEFT Button TP_LEFT Button 5 4 1
2 17 18 G2 19
TP_P5 TP_P5 C141
6 5 7 1U_0402_6.3V6K GND 16 17 G1

AZ5215-01F_DFN1006P2E2
6 GND1 16

1
8 41,44 USB_ON# 4 3 USB_OC2# R67 1 2 0_0402_5% USB20_P2_CONN 15
GND2 2 ENB OCB USB_OC2# 9 9 USB20_P2 1 2 0_0402_5% USB20_N2_CONN 14 15
D17 R66

1
9 USB20_N2 14
1

5
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
ACES_50503-0060N-001 SY6288D20AAC_SOT23-5 1 13
SW1 SW2 ME@ R254 1 2 0_0402_5% USB20_P3_CONN 12 13
C142
A

A
A1

GND1

A1

GND1
EVQPLHA15_4P

EVQPLHA15_4P 9 USB20_P3 12
1

1
DT2 DT3 1000P_0402_50V7K R255 1 2 0_0402_5% USB20_N3_CONN 11
9 USB20_N3 11

2
Low Active 2A EMC_NS@ 10
For 14" For 15"
1

1
EMC_NS@ 2 9 10

2
9
GND2

GND2

PLUG_IN 8
LID_SW# 44 43 PLUG_IN 7 8
1 VDD 1 VDD
B1

B1

7
B

B
2

2
14@ 15@ RING3_CONN 6
EMC_NS@ EMC_NS@ 43 RING3_CONN 5 6
3

2
4 5
RING2_CONN 3 4
2 CLK 2 CLK For EMC 43 RING2_CONN 3
HP_OUTR 2
43 HP_OUTR 2
43 HP_OUTL HP_OUTL 1
1
TP_RIGHT Button TP_RIGHT Button
TP_P6 TP_P6 L14 EMC_NS@ ACES_50505-0184N-P01
3 DAT 3 DAT NOVO_BTN# ON/OFFBTN# USB20_P2 1
1 2
2 USB20_P2_CONN ME@
1

B B
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

USB20_N2 4 3 USB20_N2_CONN
4 GND 4 GND SW3 SW4 4 3
A

A
A1

GND1

A1

GND1
EVQPLHA15_4P

EVQPLHA15_4P
1

DT4 DT5 EXC24CH900U_4P

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
1

1
1

D20 D21
5 TP-L 5 TP-L

1
GND2

GND2

L17 EMC_NS@
USB20_P3 1 2 USB20_P3_CONN
B1

B1

1 2
B

B
2

14@ 15@

2
EMC_NS@ EMC_NS@
6 TP-R 6 TP-R
3

EMC@ EMC@ USB20_N3 4 3 USB20_N3_CONN

2
4 3
For EMC EXC24CH900U_4P

For 14" For 15"

44 PWR_LED# PWR_LED# LED1 1 2 R142 1 2 1.5K_0402_5% +5VALW

1

D16 @ LTW-C193TS5
1

AZ5425-01F_DFN1006P2E2
2
2

BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%

44 BATT_LOW_LED# +3VALW
LTST-C193KFKT-LC
1

D18 @
1

AZ5425-01F_DFN1006P2E2

A A
2
2

BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%

44 BATT_CHG_LED# +5VALW
LTW-C193TS5
1

D19 @
1

AZ5425-01F_DFN1006P2E2 Title
Security Classification LC Future Center Secret Data
Issued Date 2014/12/11 Deciphered Date 2015/12/11 KBD/PWR/IO/LED/TP Conn.
2

check LED location and BOM structure when placement and Load BOM, PWR LED and BATT LED THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
have the same location on 14"/15" 02/26 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 45 of 60
5 4 3 2 1
 A B C D E

Load Switch
+5VALW To +5VS +3VS, C173 --> 2.74ms
+3VALW To +3VS +5VS, C176 --> 2.03ms
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
R64 1 2 0_0402_5% 3VSON
+5VALW U13 +5VS
1 14 J12 @
2 VIN1_1 VOUT1_2 13 +5VS_LS 1 2
1 VIN1_2 VOUT1_1 1 2 1

1 5VSON 3 12 C176 1 2 1000P_0402_50V7K JUMP_43X118 1

SUSP# R27 1 2 0_0402_5% 5VSON EN1 SS1
C177 4 11 C174 @
+5VALW BIAS GND
1U_0402_6.3V6K 0.1U_0402_10V7-K
+3VALW 2 3VSON 5 10 C173 1 2 2200P_0402_25V7-K 2 +3VS
1 1 EN2 SS2 J11 @
C180 C179 6 9 +3VS_LS 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K 7 VIN2_1 VOUT2_2 8 1 2
2 2 VIN2_2 VOUT2_1 JUMP_43X118
1 1
15
C178 GPAD C175 @
Need Short
1U_0402_6.3V6K APL3523AQBI-TRG_TDFN14_2X3 0.1U_0402_10V7-K
2 @ 2

2 2
+3VALW Need short +3VALW_PCH
+5VALW
J7 @
1 2
1 2
1

JUMP_43X79

22U_0603_6.3V6-M
R155 1

C1103
100K_0402_5% @
@ LP2301ALT1G_SOT23-3 Id=3.2A
2

D
PCH_PWR_EN#_R R158 1 @ 2 100K_0402_5% PCH_PWR_EN# Q29 3 1 @

1
1

Q30 D C130

G
2
PCH_PWR_EN 2 0.01U_0402_25V7K
44,56 PCH_PWR_EN
G @
2
@ S 2N7002KW_SOT323-3
3
1

PCH_PWR_EN#_R

R162 1
100K_0402_5% C131
@ .1U_0402_10V6-K
2

@
1

2
R87
100K_0402_5%
@
2

3 3

+5VLP
+5VALW
For DisCharge
1

R156 +0.675VS
100K_0402_5% R157
100K_0402_5%
1

@
2

R159
2

SUSP @ 47_0603_5%
34 SUSP
2
1

Q10 D D Q11
2 @ 2 SUSP
44,55 SUSP# G G

S 2N7002KW_SOT323-3 2N7002KW_SOT323-3 S
3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 46 of 60

A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3 +3V_PCH

V
PU301 PU904

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801

V
PU501
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

ZZZ1 ZZZ2 ZZZ3 ZZZ5 ZZZ6 ZZZ7

ZZZ4 UV1 EXO@ RV16 EXO@ RV19 EXO@

Hynix Samsung Micron Hynix Samsung Micron

H4GX4@ S4GX4@ M4GX4@ H2GX4@ S2GX4@ M2GX4@
PCB PN EXO-Pro GPU 0_0402_5% 0_0402_5% X7607012001 X7607012003 X7607012004 X7607012101 X7607012103 X7607012104
DA60000ZS00 SA000074V10 SD02800008J SD02800008J
PCB_MB GPU X76 BOM
D D

UC1 7GM00@ UC1 7GP00@ UC1 7GV00@ UC1 7GV10@ UC1 7GM10@ UC1 7H800@ UC1 7HH00@ RV71 SINGLERANK@ RV72 SINGLERANK@ RV75 SINGLERANK@ RV76 SINGLERANK@

SKL-U CPU SKL-U CPU SKL-U CPU SKL-U CPU SKL-U CPU SKL-U CPU SKL-U CPU 40.2_0402_1% 40.2_0402_1% 40.2_0402_1% 40.2_0402_1%
SA00007GM00 SA00007GP00 SA00007GV00 SA00007GV10 SA00007GM10 SA00007H800 SA00007HH00 SD034402A8J SD034402A8J SD034402A8J SD034402A8J
CPU Single-Rank

UV3 H4@ UV4 H4@ UV5 H4@ UV6 H4@ UV3 H2@ UV4 H2@ UV5 H2@ UV6 H2@
RV33 H2@

H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC2G63FFR-11C H5TC2G63FFR-11C H5TC2G63FFR-11C H5TC2G63FFR-11C

SA00007DU10 SA00007DU10 SA00007DU10 SA00007DU10 SA00005VS00 SA00005VS00 SA00005VS00 SA00005VS00 4.53K_0402_1%
SD03445318J

RV36 H4@ RV36 H2@

C 4.75K_0402_1% 4.99K_0402_1% C
SD03447518J SD03449918J

VRAM_Hynix_256M*16 VRAM_Hynix_128M*16

UV3 M4@ UV4 M4@ UV5 M4@ UV6 M4@ RV33 M4@ UV3 M2@ UV4 M2@ UV5 M2@ UV6 M2@ RV33 M2@

MT41J256M16HA-093G MT41J256M16HA-093G MT41J256M16HA-093G MT41J256M16HA-093G 4.53K_0402_1% MT41J128M16JT-093G MT41J128M16JT-093G MT41J128M16JT-093G MT41J128M16JT-093G 4.75K_0402_1%
SA000060I10 SA000060I10 SA000060I10 SA000060I10 SD03445318J SA00005M120 SA00005M120 SA00005M120 SA00005M120 SD03447518J

RV36 M4@

2K_0402_1%
SD03420018J

VRAM_Micron_256M*16 VRAM_Micron_128M*16

UV3 S4@ UV4 S4@ UV5 S4@ UV6 S4@ RV33 S4@ UV3 S2@ UV4 S2@ UV5 S2@ UV6 S2@ RV33 S2@

B K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A 8.45K_0402_1% K4W2G1646Q-BC1A K4W2G1646Q-BC1A K4W2G1646Q-BC1A K4W2G1646Q-BC1A 3.4K_0402_1% B
SA000063F20 SA000063F20 SA000063F20 SA000063F20 SD000011R00 SA00005SH40 SA00005SH40 SA00005SH40 SA00005SH40 SD03434018J

RV36 S2@
RV36 S4@

10K_0402_1%
2K_0402_1% SD03410028J
SD03420018J

VRAM_Samsung_256M*16 VRAM_Samsung_128M*16

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 48 of 60
5 4 3 2 1
 5 4 3 2 1

PCB Fedical Mark PAD

NH1 NH3 NH4
HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4 FD5 FD6

1
D D

PAD_C2P5D2P5N PAD_O2P5X2P8D2P5X2P8N PAD_O2P5X2P8D2P5X2P8N

H5 H6 H25 H26 H27 H32

H1 H3 H4 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
HOLEA HOLEA HOLEA

1
1

1
PAD_RT8P0X11P0D2P8
pad_ct8p0d2p8 Pad_ct8p0b9p0d2p8 Pad_ct8p0b9p0d2p8 PAD_SHAPET9p0X8P0B9P0D2P8 PAD_Shapet9p0x8p0b7p0d2p8 pad_cb5p0d3p3 PAD_C8P0 PAD_C8P0

C C

H21
H13 H14 H17 H31 H20 H22 H23 H24 H7 H8 H9 H11 H12 HOLEA
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
1

1
CHASSIS1_GND

pad_c8p0d7p0 PAD_CT6P0B8P0D2P3 pad_cb8p0d2p5 PAD_OT6P0X5P5D3P3X2P8 pad_c5p5d3p3 pad_c5p5d3p3 pad_c5p5d3p3 pad_c5p5d3p3 pad_c5p0d4p0 pad_c5p0d4p0 pad_c5p0d4p0 PAD_CB9P0D2P5 pad_c6p0d4p6 PAD_CT8P0B7P0D2P5

B B
GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8 GP13 GP14
PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_R4P72X1P9 PAD_R4P72X1P9
@ @ @ @ @ @ @ @ @ @
1

1
1

1
For EMC
GP9 GP10 GP11 GP12
PAD_RT2P5X2P3 PAD_RT2P5X2P3 PAD_R2P65X2P22 PAD_R2P65X2P22
@ @ @ @
1

FFC CONN GROUND PAD

1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Thursday, May 28, 2015 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

Silergy

D
SY8288RAC +1.0VALW/7.5A D

QFN20_3X3
Converter
SUSP# EN PGOOD
FOR PCH

B+
+5VLP/ 100mA
Silergy
SYX198CQNC +5VALW/6A
Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
PAGE 39

ANPEC
+3VLP/ 100mA APL5930CKAI-TRG
Silergy +1.8VALW/1A
SY8286BRAC SO8
QFN20_3X3 +3VALW/ 5A EN PGOOD
Converter
C EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD C
PAGE 39

Silergy
SY8089AAAC
Richtek +1.35V/14A SOT23-5 +0.95VGS/2A
NB685GQ-Z Switch Mode
FOR GPU
SYSON S5 QFN16_3X3 EN
SUSP# S3 +0.675VS/2A
TI Switch Mode
FOR DDR PGOOD
BQ24780SRUYR
Battery Charger
Switch Mode
Onsemi CPU Core/23A
PAGE 46

NCP81206MNR2G VCCGT/25A
QFN60_7X7
Switch Mode VCCSA/7A
VR_ON
SMBus EN FOR CPU Core PGOOD VGATE
B
PGOOD_NB B

Battery Intersil
Li-ion ISL62771HRTZ
4S1P TQFN40_5X5 +VGA_CORE/31A
VIDs
Switch Mode
NVDD_PWR_EN EN FOR GPU VDDC PGOOD VGA_PWRGD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 50 of 60
5 4 3 2 1
 5 4 3 2 1

VIN
7A_24VDC_429007.WRML

JDCIN1 PF101 PJ101

1 APDIN 1 2 APDIN1 2 1
1 2 2 1
2 3 @ JUMP_43X118
3 ADAPTER_ID 44,53

470P_0402_50V7K
4
4

1000P_0402_50V7K

470P_0402_50V7K

1000P_0402_50V7K
5
5

EMC@
1

1
EMC@
PC101

PC102

PC103

PC104
D ACES_50299-00501-003 D

EMC@

EMC@
ME@

2
+3VL

1
PR1015
1.5K_0402_5%

2
VCCRTC

1
PR1016
45.3K_0402_1%
PD101
RTC_VCC

2
2

1 RTC_VCC 20MIL
JRTC1 +3VL 20MIL
C 3 2 PR101 1 1 C
2 1 VCCRTC 20MIL
1K_0603_5% 3 2
G1
2

@ BAT54CW_SOT323-3 4
PC105 G2
1U_0402_6.3V6K ACES_50273-0020N-001
1

ME@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DCIN / RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

SUYIN_125022HB008M202ZL VMB2
8A_24V_F1206HI8000V024T VMB EMC@
D JBATT1 D
PF201 HCB2012KF-121T50_0805
1 PL201
1 2 1 2 1 2
9 2 3 BATT+
EC_SMCA PR202 1 2 100_0402_1%
EC_SMB_CK1 44,53
10 GND1 3 4 EC_SMDA 1 2 1 2
GND2 4 EC_SMB_DA1 44,53
5 PR201 100_0402_1%
5 6 PL202
6 7 HCB2012KF-121T50_0805
7

2
8
8 EMC@

1
ME@ PC201 PC202
1000P_0402_50V7K 0.01U_0402_25V7K

2
EMC@ EMC@

PD201

EMC_NS@

AZC199-02S.R7G_SOT23-3

1
Reverse PD201 PD202 For EMI request

PR209
1 2
+3VALW
100K_0402_1%

PR213
C BATT_TEMP_IN 1 2 C
10K_0402_5%
BATT_TEMP 44,53 A/D
1

PD202
1

EMC_NS@
AZ5215-01F_DFN1006P2E2
2
2

PR227
1 2
B+ +20VSB
0_0603_5%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

AON6414AL_DFN8-5
VIN PQ311 PQ312
P3
AON7408L_DFN8-5
P2 @ PR301
1 1 PJ301 0.01_1206_1%
2 2 JUMP_43X118
5 3 3 5 1 2 1 4
1 2 B+
2 3

0.1U_0402_25V6

1000P_0402_50V7K

1000P_0402_50V7K
D D

10U_0603_25V6-M

10U_0603_25V6-M

0.1U_0402_25V6
0.022U_0402_25V7K
4

2
EMC@

EMC@
PC311

PC317

PC331
EMC_NS@

EMC_NS@
1

2
PC303

PC304

PC312
EMC_NS@

EMC_NS@
1

PC302

1
PC301 PR302

1
4.7_0603_5% PQ314

2
470P_0402_50V7K AON7408L_DFN8-5

5
0.1U_0402_25V6

2
PC305
1 2

BQ24780_BATDRV 4

1
3 1

D
PC306
@ PQ313 PC307 0.1U_0402_25V6

1
2N7002KW_SOT323-3 1U_0603_25V6K

3
2
1
2
PR303

G
499K_0402_1% PC308

2
2 1 2 1 0.01U_0402_25V7K

1
VIN BATT+

2
1M_0402_5% 1M_0402_5%
PR304 PR305
@ @

BAT54CW_SOT323-3
PD302
2

3
B+
PQ315

2200P_0402_50V7K
2N7002KW_SOT323-3
VIN

10U_0805_25V6K

10U_0805_25V6K
1
1

2
EMC@
D

PC310

PC313
4.02K_0603_1%

4.02K_0603_1%

ACN
ACP
1 2 2
PR310

PR311

PC314
44 ACOFF
PR309 G

1
2
0_0402_5%
2

5
@ S PR314 BQ24780_VDD
@
3

1
C PR313 10_1206_5% C
PR312 64.9K_0603_1% 1U_0603_25V6K

ACN
ACP
10K_0402_1% 1 2 432K_0603_1% PC315

1
@ PR315 2 1 780_VCC 28 24 1 2 PQ316
1

2
VCC REGN 2.2U_0603_10V6-K PC316 4
1 2 ACDET 6 AON7408L_DFN8-5
PC309 ACDET PR316 PC318
0.1U_0402_25V6 25 BST_CHG1 2 2 1
BTST 2.2_0603_5% PR317

3
2
1
BQ24780SRUYR_QFN24_4X4 0.047U_0603_16V7K 4.7UH_PCMB063T-4R7MS_5.5A_20% 0.01_1206_1%
3 26 DH_CHG PL302
CMSRC HIDRV 1 2 CHG 1 4 BATT+
@ 2 PR339 1 20K_0402_1% 4
ACDRV 2 3

1
BQ24780_VDD 100K_0402_1% 2 PR324 1 @ 27 LX_CHG
PHASE PR321

10U_0805_25V6K

10U_0805_25V6K
2

2
0_0402_5% 1 PR325 2 ACIN_R 5 2.2_0805_5%

PC319
44 ACIN ACOK EMC_NS@

PC320
0_0402_5% 1 PR320 2 EC_SMB_DA1_R 11

1
44,52 EC_SMB_DA1 SDA PU301 23 DL_CHG PQ317 4
LODRV

1
0_0402_5% 1 PR322 2 EC_SMB_CK1_R 12 22 AON7408L_DFN8-5
44,52 EC_SMB_CK1 SCL GND PC321
1200P_0402_50V7-K

3
2
1

2
0_0402_5% 1 PR323 2 ADP_I_R 7 29 EMC_NS@

0.1U_0402_25V6

0.1U_0402_25V6
44 ADP_I IADP PAD

1
IDCHG 8 18 BQ24780_BATDRV

PC322

PC323
IDCHG BATDRV
9 PR338 10_0603_5%
Psys

2
PMON 17 2 1
BATSRC
100P_0402_50V8J

100P_0402_50V8J
2

20 SRP_R 2 1 SRP
10 SRP PR328 10_0603_5%
44,59 VR_HOT#
100P_0402_50V8J

1
PROCHOT#
PC324

PC325
1

13 PC327
PC326

@ CMPIN
0.1U_0402_25V6

2
BATPRES#
TB_STAT#
14
1

CMPOUT 19 SRN_R 2 1 SRN

B
ILIM 21 SRN PR329 10_0603_5% B
ILIM
2

PR330

16

15
0_0402_5%
+3VALW VIN
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
PR331 14.7K_0402_1%
316K_0402_1% PR332
1

1
1

PR334 PR333
750_0603_1% @ PC328 100K_0402_1%
PR335 0.1U_0402_25V6
2

1M_0402_5%
2

2
2

@
2

D PQ310A
PR336 2 ADAPTER_ID_ON#_G
0_0402_5% G

S 2N7002KDWH_SOT363-6
1

@
ADAPTER_ID 44,51
1

D
680P_0402_50V7K

5 ADAPTER_ID_ON# 44
1

PR337 @ G
1M_0402_5%
1
0.1U_0402_25V6

S PQ310B
PC329

4
1

PD304 2N7002KDWH_SOT363-6
PC330

A AZ5123-01F.R7G_DFN1006P2X2 A
2

@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 53 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW

2
PR407
D 100K_0402_5% D
@
B+ @

1
PJ401 PU401
2 1
1.5A +3V_VIN 5 9 +3V_PWRGD
2 1 4 IN1 PG 1 +3VBS 1 2

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
1

1
3 IN2 BS PC403
2 IN3 +3VALW

SY8286BRAC_QFN20_3X3
JUMP_43X79 0.1U_0603_25V7-M

PC401

PC402

PC452
IN4 6 @
4A

2
EMC@ 7 LX1 19 PL401 PJ402
8 GND1 LX2 20 +3VLX 1 2 +3VALW_P 2 1
18 GND2 LX3 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
21 GND3
GND4

1
PR414 JUMP_43X79
2 1 EC_ON_R 2 1 +3VALW_EN 12 14 +3VALW_P PR403

PC434

PC432

PC431

PC435
44 EC_ON 0_0402_5% 0_0402_5% +3V_VIN 11 EN1 OUT 2.2_0805_5%

2
PR415 EN2 13 +3VALW_FB EMC_NS@
10 FF

2
15 NC1
100mA +3VLP

1
39 EC_ON_R 16 NC2 17

1M_0402_5%
0.1U_0402_25V6
NC3 LDO

1
PR401
1
PR417 PC410

PC408

4.7U_0603_6.3V6K
1
2 1 @ 1200P_0402_50V7-K

2
44 MAINPWON 0_0402_5% EMC_NS@

PC409
2

2
2

2
PR429
330_0603_5%
@
1 1

D PC411
PQ405 PR405
1

2 1 2 1 2
PR427 G PC425
100K_0402_5% 2.2U_0603_10V7K 1000P_0402_50V7K 1K_0402_1%
+3VL
2

@ S @
+3VLP
3

2N7002KW_SOT323-3 @
2

PJ404
@ 2 1
2 1
C C

JUMP_43X39

+3VALW

2
PR406
100K_0402_5%
@
B+

1
@ PU402
PJ405
2 1
2.5A +5V_VIN 8 2 +5V_PWRGD
2 1 IN PG
0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
1

SYX198CQNC_QFN10_3X3

PC415
PC413

PC414

JUMP_43X79 9 6 +5VBS 1 2 +5VALW

PC412

GND BS 3.3UH_PCMB063T-3R3MS_6.5A_20%
5A
2

EMC@ PC416 0.1U_0603_25V7-M PL402 PJ406

1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
VCC LX 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR409 1U_0603_25V6M PR410

1
EC_ON_R 1 2 +5VALW_EN 1 4 +5VALW_OUT 1 2+5VALW_P JUMP_43X79
B EN OUT 0_0402_5% PR411
B

PC417

PC418

PC419

PC420
0_0402_5% 2.2_0805_5% @
100mA

2
+5VFB 3 7 EMC_NS@
FB LDO +5VLP
2
1M_0402_5%

4.7U_0603_6.3V6K
1

1
1

1
PR412

PC422

@ PC421 PC423
2

0.1U_0402_25V6 1200P_0402_50V7-K
2

EMC_NS@
2

PC424 PR413
1 2 1 2

6800P_0402_25V7-K 1K_0402_1%

6800pf soft start 2ms

47nf soft start 7ms

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 54 of 60
5 4 3 2 1
 A B C D

B+ @ 2A
PJ501
2 1 1.35V_B+
2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
EMC@
PC503

PC504

PC505
@
JUMP_43X79 @ PJ502
2 1

2
1

0.1U_0603_25V7-M 2 1 1

PU501 0_0603_5% PC506 JUMP_43X118

1 10 BST_1.35V 1 PR506 2 2 1 0.68UH_PCMB063T-R68MS_16A_+-20%
VIN BST PL501 PJ503
PR501 0_0402_5% 9 LX_1.35V 1 2 1.35V_L 2 1
1 2 S3_1.35V 16 SW 2 1
+1.35V

NB685GQ-Z_QFN16_3X3
5 CPU_DRAMPG_CNTL PR503 EN1 JUMP_43X118

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@ 44 SYSON 1 2 S5_1.35V 15 13 1.35V_FB @ 220P_0402_50V7K @
EN2 FB

1
PC515

PC516

PC517

PC518

PC519
2 1 2 1

EMC_NS@
0_0402_5% 0_0402_5%

2.2_0805_5%
44 VDDQ_PGOOD 1A DIS ------11A

PR508
2 PR511 1 1M_0402_5% @ PC510 @
44,46,58 SUSP# 2 1 12 6 1.35V_L PR513

0.1U_0402_10V7K

0.1U_0402_10V7K
+0.675VSP

2
PR502 100K_0402_1% PG VDDQ

2
PC501 @

PC502
DDR_3V3 3

2
3V3

1
5

499_0402_1%
@

1.35V_SN

41.2K_0402_1%
1U_0402_6.3V6K
VTT

PR512

PR509
1

2
@
PC509
4

4.7_0402_5%

1200P_0402_50V7-K
AGND

1 PR507 2
8
VTTS

1
2

EMC_NS@
2

2
PGND

PC512
7 VTTREF

22U_0603_6.3V6-M
VTTREF @

1
1
PC508
Mode 14 11 PJ504
MODE OTW# 2 1

1U_0402_6.3V6K
+0.675VSP 2 1 +0.675VS
1.35V_FB

2
2

PC511
1.35V_GND
PR504 JUMP_43X79
+3VALW

1
0_0402_5%

2
PR510
32.4K_0402_1%

1
1.35V_GND

2
1.35V_GND
2 2

1.35V_GND

PJ505
1 2

JUMPER
@

1.35V_GND

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 1.35VS/+0.675VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 55 of 60
A B C D
 A B C D

+5VALW

500mA

1
PC601
1U_0402_6.3V6K TP Pin connect to GND +1.8VALW_L +1.8VALW

2
500mA
1 PU601 1

PJ601 6 PJ602
2 1 +1.8VALW _VIN 5 VCNTL 3 2 1
+3VALW 2 1 9 VIN VOUT1 4 2 1
TP VOUT2

22U_0805_6.3V6M
JUMP_43X39 JUMP_43X39

1
2 1 EN_+1.8VALW 8 @
44,46,52,56 PCH_PW R_EN EN

1
@ 0_0402_5% 7 2 +1.8VALW _FB PC603 @

PC604
GND
PC602 PR604 POK FB PR602 220P_0402_50V7K

.1U_0402_10V6-K

2
4.7U_0603_6.3V6K 30K_0402_1%

1
@ APL5930CKAI-TRG_SO8

PC607

2
100K_0402_5%
1
2

PR617
@

1
PR605

2
23.7K_0402_1%

+3VALW

2
+3VALW
2 2

1
PR607
10K_0402_5%
@
B+

2
PJ603 PU602
2 1 VIN_+1.0VALW 2 9 0.1U_0603_25V7-M
2 1 3 IN1 PG PC619 @ +1.0VALW
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

IN2
1

JUMP_43X79 4 1 +1.0VALW _BS 1 2 PL602

IN3 BS PJ604
1

@ EMC@ @ 5 0.68UH_PCMB063T-R68MS_16A_+-20%
PC608

PC609

PC610

IN4 6 +1.0VALW _LX 1 2 +1.0VALW _L 2 1

2

SY8288RAC_QFN20_3X3
7 LX1 19 2 1
2

8 GND1 LX2 20
GDN2 LX3 JUMP_43X118

1
100K_0402_5% 18

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
GND3

1
@ PR608

330P_0402_50V8J
PR614 14 2.2_0805_5%

PC611

PC612

PC613

PC614
1 2 +1.0VALW _ILNT 13 FB EMC_NS@

PC618
+3VALW

2
ILMT

1
1 2
1

10K_0402_5%
PR616 1 2 11
+1.0VALW _EN 17 +1.0VALW _LDO +1.0VALW
PCH_PW R_EN

2 2
EN VCC

1
1M_0402_5% PC615

1
@ PR610 10 1200P_0402_50V7-K PR613
TDC :7.68A

2
15 NC1 12 EMC_NS@ PR618 20K_0402_1%
+3VALW
2

BYP NC2
1

16 PC632 1K_0402_1%
OCP :14A

2
PC616 NC3 21 4.7U_0603_6.3V6K

2
TP
1

.1U_0402_10V6-K
2

1
3 PC627 +1.0VALW _FB 3

4.7U_0603_6.3V6K
2

1
PR612
29.4K_0402_1%

2
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +1.8VAWL/+1.0VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 56 of 60
A B C D
 5 4 3 2 1

D D

+3VS
1A 2A +0.95VSP_VGA +0.95VGS
PX@ PX@
PU701
1UH_PH041H-1R0MS_3.8A_20%
PJ701 PL701 PJ702
2 1 0.95VGS_VIN 4 3 0.95VGS_LX 1 2 2 1
2 1 IN LX 2 1

1
JUMP_43X79 2 JUMP_43X79

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
@ GND PR702 @
5 1 2.2_0603_5%

PC701

PC702

68P_0402_50V8J
FB EN

1
EMC_PXNS@

59K_0402_1%

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2

1
PR706

PC708
1 2
SY8089AAAC_SOT23-5

PX@

PX@

PC703

PC704
FB=0.6Volt

2
PX@ PX@ PC707

2
680P_0402_50V7K

2
@ EMC_PXNS@
PD701 PX@ PX@
1 2
0.95VGS_FB

PR703
2 1 0.95VGS_EN
8,24,58 PXS_PWREN 47K_0402_5%

1
PX@

1
PR707

1
PR705 PC706 100K_0402_1%
1M_0402_5% .1U_0402_10V6-K PX@

2
PX@ PX@

2
C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +0.95VS_VGA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 57 of 60
5 4 3 2 1
 5 4 3 2 1

+VGA_B+
D
B+ D
@
PJ801
1.5A 2
2 1
1

JUMP_43X79

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
EMC_PX@

1
PC801

PC802

PC803
5

2
PQ801

33K_0402_5%
AON6372_DFN8-5

1
0_0402_5%

10K_0402_5%

10K_0402_5%
PR802
PX@

PR801

PR803

PR804
PX@ PX@

@
VGA_UGATE1 4
+VDDIO_GPU

2
2

2
PX@ PX@ PX@ PX@
PR805 0.22UH_PCMB063T-R22MS_23A_20%

3
2
1
1

1
PC804 PC805 1 2 PL801
.1U_0402_10V6-K 1U_0402_6.3V6K
+5VS
VGA_PHASE1 1 2 +VGA_CORE

1200P_0402_50V7-K 2.2_0805_5%
@ PX@ 0_0402_5%
2

EMC_PXNS@
PX@ PQ802

PR808
PR807 PC806 AON6764_DFN8-5

40

39

38

37

36

35

34

33

32

31
PU801 1
VGA_BOOT1 2 1 2

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
+3VGS

PX@

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
2.2_0603_5% 0.22U_0603_16V7K 1 1 1

2
+5VS PX@ PX@
1

PC807

PC808

PC818
PR806 PX@ 100K_0402_1% VGA_LGATE1 4 PR809 PR810 + + +

PC809
PR811 1 2 1 30 3.65K_0402_1% 10_0402_1%
NTC_NB BOOT2

EMC_PXNS@
2.2K_0402_1% PR813 PX@ 100K_0402_1% PX@ PX@

2
1 2 2 29 2 2 2
PX@

1
IMON_NB UGATE2 PR815 PX@ PX@ PX@
2

3
2
1
3 28 0_0402_5%

VSUM+
21 GPU_SVC SVC PHASE2

VSUM-
PX@
PR814 2 PX@ 1 0_0402_5% VRHOT_L 4 27

1
21 GPU_HOT# VR_HOT_L LGATE2
C C
5 26 VGA_VDDP
21 GPU_SVD SVD VDDP
6 25 VGA_VDD 1 PX@ 2
+VDDIO_GPU VDDIO VDD
ISL62771HRTZ_TQFN40_5X5 1_0603_5%
7 24 VGA_LGATE1 PR816
21 GPU_SVT SVT LGATE1

1
PR817 2 PX@ 1 150K_0402_5% 8 PX@ 23 VGA_PHASE1 PC810 PC811
8,24,57 PXS_PWREN ENABLE PHASE1 1U_0603_25V6K
1U_0603_25V6K

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR818 2 PX@ 10_0402_5% 9 22 VGA_UGATE1 PX@ PX@
PD801 20 GPU_PWROK PWROK UGATE1
1

@
1 2 PC812 VGA_IMON 10 21 VGA_BOOT1
VGA_IMON IMON BOOT1

1
PC829

PC830

PC831

PC832
.1U_0402_10V6-K
2

PGOOD
ISUMN
ISUMP

COMP
ISEN2

ISEN1

VSEN
RB751V-40_SOD323-2 PX@
NTC

RTN

2
FB

TP
PR822
2

2 PX@ 1 PX@ @ PX@ @

+3VGS
11

12

13

14

15

16

17

18

19

20

41
2

PR820 PR821 PC816 100K_0402_1%

1000P_0402_50V7K

62771_COMP
133K_0402_1%

VGA_VSS_SEN
VGA_CORE_SEN
1.91K_0402_1%
1

62771_FB
PX@ PX@ PX@
1

VGA_PWRGD 8,20,44
1

+3VGS

VGANTC

+5VS
B B

PR826 2 PX@ 1 10K_0402_5%

PR829 2 PX@ 1 10K_0402_5%

1

PC821 PC822 PC823 PX@

0.22U_0402_10V6K 1 2 PX@ PX@
0.22U_0402_10V6K PX@ PC824 PR831 PC825 PR832
2

PX@ 0.1U_0402_25V6 PR830 PX@ 1 2VGA_FB_2 1 PX@ 2 1 2 1 @ 2

VSUM- 1 2
100P_0402_50V8J 499_0402_1% 47P_0402_50V8J 32.4K_0402_1%
1

1.2K_0402_1%
330P_0402_50V8J

PX@ PR833 PR834 PR836 PX@ PR837 PC827

PR835
1
PC828

2.61K_0402_1% 3.9_0402_1% PR839 PC826 @ 1 2 1 PX@ 2VGA_FB_1 1 2

1

1 2 PX@ PX@ 2 @ 1 1 2 PX@

PR838 1K_0402_1% 54.9K_0402_1% 150P_0402_50V8-J
2

2
10K_0402_1%_TSM0A103F34D1RZ

93.1K_0402_1% 11K_0402_1% 10K_0402_5% 0.22U_0402_10V6K

0.047U_0402_25V7K

0.047U_0402_25V7K

VGANTC PX@ PX@ @

2

2 PR8401 VGA_FB_3 1 2
2

1
PX@
PH801

PC839

PC840

PH802
2K_0402_1% PC841
VGA_NTC_1 2 1 680P_0402_50V7K
2

@
1

470K_0402_5%_TSM0B474J4702RE PX@ PX@

1

PX@ VSUM+
PR841
10.5K_0402_1% VGA_CORE_SEN 21
PX@
330P_0402_50V8J
2

PX@
PC842
2

A A

VGA_VSS_SEN 21
1

PC843
0.1U_0402_25V6
2

PX@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR-VGA_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 58 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCST_CPU
+5VS +5VS
B+

2
2.2_0603_5% 2.2_0603_5%

1
PR922 PR926

1
+VCCST_CPU PC918

1K_0402_1%

75_0402_1%

100_0402_1%
45.3_0402_1%
PR923

PR933

PR943

PR932
1U_0402_6.3V6K

2
@

2.2U_0603_10V7K

2.2U_0603_10V7K
D D

2
Psys

PC912

PC916

VR_VCC
1

VR_VRMP

1
VR_PVCC
PC920

1
@ 0.01U_0402_25V7K

1K_0402_1%

1K_0402_1%

2
PR944 PR936

PR945

PR946
54.9_0402_1% @ @ 10_0402_1%
VR_SVID_DAT_1 2 1

18

13

12
VR_SVID_DAT 12
20K_0402_1% PU901 NCP81206MNTXG_QFN52_6X6 PR937

2
1 PR940 2 50 36 VR_SVID_DAT_1 0_0402_5%

PVCC

VCC

VRMP
0_0402_5% PSYS SDIO 38 VR_SVID_CLK_1 VR_SVID_ALRT#_1 2 1
SCLK 37 VR_SVID_ALRT# 12
PR916 VR_SVID_ALRT#_1 PR938
2 1 VR_EN 41 ALERT# 49.9_0402_1%
44 EC_VR_ON EN VR_SVID_CLK_1 2 1
39 VR_SVID_CLK 12
DRON DRON 60
42
44 CPU_VR_READY VR_RDY
35
44,53 VR_HOT# VRHOT# PR919 PC910
26 Vcore_BST 1 2 1 2
BST3 23.2K_0402_1%
2.7K_0402_1% 1500P_0402_50V6-K
VCORE PORTION 2.2_0603_5% 0.22U_0603_16V7K 1 PR947 2
SW3 59,60
1 PR903 2 2 1 PC902 Vcore_COMP 30 25
COMP_1a HG3 HG3 60
20K_0402_1%
1 2 2 PR901 1Vcore_ILIM 31 PH905
22K_0402_1%
PC901 15P_0402_50V8J 1 2 ILIM_1a 24 1 PR948 2 2 1
SW3 SW3 59,60 +CPU_CORE 12,60
1.74K_0402_1% 1000P_0402_50V7K PC909
1 PR913 2 Vcore_VSP 28 100K_0402_1%_NCP15WF104F03RC
12 VCORE_VCC_SEN VSP_1a
1 2 1 2 23
LG3 60
2

PC913 PR910 PC904 1000P_0402_50V7K 1K_0402_1% LG3/ICCMAX_1b 11K_0402_1% 1 2

1000P_0402_50V7K 1.74K_0402_1% 1 PR911 2 Vcore_VSN 29 1 PR941 2 PC942 3300P_0402_50V7K
470P_0402_50V7K VSN_1a
1

1 2 2 1 Vcore_IOUT 34 33 Vcore_CSP 1 2
12 VCORE_VSS_SEN IOUT_1a CSP_1a
330P_0402_50V7K PC906 PC911 PC922 3300P_0402_50V7K
2 1 27 32
PR917 TSENSE_1ph CSN_1a
C C
49.9K_0402_1%
Vcore_TSENSE
VCCGT PORTION 118K_0402_1%
1

7 GT_CSSUM 1 PR949 2
CSSUM_2ph SW1 59,60
PR942
MOSFET

0_0402_5% 6 GT_CSCOMP PR950 1 2 75K_0402_1% 1 2 PR904

470P_0402_50V7K CSCOMP_2ph 147K_0402_1%
2 1 PC930 1 2
100K_0402_1%_NCP15WF104F03RC

PH901 1 2 PC925
2 1 GT_IOUT 1 220K_0402_5%_ERTJ0EV224J 330P_0402_50V7K
1

27.4K_0402_1% IOUT_2ph 5 GT_ILIM 2 1 2 1

8.25K_0402_1%

.1U_0402_10V6-K

ILIM_2ph
1

PR959 100K_0402_1% PR951 12.7K_0402_1% PC914 330P_0402_50V7K

Place close to

PH902

PR931

PC924

1 PR902 2 8 GT_CSREF 1 2
CSREF_2ph +VCC_GT 12,60

0.22U_0603_16V7K
2

GT_DIFFOUT 2 14 GT_BST 1 2 PR924

0.01U_0402_25V7K
2

470P_0402_50V7K PR934 2200P_0402_50V7K DIFFOUT_2ph/ICCMAX_2ph BST1 PR925 2.2_0603_5% 10_0402_1%

PC915
1 PR914 2 1 2 1 2 1 2 GT_COMP 4

PC917
2

1
49.9_0402_1% PC907 13.7K_0402_1% PC908 COMP_2ph 15
1 2 1 2 HG1 HG1 60

1
PR918 PC932 10P_0402_50V8J

2
1K_0402_1% GT_FB 3 16 PC926
FB_2ph SW1 SW1 59,60
0.047U_0402_16V7K

2
17
LG1/ROSC LG1 60
PR954
2 1
51 14K_0402_1%
12 VCCGT_VCC_SEN VSP_2ph 10 1 2
GT_CSP
CSP1_2ph SW1 59,60
2

1.5K_0402_1% PR953
PC931 1 PR964 2 GT_VSN 52 1.8K_0402_1%
1000P_0402_50V7K VSN_2ph 9 1 2
+5VS
1

1 2 CSP2_2ph 0_0402_5%
12 VCCGT_VSS_SEN 22
PC933 2200P_0402_50V7K PR952
BST2

GT_TSENSE 11 21
B TSENSE_2ph HG2 B

20 PR927
1.5K_0402_1% 0.015U_0402_25V7-K SW2 51.1K_0402_1%
1 PR965 2 2 1 PC936 SA_COMP 47 40 1 2
1

COMP_1b PWM/ADDR_VBOOT 180K_0402_1%

PR960 1 2 PR912 1 PR956 2
0_0402_5% PC935 15P_0402_50V8J 2 1 SA_ILIM 46
VCCSA PORTION VCCSA_Phase 60
ILIM_1b PWM 60
54.9K_0402_1%
PH904
1 2 84.5K_0402_1%
100K_0402_1%_NCP15WF104F03RC

1000P_0402_50V7K PC940 1 PR957 2 2 1

+VCCSA 13,60
5.76K_0402_1% 22.6K_0402_1%
1

1 PR966 2 SA_VSP 49 19 Vcore_ICCMAX 1 PR955 2 100K_0402_1%_NCP15WF104F03RC

8.25K_0402_1%

.1U_0402_10V6-K

13 VCCSA_VCC_SEN
1

5.76K_0402_1% VSP_1b LG2/ICCMAX_1a

PH903

PR963

PC934

1 PR907 2 1 2 1K_0402_1% 1 2
PC937 PC938 1000P_0402_50V7K 1 PR970 2 SA_VSN 48 PC941 1500P_0402_50V6-K
2

VSN_1b
IOUT_1b

1000P_0402_50V7K 44 SA_CSP 1 2
2

CSP_1b
EPAD

1 2 PC927 1000P_0402_50V7K
13 VCCSA_VSS_SEN 45
330P_0402_50V7K PC939
CSN_1b
43

53

SA_Iout
1

1
470P_0402_50V7K PR958
PC929 226K_0402_1%
2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Thursday, May 28, 2015 Sheet 59 of 60
5 4 3 2 1
 A
B
C
D

59,60

59
59
59,60

59
59

LG1
HG1

SW1
LG3
HG3

SW3

4
4

5
5

4
4

3 5 3 5
2 2
1 1 3 5 3 5
2 2
1 1

PQ1006
PQ1005
PQ1002
PQ1001

AON6764_DFN8-5
AON6372_DFN8-5
AON6764_DFN8-5
AON6372_DFN8-5

2 1 2 1
2 1 2 1
EMC@

PC1047
PR1008
PR1002

EMC@
EMC@
PC1026

+5VS PC1001

EMC_NS@
EMC_NS@
0.1U_0402_25V7-K

2.2_0805_5%
2.2_0805_5%

2 1

1200P_0402_50V7-K
EMC@
1000P_0402_50V7K

PC1032
0.1U_0402_25V7-K PC1002
1

2 1 10U_0805_25V6K
2 1
1

1
PC1033 PC1003
PR1014

10U_0805_25V6K 10U_0805_25V6K
2.2_0603_5%

2 1 PC1034 2 1
PL1001

1U_0402_10V6K

PL1003
2 1
2

4
4

PC1031

2
10U_0805_25V6K
2 1
CPU_VIN

59
59
0.15UH_PCMB063T-R15MS_30A_20%

0.15UH_PCMB063T-R15MS_30A_20%
2

DRON
PWM
2

SW3
@

SW1
PJ1001

CPU_VIN
1

+VCC_GT
59,60
+CPU_CORE
JUMP_43X79

59,60
1

12,59
12,59

PR1005
2
1
+

10_0402_5%
0_0402_5%

1
1

+
+

2
1 PR1004 2

2 3
2 3

PC1045 PC1015
PC1004

220U_D2_2VM_R6M 220U_D2_2VM_R6M
68U_25V_M

1
+
VCCSA_EN

2 3
EMC_NS@
VCCSA_VCC

VCCSA_PWM

PC1066 PC1078
220U_D2_2VM_R6M 0.1U_0402_25V7-K
B+

9
3
2
4

2 1
EMC_NS@
EN

PC1080
VCC
PU902

PWM

FLAG

0.1U_0402_25V7-K EMC_NS@
2 1 PC1079
2200P_0402_50V7K
2 1
EMC_NS@
SW
BST

GND
DRVH

DRVL

PC1081
2200P_0402_50V7K
6
5
7
8
1

NCP81253MNTBG_DFN8_2X2

2 1
+CPU_CORE

VCCSA_BST

3
3

+VCC_GT
1

2 1 2 1
@

PC1067 PC1052
PR1013

VCCSA_LG
VCCSA_HG

22U_0603_6.3V6-M 22U_0603_6.3V6-M
2.2_0603_5%
2

VCCSA_Phase

2 1 2 1

PC1068 PC1053
22U_0603_6.3V6-M 22U_0603_6.3V6-M
1

Issued Date
2 1 2 1
@

PC1069 PC1054
PC1030
2

Security Classification
22U_0603_6.3V6-M 22U_0603_6.3V6-M
0.22U_0603_16V7K

2 1 2 1

PC1070 PC1055
22U_0603_6.3V6-M 22U_0603_6.3V6-M
4
4

2 1 2 1

PC1071 PC1056 3 5 3 5
22U_0603_6.3V6-M 22U_0603_6.3V6-M 2 2
2 1 2 1 1 1

2013/11/08
PC1072 PC1057
22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1 2 1
2 1 2 1
PQ1004
PQ1003

@
AON7506_DFN

PC1073 PC1058
22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1022 PC1005
2 1 2 1 22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1 2 1 2 1 2 1
AON7408L_DFN8-5

PC1074 PC1059 PC1016 PC1006

22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M
PC1046
PR1006

2 1 EMC@ 2 1 2 1
2 1 PC1027
EMC_NS@
EMC_NS@
@
@

PC1075 0.1U_0402_25V7-K PC1023 PC1007

2.2_0805_5%

2
2

22U_0603_6.3V6-M PC1060 2 1 22U_0603_6.3V6-M 22U_0603_6.3V6-M

2 1 2 1 2 1
1200P_0402_50V7-K

22U_0603_6.3V6-M
2 1
Deciphered Date
@

PC1076 PC1017 PC1008

1

22U_0603_6.3V6-M PC1061 PC1028 22U_0603_6.3V6-M 22U_0603_6.3V6-M

2 1 22U_0603_6.3V6-M 10U_0805_25V6K
2 1 2 1 2 1 2 1
LC Future Center Secret Data

PC1077
@
PL1002

22U_0603_6.3V6-M PC1062 PC1029 PC1025 PC1009

22U_0603_6.3V6-M 10U_0805_25V6K 22U_0603_6.3V6-M 22U_0603_6.3V6-M
2

2 1 2 1 2 1
2 1
PC1063 PC1018
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
0.47UH_PCMB063T-R47MS_18A_20%

22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1013

2 1 22U_0603_6.3V6-M
2013/11/08

2 1 2 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
@

PC1024
PC1064 22U_0603_6.3V6-M PC1010
22U_0603_6.3V6-M 2 1 2 1 22U_0603_6.3V6-M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

2 1
+VCCSA

PC1036 PC1019
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

22U_0805_6.3V6M 22U_0603_6.3V6-M PC1011

2 1
2

22U_0603_6.3V6-M
VCCSA_Phase
@

13,59

2 1 2 1
C
+VCC_GT
PJ1002
@

PC1020
59
1

Size

Date:

PC1037 22U_0603_6.3V6-M PC1014

Title

22U_0805_6.3V6M 22U_0603_6.3V6-M
JUMP_43X79
1

2 1
2 1 2 1
PC1021
PC1038 22U_0603_6.3V6-M PC1012
22U_0805_6.3V6M 22U_0603_6.3V6-M
2 1
B+

Document Number

PC1039
22U_0805_6.3V6M
2 1
PWR_CPU_Core

PC1040
Thursday, May 28, 2015
+CPU_CORE

22U_0805_6.3V6M
1
1

2 1

PC1041
22U_0805_6.3V6M

2 1
Sheet
BMWQ1&Q2
@

PC1042
22U_0805_6.3V6M
+VCCSA

60
of
60
Rev
0.3
A
B
C
D