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Incisive ® Verification Kits UVM Multi-Language Reference Product Version 12.1 June 2012
Incisive ® Verification Kits UVM Multi-Language Reference Product Version 12.1 June 2012

Incisive ® Verification Kits

UVM Multi-Language Reference

Product Version 12.1 June 2012

© 2009-2012 Cadence Design Systems, Inc. All rights reserved worldwide. Printed in the United States of America.

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Contents

1

About This Book

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.1-1

1.1

Conventions in This Book

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1-2

2

Multi-Language UVM (ML-UVM) Features for e and SystemVerilog .

2-1

2.1 Requirements for Multi-Language Verification Environments

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2-1

2.2 Multi-Language UVM (ML-UVM) Features

 

2-2

2.2.1

Enabling the ML-UVM Features

 

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2-3

2.3 Multi-Language Trees of UVCs

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2-3

2.3.1 Specifying Top Entities

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2-5

2.3.1.1 -uvmtest Switch for irun (and ncsim)

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2-5

2.3.1.2 -uvmtop Switch for irun (and ncsim)

 

2-6

2.3.1.3 Top Entities Build Order

 

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2-6

2.3.2 Example: Specifying Top Entities

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2-6

2.4 Synchronized Elaboration Phases

 

2-7

2.4.1 Elaboration Phases in the Various Languages

 

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2-7

2.4.2 Synchronized Elaboration Phases with ML-UVM

 

2-8

2.4.3 Starting Point for Quasi-Static Elaboration

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2-11

2.4.4 Using the UVM-SV Configuration Database

 

2-11

2.4.5 Required Changes to User Code

 

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2-13

2.4.6 Example: Synchronized Elaboration Phases

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2-13

2.4.6.1 Trivial SystemVerilog Testbench

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2-14

2.4.6.2 Trivial e Testbench

 

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2-14

2.4.6.3 Trivial e Test File

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2-15

2.4.6.4 Using the e Test as the First Top Entity

 

2-15

2.4.6.5 Using the SystemVerilog Component as the First Top Entity

 

2-16

2.4.6.6 Using Multi-Step Mode Simulation instead of irun

 

2-17

2.5 Data Communication Using TLM

 

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2-18

Contents

 

2.5.1

Advantages of Using TLM

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2-18

2.5.2

Requirements for Using TLM in Multi-Language Verification Environments

2-19

2.5.3

Connecting TLM Ports Across Languages

 

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2-20

 

2.5.3.1 Summary of ML-UVM Features for TLM

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2-20

2.5.3.2 Connecting TLM Ports Between e and SystemVerilog

 

2-21

2.5.3.3 ML-UVM External Path Strings

 

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2-22

 

2.5.4

Passing Transactions Across Languages

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. 2-22

 

2.5.4.1

Type Mapping between e, SystemVerilog, and SystemC

 

2-23

 

2.5.5

Example: e to SystemVerilog TLM Port Connection

 

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2-24

2.5.6

Example: Passing a Compound Transaction

 

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2-26

2.5.7

Matching TLM Ports in ML-UVM

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2-28

2.6

Limitations in This Release

 

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. 2-30

3 Using SystemVerilog Sequences in an e Testbench

 

.3-1

3.1 About Running Sequences in Multi-Language Environments

 

3-1

3.2 Mixed-Language Sequences API

 

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3-2

 

3.2.1 ml_proxy_seq_driver

 

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3-2

 

3.2.1.1

update_item_after_done()

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3-3

 

3.2.2 ml_uvm_sequencer_stub

 

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3-4

 

3.2.2.1 Accessing the ml_uvm_seq Package

 

3-5

3.2.2.2 assign_sequencer()

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3-5

3.2.2.3 prepare_item_to_send()

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3-6

 

3.2.3 Limitations

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3-7

4 Multi-Language UVM (ML-UVM) Reference

 

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.4-1

4.1 ML-UVM irun Command Line Switches

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4-1

 

4.1.1 -uvmtest

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4-1

4.1.2 -uvmtop

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4-3

4.1.3 -ml_uvm

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4-4

4.2 ML-UVM e Utilities

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4-5

 

4.2.1

ml_uvm.connect_names()

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4-5

4.3 ML-UVM SystemVerilog Utilities

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4-6

 

4.3.1 ml_uvm::connect()

 

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4-7

4.3.2 ml_uvm::connect_names()

 

4-8

4.3.3 ml_uvm::external_if()

 

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4-9

Contents

5 UVM Interface Generator (UIG) Reference

.5-1

5.1 Overview of UIG Task Flow

 

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5-2

5.2 UIG Invocation

 

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5-5

5.2.1

run_uig.sh

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5-6

5.3 e Export File

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5-8

5.3.1 e Export File Syntax

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5-9

5.3.2 #include

 

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5-13

5.3.3 Top-Level Attributes

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5-14

5.3.4 UVM Component Element

 

5-16

5.3.5 Sequence Element

 

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5-24

5.3.6 in|inout|out Field Element

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5-28

5.3.7 Item Element

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5-29

5.3.8 Method Elements

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