Digital Electronics: EE2403

Prof Tong Sun

– Office: C151
– Phone: 020 70408128
– Fax: 020 70408568
– e-mail: t.sun@city.ac.uk
– http://www.staff.city.ac.uk/~tong
Module outline
– Logic Design Fundamentals
» Combinational logic
» Sequential logic
– Introduction to VHDL
Digital Electronics: EE2403
Recommended books
– M Morris Mano, Digital Design (third edition),
Prentice Hall 2002
– Charles H Roth, Jr. Digital Systems Design
Using VHDL, PWS Publishing Company, 1998
– S Yalamanchili, VHDL: A Starter’s Guide
(second edition), Pearson Prentice Hall, 2005
– Alan B Marcovitz, Introduction to Logic Design,
McGraw-Hill Higher Education, 2002
– Victor P Nelson, H Troy Nagle, J David Irwin
and Bill D Carroll, Digital Logic Circuit Analysis
& Design, Prentice Hall, 1995
Credit Assessment and Programme Specification (CAPS)

Module: 15 credit points

A typical pattern of a 15 credit module
– 20 hours lectures
– 10 hours tutorial
– 15 hours coursework or laboratory
– 7 hours of private study per credit point
Module pass requirements
– 40% aggregate pass mark is required (35%
for written exam, 40% for coursework/lab)
– Written exam : coursework/lab = 70% : 30%
Lab Sessions
Logic Circuit Design in CG04 (formerly
CM204), Prof Lai
– Weeks 2 to 4 (08/10, 15/10, 22/10), BEAS2, BEAB2,
ELES2, CSYS2, Wednesdays 9:00-11:00
– Weeks 5 to 7 (29/10, 05/11, 12/11), COMB2, ELEB2,
CSYB2, Wednesdays 9:00-11:00
Lab supervisors
– Prof L Lai
– Dr Daniel Nankoo
– Mr Jim Ford
Tutorial Sessions
Friday morning 12:00-13:00 after the two-
hour lecture
Tutorial sheets are published the week before
the tutorial sessions
Introduction
Combinational logic
– has no memory
– the present output depends only on the present
input
Sequential logic
– has memory
– the present output depends not only on the
present input but also on the past sequence of
inputs
A good understanding of sequential network
timing and synchronous design is essential to
the successful design of digital systems
Combination logic
Boolean algebra and algebraic simplification
Karnaugh maps
Designing with NAND and NOR gates
MSI combinational logic circuit components
– Binary adders
– Magnitude comparator
– Decoders/demultiplexers
– Data selectors/multiplexers
PLD (programmable logic device) components
– Read-only Memory (ROM)
– Programmable Logic Array (PLA)
– Programmable Array Logic (PAL)
Definition of binary logic (a)
Binary logic consists of binary variables and
logical operation
– The variables are designated by letters of the
alphabet such as A, B, C, x, y, z, etc. with each
variable having two and only two distinct possible
values: 1 and 0
– Three basic logical operations: AND (represented
by a dot or by the absence of an operator), OR
(represented by a plus sign) and NOT (represented
by a prime, sometimes by a bar)
Definition of binary logic (b)

Comparison of binary logic and binary arithmetic

– Similarity: multiplication and addition
– Difference:
» An arithmetic variable may consist of many
digits; a logic variable is always either a 1 or a
0
» In binary arithmetic: 1+1=10; whereas in
binary logic: 1+1=1
Boolean algebra (a)
In 1854 George Boole introduced a systematic
treatment of logic and developed for this purpose an
algebraic system called Boolean algebra
Boolean algebra (b)
Comparing Boolean algebra with arithmetic and
ordinary algebra, we note the following differences:
– The distributive law of + over ·, i.e. x + yz =
(x+y)(x+z), is valid for Boolean algebra, but not for
ordinary algebra
– Boolean algebra does not have additive or
multiplicative inverse; therefore, there are no
subtraction or division operations
– Postulate 5 defines an operator called complement
that is not available in ordinary algebra
– Duality principle: each relationship, law or theorem
has a dual, obtained by replacing every occurrence
of 1 by 0, 0 by 1, + by · and · by +
Boolean algebra (c)

Note that theorem 1(b) is the dual of theorem 1(a) and that
each step of the proof in part (b) is the dual of part (a).
Any dual theorem can be similarly derived from the proof
of its corresponding pair
Boolean functions (a)
The operator precedence for evaluating Boolean
expressions is (1) parentheses, (2) NOT, (3) AND, and (4)
OR
In ordinary arithmetic, the same procedure holds (except
for the complement) when multiplication and addition are
replaced by AND and OR, respectively
A Boolean function is an expression formed with binary
variables, the two binary operators OR and AND, and
unary operator NOT, parentheses, and an equal sign
– An algebraic expression
– A truth table
– A Boolean function may be transformed from an algebraic
expression into a logic diagram composed of AND, OR and
NOT gates
 Digital logic gates (a)
The electrical circuits which perform logical operations
are called gates
Digital logic gates (b)
Other logic operators
NAND operator: performs the AND operation
followed by the NOT operation; symbol ↑, but
rarely used in engineering
NOR operator: performs the OR operation
followed by the NOT operation; symbol ↓, but
rarely used in engineering
Exclusive OR operator: operating on two variables
A and B is true if A or B is a 1, but not when both A
and B are 1, i.e. it excludes both A and B being a 1;
symbol ⊕
Exclusive NOR operator: The exclusive-NOR
function is true if both A and B are the same and is
false if A and B are different; also called
‘equivalence’(≡); symbol ☼
Boolean functions (b)
Example 1:
(a) represent following functions in a truth table:
F1 = xyz´; F2 = x + y´z; F3 = x´y´z +x´yz + xy´ and F4
= xy´ + x´z
Boolean functions (c)
Example 1:
(b)Implement these functions with gates
Boolean functions (d)
Minterms and Maxterms (a)
A minterm or a standard product: n variables forming
an AND term, with each variable being primed or
unprimed, provide 2n possible combinations
– mj is the symbol for each minterm, where j denotes
the decimal equivalent of the binary number
A maxterm or a standard sum: n variables forming an
OR term, with each variable being primed or
unprimed, provide 2n possible combinations
Any Boolean function
– can be expressed as a sum of minterms (by ‘sum’ is
meant the ORing of terms)
– Any Boolean function can be expressed as a product
of maxterms (by ‘product’ is meant the ANDing of
terms)
 Minterms and Maxterms (b)
Boolean functions expressed as a sum of
minterms or product of maxterms are said to be
in canonical form
Minterms and Maxterms (c)
Example 2:
Express the Boolean functions from the given truth
table by (a) a sum of minterms (b) product of maxterms
Minterms and Maxterms (d)
Solution:
Conversion between canonical forms
Consider the function:

This has a complement that can be expressed as

If we take the complement of F´ by DeMorgan’s

theorem, F will be

From the table, it is clear that the following relation

holds true:

The maxterm with subscript j is a complement of the

minterm with the same subscript j, and vice versa
Sum of minterms (a)
It is sometimes convenient to express the Boolean
function in its sum of minterms form. If not in this
form, it can be made so by first expanding the
expression into a sum of AND terms
Example 3:
Express the Boolean function F = A + B´C in a sum
of minterms
Solution 1:
The function has three variables, A, B and C. The
first term A is missing two variables; therefore
Sum of minterms (b)
This is still missing one variable:

The second term B´C is missing one variable:

But AB´C appears twice, and according to theorem 1

Sum of minterms (c)
Solution 2:
An alternative for deriving the minterms of a Boolean
function is to obtain the truth table of the function
directly from the algebraic expression and then read the
minterms from the truth table

From the truth

table, we can then
read the five
minterms of the
function to be 1, 4,
5, 6 and 7
Product of maxterms (a)
Example 4:
Express the Boolean function F = xy + x´z in a
product of maxterm form
Solution:
First, convert the function into OR terms using
the distributive law:
Product of maxterms (b)
The function has three variables: x, y and z. Each
OR term is missing one variable; therefore

Combining all the terms and removing those that

appear more than once

A convenient way to express this function is

Standard forms
A literal is a primed or unprimed variable and the
two canonical forms of Boolean algebra are very
seldom the ones with the least number of literals
Standard form: the term that form the function may
contain one, two, or any number of literals
– The sum of products: a Boolean expression
containing AND terms, called product terms, of
one or more literals each
– A product of sums: a Boolean expression
containing OR terms, called sum terms, of one or
more literals each
Boolean minimization by algebraic means (a)
Grouping of terms
for example: A + AB + BC = A(1+B) + BC
= A + BC
Multiplication of terms by redundant variables
for example:
AB + AC´ + BC = AB(C + C´) + AC´ + BC
= ABC + ABC´ + AC´ + BC
= BC(1+A) + AC´(1+B)
= AC´ + BC
Boolean minimization by algebraic means (b)
Using De Morgan’s theorem
for example:
(AB´C)´ + (ACD)´ + BC´
= (A´+B+C´) + (A´+C´+D´) + BC´
= A´+B+C´+D´
Using distributive law
for example: A + A´B = (A+A´)(A+B)
=A+B
Karnaugh map minimization method (a)

A Karnaugh map consists of a grid of squares,

each square representing one canonical
minterm combination of the variables or their
inverse
– Arranged with squares representing minterms
which differ by only one variable to be adjacent
both vertically and horizontally
– Squares on one edge of the map are regarded as
adjacent to those on the opposite edge
Karnaugh map minimization method (b)
Minimization technique using Karnaugh map (a)
The expression to be minimized should
generally be in sum-of-product form
The function is ‘mapped’ onto the Karnaugh
map by marking a 1 in those squares
corresponding to the terms in the expression
to be simplified
Pairs of 1’s on the map which are adjacent
are combined using the theorem:
P (A+A′ ) = P
Where P is any Boolean expression
Minimization technique using Karnaugh map (b)
If two or more pairs are also adjacent, these
can also be combined using the same
theorem.
The minimization procedure consists of
recognizing multiple pairs
A group of two 1’s eliminates one variable
from the original minterm while a group of
four 1’s eliminates two variables and a group
of eight 1’s eliminates three variables
Examples of grouping on Karnaugh map (a)
Examples of grouping on Karnaugh map (b)
Examples of minimization using Karnaugh map (a)
Example 5:
Simply the Boolean function:
F(x, y, z) = Σ (0, 2, 4, 5, 6)
Solution:
First, we combine the four adjacent squares in the
first and last columns to give the single literal term
z´
Examples of minimization using Karnaugh map (b)
The remaining single square representing minterm 5
is combined with an adjacent square that has already
been used once. This is not only permissible, but
rather desirable. The simplified function is
F = z´ + xy´
Examples of minimization using Karnaugh map (c)
It is not necessary to convert the original function
into canonical form before minimization
– Each term in the function can be mapped onto the
Karnaugh map directly, noting that a term with
one variable missing maps onto two adjacent
squares, a term with two variables missing maps
onto four squares, etc.
Example 6:
Simplify the Boolean function
F = A´B´C´+B´CD´+A´BCD´+AB´C´
Examples of minimization using Karnaugh map (d)
Solution:
The area in the map covered by this function consists
of the squares marked with 1’s in the figure
Each term of three literals is represented in the map by
two squares
The simplified function is: F = B´D´+A´CD´+B´C´
Don’t-care condition (a)
If a certain combination of variables cannot occur or
it does not matter what the outputs are if the
combination does occur, the combination is known
as a don’t-care condition
Don’t-care conditions are marked on the Karnaugh
map as X’s
Each X can be considered as either a 0 or 1,
whichever is best for minimization
A function with one or more don’t-care conditions is
called an incompletely specified function
Example 7:
Design a circuit which generates the even parity bit
for a 4-bit binary coded decimal (BCD) digit
Don’t-care condition (b)
Solution:
The circuit has four inputs to enter the BCD digit
and one output, the parity bit
Assuming that a valid BCD digit is entered, the
combinations 1010 (10 decimal), 1011 (11 decimal),
1100 (12 decimal), 1101 (13 decimal), 1110 (14
decimal) and 1111 (15 decimal) do not occur and
can be considered as don’t-cares
The parity bit is a 1 whenever there are an odd
number of 1’s in the BCD number, which creates an
even number of 1’s in all
Don’t-care condition (c)
The parity function, simplified expression and the
circuit are shown in the figure
Don’t-care condition (d)
Multilevel NAND circuits
NAND and NOR gates are more common because
they are readily available in integrated-circuit form
Universal gate: any digital system can be
implemented with NAND gates, see the figure
Boolean function implementation using NAND circuits (a)
From a Boolean expression
– Draw the logic diagram with AND, OR, and inverter
gates
– Convert all AND gates to NAND gates with AND-
invert graphic symbols
– Convert all OR gates to NAND gates with invert-
OR graphic symbols

Check all small circles in the diagram

Boolean function implementation using NAND circuits (b)
Example 8:
Implement the multilevel Boolean expression F =
(CD + E)(A + B′) using NAND circuits
Solution:
Boolean function implementation using NAND circuits (c)
Multilevel NOR circuits
Universal gate: any digital system can be
implemented with NOR gates
Boolean function implementation using NOR circuits (a)
From a Boolean expression
– Draw the logic diagram with AND, OR, and inverter
gates
– Convert all OR gates to NOR gates with OR-invert
graphic symbols
– Convert all AND gates to NOR gates with invert-
AND graphic symbols

– Check all small circles in the diagram

Boolean function implementation using NOR circuits (b)
Example 9:
Implement the multilevel Boolean expression F =
(AB + E)(C + D) using NOR circuits
Solution:
Boolean function implementation using NOR circuits (c)
Binary adders (a)
Half-adder: the circuit accepts two inputs, A and B,
and generates two outputs, SUM and CARRY
according to the table
Half adder truth table
Binary adders (b)
The Boolean expression for SUM and CARRY:
SUM = A' B + AB '
CARRY = AB
Half adder circuit
Binary adders (c)
Full adder: adds two binary digits A and B together
with a ‘carry-in’ from a previous addition. A full
adder has three inputs, A, B and ‘CARRY-IN’
(abbreviated here to Cin), and two outputs, SUM and
‘CARRY OUT’ (abbreviated to Cout)
Full adder circuit
Binary adders (d)
The Boolean expression for SUM and Cout:
SUM = A' B' Cin + A' BC 'in + AB ' C 'in + ABCin
Cout = A' BCin + AB ' Cin + ABC 'in + ABCin
Full adder circuit
Binary adders (e)
A full adder can also be formed from two half adders
Binary adders (f)
Implementation of a full adder
Binary parallel adders (a)

Parallel adder: a digital circuit that produces

the arithmetic sum of two binary numbers in
parallel. It consists of full-adders connected in a
chain, with the output carry from each full-adder
connected to the input carry of the next full-
adder in the chain
The figure shows the interconnection of four
full-adder (FA) circuits to provide a 4-bit binary
parallel adder
Binary parallel adders (b)

Carry propagation: The longest propagation delay

time in a parallel adder is the time it takes the carry
to propagate through the full adders
Binary parallel adders (c)
The carry propagation time is a limiting factor on the
speed with which two numbers are added in parallel
– Employ faster gates with reduced delays
– Increase the equipment complexity to reduce the
delay time, for example, look-ahead carry
Consider the circuit of the full-adder:
Binary parallel adders (d)
If we define two new binary variables:
Pi = Ai ⊕ Bi
Gi = Ai Bi

Gi is called a carry generate and it produces

an output carry when both Ai and Bi are one,
regardless of the input carry
Pi is called a carry propagate because it is the
term associated with the propagation of the
carry from Ci to Ci+1
Binary parallel adders (e)
The output sum and carry can be expressed as
Si = Pi ⊕ Ci
Ci +1 = Gi + Pi Ci

Carry output of each stage:

 Binary parallel adders (f)
look-ahead carry generator
Binary parallel adders (g)
C4 does not have to wait for C3 and C2 to
propagate; in fact, C4 is propagated at the
same time as C2 and C3
The construction of a 4-bit parallel adder with
a look-ahead carry scheme is shown below
After the P and G signals settle into their
steady state values, all output carriers are
generated after a delay of two levels of gates
Binary parallel adders (h)
Magnitude comparator (a)
A magnitude comparator is a combinational
circuit that compares two numbers, A and B,
and determines their relative magnitudes
Consider two numbers, A and B, with four
digits each

A = A3 A2 A1 A0
B = B3 B2 B1 B0
Magnitude comparator (b)
The equality relation of each pair of bits can
be expressed logically with an equivalence
function:
xi = Ai Bi + Ai ' Bi ' i = 0, 1, 2, 3
where xi = 1 only if the pair of bits in position
i are equal, i.e., if both are 1’s or both are 0’s
To determine if A is greater than or less than
B, we inspect the relative magnitudes of pairs
of significant digits starting from the most
significant position.
 Magnitude comparator (c)
The sequential comparison can be expressed
logically by the following two Boolean
functions
( A > B ) = A3 B3 '+ x3 A2 B2 '+ x3 x2 A1 B1 '+ x3 x2 x1 A0 B0 '
( A < B ) = A3 ' B3 + x3 A2 ' B2 + x3 x2 A1 ' B1 + x3 x2 x1 A0 ' B0
Magnitude comparator (d)
Decoders/demultiplexers (a)
A decoder is a combinational circuit that converts
binary information from n input lines to a maximum
of 2n unique output lines
Most IC decoders include one or more enable inputs
to control the circuit operation
Decoders/demultiplexers (b)

The small circle

– at input E indicates that the decoder is enabled when E =
0
– at the outputs indicate that all the outputs are
complemented
A demultiplexer is a circuit that receives information
on a single line and transmits this information on
one of 2n possible output lines
Decoders/demultiplexers (c)
Because decoder and demultiplexer operations are
obtained from the same circuit, a decoder with an
enable input is referred to as a decoder/demultiplexer
Decoders/demultiplexers (d)
Example 10:
Implement a full-adder circuit with a decoder and
two OR gates
Solution:
The functions for the full-adder:

s( x, y , z ) = ∑ (1, 2, 4, 7)
C ( x, y , z ) = ∑ (3, 5, 6, 7)
Decoders/demultiplexers (e)
There are three inputs and a total of eight
minterms, a 3-to-8-line decoder is needed
 Data selectors/multiplexers (a)
A data selector or multiplexer is a logic circuit which
allows one of several data inputs to be selected and fed to
a single output
Data selectors/multiplexers (b)
Example 11:
Implement the function of three variables:
F ( A, B, C ) = ∑ (1, 3, 5, 6)
with a 4-to-1 multiplexer
Solution:
Data selectors/multiplexers (c)
The output is 0 when BC = 00 regardless of the
value of A
The output is 1 when BC = 01 regardless of the
value of A
When BC = 10, the output will be equal to 1 only
for minterm m6 = ABC′
When BC = 11, the output will be equal to 1 only
for minterm m3 = A′BC
Data selectors/multiplexers (d)
A general procedure for implementing any Boolean
function of n variables with a 2n-1-to-1 multiplexer
– Express the function in its sum of minterms,
assume the sequence chosen is ABCD
– Connect the n-1 variables to the selection lines of
the multiplexer, with B connected to the higher
order selection line
– List the inputs of the multiplexer and under them
list all the minterms in two rows –
» In the first row, A is complemented
» In the second row, A is uncomplemented
Data selectors/multiplexers (e)
– Circle all the minterms of the function
» If the two minterms in a column are not
circled, apply 0 to the corresponding
multiplexer input
» If the two minterms are circled, apply 1 to the
corresponding multiplexer input
» If the bottom minterm is circled and the top is
not circled, apply A to the corresponding
multiplexer input
» If the top minterm is circled and the bottom is
not circled, apply A′ to the corresponding
multiplexer input
Data selectors/multiplexers (f)
Example 12
Implement the following function with a multiplexer:
F ( A, B, C , D ) = ∑ (0, 1, 3, 4, 8, 9, 15)
Solution:
This is a four-variable function, we need a multiplexer
with three selection lines and eight inputs
Three types of PLDs (a)
The advantage of using PLDs is that they can be
programmed to incorporate complex logic functions
within one LSI circuit
– The programmable read-only memory (PROM)
has a fixed AND array and programmable fuses
for the output OR gates
– The programmable array logic (PAL) has a fused
programmable AND array and a fixed OR array
– The most flexible PLD is the programmable logic
array (PLA), where both the AND and OR arrays
can be programmed
Three types of PLDs (b)
Read-only memory (ROM) (a)
A ROM is a device that includes both the
decoder and the OR gates within a single IC
package. It consists of n input lines and m
output lines
– Each bit combination of the input variables
is called an address
– Each bit combination that comes out of the
output lines is called a word
A ROM is characterized by the number of
words 2n and the number of bits per word m
Read-only memory (ROM) (b)
Read-only memory (ROM) (c)
For a 2n×m ROM, the blowing of the fuses is
referred to as programming the ROM
(PROM)
Example 13:
Implement the Boolean function:
F1 ( A1 , A0 ) = ∑ (1, 2, 3)
F2 ( A1 , A0 ) = ∑ (0, 2)
by means of a ROM
Read-only memory (ROM) (d)
Solution:
The size of the ROM that implements the
combinational circuit must be 4×2
Read-only memory (ROM) (e)
Types of ROMs
– Mask programming: done by the manufacturer during the
last fabrication process of the unit (economical only for
large quantities)
– PROM: allows the user to program the unit in the
laboratory (economical for small quantities)
– Erasable PROM or EPROM: When an EPROM is placed
under a special ultraviolet light for a given period of time,
the ROM returns to its initial state and can be
reprogrammed
– Electrically erasable PROMs or EEPROMs: erased with
electrical signals instead of ultraviolet light
Read-only memory (ROM) (f)
Interpretation of ROM:
– Memory: commonly used to designate a storage
unit
– Read: commonly used to signify that the contents
of a word specified by an address in a storage
unit is placed at the output terminals
ROM is a memory unit with a fixed word pattern
that can be read out upon application of a given
address. The bit pattern in the ROM is permanent
and cannot be changed during normal operation
Programmable logic array (PLA) (a)
For cases where the number of don’t-care conditions
is excessive, it is more economical to use PLA,
which is similar to ROM in concept, but does not
provide full decoding of the variables
In the PLA, the decoder in ROM is replaced by a
group of AND gates, each of which can be
programmed to generate a product term of the input
variables
The AND and OR gates inside the PLA are initially
fabricated with fuses among them to enable the
desired connections by blowing appropriate fuses
Programmable logic array (PLA) (b)

A ROM implements a combinational circuit in its

sum of minterms form, a PLA implements the
functions in their sum of products form
Programmable logic array (PLA) (c)
Example 14:
A Boolean function is defined by the truth table

Implement the circuit with a PLA having three

inputs, three product terms and two outputs
Programmable logic array (PLA) (d)
Solution:
Map simplification:
Programmable logic array (PLA) (e)
Programmable array logic (PAL) (a)
A compact form of the internal logic of PLDs can be
referred to as array logic

When designing with a PAL, the Boolean functions

must be simplified
Unlike the PLA, a product term cannot be shared
among two or more OR gates
 Programmable array logic (PAL) (b)
Example 15:
Considering the following Boolean functions,
design a combinational circuit using a PAL:

w( A, B, C , D ) = ∑ ( 2, 12, 13)
x ( A, B, C , D ) = ∑ (7, 8, 9, 10, 11, 12, 13, 14, 15)
y ( A, B, C , D ) = ∑ (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z ( A, B, C , D ) = ∑ (1, 2, 8, 12, 13)
Programmable array logic (PAL) (c)
Solution:
Simply the four functions to a minimum number of
terms:
Programmable array logic (PAL) (d)
Programmable array logic (PAL) (e)