FRAM MCUs For Dummies, Part 1

V.C. Kumar, Texas Instruments - August 20, 2012

Editor’s note: Demand for memory is insatiable at all levels of systems design. As
designers look to respond with larger memory stores and more complex memory
architectures, a greater understanding about a broad range of memory types becomes
more critical. This excerpt of Texas Instruments FRAM MCUs For Dummies by V.C.
Kumar offers a detailed look at FRAM technology and its characteristics. In part 1 of
this series, author Kumar reviews the basics of FRAM technology.

Excerpted from Texas Instruments FRAM MCUs For Dummies®, © 2012 John Wiley & Sons, Inc.
Available exclusively from Mouser Electronics, Inc. To request your free copy, please visit
www.mouser.com/framfordummies.

Chapter 2. Understanding FRAM

● Getting to know FRAM

● Comprehending basic FRAM functionality
● Delving into FRAM process technology

Over the years, embedded systems have used a number of different types of memory. Each of these
memory types has come with a set of advantages and disadvantages. TI’s FRAM technology offers a
new unified path that combines the best characteristics of embedded memory systems into a single
package. This chapter shows you how FRAM functions.

Introducing FRAM
The memory used in embedded systems has traditionally come in two flavors: nonvolatile and
volatile (see Figure 2-1):

● Nonvolatile memory is typically used to store programs and data when power to the system is
switched off. Traditionally, updates in this type of memory are infrequent because of technology
constraints such as power consumption, time to program, and so on.
● Volatile memory is typically used to run programs and to store dynamic variables or data that are
often updated. You generally aren’t required to save the contents of volatile memory for future
access in case of power loss.
 Figure 2-1. Embedded memory categories.

An emerging trend is the search for a unified (or universal) embedded memory, which is a
technology that offers the advantages of non-volatility with a fast read/write option. Several
technologies have been considered or tested for a variety of applications, such as low power, fast
speeds, and so on.

FRAM is one of these unified memory technologies. Other emerging unified memory technologies
include:

● MRAM: Magnetoresistive Random Access Memory (MRAM) is a nonvolatile random access

technology where the data is stored as a magnetic state rather than a charge. The data state is
sensed by measuring the electrical resistance of the cell. MRAM is arguably the most mature of the
other unified memory technologies.
● PRAM: Phase-change Random Access Memory (PRAM) is being positioned as a high-density
unified-memory technology. It is based on the unique behavior of chalcogenide glass material.
Heat produced by the passage of an electric current switches this material between four states:
crystalline, amorphous, and two distinct partially crystalline states. The electrical resistivity is
different in each of these states and is measured to identify the data state of the cell.
● RRAM: Resistive Random Access Memory (RRAM) is based on memristors. The concept is that
dielectrics that are normally insulating can become conducting through formation of filaments or
other conductive paths on application of a sufficiently high voltage. This state can be reset
(conductive path broken). The resistance (high, low) can indicate the memory state.

Figure 2-2 compares FRAM to other existing embedded memory technologies, including flash. As
you see in the figure, FRAM is a great fit for ultra-low-power embedded applications.
 Figure 2-2. FRAM memory comparison.

Understanding FRAM Functionality

Understanding FRAM Functionality
Embedded EEPROM (Electrically Erasable Programmable Read-Only Memory) and flash memory
technologies employ a floating gate charge storage design that transports electrons onto a
polysilicon floating gate isolated by an oxide insulator. To reliably produce and store data, a thick
oxide (>8 nm) is typically required, necessitating a high voltage of 10–14 volts to embed the
electrical charge. To create the high voltage on the IC (Integrated Circuit), additional circuits, such
as large transistors and charge pumps, are required.

A disadvantage of the high-voltage circuitry is that it does not easily scale to smaller IC
manufacturing process technologies (or “nodes”). A driving force behind the manufacture of ICs is
miniaturization, and products in smaller process nodes can take better advantage of faster
computing and decreased power consumption. Embedded EEPROM and flash memory require
specially designed high-voltage transistors that can be difficult or technically infeasible to further
reduce in size, thus putting limitations on the ability to scale to smaller chip manufacturing process
technologies.

Further, the programming process for EEPROM and flash memory, in which data is written to by
putting a charge onto the floating gate, limits the write cycle endurance of these memory
technologies.

Embedded FRAM is a nonvolatile memory technology like EEPROM and flash; however, the
similarities end there. As the “RAM” part of the name suggests, FRAM behaves similarly to
DRAM (Dynamic Random Access Memory). It allows random access to each individual bit
for both read and write. FRAM uses tiny ferroelectric crystals integrated into a capacitor.
Ferroelectric properties
A ferroelectric crystal is a dielectric with a reversible spontaneous electrical polarization. There is
no magnetic field sensitivity or disruptions that are associated with iron. The polarization-voltage
hysteresis loops for ferroelectric materials are very similar to the B-H curves of magnetic materials,
as shown in Figure 2-3.

Figure 2-3. Polarization hysteresis loop.

Although “ferro” means iron, FRAM does not contain iron.

In contrast to the complex charge storage mechanism used in EEPROM and flash, FRAM stores
information through the use of a spontaneous, stable electric dipole found in the ferroelectric
crystal. Intrinsically, the dipole atom within a ferroelectric crystal has either positive or negative
orientation, as shown in Figure 2-4.
 Figure 2-4. Dipole positions of ferroelectric crystals.

The embedded FRAM technology from TI uses PZT (Lead Zirconate Titanate or
Pb(Zrx,Ti1-x)O3). This material has a x1-x3 tetragonal perovskite (ABO3) crystal structure, as
shown in Figure 2-5. In PZT, the Ti+4 and Zr+4 ions sit either a small distance (~0.1A) above
or below the center of the cell, while the faces are occupied by O-2 ions. These locations are
minimum energy sites with the location at the center forming an energy barrier to move
between these preferred locations. The displacement of the Ti/Zr ions from the center of
the structure creates the electrical dipole with the oxygen (O-2) ions.

Figure 2-5. Lead-Zirconate-Titanate structure.

Applying an electrical field polarizes the material by creating large regions of the crystal with Ti/Zr
ions all oriented the same direction (domains). By applying a voltage of opposite polarity above the
coercive voltage, the Ti/Zr ions will have enough energy to overcome the energy barrier in the
center of the cell to move to the other low-energy site as Figure 2-5 illustrates. The polarization
change due to ferroelectric switching generates a large charge compared to traditional dielectrics
like SiO2. The equivalent dielectric constant for PZT during switching is >1000 compared to SiO2 of
only 4.

Bit cell structure

Bit cell structure
Memory bit cells can be created using data stored in either 1 Transistor and 1 Ferroelectric
Capacitor (1T-1C mode) or 2 Transistors and 2 Ferroelectric Capacitors (2T-2C mode). A
ferroelectric capacitor is the basis for a FRAM memory cell, as shown in Figure 2-6. This figure
shows both a 1T-1C and a 2T-2C schematic diagram. Note that the 1T-1C diagram is similar to
DRAM. The difference is that in DRAM technology, the plate line is called cell plate and is held at a
constant voltage, while in a FRAM, the plate line is pulsed. As in a DRAM, a bit is at the intersection
of columns of bit lines and rows of word lines. The word line is used to select which capacitors are
connected to the bit line and then when the plate line is pulsed, the charge from the capacitor is
shared with the bit line capacitance. The sense amp detects the voltage difference between the bit
line (BL) and the bit line bar (BLb).

Figure 2-6. FRAM 1T-1C schematic diagram (A,B) and 2T-2C schematic diagram (C,D).

The key element to note is that in a 2T-2C architecture, there are higher measured signal margins
(see Figure 2-7), which lead to fewer bit fails; however, the result is reduced data density because
two cells per bit are used. 1T-1C architecture uses a reference voltage, as shown in Figure 2-8.
 Figure 2-7. Signal margin in 2T-2C architecture.

Figure 2-8. Signal margin in 1T-1C architecture.

FRAM read/write operations

FRAM read/write operations
Read and write operations represent the fundamental way that data is accessed and stored in
semiconductor memory. An FRAM memory cell consists of a ferroelectric capacitor containing
crystalline PZT, which contain many ferroelectric domains, each of which has the same dipole
orientation. The capacitor is connected to by a plate line and bit lines (see Figure 2-9) and a
transistor switch to access the capacitor. For PZT materials, this is a titanium or zirconium ion in a
lead/oxygen crystal lattice.
 Figure 2-9. FRAM cell structure.

Intrinsically, the dipole atom within a ferroelectric crystal has either a positive or negative
orientation. When combined together, the dipoles create a polarization (or charge per unit area
within the crystal). In contrast to the complex charge storage mechanism used in embedded flash or
EEPROM, FRAM stores information through the use of a stable electric dipole found in the
ferroelectric crystal. The orientation of the dipole within the ferroelectric crystals that make up the
capacitor material can be set and reversed through the application of an external voltage on either
the plate line or the bit line.

To read the data from a FRAM memory cell, a voltage is placed on the plate line; the key here is that
you are always trying to set the cell to a 0 state. If the voltage causes dipoles inside the capacitor to
flip orientation, then a large induced charge (Q) is generated on the bit line.

If the orientation of the dipole is already negative prior to applying voltage to the plate line in a read
cycle, then the dipole direction doesn’t change and a small induced charge (Q) is created on the bit
line. So, in reading the data from an FRAM memory cell, a small induced charge is a 0 bit and a
large induced charge is a 1 bit (see Figure 2-10).

Figure 2-10. Reading a FRAM cell.

The key to note here is that because you are potentially changing the state in order to
perform a read, FRAM always requires a memory state refresh after a read. This refresh
operation is automatically done by the memory controller and requires no action by the
user. This behavior is very similar to the way DRAM behaves.

Writing to FRAM is also simple. To write a 1, you apply a volt.age to the bit line to force a change in
the orientation of the dipole to a positive 1 bit. To write a 0, you apply voltage to the plate line to
move state to 0 (see Figure 2-11).
 Figure 2-11. Writing to a FRAM cell.

FRAM Process Technology

Currently, TI manufactures FRAM in the 130nm process geom.etry. FRAM is a 2 mask adder to the
standard Complementary Metal-Oxide Semiconductor (CMOS) process, as shown in Figure 2-12.

The FRAM process flow starts with the standard logic 130nm front-end process flow. This process is
stopped after the CONTACT layer. At that point, instead of proceeding with the metal masks, the
FRAM process module is inserted. After the FECAP and Via0 layers are fabricated, standard logic
metal backend process flows are used.

Figure 2-12. FRAM in the wafer fabrication process.

Excerpted from Texas Instruments FRAM MCUS For Dummies®, © 2012 John Wiley & Sons, Inc.
Available exclusively from Mouser Electronics, Inc. To request your free copy, please visit
www.mouser.com/framfordummies.