J Comput Electron
DOI 10.1007/s10825-016-0804-7
A novel robust exclusive-OR function implementation in QCA
nanotechnology with energy dissipation analysis
Gurmohan Singh1 · R. K. Sarin2 · Balwinder Raj2
© Springer Science+Business Media New York 2016
Abstract Numerous scientific and fundamental hindrances
have resulted in a slow down of silicon technology and
opened new possibilities for emerging research devices and
structures. The need has arisen to expedite new methods
to interface these nanostructures for computing applica-
tions. Quantum-dot Cellular Automata (QCA) is one of
such computing paradigm and means of encoding binary
information. QCA computing offers potential advantages
of ultra-low power dissipation, improved speed and highly
density structures. This paper presents a novel two-input
Exclusive-OR (XOR) gate implementation in quantum-dot
cellular automata nanotechnology with minimum area and
power dissipation as compared to previous designs. The pro-
posed novel QCA based XOR structure uses only 28 QCA
cells with an area of 0.02 µm2 and latency of 0.75 clock
cycles. Also the proposed novel XOR gate is implemented in
single layer without using any coplanar and multi-layer cross-
over wiring facilitating highly robust and dense QCA circuit
implementations. To investigate the efficacy of our proposed
design in complex array of QCA structures, 4, 8, 16 and 32-bit
even parity generator circuits were implemented. The pro-
posed 4-bit even parity design occupies 9 and 50 % less area
and has 12.5 and 22.22 % less latency as compared to pre-
B Gurmohan Singh
gurmohan@cdac.in
R. K. Sarin
sarinrk@nitj.ac.in
Balwinder Raj
rajb@nitj.ac.in
1 nano-scaled technologies to solve the problems being faced
Senior Engineer, DEC-Division, Centre for Development of
Advanced Computing (C-DAC), Mohali 160071, India
2 Nowadays, it has become realistic to manipulate one
Electronics & Communication Engineering Department, Dr.
B.R. Ambedkar National Institute of Technology, Jalandhar,
Punjab 144011, India
vious designs. The 32-bit even parity design occupies 22 %
less area than the best reported previous design. The proposed
novel XOR structure has 28 % less switching energy dissipa-
tion, 10 % less average leakage energy dissipation and 19 %
less average energy dissipation than best reported design. The
simulation results verified that the proposed design offers
significant improvements in terms of area, latency, energy
dissipation and structural implementation requirements. All
designs have been functionally verified in the QCADesigner
tool for GaAs/AlGaAs heterostructure based semiconductor
implementations. The energy dissipation results have been
computed using an accurate QCAPro tool.
Keywords Quantum-dot cellular automata · Majority
gate · Multilayer · QCADesigner · QCAPro · XOR gate
1 Introduction
Silicon technology has experienced tremendous improve-
ments following the foot-prints of Moore’s law for more than
four decades. However, technological and fundamental lim-
its have slowed this progress. With continuous scaling of
feature size, the transistor density and heat generated per
switching cycle has increased tremendously, and existing
heat removal techniques are not effective [1]. The excessive
heat generated cause harm to the chip. Also, the transistor
based nano-switch becomes increasingly leaky with further
scaling resulting in degradation of the Ion /Ioff ratio. The
demarkation between the ON and OFF state has further dete-
riorated. There is imminent need to develop new innovative
by silicon technology [1].
electron at a time, and to develop nanostructures based
on individual electrons [1,2]. QCA is a nanocomputing
123

paradigm that offers a new way of encoding, processing
and transferring binary information. Quantum dots are tiny
nanostructures assembled in the form of arrays for compu-
tation and signal processing. The QCA architecture uses an
arrangement of single electrons that communicate with each
other by Coulombic repulsion over large arrays. This is an
important shift from the existing current-switching transis-
tors. The QCA approach adopts a smart information coding
mechanism appropriate for nanostructures, thus eliminating
problems of current-switching transistors. A QCA array of
cells contains information in the arrangement of polarization
of electronic charges and not in the transport of charges i.e.
QCA cells interact with adjacent cells to directly produce
the dynamics and settles to one of the two ground states. The
alignment is controlled by an external clock and operates
according to the rules of Boolean logic [3–6].
Sheikhfaal et al. [7] introduced a new design of a two-input
XOR gate utilizing an ultra-low power and low-complexity
five-input majority gate. They also carried out power dis-
sipation and structural analysis of the five-input majority
gate. Angizi et al. [8] presented a new robust wire cross-
ing method and implemented it into new 2-input and 3-input
XOR designs. Srivastava et al. demonstrated a new tool,
QCAPro [9], for power estimation and the upper bound of
power estimation in QCA circuits [10]. Timler and Lent
[11] developed a theoretical approach based on the den-
sity matrix formalism for calculating energy dissipation in
QCA circuits. Tougaw and Lent [12] examined the dynamic
behavior of arrays of isolated QCA cells with focus on assess-
ing the intrinsic switching behavior [13]. Beigh et al. [14]
implemented several designs of QCA based XOR gates and
evaluated their performance in terms of cell count, number
of crossovers and delay. Chabi et al. [15] presented simple
and dense multiplexer and Exclusive-OR designs employing
5-input majority gate in Exclusive-OR function realization.
In this paper, we implemented a structurally robust and
efficient Exclusive-OR (XOR) function in QCA with mini-
mum latency (delay), area, complexity and energy dissipa-
tion. This paper is organized as follows: Sect. 2 presents
the QCA background, elementary QCA nanostructures, QCA
based five-input majority gate and QCA technology develop-
ments. Section 3 presents proposed Exclusive-OR structures
and a 4-bit even parity generator design implemented using
Fig. 1 a Basic four-dot QCA
cell; b Cell representing binary
logic ‘1’ and c Cell representing
binary logic ‘0’
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J Comput Electron
proposed novel XOR gate. Section 4 illustrates the simu-
lation results obtained from the QCADesigner tool for the
proposed XOR designs, 4-bit even parity generator design
and comparison results of the Exclusive-OR designs and even
parity generator design of different bit-length with previous
reported designs. Section 5 illustrates the energy dissipation
results computed using the QCAPro tool. Conclusions are
covered in Sect. 6.
2 Quantum-dot cellular automata (QCA) review
2.1 QCA background
A QCA cell is a tiny nanostructure constructed from an
arrangement of quantum dots. The Fig. 1a shows a typical
four quantum-dot QCA cell. The quantum dots are the places
where an electron can reside by tunneling to them. Two elec-
trons are introduced within a cell that can tunnel amongst
the four dots. Electrons can tunnel from one quantum-dot
to another within the cell only and no tunneling is allowed
between adjacent cells [5,6,16–19]. The numbering of the
quantum dots in the cell starts clockwise from the dot 1 to 4.
The near-dot distance is ‘L’. The Fig. 1b, c show a QCA cell
with electronic polarizations representing binary logic ‘1’
and ‘0’ respectively. This QCA cell is an exciting dynami-
cal model. The two electrons within a QCA cell experience
mutual Columbic repulsion and in absence of any external
influence, seek to occupy diagonal positions. These two pos-
sible diagonal positions are called ground states of the cell. If
electrons are in quantum dot positions 1 and 3 respectively,
then the cell has a polarization P = +1, while electrons in
quantum dot positions 2 and 4 give P = −1.
The polarization of a cell in isolation is different. The
polarization changes if a cell is surrounded by other cells.
No electron tunneling is allowed from one cell to another by
ensuring larger distance between two dots of two cells than
distance between two dots within the same cell [5,6,16–19].
2.2 Elementary QCA nanostructures
The two different ground state polarizations in a QCA cell are
used to represent two states in digital logic. This is of great
J Comput Electron

Input Input Input Output

Output
(P=1) (P=1) (P=1) (P= -1)
(P= -1)

Output
(P=1)

(a) (b) (c)

Fig. 2 a a QCA binary wire, b an inverter and c an alternate inverter configuration [18]

Input 1 Input 1 Input

Input 2
Input 2
Input 2

Output Output
Output
Input 3

Fixed Polarization (P=1) Fixed Polarization (P= -1)

(a) (b) (c)
Fig. 3 a Majority logic gate; b OR logic using majority gate and c AND logic using majority gate [18]

importance in implementing QCA based digital circuits [18]. Table 1 3-input majority gate A B C Output
Figure 2a shows a typical example of a binary wire realiza- truth table [18]
tion in QCA cell array. Figure 2b, c represent two different 0 0 0 0
implementations of the inverter in QCA nanotechnology. In 0 0 1 0
a QCA array of cells, the driver cell polarization is kept fixed 0 1 0 0
and sets final state of the entire array. If the QCA cells are 0 1 1 1
arranged in a line of cells, then whatever is the polarization 1 0 0 0
of the driver cell, the whole array settles to that polarization, 1 0 1 1
thus realizing a binary wire. In this information flow from 1 1 0 1
input to output, no electric current flows from one cell to 1 1 1 1
the next cell down the line, which results in ultra-low power
dissipation [17,18].
A three-input majority gate is shown in Fig. 3a. The major-
The logic expression for the output of a 3-input majority
ity gate is the most basic QCA logical device. The middle cell
gate is given as:
has 3 fixed inputs, labeled as inputs 1, 2 and 3, respectively.
The middle cell attains its polarization according to the polar-
ization of the majority of inputs. The output cell may feed to
M A J 3 (A, B, C) = AB + BC + AC (1)
some other cell or other wires. In a particular computation,
the polarization of an input cell is fixed and the polarization
of the output cell settles as per the final ground state of all
cells in a QCA gate or array. Table 1 shows the truth table
of the 3-input majority gate. If we implement this majority
gate using CMOS transistors, then it requires 26 transistors.
However, if we implement it using QCA cells it needs only
5 cells providing a more compact majority logic [17,18].
The majority gate can be configured as programmable
AND and OR gates if we set one of its inputs in the polar-
ization state ‘−1’ or ‘1’. Figure 3b, c show programmable
OR and AND gate realizations with a majority gate. So, the
majority gate along with inverter and AND/OR functionality
confirms that QCA logic offer logical completeness [18]. Fig. 4 Five-input majority gate [20]

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Fig. 5 a Schematic of the proposed XOR2 gate implemented using conventional design approach and its b QCA implementation
Y
X (Y+Z) if Select=0
X
MAJ5 Out =
(X+ YZ) if Select=1
Z aluminum islands. The size of the aluminum islands were
Select
Fig. 6 Two different function realizations using 5-input majority gate
[21]
2.3 QCA based five-input majority gate
New five-input majority gate structures have been presented
for complex QCA circuit implementations [20,21]. The five-
input majority gate can significantly reduce the hardware
requirements for complex QCA circuits. Also, it facilitates
QCA circuits to be simpler in level, gate counts and clock.
Figure 4 shows the structure of a five-input QCA majority
gate. The logic expression for output of five-input majority
gate is described by Eq. 2.
M (A, B, C, D, E)
= ABC + AB D + AB E + AC D + AC E
+ AD E + BC D + BC E + B D E + C D E (2)
2.4 QCA technology developments
Quantum Cellular Automata is still a commercially unre-
alized technology. Many researchers have demonstrated
experimental QCA devices at cryogenic temperatures. There
are broadly four major classes of QCA fabrication technolo-
gies: Metal-island; Semiconductor; Molecular; and Magnetic
or nanomagnetic logic. The QCA concept does not depend
on the material system in which it is implemented [22]. The
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J Comput Electron
metal-island technology [5,6] was used to demonstrate the
concept of QCA. The quantum dots were developed using
relatively large, so to observe electron switching, the metal-
island devices had to be kept at cryogenic temperatures.
Semiconductor QCA implementations [23–26] could be used
to realize QCA devices with advanced CMOS fabrication
processes. Current CMOS processes still have not reached
a point where the mass production of QCA devices would
become a reality. However, as the feature size is continually
shrinking, the bulk-production of solid-state QCA devices
suitable for room temperature operation could become fea-
sible in this technology as it approaches a few nanometers.
Many researchers are prototyping QCA devices using this
implementation technology. From experimental results, it is
observed that semiconductor and metal implementations [27]
suffer from two major drawbacks: the operating temperature
and the need for careful tuning of each cell. These drawbacks
are due to the very small value of the electrostatic energy
splitting (in meV). Such a small value of energy splitting
restricts the operating temperature (below 7 K). The electro-
static energy splitting can be enlarged by minimizing the size
of the cell (it scales linearly with the inverse of cell size). But
reduction in cell size results in fabrication errors and many
technological problems.
Nowadays, most QCA researchers are currently focusing
on molecular QCA [28–30]. The molecules act as QCA cells
and are bonded to the substrate surface at adjacent sites. The
redox sites plays role of quantum dots. The electrostatic inter-
actions induce the free electrons in the molecule to switch
position between available redox sites. The molecules are
very good charge containers and the interactions have suf-
ficiently high energy to ensure room temperature operation.
J Comput Electron

Fig. 7 a Schematic design of the proposed novel XOR1 gate and its b QCA implementation

Fig. 8 Simulation results for

the presented 2-input novel
Exclusive-OR (XOR1) design

Molecular QCA have a highly symmetric cell structure, very Table 2 Coherence engine simulation parameters [36]
high switching speeds, and extremely high device density. Parameter Value
They can be produced in bulk by means of self-assembly.
The major hindrances are choice of molecules, the design Cell width (nm) 18
of appropriate interfacing mechanisms, and clocking tech- Cell height (nm) 18
nology. These issues need to be resolved before molecular Quantum-dot diameter (nm) 5
QCA can be implemented. Further research work is needed to Relaxation time (s) 1.0e−15
fully evaluate the technological potential of molecular QCA Time-step (s) 1.0e−16
architectures. Total simulation time (s) 7.0e−11
Magnetic or nanomagnetic QCA [31–33] is based on the Clock-high (Joule) 9.8e−22
magnetostatic interaction between magnetic nanoparticles. Clock-low (Joule) 3.8e−23
The moment of these nanoparticles is either anti-parallel Clock amplitude factor 2.0
or parallel with reference to the axis of the chain. Several Radius of effect (nm) 80
researchers experimentally demonstrated that magnetic QCA Relative permittivity 12.9
implementations can be realized in current technology with Layer separation (nm) 11.5
large dot size (about 100 nm). The nanomagnets must be mag-
netically bistable, with large anisotropy, low coercivity, and a

123

Fig. 9 Simulation results for
the presented 2-input
Exclusive-OR (XOR2) design
Fig. 10 Simulation results for
the 4-bit even-parity generator
circuit
remanence equal to their saturation state [22]. Magnetic QCA
operate at room temperature in current technology. However,
the clock speed in magnetic QCA is limited for few hundred
megahertz. Magnetic QCA circuits could find applications
where speed is not important and the main requirement is
extremely low power consumption.
3 Proposed QCA exclusive-OR (XOR) structures
Exclusive-OR (XOR) gates find wide spread applications
in communication circuits. They are widely used in parity
checking, detection and correction operations in the receiver
and sender units. They are also widely used in arithmetic
and logical unit (ALU) of a processor. In this research work,
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J Comput Electron
we identified that a robust area and power efficient high
speed XOR gate design is the demand of complex QCA
circuits and architectures. Most existing XOR gate imple-
mentations use multilayer or coplanar crossover wiring. Two
useful Exclusive-OR designs are presented in [7,8]. We real-
ized two Exclusive-OR structure implementations in QCA
nanotechnology using two different design approaches.
3.1 Conventional design approach
The conventional Exclusive-OR design approach uses three
3-input majority gates and two inverters. This conventional
design approach has been proposed by different authors
[14,17,34,35]. The schematic diagram of this design and its
implementation in quantum-dot cellular automata are shown
J Comput Electron
Fig. 11 a Schematic design of the 4-bit even parity generator and its b QCA implementation
Table 3 Truth-table of 4-bit even parity generator
Input vectors
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
in Fig. 5a, b, respectively. The output expression in this
approach is computed as:
M A J 3(M A J 3( Ā, B, 0), M A J 3(A, B̄, 0), 1)
= M A J 3( ĀB, A B̄, 1)
= ĀB + A B̄
3.2 Novel design approach
Output
This novel Exclusive-OR design approach uses one 3-input
C D
majority gate, one 5-input majority gate and 2 inverters. Two
0 0 0 Boolean functions Maj5 (Y, X, X, Z , 0) = X (Y + Z ) and
0 1 1 Maj5 ((Y, X, X, Z , 1) = X + Y Z have been realized [15] by
1 0 1 changing the value of the Select input to ‘0’ and ‘1’ respec-
1 1 0 tively in a 5-input majority gate as shown in Fig. 6. The X
0 0 1 input has twice the effect of the other inputs on the output
0 1 0
function in these realizations.
In our novel implementation, we have realized the
1 0 0
Exclusive-OR function using Maj5 (Y, X, X, Z , 0) = X (Y +
1 1 1
Z ) function. The E input of five input majority gate is
0 0 1
employed as select input and permanently fixed at logic
0 1 0
‘0’.The remaining inputs of five-input majority gate are set
1 0 0
at Y = Ā, X = A + B and Z = B̄ (Fig. 7). The output of
1 1 1
this five-input majority gate simplify according to Eq. 3 to
0 0 0
produce the Exclusive-OR (XOR) output.
0 1 1
1 0 1
1 1 0
M( Ā, A + B, A + B, B̄, 0)
= (A + B)( Ā + B̄)
= ĀB + A B̄ (3)
The schematic diagram of this novel Exclusive-OR design
and its implementation in quantum-dot cellular automata are
shown in Fig. 7a, b, respectively.
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 J Comput Electron

Table 4 Comparison of the single layer two-input QCA exclusive-OR designs

2 input XOR gate Area Cell 3-input 5-input No. of Latency Cross-over type
(µm2 ) count majority gates majority gates inverters (clock cycles)

Reported design [7] 0.02 32 1 1 1 1 Not required

Reported design [8] 0.06 67 1 1 1 1.25 Coplanar
Proposed novel XOR1 design 0.02 28 1 1 2 0.75 Not required
Proposed XOR2 design 0.04 32 3 – 2 1 Not required

Table 5 Comparison of even parity generator designs for various bit- When inputs (AB) are “00” or “11”, the output is “0” and
length when inputs (AB) are “01” or “10” means both are different,
Circuits No. of No. of Circuit Latency the output is “1”. Thus, the simulation results completely
bits cells area (µm2 ) (clock cycles) verified the functionality of Exclusive-OR gate.
Figure 9 represents the simulation waveforms for the pro-
Reported data 4 98 0.11 2
[7] posed 2-input Exclusive-OR (XOR2) design implemented
8 241 0.37 3
using conventional design approach. As shown by the arrow
16 537 1.04 4
in Fig. 9, the output appears after a latency of 1 clock cycle
32 1167 2.67 5
after the input vectors are applied.
Reported data 4 188 0.2 2.25
[8]
Figure 10 shows simulation waveforms for the 4-bit even
8 369 0.49 2.25
parity generator implemented using 3 proposed novel XOR1
16 847 1.46 3.25
gates as shown in Fig. 11b. The truth table for 4-bit even
32 1862 3.58 4.25 parity generator is shown in Table 3. When number of “1s”
Proposed 4 87 0.10 1.75 in the 4-bit input vector is odd, then the output of even parity
Novel XOR1 8 213 0.30 2.75
based designs generator is “1”. Similarly, when the number of “1s” in the 4-
16 480 0.81 3.75 bit input vector is even, the output is “0”. The output appears
32 1044 2.08 4.75 after a latency of 1.75 clock cycles as shown by the arrow
after the input vectors (ABCD) are applied.
Table 4 illustrates the comparison of the proposed
4 Simulation results Exclusive-OR designs with the previous reported designs.
The proposed novel XOR1 design uses only 28 cells with an
To verify our proposed designs as well as previous designs area of 0.02 µm2 and latency of only 0.75 clock cycles. The
of Exclusive-OR gates, we used QCADesigner version 2.0.3 QCA implementation of the proposed novel XOR1 design in
with the coherence vector simulation engine setup [36,37]. Fig. 7b offers single layer accessibility to its inputs and out-
Table 2 briefly lists various parameter values used in the put; as the input and output cells are not surrounded by other
coherence vector simulation mode. The value of the rel- cells. Also, the design does not use any rotated and translated
ative permittivity has been set to 12.9 as the default for cells. These structural features of this novel design facilitate
GaAs/AlGaAs heterostructure based semiconductor imple- highly dense circuit implementations. To prove that the pre-
mentations. Figure 8 presents the simulation waveforms for sented design is better in terms of the number of cells, the
the proposed novel 2-input Exclusive-OR (XOR1) design. circuit area and number of clock cycles, 4-, 8-, 16- and 32-
As shown by the arrow in Fig. 8, the output appears after a bit even parity generator circuits were implemented in QCA.
latency of 0.75 clock cycle after the input vectors are applied.

Table 6 Energy dissipation results

2-bit XOR circuit Average leakage Average switching Average energy
energy dissipation (meV) energy dissipation (meV) dissipation (meV)

0.5Ek 1.0Ek 1.5Ek 0.5Ek 1.0Ek 1.5Ek 0.5Ek 1.0Ek 1.5Ek

Reported design in [7] 11.51 31.91 54.69 35.78 30.48 25.66 47.28 62.39 80.34
Reported design in [8] 19.65 59.28 106.51 126.79 112.29 97.95 146.44 171.57 204.47
Proposed Novel XOR1 10.78 28.57 48.15 25.43 21.71 18.4 36.20 50.28 66.58
Proposed XOR2 9.73 29.7 52.78 40.08 33.73 28.05 49.81 63.49 80.83

123
J Comput Electron

Average Switching Energy Dissipaon 140 120

Average Leakage Energy Dissipaon

120 0.5Ek
100
100 0.5Ek 1.0Ek
1.0Ek 80 1.5Ek
80
(meV)

1.5Ek

(meV)
60 60

40 40

20
20
0
[15] [16] Proposed Proposed 0
Novel XOR1 XOR2 [15] [16] Proposed Proposed
Novel XOR1 XOR2
Fig. 12 Average switching energy dissipation of presented novel 2-
input exclusive-or gate under three different tunneling energy levels (T Fig. 13 The average leakage energy dissipation of presented novel 2-
= 2.0 K) (Color figure online) input Exclusive-OR gate under three different tunneling energy levels
(T = 2.0 K) (Color figure online)

The Table 5 summarizes the comparison of even parity gener-

ator designs of different bit-length. The proposed 4-bit even 250
parity design occupies 9 and 50 % less area and has 12.5 and
22.22 % less latency as compared to similar Exclusive-OR Average Energy Dissipaon (meV) 200 0.5Ek
structures reported in [7,8]. The 32-bit even parity design 1.0Ek
occupies 22 % less area than the best reported designs in [7]. 150 1.5Ek
It has been observed that as the complexity of QCA designs
increases, the proposed novel Exclusive-OR design offers 100
huge advantage in terms of area.
50

5 Energy dissipation results

0
[15] [16] Proposed Proposed
The instantaneous total power equation for a QCA cell [11, Novel XOR1 XOR2
12] can be computed as
Fig. 14 The average energy dissipation of presented novel 2-input
   
d h̄ d h̄ d Exclusive-OR gate under three different tunneling energy levels (T =
Ptotal = E=  .λ
  + .  = P1 + P2
 2.0 K) (Color figure online)
dt 2 dt 2 dt
(4)

The first term P1 in equation (4) represents two major com-
ponents viz. the power gain obtained due to the difference
of input and output signal power (Pin − Pout ) and the power
transferred from clock signal to the cell. The second term P2
represents the dissipated power (Pdiss ) [11]. The total dissi-
pated power in an array of QCA circuits can be computed by
adding the power dissipation of all cells.
Using these concepts for power analysis of QCA circuits,
the authors of [10] introduced a power dissipation model
for QCA circuits. They categorized the total power into two
major parts called switching and leakage power. All power
losses during clock transitions result in leakage power and
power loss per clock cycle at each cell result in switch-
ing power. Using this power dissipation model, an accurate
power estimation tool QCAPro is presented in [9]. The
QCAPro tool has been used to calculate the power consump-
tion analysis of the proposed QCA exclusive-OR designs as
well as previous designs. All designs have been examined for
3 different tunneling energy levels: 0.5Ek , 1.0Ek and 1.5Ek
at 2 K temperature. The average leakage energy dissipation,
average switching energy dissipation and average energy dis-
sipation have been computed.
Table 6 lists the energy dissipation results and Figs. 12,
13 and 14 show the bar-graph comparison of the proposed
designs with previous reported designs in terms of average
switching energy dissipation, leakage energy dissipation and
average energy dissipation, respectively. From the results, it
is observed that the proposed novel XOR1 design has 28 %
less switching energy dissipation, 10 % less average leakage
energy dissipation and 19 % less average energy dissipation
than best reported design in [7] at 1.0Ek tunneling energy
level. It is also anticipated that the use of the proposed novel

123

Fig. 15 a Thermal layout for
the average energy dissipated in
each cell of the proposed Novel
XOR1 design and b Thermal
layout for the average energy
dissipated in each cell of the
proposed XOR2 design
XOR1 design to build complex QCA designs will offer more
energy savings.
Figure 15a, b show the thermal layouts for the average
energy dissipation in each cell of the proposed XOR1 and
XOR2 designs. The dark QCA cells indicate more energy dis-
sipation on an average. The white cell represents the inputs.
These thermal layouts were generated in QCAPro tool by
simulating the proposed 2-input Exclusive-OR designs over
all possible input vector combinations from 00 to 11 for 1.0Ek
tunneling energy level and at 2.0K temperature.
6 Conclusions
This paper presents a novel approach to implementing
a two-input Exclusive-OR (XOR) gate implementation in
quantum-dot cellular automata with minimum area, latency
(delay), complexity and energy dissipation as compared to
previous designs. QCADesigner tool is used to design and
functionally simulate the proposed designs and QCAPro, an
accurate power estimator tool, is used to calculate the switch-
ing, leakage and average energy dissipation. The presented
novel XOR gate design utilizes a three-input majority gate, a
five-input majority gate and two inverters only. It uses only
26 normal QCA cells and 2 fixed polarization cells and has
latency of only 0.75 clock cycles. Also, the proposed novel
QCA XOR structure offers single layer accessibility to its
inputs and output without any coplanar cross-over wiring
and does not use any rotated and translated cells. These
structural features of this novel design facilitate highly dense
circuit implementations. The proposed novel XOR1 design
has 28 % less switching energy dissipation, 10 % less aver-
age leakage energy dissipation and 19 % less average energy
dissipation than the best reported design. To prove that the
presented design is better in terms of number of cells, cir-
cuit area and number of clock cycles, 4-, 8-, 16- and 32-bit
even parity generator circuits were implemented in QCA.
The proposed 4-bit even parity design implemented using
the proposed novel XOR1 occupies 9 and 50 % less area
and has 12.5 and 22.22 % less latency as compared to simi-
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J Comput Electron
lar reported designs. The 32-bit even parity design occupies
22 % less area than the best reported designs.
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