Funcionamento T CON

Outline
Flat Panel Display : Principle and

Driving Circuit Design Ch4. Driving Circuits Design of A-Si TFT
– Gate Driving Circuit
Chapter 4 – Source Driving Circuit
Driving Circuit Design of A-Si TFT – LCD-TV Driving Technology

– Small-Size TFT-LCD Driver IC
中興大學電機系 / 汪芳興 – Trends of Digital Interface
98(上) 1
98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 2 / 195
Introduction to LCD Driver IC Driving Circuits of TFT- LCD Module

• Improved Visualization: Y PCB
G1
– A Fundamental Market Enabler ASIC
Y-Driver IC
TFT-LCD
TFT-LCD
Connector
1280*(3)*1024
Connector
LVDS LVDS Timing 1280*(3)*1024
LVDS Timing
Receiver
Receiver Controller
Controller Pixels
Pixels
+5V G1024
D1 D3840
4 CCFL
DC/DC
DC/DC Gamma
X-Driver IC
Converter
Converter Correction
I/F + X PCB DC POWER

Inverter
98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 3 / 195 98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 4 / 195
Driving Circuits of TFT- LCD Module Gate Driver IC
• Example • Also called scan driver or row driver
• Function
– Read in start signal
– Progressively turn on pixel TFTs on each gate line
– Turn off TFT during pixel holding period
• Design consideration
– RC delay of bus line (for large-size panel)
• Capacitive coupling driving (CC driving)

• Gate-driver in panel
Gate Driver Architecture Timing of Gate Driver

256 CLK
RESET
Up/Down Bi-directional Shift Register CLK
VDD SP1 SP2
digital GND S/R S/R S/R S/R S/R STP
CLK
SP1
CLK G1
level level level level level Gate driver 1
Level Shifter
ENB shift shift shift shift shift G2
VGG
analog
VEE
buffer buffer buffer buffer buffer Output Buffer G256
Gate driver 2
G1
Out1 Out2 Out3 Outn
G2
To Display Area
S/R frequency : 10k~75kHz , Output voltage range : > 12V Gate driver 1 Gate driver 2
Gate driver IC 電路方塊圖
Key Specifications Package of Driver IC
• Channel number
(240,256,264,270,300,308…)
• Max. operation frequency (200KHz, 500KHz)
• 2 level or 3 level driving
• Operation voltage
– digital : 5V, 3.3V
– analog : VGG>20V, VEE<-10V
• Package (TCP, COG, COF)
Package of Driver IC Package of Driver IC
Channel Number vs. Resolution Power On/Off Sequence
• Gate driver : No. of driver and No. of output

channel
lines 6 5 4 3
VGA 480 120
SVGA 600 120 150 200
This IC is a high-voltage LCD driver,
XGA 768 128 154 192 256 so it may be damaged by a large
current flow if an incorrect power
SXGA 1024 256 sequence is used. Connecting
the drive powers, VEE & VGG,
UXGA 1200 240 300 after the logical power, VDD, is
the recommended sequence.
Gate Driver Circuits CMOS Shift Register

Static S/R
Example
φ φ
IN OUT
φ φ
Shift register Level shifter Buffer
Shift Register Shift Register – Latch 1
/CLK CLK
• Latch W X
G1
CLK /CLK
– Basic memory
SP(L)
element N1 N2
– Two cross-coupled ENB1

ENB2
logic inverter
– Bistable circuit G2
Y Z
S1 S2 US 6,157,361
SHARP
Shift Register – Latch 2 Level Shifter – Example 1
Inverter Type
Vcc Vpp
Vdd
T1 P1 P2
IN /OUT Vin Vout
T2 N1 N2
GND GND GND
¾ With both transistors of the inverters turned on, a current path from the supply voltage
US 6,724,361 B1 to ground is present, resulting in undesirable power consumption.
Ref : Low Power Digital VLSI Design, A. Bellaouar, M. Elmasry
Level Shifter – Example 2 Output Buffer
Vdd Vdd
Vdd Vdd
Latch Type
P3 P4
M3 M6
Vout
Vcc Vcc
IN OUT
M2 M5
P1 Vcc N3 P2 N4 Vcc
INPUT /INPUT
Vin OUTPUT
M1 M4
N1 N2
US 4,486,670
INTERSIL GND GND Area ratio = e (2.7) ~ 3
GND GND
¾ This circuit overcomes the problem of direct power consumption by using a latch.
TSMC HV Process Roadmap of High Voltage Technology

• Roadmap of TSMC HV technology
Source : Web of TSMC

Source : Web of TSMC
Two-Line Scanning Two-Line Scanning
• Frame inversion • row inversion Vd,N+1
Vd,N
• column inversion • dot inversion Vd,N-1
line time (N-2)th (N)th Vd,N-2
Vd 1 Vd 2 Vd 3
Vg, N-2
Vpixel
TFT
Cst
Vg, N-1 CLC
Vg, N
~10us ~10us
1 frame ~16ms
•First pulse is for precharge
Scan Driver Consideration Gate Driver Design

Toshiba 15” UXGA
Dual Driving
Shut circuit was inserted
between S/R outputs and
L/S inputs to avoid over
current phenomena due to
timing difference between
right and left side scan
> 40“ ? driver outputs.
Level shifter is divided in
stages First stage is
two stages.
made to shift high level
from 10 V to 15 V, second
stage is made to shift low
level from 0 V to –2 V..
The scan driver with both side driving effectively reduces the RC time constant of the
gate line. Ref:SID 00’, p.1121
Ref:IDW 00’, p.167
Three-level Capacitive Coupling Driving
(C. C. Driving) Three-level C. C. Driving
• Cst on gate
3-level ΔV 1 = Vghl ×
Cgd
Clc + Cst + Cgd + Cds Considerpreviouscase,
Scan line n
Vgc 0.05× 25
Cgd Vghl ΔV 2 = Vgc ×
Cst ΔVgd = = 1.47V
Clc + Cst + Cgd + Cds 0.4 + 0.4 + 0.05
Cgd 0.05
Vgc = ΔVghl × = 25 = 2.778
Clc Cst Cgd Cs + Cgd 0.4 + 0.05
Cds ΔV 3 = Vgc ×
Vcom Clc + Cst + Cgd + Cds
If ΔV 1 = ΔV 2 + ΔV 3 i.e. Vghl × Cgd = Vgc × (Cst + Cgd )

Scan line n-1
Cgd
Vgc = Vghl × , then
V3 Cst + Cgd
V1
ΔV 1 = ΔV 2 + ΔV 3
Pixel voltage V2 • Feed-through effect is eliminated.
Three-level C. C. Driving Four-level C. C. Driving

• Cs on Gate with 3-Level Driving Scheme
Cs on gate
Vg Ve+
GN-1(+) GN-1(-)
Scan line n-1
Black(+) Black(+) Vcom

Cds Vg
Black(+) GN(-) Ve-
GN(+)
Clc Cst
Positive Driving Positive Driving
Positive Driving Cgd VP
Data White(+) White(+) Final VP V6
Vblack(+)
Cente White(-) White(+) Temporal White(-) Vcom Scan line n V5
r White(-) Vcom V4
Negative Driving Negative Driving Vcom
Negative Driving
•line inversion
V1
Black(-) Black(-)
•low voltage source driver Vblack(-) V2
Data Line Black(-) Final Pixel

•complex scan driver V3
Voltage Level Temporal Pixel

Voltage Level Negative Polarity Positive Polarity
Voltage Level Not valid for Vcom AC
Four-level C. C. Driving Four-level C. C. Driving
• Cs on Gate with 4-Level Driving Scheme
ΔV1 = (Vg + (Ve−))×
Cgd
ΔV 4 = (Vg − (Ve+))×
Cgd
Black(+)
(Cst + CLC + Cgd) (Cst + CLC + Cgd)
Cst Cst Black(+)
ΔV 2 = (Ve+) × ΔV 5 = (Ve−) ×
(Cst + CLC + Cgd) (Cst + CLC + Cgd)
Positive Driving
Positive Driving
Cgd Cgd
ΔV 3 = (Ve−) × ΔV 6 = (Ve+) ×
(Cst + CLC + Cgd) (Cst + CLC + Cgd) Data White(+) Data White(+)
Center White(-) Center White(-)
Q ΔV1 + ΔV 2 − ΔV 3 = −ΔV 4 + ΔV 5 − ΔV 6 Negative Driving

Negative Driving
Cgd
∴(Ve−) − (Ve+) = 2Vg × Black(-)
Cst Data Line

Black(-)
Voltage Level
• Pixel voltages of positive polarity and negative polarity for Final Pixel
Voltage Level
LC cell are symmetry.
Comparison of Addressing Trend of Gate Driver IC

• package ：
Frame Row Column Dot – TCP（Tape Carrier Package）→
Common – COG（Chip on Glass） →
AC/DC AC/DC DC DC
voltage – COF （Chip on Film） →
Output Low/high Low/high high high – GIP（Gate-Driver In Panel）。
range voltage voltage voltage voltage
2-level
driving
V V V V
3-level
driving
X/V X/V V V
4-level
driving
X/V X/V X X
Vcom AC/DC
Gate-Driver In Panel Ch4. Driving Circuits Design of A-Si TFT
• Gate Driving Circuit

• Source Driving Circuit
– Driver Architectures
– Driver Specifications
– DAC
– Output Buffer
– Low power consumption
• LCD-TV Driving Technology
• Small-Size TFT-LCD Driver IC
• Trends of Digital Interface
Source Driver Circuits Analog Data Driver

• Also Called Column Driver (Data Driver) • Serial In, Serial Out • Serial In, Parallel Out
• Driver Architectures Shift Register Shift Register

– Line-at a-time (LAAT) Qi-1 Qi Qi+1 Qi+2
Qi Qi+1 Video in
Video
– Point-at a-time (PAAT) in
Sample
• Data Drivers Types capacitor
pixel pixel control

– Analog Data Driver
hold
– Digital Data Driver capacitor
Shorter charging time pixel
Comparison of Analog Data Driver LAAT Driver Architecture
For a-Si TFT-LCDs
SISO SIPO CLK, DIO S/R S/R S/R S/R S/R S/R S/R S/R
1 phase 1 phase
Video in Sample Sample Sample Sample Sample Sample Sample Sample
Circuits complexity
lowest higher
Hold Hold Hold Hold Hold Hold Hold Hold
Pixel charging time TVL / Pix-H TVL Driver IC
Buffer Buffer Buffer Buffer Buffer Buffer Buffer Buffer
Sample time TVL / Pix-H TVL / Pix-H
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
1 2 3 4 5 6 7 8
S/R frequency 1/(TVL / Pix-H ) 1/(TVL / Pix-H)
Array Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
Reformed video
needed
No No
All video signals stored in A latches are written to B latches simultaneously in each horizontal
scanning period. Features: (1) has sufficient charging capability; (2) very difficult to achieve good
TVL :vertical line time, Pix-H :horizontal pixel number uniformity of output voltages of the analog buffer.
PAAT Driver Architecture LAAT vs. PAAT

For some large-size LTPS TFT-LCDs
CLK, DIO S/R S/R S/R S/R
Video Sample Sample Sample Sample
in
Hold Hold Hold Hold
Driver Buffer Buffer Buffer Buffer
DeMUX 1:2 DeMUX 1:2 DeMUX 1:2 DeMUX 1:2
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel

1 2 3 4 5 6 7 8
• Sanyo has been selling products using the PAAT technology. Since
small-size panels have only 234 scan line, there is sufficient time to use
Pixel Pixel Pixel Pixel
Array Pixel Pixel Pixel Pixel
PAAT technology.
• Seiko-Epson has adopted the LAAT architecture because there studies
Seiko-
A high speed and wide voltage range analog interface circuit that consumes a large amount of power
is required !! Feature : (1) less data driver ICs ; (2) shorter pixel charging time than LAAT.
indicated that the crosstalk on a multiplexed circuit was too severe.
Max. Frequency of Shift Registers Digital Data Driver
(a) Decoder type is very difficult

to achieve full gray scale
because the circuit
configuration is too complicated !
(b) DAC type is the most

promising one because it has a
less complicated configuration
while keeping full digital
interface !
Vcc=5V, Freq.<2MHz @ μn/p=70/35 cm2/Vs (a) (b)

Ref:SID’96 Digest. pp.673. Ref:IDW 00’ p.171
Comparison of Digital/Analog Data Architecture of Source Driver IC for

Driver Large-Size TFT-LCDs
DIO1 DIO2
S/R S/R S/R S/R S/R
CLK
Digital Analog
receiver
Sample Sample Sample Sample sample
circuits Data
Data
complex simple in
Reg. Reg. Reg. Reg. reg.
complexity
Hold Hold Hold Hold Hold
noise immunity high low Latch Signal
Reg. Reg. Reg. Reg. Reg. Digital Part
gamma Yes No Level Level Level Level Level Analog Part
correction Shifter Shifter Shifter Shifter Shifter Level Shifter
video signal Compatible to ADC needed Polarity Signal

Gamma Digital/Analog Converter, DAC
processing PC Reference
voltages
cost high low Buffer Buffer Buffer Buffer Buffer Output buffers
Out1 Out2 Out3 Outn

To LCD data line
Timing Diagram of Source Driver Timing Diagram of Source Driver
128 CLKs 128 CLKs LD(CLK1)
CLK
POL
DIO1
Positive
DIO2
Odd outputs
High-Z High-Z
Data latch P1 P2 P3 P4 P5 P127 P128 P129 P130 P131 P132 P133
Even outputs Negative
High-Z
Tst Tst
Invalid Driver 1 Driver 2
Output load condition : 1K 1K 1K 1K 1K
Output
1st 384 Outputs 2nd 384 Outputs
15P 15P 15P 15P 15P
for 1~128 Pixel for 129~256 Pixel
Vcom
Key Specifications Channel Number vs. Resolution

• Channel number (384, 402, 420, 480, 640, 720…) • Source driver : No. of driver and No. of output channel
• Gray scale (6 bit, 8 bit, 10 bit…) No. of lines 12 10 9 8 7 6 5
• Max operation frequency (45MHz, 55MHz, 65MHz, 75MHz…) VGA 640x3 192 240 384
• Pixel charging time (eg. R=2k, C=20pF, 6.5us 90%, 11.5us 99.9%) SVGA 800x3 240 300 402 480
• Frame/row/column/dot inversion XGA 1024x3 312 384
• Output voltage deviation (±20mV, ±10mV, ±5mV, ±3mV)
SXGA,WXGA 1280x3 384 480 640
• Output voltage (10V, 12V, 13.5V, 15V, 18V)
WXGA 1366x3 414
• Interface (TTL, RSDS, mini-LVDS)
SXGA+ 1400x3 420
• Operation voltage (2.5V, 3.3V)
WXGA 1440x3 432 480
• No. of Gamma reference voltage (10, 14, 18)
UXGA 1600x3 402 480
• Package (TCP, COG, COF)
WSXGA+ 1680x3 420 720
• Others (data inversion, low-power mode, offset canceling, charge
sharing …etc.) HDTV 1920x3 480 642 720
QXGA 2048x3 512
Resolution vs. Max. Frequency D/A Converter
Frame rate 60 Hz 60 Hz 75 Hz 75 Hz
• Fundamentals of Data Converter
Pixel Horizontal Pixel Horizontal
frequency period frequency period
VGA 25.2 MHz 31.7 μs 31.5 MHz 26.7 μs

• Digital-to-Analog Converters
SVGA 40 MHz 26.4 μs 49.5 MHz 21.3 μs
XGA 65 MHz 20.7 μs 78.75 MHz 16.7 μs
SXGA 108 MHz 15.6 μs 135 MHz 12.5 μs
UXGA 162 MHz 13.3 μs 202.5 MHz 10.7 μs

資料來源：Philip E. Allen, Douglas R. Holberg, ”CMOS analog circuit design”, Oxford, 2002.
Higher resolution, shorter pixel charging time, higher driving frequency 林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫.
Fundamentals of Data Converter Idea D/A Converter
• Ideal D/A converter • Ideal N-bit DAC

Digital input
• Quantization error in ideal DACs Bin =
bn −1 bn − 2
+ + L +
b1
+
b0
• Performance limitation 21 22 2 n −1 2 n
• Offset error Where bi is 1 or 0, i.e. binary, bn-1 is the MSB, and b0 is the LSB
• Gain error
• Accuracy
資料來源：Philip E. Allen, Douglas R. Holberg, ”CMOS analog circuit design”, Oxford, 2002. 資料來源：Philip E. Allen, Douglas R. Holberg, ”CMOS analog circuit design”, Oxford, 2002.
林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫. 林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫.
Idea D/A Converter (cont') Idea D/A Converter (cont')
• Analog output Vout is related to Bin through an • An ideal 2-bit DAC example：
analog reference, VRef Input-output transfer curve. In
1. Vout and VRef may be voltage, current, or charge. general, the maximum value of
2. We assume here that they are voltage (for simplicity) Vout is not VRef but rather
-n
VRef(1-2 ) or equivalently, VRef-
3. Definitions：
VLSB.
⎛b b b b ⎞
Vout = V ref ⎜ n −1 1 + n −2 2 + L + n1−1 + 0n ⎟ = V ref × Bin ,
⎝ 2 2 2 2 ⎠
• A multiplying DAC (MDAC) is realized by simply
V ref allowing the reference signal, VREF, to be a varying
V LSB = , where VLSB is defined as the voltage changes
2N when one LSB changes. input signal along with BIN. Such an arrangement results
in Vout being proportional to the multiplication of the input
• 1 LSB = 1/2N unitless definition.
signals, BIN and VRef.
林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫.
Quantization Error in DACs Performance Limitation

• Quantization error (noise) is the inherent uncertainty in • Definitions for determining the transfer
digitizing an analog value with a finite resolution converter. responses for DACs.
It is equal to the analog output of the infinite-bit DAC – The transfer response of a DAC is defined to be the
minus that of the finite-bit DAC. analog levels that occur for each of the digital word.
• Fig 10.1.4 & 10.1.5. • Resolution
– The number of distinct analog levels corresponding
to different digital words. Thus, an N-bit resolution
implies that the converter can resolve 2N distinct
analog levels.
Offset Error Gain Error
• Offset error is in units of LSBs. • Gain error is the difference at the full-scale value between
the ideal and actual when the offset error has been
• Offset error is the output that occurs for the input reduced to zero.
code that should produce zero output.
• Gain error is in units of LSBs.
Vout
Eoff ( DAC ) = 0...0
• DACs︰
VLSB ⎛ Vout Vout ⎞
E gain ( DAC ) = ⎜ 1...1 − 0...0 ⎟ − (2 − 1)
N
2-bit example： ⎝ VLSB VLSB ⎠

2-bit example︰
Accuracy Accuracy (cont’)
• Absolute accuracy • Accuracy can be expressed as a percentage error of

– The difference between the expected and actual full-scale value, as the effective number of bit, or as
and transfer response. a fraction of an LSB.
– For example, a 12-bit accuracy implies that the converter’s
– Includes 1.offset error, 2. gain error, 3. linearity
error is less than the full-scale divided by 212.
error
– A converter may have 12-bit resolution with only 10-bit
• Relative accuracy accuracy, or 10-bit resolution with 12-bit accuracy.
– The accuracy of offset and gain errors have been – An accuracy greater than the resolution means that the
converter’s transfer response is very precisely controlled.
removed
(better than the number of bits of resolution)
D/A Converter Digital-to-Analog Converters
• Nyquist-rate D/A converters

• Fundamentals of Data Converter • Decoder-based DAC
• Digital-to-Analog Converters • Binary-weighted converters
• Glitches
• Thermometer-code DACs
Nyquist-rate D/A converters Decoder-Based DAC
• Four main types • Most straight forward approach

9 Decoder-based – Create 2N reference signals and pass the
appropriate signal to the output.
9 Binary-weighted
• Three main types︰
9 Thermometer-code
– Resistor string
9 Hybrid
– Folded resistor-string
– Multiple resistor-string
Decoder-Based DAC Resistor-string DAC
VRef
• Example 1︰a 3-bit DAC

• Most straight forward approach with transmission gate, R
b0 b0
– Create 2N reference signals and pass the tree-like decoder. R

b1 b1
appropriate signal to the output. R

Transmission gates might be
• Types︰ used rather than n-channel
R
b2
Vout
–Resistor string switches. R
R
– Folded resistor-string ¾ Extra drain and source
R
capacitance (to GND) is offset
b2
by the reduced switch resistance. R
¾ Larger layout R
¾ Can operate closer to positive Bin = b22-1+b12-2+b02-3
supply voltage. 2N resistors
Resistor-string DAC (cont’) Resistor-string DAC (cont’)

• Only n-channel switches are used • Speed
1. About the same speed as the transmission gate – Can be estimated using open-circuit time-constant
implementation. approach (refer to microelectronics textbook written by
2. Compact layout (no contacts are required in the tree) Sedra and Smith)
• Monotonicity is guaranteed (if the buffer’s offset – Time-constant
does not depend on its input voltage) ≈ 3Rtr Ctr + 2 ⋅ 3Rtr Ctr + L + N ⋅ 3Rtr Ctr
• The accuracy of this DAC depends on the type of = N ( N + 1) (2 ⋅ 3Rtr Ctr )
resistor uesd. Polysilicon (20-30 Ω/□) can have
up to 10 bits of accuracy. Where Rtr is on resistance of switches,
Ctr is drain or source capacitance of switches, and
N is bit number.
林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫. 資料來源：Philip E. Allen, Douglas R. Holberg, ”CMOS analog circuit design”, Oxford, 2002.
Resistor-string DAC (cont’) Decoder-Based DAC
VRef
• Example 2︰a 3-bit DAC with digital R

• Most straight forward approach
decoding. – Create 2N reference signals and pass the
R b2
Compared to example1：
appropriate signal to the output.
1. Higher speed R
b1
2. More area for decoding circuit R • Types︰
Speed b0
R – Resistor string
Time-constant ≈Rtr· 2NCtr
For N≦6 example 2 is faster R –Folded resistor-string
For N>7 example 1 is faster R
• Compromise between example 1 and
R
example 2.
Vout
R
¾ Folded resistor-string DAC N
2 resistors (all equal-sized)
資料來源：林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫.
Folded resistor-string DAC Folded resistor-string DAC (cont’)

• Reduced the amount of digital decoding
• Reduce large capacitive loading
• Decoding is very similar to that for a digital memory
• Example：
– 4 bit (2 bit+2 bit) DAC
– Time constant ≈ Rtr·(22Ctr)+2Rtr·(22Ctr)
• Other design examples：
– 12 bit = 6 bit + 6 bit, or 4 bit + 4 bit + 4 bit, or ……
– 10 bit = 5 bit + 5 bit, or 3 bit + 3 bit + 4 bit, or ……
蘇育民, “數位類比轉換器設計與測試之研究,” 暨南國際大學電機工程學系碩士論文, 2004
Binary-Weighted (or Binary-Scaled)
Digital-to-Analog Converters
Converter
• Nyquist-rate D/A converters • An appropriate set of signals that are all related in a
binary fashion
• Decoder-based DAC • The binary array of signals might be voltages,
charges, or currents.
• Binary-weighted converters
• Five main types：
• Glitches – Binary-weighted resistor DAC
– Reduced-resistor-ratio ladders
• Thermometer-code DACs – R-2R-based DAC
– Charge-redistribution switched-capacitor DAC
– Current-mode DAC
Binary-Weighted Resistor DAC Binary-weighted resistor DAC (cont’)

• 4-bit example： • Does not require many resistors or switches.
• Disadvantage
1. Resistor ratio and current ratio are on the order
of 2N. If N is large, this large current ratio
requires that the switches also be scaled so that
equal voltage drops appear them.
⎛ b b b ⎞ ⎛R ⎞ 2. Monotonicity is no guaranteed.
Vout = − RFVref ⎜ − 3 − 2 − 1 ⎟ = ⎜ F Vref ⎟ BIn
⎝ 2 R 4 R 8R ⎠ ⎝ R ⎠ 3. Prone to glitch.
where : BIn = b3 2−1 + b2 2−2 + b1 2−3 +LL
資料來源： Philip E. Allen, Douglas R. Holberg, ”CMOS analog circuit design”, Oxford, 2002, p.624 資料來源： Philip E. Allen, Douglas R. Holberg, ”CMOS analog circuit design”, Oxford, 2002, p.624
Reduced-resistor-ratio Ladders Reduced-resistor-ratio Ladders (cont’)
• Reduce the large resistor ratios in a binary- • An additional 4R was added such that
weighted array resistance seen to right of the 3R equals R.
• Introduce a series resistor to scale signals in • One-fourth the resistance ratio compared to
portions of the array the binary-weighted case.
– Ex : VA= -1/4VRef • Current ratio has remained unchanged
– Switches must be scaled in size.
• Repeating this procedure recursively, one can
obtain an R-2R ladder.
資料來源：林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫.

資料來源:林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫.
R-2R-based DAC R-2R-based DAC (cont’)

• Smaller size and better accuracy than a binary-sized • R-2R ladder DAC with equal currents through switches
approach • Slower since the internal nodes exhibit some voltage swings (as
– Small number of components
opposed to the previous configuration where internal nodes all
– Resistance ratio of only 2
remain at fixed voltage).
Vref N
bi ⋅ I R ⎛R ⎞ N b
• 4-bit example︰ I R = , and _ Vout = RF ⋅ ∑ = Vref ⋅ ⎜ F ⎟∑ ii
2R i =1 2i −1 ⎝ R ⎠ i =1 2
• Current ration is
still large→ large
ratio of switch
sizes
資料來源：呂學旺, “場發射顯示器驅動電路之設計,” 國立交通大學電子工程學系碩士論文, 1994.

魯得中, “場效激發元件驅動器的設計,” 國立交通大學電子工程學系碩士論文, 2003.
資料來源： Philip E. Allen, Douglas R. Holberg, ”CMOS analog circuit design”, Oxford, 2002, p.625
Charge-redistribution switched-capacitor DAC Current-mode DAC
• Insensitive to Op Amp input-offset voltage, 1/f noise, • High-speed
and finite amplifier gain. • Switch current to output or to ground
• An additional sign bit can be realized by • The output current is converted to a voltage through RF.
interchanging the clock phases (shown in
• The upper portion of current source always remains at
parentheses)
ground potential.
Digital-to-Analog Converters Glitches

• A major limitation during high-speed operation
• Nyquist-rate D/A converters
• Mainly the result of different delays occurring when
• Decoder-based DAC switching different signals
• Example︰01111……1→1000……0
• Binary-weighted converters 1. I1 represents the MSB current and I2 represents the sum
of (N-1) LSB currents.
• Glitches
2. The MSB current turns off slightly early, causing a glitch
• Thermometer-code DACs of zero current.
Glitches (cont’) Digital-to-Analog Converters
• Glitch disturbance can be reduced by： • Nyquist-rate D/A converters

1. Limiting the bandwidth (placing a capacitor • Decoder-based DAC
across RF) • Binary-weighted converters
2. Using a sample and hold on the output signal. • Glitches
3. Modifying some or all of the digital word from a
• Thermometer-code DACs
binary code to a thermometer code.
Thermometer-Code DAC Thermometer-Code DAC (cont’)

• Digital recode the input to a thermometer-code equivalent.
• Total area required by the transistor switches is the same.
• All transistor switches are of equal sizes since they all
pass equal currents.
• Example： Thermometer-code resistor DAC
• Advantages over its binary-weighted counterpart

1. Low DNL errors
2. Guaranteed monotonicity
3. Reduced glitching noise
• Does not increase the size of the analog circuitry compared
to a binary-weighted approach.
Thermometer-Code Current-Mode DAC
Thermometer-Code Current-Mode DAC
(cont’)
• In high-speed applications
• Row and column decoders
1. The output current feeds directly into an off-chip
• Inherent monotonicity 50Ω or 75Ω resistor, rather than an output opamp.
2. Cascode current sources are used to reduce current-
• Good DNL errors source variation due to voltage changes in Vout.
• INL errors depend on the placement of the
current sources
Examples of DAC 1 Examples of DAC 2.

• Chun-Yueh Huang; Tsung-Tien Hou; Hung-Yu Wang; “A 10 bit 100-MHz
12-bit DAC Paper- A Novel Linear Digital-to-Analog Converter using
current-steering DAC” ASIC, 2005. ASICON 2005. 6th international
Capacitor coupled Adder for LCD Driver ICs
Conference On Volume 1, 24-0 Oct. 2005 Page(s):411 - 414
Examples of DAC 3 R-String DAC
5
• 12 Bit Linear DAC using capacitor coupled adder b1 b1 b2 b2 b3 b3
R/2
R out
R/2
-19
R-String DAC (cont’) D/A Converter of Source Driver IC

DAC with
ROM
Decoder
Gamma Correction Gamma Correction
T-V curve is non-linear.
10 Gamma Voltage 18 Gamma Voltage
Adjust the voltage of V1~V8 to obtain the desire transmittance.
資料來源： Datasheet of Novetek Corp.
R-String (ROM Decoder) DAC Output Buffer
z Advantages Rail to rail OP-AMP

Polarity
control
¾Simple architecture signal -
Odd
¾Low noise Gamma
Voltage DAC P + Output
¾Optimized gamma curve (+)

To data line
z Disadvantages -
Even
¾Large area Gamma
Voltage DAC N
+ Output
¾Area increase rapidly as bit number increases (-)
¾Steady current consumption in R-string
Output Buffer OP-AMP – An Example
P/N type OP-AMP Polarity

control
signal
Gamma Odd
-positive Output
Voltage DAC P buffer
(+) +
To data line
Even
Gamma
-
negative Output
z Wide Dynamic Range (Rail to Rail )
buffer
Voltage DAC N + z Low deviation
(-)
z High driving ability
Positive and negative signals are applied by DAC1 and DAC2 separately. Dynamic range of each DAC is z Low power consumption
reduced to ½ compared with conventional ones.
z Optimum OP AMP. area
Design of Output Amplifier Design of Output Amplifier

• OP-AMP • CMOS OP-AMP
Vdd Compensation
circuitry
+
+
- + Vout’
V1 Differential High-gain Vout Output
V1 + Vout=Av(V1-V2) Transconductance
V2 stage stage Buffer
- V2 Vss
- -
Bias Circuitry
Ref: P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” 2nd Ed., Oxford, 2002 Ref: P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” 2nd Ed., Oxford, 2002
Model for a Nonideal Op-Amp Classification of Op-Amp
conversion Hierarchy
Classic differential modified differential

voltage to current amplifier amplifier 1st
voltage
stage
Differential-to-
Source/sink MOS diode
Current to voltage single-ended load
Vout(s)= Current load load
(current mirror)
Current
Av(s)[v1(s)-V2(s)] stage
• Finite differential-input impedance Rid, Cid Transconductance Transconductance
±Ac(s)[v1(s)+V2(s)]/2 voltage to current
• Output resistance Rout grounded gate grounded gate 2nd
• Common-mode input resistance Ricm voltage
stage
• Input offset voltage Vos Class A (source
Current to voltage Class B (push-pull)
• Input offset current Ios=|IB1-IB2| or sink load)
• Common-mode rejection ratio : v1/CMRR
• Noise : in2, en2 Ref: P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” 2nd Ed., Oxford, 2002
Analog CircuitNCHU
Ref: P. E. Allen, D. R. Holberg, “CMOS 98(上) / EE / 汪芳興 / fansen@dragon.nchu.edu.tw
Design,” 2nd Ed., Oxford, 2002 Page 109 / 195 98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 110 / 195
Examples of Op-Amp Design of Op Amp

• Classical two-stage • Folded-cascode op • Procedures
CMOS op amp amp
– Choosing or creating the basic
structure
– Select dc currents and transistor 1. Hand
calculation
size 2. Computer
– Boundary conditions simulation
• Process specification (Vt, k’, Cox…)
• Supply voltage/current and range
• Operating temperature and range
Ref: P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” 2nd Ed., Oxford, 2002 Ref: P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” 2nd Ed., Oxford, 2002
Model Parameters for a Typical CMOS
Design of Op Amp Bulk Process
– Performance requirement Example Parameter Process description Typical parameter value unit
• Gain ≧70 db symbol n-channel p-channel
• Gain bandwidth ≧5 MHz Threshold voltage V
VT0 0.7±0.15 -0.7±0.15
• Settling time ≦1 us (VBS=0)
• Slew rate ≧5 V/us Transconductance uA/V2
K’ 110.0±10% 50.0±10%
• Input common-mode range, ICMR ≧±1.5 V parameter (in sat.)
• Common-mode rejection ratio, CMRR ≧60 db γ Bulk threshold 0.4 0.57 V1/2
• Power-supply rejection ratio, PSRR ≧60 db parameter
• Output voltage swing ≧±1.5 V λ Channel length 0.04(L=1um) 0.05(L=1um) V-1
modulation parameter 0.01(L=2um) 0.01(L=2um)
• Output resistance N/A
• Offset ≦ ± 10 mV Surface potential at V
2|φF| strong inversion
0.7 0.8
• Noise ≦100 nV/√Hz@1 kHz
• Layout area ≦ 5000 x (min. L)2 Model parameters for a typical CMOS bulk process using the simple
model with values based on a 0.8um silicon-gate bulk CMOS n-well
Analog CircuitNCHU
Design,” 2nd Ed., Oxford, 2002 Page 113 / 195 Analog CircuitNCHU
Design,” 2nd Ed., Oxford, 2002 Page 114 / 195
Design of Op Amp Frequency and Phase Response (1/3)

• Procedures • For a single-loop, negative-feedback system
– Decide on a suitable configuration

• Trade-off between noise, offset, power… F(s)
-
– Determine the compensation method
Vin(s) Σ A(s) Vout(s)
• Especially for very large CLOAD +
– Design device sizes for proper dc, ac, and Stable Î |A(jω0°) F(jω0°)| = |L(jω0°)| < 1
transient performance where ω0° is defined as Arg[- A(jω0°) F(jω0°)] = Arg[L(jω0°)] = 0°
• Hand calculation : 80% Æ important to get a feel or Arg[- A(jω0dB) F(jω0dB)] = Arg[L(jω0dB)] > 0°
for sensitivity of parameter variation where ω0dB is defined as |A(jω0dB) F(jω0dB)| = |L(jω0dB)| = 1
• computer simulation : 20% Æ for optimization
Rule: (use of simulator) x (common sense) = constant Ref: P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” 2nd Ed., Oxford, 2002
Analog CircuitNCHU
Design,” 2nd Ed., Oxford, 2002 Page 115 / 195 98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 116 / 195
Frequency and Phase Response (2/3) Frequency and Phase Response (3/3)
• Bode Plots: • Time response of a second-order system
– |A(jω) F(jω)| & Arg[- A(jω) F(jω)] – Large P.M. results in less ‘ringing’ Æ good stability
– P.M. >45° (at least), > 60° (preferable)
Phase Margin
ΦM = Arg[L(jω0dB)]
Analog CircuitNCHU
Second-order Uncompensated Op Amp Miller Compensation of Op Amp

• Small-Signal Equivalent Circuit • Miller Compensation Technique
P’1=-1/(RICI)
P’2=-1/(RIICII) CII >> CI, CC
P1= -1/(gmIIRIRIICC)
If F(s)=1 (worst case)
PM << 45°
P2= - gmIICC /(CICII+ CCCII+ CICC) ≒ - gmII/CII
Æneed compensation Z1 = gmII/CC
Ref: P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” 2nd Ed., Oxford, 2002
Miller Compensation of Op Amp Two Stage Op Amp with Parasitic C
• Root locus plot of the • There are more than two pole due to C1, C2, C3,......
loop gain F(s)=1 • We will concentrate on two most dominant (small) pole
and the RHP zero. − GI GII − ( gds2 + g ds4 )(gds6 + gds7 )
p1 ≅ =
gmII CC gm6CC
• Bode plots − gmII − gm6
p2 ≅ =
– P2 does not affect the CII C2
magnitude until after
gmI gm2
|AF|<1 z1 ≅ =
– Z1 increases the phase CC CC
shift Unit gain bandwidth：
g mI g m 2
GB ≅ =
CC CC
Analog CircuitNCHU
Miller Compensation Technique Miller Compensation Technique

• P1：miller pole and accomplish the desire • P2：output
output pole,
pole at least equal to GB and is due to the
capacitance at the output of the op amp.
compensation
• CII = CL(load capacitance).
• M6 is a NMOS. CC is multiplied by the gain of the
• Since |p2| is near or greater than GB, the reactance of CC
2nd stage, gmIIRII, to give a capacitor in parallel is approximately 1/(GBCC) and is very small.
with RI of gmIIRIICC • M6 is a MOS diode and its small signal resistance is gm6-1.
• Multiplying gmIIRIICC times RI and • Multiplying gm6-1. by CII and inverting gives
inverting it. Then we get − g mII − g m 6
p2 ≅ =
− GI GII C II C2
p1 ≅ =
g mII CC
− ( g ds 2 + g ds 4 )( g ds 6 + g ds 7 )
g m 6 CC
Analog CircuitNCHU
Miller Compensation Technique Output Deviation of Buffer
• Z1 (the RHP zero) boosts the loop gain magnitude
while causing the loop phase shift to become VDD Vo,
absolute offset,
more negative. Æ undesirable between chip
• It worsens the stability of the op amp. RII idea voltage
CC
• It comes from the two feedback path. Vout
+
V’’ + M6 Vx,
- idea voltage Vdvo,Output deviation
V’ of gray m
-
• The signals through these two paths Voc,
Output offset
may be equal and opposite and cancel, between chip to V(m, ave),
creating the zero. chip Average output voltage
of gray m
⎛ − g m 6 RII (1 / sCC ) ⎞ ⎛ RII ⎞ − RII ( g m 6 / sCC − 1) IC1 IC2
Vout ( s ) = ⎜⎜ ⎟⎟V '+⎜⎜ ⎟⎟V ' ' = V
⎝ RII + 1 / sCC ⎠ ⎝ RII + 1 / sCC ⎠ RII + 1 / sCC
Offset Cancellation Layout of Source Driver

Phase 1 Length
Caz +
Channel 381
Channel 383
Channel 382
Channel 384
Height
Channel 1
Channel 3
Channel 2
Channel 4
- 384 channel Gamma
-+ Vo=Vin+Voffset
- Vin source driver resistor
Vin -+ + Voffset
Vo=Vin+Voffset Vcaz=(Vin+Voffset)-Vin
Voffset
Channel 418
Channel 420
Channel 417
Channel 419
420 channel
Channel 2
Channel 4
Channel 1
Channel 3
Phase 2 Gamma
source driver resistor
Caz
-+
Vin + - Vo=Vin+Voffset-Vcaz
Channel 478
Channel 480
Channel 477
Channel 479
Voffset 480 channel
Channel 1
Channel 3
Channel 2
Channel 4
Vo=Vin Gamma
source driver resistor
How Long the Ph1 is enough to sample the correct Voffset?
How Long the Ph2 is enough to charge the pixel voltage?
Layout length/channel ＜ 2 cm / 480 = 41 um
TSMC HV Process Power Saving mode (1)
Start pulse input for 1st IC

Turn on one clock
Start pulse output for 1st IC
Clock disable signal for 1st IC
P = fd*Cload*VDD2
Start pulse input for 2nd IC
Start pulse output for 2nd IC

dV
Clock disable signal for 2nd IC I =C×
dt
Start pulse input for 8th IC
Start pulse output for 8th IC

Clock disable signal for 8th IC
Start pulse 1st IC 2nd IC 3rd IC 4th IC 5th IC 6th IC 7th IC 8th IC
LCD Panel
Power Saving mode (2) Power Saving mode (3)
Distribute clock tree Dual edge clocking
Shift Shift Shift Shift Shift Shift

Register Register Register Register Register Register
CK1
clock XCK1
CK2
clock XCK2
Shift Shift Shift Shift Shift Shift

Register Register Register Register Register Register
Clock 1
Clock 2
1 2 3 4
Clock 1
Clock 2
Charge Sharing Charge Sharing
• Because only half of the charges with positive potential are
recycled, power saving efficiency of the previous charge
sharing is theoretically limited to 50%.
-
Vgmama+ O.P.
DAC P + Odd
Data Output
Charge Sharing
Control signal To data
line
Even
Output
Vgmama- -
O.P.
DAC N +
Data
Waveform of LCD Driver Power Consumption of LCD Source Driver
Power Consumption
/ IC
Large size panel
4~8mA
CNS for Car

2~3mA
DSC, Game, PDA

0.5 ~ 2 mA
Mobile-phone
< 0.3mA,
(power saving )
Trend of LCD Source Driver Outline
z 6-bit / 8-bit to 10 bit resolution Ch4. Driving Circuits Design of A-Si TFT
z 384 / 480 to >500 output channels for SXGA+ / – Gate Driving Circuit
WSXGA+ / UXGA / WUXGA panel
– Source Driving Circuit
z TTL to RSDS/mini-LVDS data interface for low power
and EMI issue – LCD-TV Driving Technology
z 10V to 18V for wide-view-angle panel – Small-Size TFT-LCD Driver IC
z Reduced chip size for cost down
– Trends of Digital Interface
z Low power consumption
z TV application
LCD TV vs. LCD Monitor LCD TV Electronics

LCD Control Board
LCD Module
Mini-
Mini-LVDS/
ASIC
(T-CON,
RSDS/ Gamma Volt. Gen. Data driver
TTL/
Antenna RSDS/TTL
Tuner OSD γ PCB with data bus
RF in transmitter)
Composite Video
video Y/C
Decoder De-interlace cable
YCbCr
Display Area
YPbPr Sync TTL/
Sep. ADC LVDS/ HDTV : 1920x1080; 1280x720
Analog Scaler TMDS WXGA : 1366x768/1280x768
RGB
TMDS SDTV : 720x480
Digital Rx
DVI
DC/DC
MCU power
Inverter Back light unit
Antenna
Cable Set-Top Box
Scan driver
Digital TV System LCD-TV Control IC
• Trumpion-Zipro Chip
Scaler IC
VSB/COFDM MPEG2
Digital Tuner POD/CI
Demodulator Decoder
32MB DDR
SDRAM
LCD TV Block Diagram De-interlace

POWERAMP
LA4260/61
LA7585 LA4265/70 LA4266/4267/4268
SVC208
NTSC/PAL
LA7587/88 LA4280/82
AF/Output
LA4276/4277/4278
• example
SVC230 LA7565 STK401-
STK401-XXX
TUNER SAW VIF/SIF ELECTRONIC

VOL.
EXTERNAL LC41XX
SOUND
RGB DECODER LC758XX
LA76818
PANEL 1/F LCD
LA863228
γ CORRECT DRIVER
LCD
EXTERNAL SWITCH PANEL
VIDEO スキャンコンバータ
LA7221 LC74723M
2SC3950 OSD LC74725M
Audio/video Switch
ビデオ出力ドライバ CONTROLLER LC74781M
LC875448A
RESET MICON LC74782M
LC87F54C8A
LC74883M
Complex Devices BACK LIGHT
(PNP+NPN) DC-
DC-DC DC-
DC-AC
Power MOSFET CONVERTER INVERTER LA5661/LA5662
CPH5506
CPH3115/3109 FTS2005/FW332/ECH8605~6
Diodes
FSS140/132/134 CPH5702/CPH5706 2SD1804T/2SD1802T
SBS004/005/006 2SC5706-
2SC5706-PM/2SJ503/2SJ485
CPH3304/3414
SBE001/SBE002 CPH3109/3116/3216/3205/3212/5504
2SA2039/2SC5566/2SC5707
Luminance of LCD vs. CRT Black Insertion
• Emulate impulse-type display
– Turn off backlight
– Insert black data or clear the data on pixel
• Double frame rate (60 -> 120 -> 240 Hz)
Display Quality for Moving Picture ： Which is Better ？
Adjustable Gamma Curve Adjustable Gamma Curve
Gamma control code example

(from T-CON) 8-bit Data
γ−1.8
R1 string V0~V255
switch γ−2.2 DAC Vout
Vref [1:18]
R2 string
γ−2.6
R3 string
Use external Gamma control code to control final Gamma resistance rings
γ−1.8 γ−2.2 γ−2.6
Over 8-bit Color Depth Overdrive for LCD TV
Conventional Overdrive
Over-8 bit data Gray Level Gray Level
Gn'
new DAC Gn Gn
Vref [1:18] with Vout (over-8 bit resolution)
γ-R string
Ideal Response / Voltage by Driver
Gn-1 Voltage by Driver Gn-1
Actual Response Overdrive Response
n-2 n-1 n n+1 n+2 n+3

8 bit Source driver IC Æ 10 bit ! Æ 12 bit ? n-2 n-1 n n+1 n+2 n+3
Frame Frame
Effect on LC Overdrive Overdrive Circuits
FFD ( Feedforward Driving )Method by Mitsubishi

Dn+1
Data Data’
Lookup Table
Dn
Memory
Read/Write address
Ctrl
Control ckts
Tr+ Tf ≈ 25ms (ON/OFF)
Tr, Tf < 20ms (Gray Level)
Dynamic Contrast Enhancement Other Technologies
¾ Over-8 bit color depth • 10 bit color depth (source driver IC)
¾ Dynamic gamma correction
– 1.07 billion colors
¾ Dynamic backlight control
• LED backlight
– R, G, B mixed LED BLU
• NTSC ratio > 100%
• R/G/B color sequential method (CF-free)
• Power consumption
• Thin module thickness
brightness
brightness
brightness
• Digital Image Processing

– Sony:WEGA engine…
Normal image bright image dark image
LCD TV Trends Outline

Technology trends and challenges Ch4. Driving Circuits Design of A-Si TFT
LCD Monitor LCD TV challenge – Gate Driving Circuit
Size 15-20” 15-20” 20-30” 32-65”
Brightness/C.R. 250/400 400~550/500~700 >550/>2k
– LCD-TV Driving Technology
Response Time 25~16ms 25~16ms 16~12ms < 8 ms COST
Viewing angle 140/160 160/160 176/176
Resolution XGA~UXGA SVGA~WXGA WUXGA~HDTV
2002~2003 2004~2008
Applications of Small Size Display Small-Size TFT-LCD Driver IC
Source
Controller Controller +
driver
0.25 μm Source driver
0.5 μm Hitachi
Single chip Samsung
奇景
DC/DC Gate DC/DC converter HV 聯詠
TFT
TFT converter driver + gate driver 智寶科技
0.6 μm HV 0.6 μm HV HV
4 Chip 2 Chip 1 Chip

TCP/COF Type COG/COF Type COG Type
小尺寸TFT-LCD驅動晶片解決方案演進圖
Architecture of One Chip TFT-LCD Single Chip TFT-LCD Driver IC for

Driver IC Mobile Phone Application
G176
G175
G177
S395
S394
S396
G2
G1
G0
• Simple IC Sketch for TFT Mobile Phone
S3
S2
S1
:::
:
:
:
VGH
– 2.5V Block：OSC, SRAM, APR, Some Logic VGL (176+2)CH
Gate Driver
Gamma
adjusting
64 396 Channel
Source Driver
Vgoff
GVDD and
– 5V Block：I/O, Source, Regulator, Charge Pump (PWR) VGS
Gate
graylevel
generator
Latch circuit
AVDD
control
– 32/40V Block：Gate, Regulator, Charge Pump (PWR) Address
Built-in GRAM
Power counter 132x18x176 bit
Supply
Circuit
Read / Write
Gate Driver Source Driver Gate Driver Data latch
Timing 18
GAMA64
PWR SRAM SRAM PWR Generator
Index Control
APR register register 18
OSC
Vcom System Interface
VDD 18/16/9/8-bit parallel, 3-pin SPI
18
VDD3
Control
R/W
SPI
Data
Voltage Setting Voltage Waveforms
VGH(+9 ~ +16.5V)
BT2-0
VGH(+9 ~ +16.5V)
AVDD(+3.5~ +5.5V)
VC2-0 BT2-0 VREG1OUT
VCI(2.5V ~ 3.3V) GVDD(+3.0~ +5.0V)
sn(source output) AVDD(+3.5~ +5.5V)
VCI1 VCOM4-0
VDD(2.0V ~ 3.3V) VRH3-0 VcomH(+3.0~ VREG1OUT) GVDD(+3.0~ +5.0V)
VDV4-0 VDD(2.0V ~ 3.3V)
VcomH(+3.0~ VREG1OUT)
VSS(0V) VCOM
-1 times -1 times VcomL(VCL+0.5 to 1.0V)
VcomL(VCL+0.5 to 1.0V)
VSS(0V)
VCL
VC3=0 VC3=1 VgoffH (~to -5.0V)
VRL3-0 VRL3-0
VgoffH (to -5.0V) Gn (Gate output)
VgoffL(VGL+0.5 to -5V)
VREG2OUT
VgoffL(VGL+0.5 to -5V)
VGL (-16.5 to -9V)

Note : 電壓波形設定示意圖
adjust the conditions of AVDD-GVDD > 0.5V, VcomL-VCL > 0.5V, and VgoffL-VGL > 0.5V with loads because
They differ depending on the display load to be driven. In addition, Vci can be directly input to Vci1.
Power Pins Description (1/2) Power Pins Description (2/2)

Symbol I/O Description
System power supply.
As NT3911 has internal regulator, VDD range varies with each mode.
VDD -
Non-regulated mode (PregB = 1) : +2.0 ~ +2.5 V Symbol I/O Description
Regulated mode (PregB = 0) : +2.0V I A reference voltage of VcomH.
VcomR
System power supply for regulator as external power. When VcomH is externally adjusted, halt the internal adjuster of VcomH by setting the register and insert a variable resistor
VDD3 -
(VDD3: +2.5 ~ +3.3 V) between VREG1OUT and VSS. When this pin is not externally adjusted, leave it open and adjust VcomH by setting the
internal register.
A power output pin for source driver block that is generated from power block.
AVDD I/O Connect a capacitor for stabilization. (AVDD: +3.5 ~ +5.5 V) VcomH O This pin indicates a high level of Vcom generated in driving the Vcom alternation.
Connect this pin to VCI2 pin. When not using a charge-pump circuit 1, leave it open. Connect this pin to the capacitor for stabilization.
Standard level for grayscale voltage generator. VcomL O When the Vcom alternation is driven, this pin indicates a low level of Vcom. An internal register can be used to adjust the
GVDD I/O
Connect a capacitor for stabilization. voltage. Connect this pin to a capacitor for stabilization.
When the VCOMG bit is low, the VcomL output stops and a capacitor for stabilization is not needed.
An internal reference power supply for VREG1OUT/VREG2OUT.
VCI I/O Connect VDD when VDD = 2.5 to 3.3 V. VGH O A positive power output pin for gate driver, internal charge-pump circuits, bias circuits, and operational amplifiers. Connect a
Connect a 2.5 to 3.3 V external-voltage power supply when VDD = 2.0 to 2.5 V. capacitor for stabilization.
Connect this pin to VCI3 pin. When not using a charge-pump circuit 2, leave it open.
VSS - System ground (0V)
VGL O A Negative power output pin for gate driver, bias circuits, and operational amplifiers.
AVSS - System ground level for analog circuit block. Connect a capacitor for stabilization. When internal VGL generator is not used, connect an external-voltage power supply
higher than -15.0 V.
A power supply pin for generating VcomL. When VcomL is higher than VSS, outputs
VCL I/O
VSS level. Vgoff I Power supply pin for off level for gate of TFT.
Connect this pin to VgoffOUT. When VgoffOUT is not used, connect an external-voltage power supply higher than -TBD V.
REGP I/O Input pins for reference voltages of VREG1OUT when the internal reference-voltage generation circuit is not used. Leave
VgoffOUT O An power output pin for gate driver.
these pins open when the internal reference-voltage generation circuit is used.
This pin is a negative voltage for the gate off level. Alternation can be synchronized by M pin. Set the internal register
VREG1OUT O This pin outputs a reference voltage for VREG1 between AVDD and VSS. When the internal reference voltage is not used, according to the structure of the TFT-display retention volume.
the reference voltage can be generated from the voltage of REGP. Connect this pin to a capacitor for stabilization. For the amplitude at the alternation driving, this pin outputs a voltage between VcomH and VcomL with the VgoffL reference
When this pin is not used, leave it open. voltage..
VREG2OUT O This pin outputs a reference voltage for VREG2 between VSS and VGL When the internal reference voltage is not used, the VgoffH O When the Vgoff alternation is driven, this pin indicates a high level of Vgoff. Connect a capacitor for stabilization. When the
reference voltage can be generated from the voltage of REGN. Connect this pin to a capacitor for stabilization. When CAD bit is low, the VgoffH output stops and a capacitor for stabilization is not needed.
this pin is not used, leave it open.
VgoffL O When the Vgoff alternation is driven, this pin indicates a low level of Vgoff. Connect a capacitor for stabilization. An internal
VcomOUT O A power supply for the TFT-display counter electrode. register can be used to adjust the voltage.
The alternating cycle can be set by the M pin. Connect this pin to the TFT-display counter electrode.
This pin is also used as equalizing function: When EQ = “High” period, all source driver’s outputs (S1 to S396) are short to
Vcom level (Hi-z).98(上)
In case of VcomLNCHU
< 0V, equalizing function/ fansen@dragon.nchu.edu.tw
/ EE / 汪芳興 must not be used. (Set EQ bit (R07h) to bePage
“00” 163
for / 195 98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 164 / 195
preventing the abnormal function.)
Power Definition (1/2) Power Definition(2/2)
(For the analog circuit) (For the regulator circuit)
Parameter Symbol Min. Typ. Max. Unit Conditions
Symbol Min. Typ. Max. Unit Conditions
AVDD 3.5 - 5.5 V Parameter
VGH 9 - 16.5 V Reference voltage for internal

RVDD 1.95 2.0 2.1 V
digital power VDD3=3.3V
LCD Supply Voltage VGL -16.5 - -9 V For the analog circuit power
RVDD driving current IRVDD - 200 500 uA
VGOFF -16 - -5 V
Reference voltage of
GVDD 3 - 5 V REGP 2.46 2.5 2.56 V VCI=3.3V, VC2-0=”100”
VREG1OUT
Internal reference power supply Reference voltage for VREG1
VCI 2.5 - 3.3 V 5.71 5.83 5.95 V
voltage grayscale voltage generator OUT VCI=3.3V, VC2-0=”100”, VRH3-0=”1001”
Output Voltage deviation Vod - ±20 - mV Source Driver VREG1OUT driving current IVREG1 1 - 2.5 mA
Output Offset between Chips Voc - ±20 - mV Source Driver Reference voltage output for VREG2
-6.47 -6.6 -6.73 V
Dynamic Range of Output Vdr 0.1 - GVDD-0.1 V S1 ~ S396 gate driver OUT VCI=3.3V, VRL3-0=”0001”
Source Driver Driving Current of S1 ~ S396; Vo=4.5V v.s 3.5V VREG2OUT driving current IVREG2 -500 - -100 uA
ISOH 50 - - uA
Outputs AVDD=5V, Gradation output GVDD driving current IGVDD 100 - 150 uA
Gate Driver Sinking Current of G0 ~ G177; Vo=-12V v.s -11.5V High level reference voltage of VCI=3.3V, VC2-0=”100”, VRH3-0=”1001”,
IGOL | -250 | - - uA VgoffH -0.85 -0.83 -0.81 V
Outputs VGH-VGOFF=30V Vgoff VDV4-0=”01101”
Gate Driver Driving Current of G0 ~ G177; Vo=18V v.s 17.5V Low level reference voltage of
IGOH 250 - - uA VgoffL -6.47 -6.6 -6.73 V VCI=3.3V, VRL3-0=”0001”
Outputs VGH-VGOFF=30V Vgoff
Power consumption for Stand- No load, VDD3=3V, VDD=2V, VCI=2.7V, High level reference voltage of VCI=3.3V, VC2-0=”100”, VRH3-0=”1001”,
Isc - - 5 uA VCOMH 4.57 4.66 4.75 V
by mode VBS=VSS and all operating is stopped Vcom VCM4-0=”10101”
IVDD - 200 500 uA Low level reference voltage of VCI=3.3V, VC2-0=”100”, VRH3-0=”1001”,
VCOML -1.13 -1.11 -1.09 V
Operating Current Vcom VDV4-0=”01101”
IVCI - 1.5 2.0 mA
(Reference for system design)

(VDD =2.0V, VDD3=3V, VSS =0V, TA=25 oC)
Power Supply Circuits GAMMA ADJUSTMENT FUNCTION

C2 C1
• The NT3911 provides the gamma adjustment function to display 262,144 colors
1
VREG2
1
VREG1
simultaneously. The gamma adjustment executed by the gradient adjustment
OUT OUT
Amplification Amplification C9
register and the micro-adjustment register that determines 8 grayscale levels.
Circuit2 Circuit 1 G VD D GVDD
(Vgoff (GVDD output
amplifier GVDD
adjustment) adjustment)
Vcom G R AM
REGN VcomH MS B L SB
adjustment Amplitude
REGP circuit adjustment
circuit
C1 5 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
VCI
VCI
Voltage VcomH
VCIOUT output VCOMH
Regulator adjustment P KP 02 PKP 01 PK P00
circuit amplifier
C12
P KP 12 PKP 11 PK P10
VCOMR VCOMOUT
A dj u s t V C O M H
v olt ag e ( w he n P KP 22 PKP 21 PK P20
using an extemal
var ia ble resistor) P o sitive P KP 32 PKP 31 PK P30
Vci1 VcomL p o larity
output
C14 C11- amplifier re g ister P KP 42 PKP 41 PK P40
VCOML
C17 C11+ C10
Charge- VgoffH P KP 52 PKP 51 PK P50
C12- pump amplitude
C18 C12+ circuit 1 adjustment P RP 02 PRP 01 PR P00
C16 AVDD circuit
P RP 12 PRP 11 PR P10
V0
VCI2 6 6 6
AVDD VgoffH VGOFFH
C21M output V RP0 3 V RP 02 VRP 01 VR P00
V1
C4 C21P
VgoffL amplifier
output C19 V RP1 4 V RP1 3 V RP 12 VRP 11 VR P10 64 g ra ysc ale 6 4 g ra ysca le 64 g rays cale
8 G raysc ale 64
C22M Charge- amplifier VGOFFOUT c o ntro l co ntro l co n tro l
C3 Am p lifie r
C22P pump <R> <G > <B >
C23M circuit 2
C2 C23P L CD d river LC D drive r LCD driver
V 63
VGH P KN02 PK N01 P KN0 0
C1 P KN12 PK N11 P KN1 0
VCI3
VGH VGOFFL
C31M P KN22 PK N21 P KN2 0
C6 C31P
Charge-
p ump C20
∫
VGL circuit 3 N eg ative P KN32 PK N31 P KN3 0
VGL C7
Vci4
p o larity
re g ister P KN42 PK N41 P KN4 0
R G B
VC1 VDD
C41-
C5 Charge- VSS P KN52 PK N51 P KN5 0
C41+
VCL
pump VCI LC D
circuit 4 VSS
P RN02 PR N01 P RN0 0
C3 P RN12 PR N11 P RN1 0
VR N03 V RN02 VR N01 V RN0 0
VRN 14 VR N13 V RN12 VR N11 V RN1 0

Configuration of the Internal Power-supply Circuit
Scan Mode Structure of Grayscale Amplifier
G1 G2
A ODD EVEN
• Gate scan mode of NT3911 is set by SM and GS bit. GS • The structure of the grayscale amplifier is shown as below. Determine
TFT
Panel bit determines the scan direction whether the gate driver 8-level (VIN0-VIN7) by the gradient adjuster and the micro adjustment
G1
G175
G175
G176
G176 G2
scans forward or reverse direction. SM bit determines the register. Each level is split by the internal ladder resistance and level
NT3911 method of display division (Even/Odd or Upper/Lower between V0 to V63 is generated.
G1 G2 division drive). Using this function, various connections G r a d ie n t a d ju s t m e n t
r e g is te r
M ic r o a d ju s t m e n t r e g is t e r ( 6 X 3 b i t s )
O s c il la t i o n a d ju s t m e n t
r e g is t e r
B ODD
TFT EVEN
between NT3911 and the liquid crystal panels can be G VDD P R P /N 0
3
P R P /N 1
3
P K P /N 0
3
P K P /N 1
3
P K P /N 2
3
P K P /N 3
3
P K P /N 4
3
P K P /N 4
3
V R P /N 0
4
V R P /N 1
5
Panel
G175 G176
accomplished V IN P /N 0
V0
G1 G175 G176 G2
NT3911
SM GS Scan Mode
8 to 1 V IN P /N 1
V1
s e le c t o r
V2
V3
G1
C
TFT
Panel
0 0 A G1ÆG2ÆG3ÆG4Æ…ÆG173ÆG174ÆG175ÆG176
G175
8 to 1 V IN P /N 2
V8
s e le c t o r
G2 V9
G176 0 1 B G176ÆG175ÆG174ÆG173Æ…ÆG4ÆG3ÆG2ÆG1 Ladder

8 to 1
s e le c t o r
V IN P /N 3
V20
V21
G1 G175 G176 G2 r e s is t a n c e
G ra y s c a le
V IN P /N 4 a m p l if i e r
NT3911 8 to 1
V43
s e le c to r
V44
G1ÆG3ÆG5Æ…ÆG173ÆG175
1 0
G1
D
TFT
Panel
C ÆG2ÆG4ÆG6Æ…ÆG174ÆG176
8 to 1
s e le c t o r
V IN P /N 5
V55
V56
G175 V57
G2
G176ÆG174ÆG172Æ…ÆG4ÆG2
8 to 1 V IN P /N 6
V62
G176
1 1 D s e le c to r
ÆG175ÆG173ÆG171Æ…ÆG3ÆG1
G1 G175 G176 G2
NT3911
V IN P /N 7
V63
98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 169 / 195 VG S 98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 170 / 195
Gamma Adjustment Register Chip Size & Pad Dimensions

• This block has the register to set up the grayscale voltage adjusting
to the gamma specification of the LCD panel. These registers can
independently set up to positive/negative polarities and there are 4- Size
type of register groups to adjust gradient and amplitude on number Items Pad name. Unit
of the grayscale, characteristics of the grayscale voltage. (average
X Y
<R><G><B> are common.) The following figure indicates the Chip size - 20720 2500
operation of each adjusting register.
Input Pad 54 100
Output Pad 36 70 um
Grayscale Voltage
Grayscale Voltage
Grayscale Voltage
Grayscale Voltage
Pad size
Dummy Pad
80 80
1,195,239,742
Grayscale Number Grayscale Number Grayscale Number Grayscale Number
a) Gradient adjustment b) Amplitude adjustment c) Reference adjustment d) Micro-adjustment
• NOTES:
• Scribe line included in this chip size (Scribe line: 120um)
Process Feature for One Chip Driver IC Product Applications
• TFT Driver IC for Mobile Phone

0.25um
Technology
1P3M (MIM Process)
LV (Dual Gate) / HV 2.5V / 5V / 40V (+/-20V)
Oxide Thickness 48A / 110A / 1000A
40V HVMOS Structure LDMOS
LV / HV Well Structure Retrograde / Drive-In Well + NBL
Isolation STI / P-EPI
Gate Material Poly (S/D Implant Doped) + Salicide
S / D Area Salicide • STN Driver IC for Mobile Phone
Capacitor MIM – NT7523為Hi-Fas CSTN One Chip Driver IC，使用0.25μm
High Rs Poly 400~2000 Ohm 2.5/5/32V Process
Source : Novatek training material Source : Novatek training material
LV and HV Device Type LTPS TFT-LCD Driver ICs

Q LV and HV Device Type and Related Data (1)
Ò 2.5 / 5V Devices Characterization
5 LV Devices ( 2.5V NMOS and PMOS, 5V NMOS and PMOS, 2.5V Native NMOS )
Simplified
STI Field Isolation T-Con Source Driver IC T-Con Source Driver IC T-Con
Triple Well Structure
De-MUX Source Driver IC
Gate Driver IC
Gate Driver IC
Gate Driver IC
Salicide Structure
Ò2.5 / 5V Devices Cross Section Sketch LTPS LTPS
A-Si TFT-LCD
TFT-LCD TFT-LCD
Conventional LTPS TFT-LCD LTPS TFT-LCD

a-Si TFT-LCD Example 1 Example 2
非晶矽與多晶矽 TFT-LCD 驅動方式比較圖
Source : Novatek training material
Outline Interfaces in TFT-LCD Monitor
Ch4. Driving Circuits Design of A-Si TFT

– Gate Driving Circuit
– LCD-TV Driving Technology
Digital vs. Analog Panel Input Interface
TTL vs. LVDS Comparison of TTL，RSDS，and Mini-
LVDS
TTL RSDS Mini-LVDS Remark

Bus lines 8-bit 24X2 24 12
6-bit 18X2 18 10
Voltage Swing 3.3V 200mV 200mV Lower amplitude for
reducing EMI
Frequency XGA 32.5M 67M 67M
(2 ports) ( 1 port) (2 ports)
SXGA 54M 54M 108M
(2 ports) (2 ports) (2 ports)
UXGA - 81M 162M
LCD ~SXGA ~ UXGA ~ QXGA
Application
PCB Area 1 0.7~0.8 0.5~0.7
T-CON Pins 6-bit ~100 ~64 ~100
Driver IC 6-bit ~80 ~60 ~50
Input Pins
Remark: RSDS and Mini-LVDS use twin-pair lines
RSDS Definition 8 Bit RGB RSDS Data
• Reduced Swing Differential Signal

– ±200 mV swing (typical)
Start pulse
– 2:1 mux - 2 data per clock cycle R0 R1
– 100 ohm differential terminals Invalid data R2 R3
– Voffset = 1.2 V R4 R5
R6 R7
– RGB data and clock only G0 G1
• Apply to bus between T-Con and Invalid data G2 G3
G4 G5
source drivers
G6 G7
– Reduce EMI B0 B1
– Reduce power consumption Invalid data B2 B3
– Reduce source driver bus width B4 B5

B6 B7
System Diagram ：
RSDS Configuration RSDS Features and Benefits
Single-end • Reduced pin T-Con counts

– Enable smaller area PCBs
• Reduced number of components
– Small area PCBs
– Lower cost
Front/Back
– Number of components：TTL:RSDS = 190:101 (in
14.1” XGA) Æ 46.8％ reduction
• Reduced number of PCB layers
– Number of layers：TTL :RSDS = 6:4
Mini-LVDS Mini-LVDS
6 bit data,
5 pairs
Data Bus Structure
Mini-LVDS RSDS vs. Mini-LVDS
8 bit data, RSDS Mini-LVDS

PCB Size Larger Smaller
6 pairs XGA: TQFP64/80
TCON TQFP100
SXGA/UXGA:TQFP128/144
Driver Size Same Same
Frequency Limitation DIO(Start Pulse) No
Resolution Limitation <= UXGA/Dual Buses QXGA or larger/Dual Buses
Possible Driver Vendors More Limited
RSDS is the major interface

Mini-LVDS become important for high resolution panel
Point to Point Differential Signaling

PPDSTM
(PPDS)
• PPDS is based largely on the • Advantages: (cont.)
– improved signal integrity.
RSDS™ Parameter RSDS PPDS
• typical RSDS bus architecture
• Advantages: Differential Signal
±200mV ±200mV • Î vias and stubs on every signal
Level
– The total number of input signals line Î creates a large number of
Common Mode
1.3V 0.8V impedance discontinuities.
for each column driver is greatly Voltage
Typical Output • point to point systemÎ no vias and
reduced. 2mA 2mA
Current stubsÎ data signal maintain higher
• 8-bit RSDS system: 12 data pairs levelÎ Higher color depth
Transmission Lines 50Ω 50Ω
and the clock pair by each column
– Major improvement in EMI
driver. Table 1. Comparison of PPDS and RSDS levels • Due to the incoming LVDS clock
• In a PPDS system: signal data pair and PPDS clock operating at
and a clock pair different frequency.
• 26 in RSDS Î 4 in PPDS
PPDS Protocol Summaries
Technology Trends of Large-Size TFT-LCD Source Driver IC
• The total reduction in

data signals from an
RSDS based system
to the PPDS 10-bit
(1024灰階)
architecture.
• The protocol is split
into 5 required interval
and 1 optional interval.
Memo
98(上) NCHU / EE / 汪芳興 / fansen@dragon.nchu.edu.tw Page 195 / 195

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Outline

Flat Panel Display : Principle and

Chapter 4 – Source Driving Circuit

Driving Circuit Design of A-Si TFT – LCD-TV Driving Technology

中興大學電機系 / 汪芳興 – Trends of Digital Interface

Introduction to LCD Driver IC Driving Circuits of TFT- LCD Module

I/F + X PCB DC POWER

• Capacitive coupling driving (CC driving)

Gate Driver Architecture Timing of Gate Driver

Gate driver IC 電路方塊圖

Package of Driver IC Package of Driver IC

• Gate driver : No. of driver and No. of output

Gate Driver Circuits CMOS Shift Register

Shift register Level shifter Buffer

– Two cross-coupled ENB1

Shift Register – Latch 2 Level Shifter – Example 1

IN /OUT Vin Vout

GND GND GND

TSMC HV Process Roadmap of High Voltage Technology

Source : Web of TSMC

Scan Driver Consideration Gate Driver Design

Ref:IDW 00’, p.167

If ΔV 1 = ΔV 2 + ΔV 3 i.e. Vghl × Cgd = Vgc × (Cst + Cgd )

Three-level C. C. Driving Four-level C. C. Driving

Black(+) Black(+) Vcom

Data Line Black(-) Final Pixel

Voltage Level Temporal Pixel

Q ΔV1 + ΔV 2 − ΔV 3 = −ΔV 4 + ΔV 5 − ΔV 6 Negative Driving

Cst Data Line

Comparison of Addressing Trend of Gate Driver IC

• Gate Driving Circuit

Source Driver Circuits Analog Data Driver

• Driver Architectures Shift Register Shift Register

pixel pixel control

PAAT Driver Architecture LAAT vs. PAAT

DeMUX 1:2 DeMUX 1:2 DeMUX 1:2 DeMUX 1:2

Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel

(a) Decoder type is very difficult

(b) DAC type is the most

Vcc=5V, Freq.<2MHz @ μn/p=70/35 cm2/Vs (a) (b)

Comparison of Digital/Analog Data Architecture of Source Driver IC for

video signal Compatible to ADC needed Polarity Signal

Out1 Out2 Out3 Outn

128 CLKs 128 CLKs LD(CLK1)

Key Specifications Channel Number vs. Resolution

VGA 25.2 MHz 31.7 μs 31.5 MHz 26.7 μs

XGA 65 MHz 20.7 μs 78.75 MHz 16.7 μs

SXGA 108 MHz 15.6 μs 135 MHz 12.5 μs

UXGA 162 MHz 13.3 μs 202.5 MHz 10.7 μs

Fundamentals of Data Converter Idea D/A Converter

• Ideal D/A converter • Ideal N-bit DAC

Quantization Error in DACs Performance Limitation

 2-bit example： ⎝ VLSB VLSB ⎠

Accuracy Accuracy (cont’)

• Absolute accuracy • Accuracy can be expressed as a percentage error of

• Nyquist-rate D/A converters

Nyquist-rate D/A converters Decoder-Based DAC

• Four main types • Most straight forward approach

• Example 1︰a 3-bit DAC

– Create 2N reference signals and pass the tree-like decoder. R

appropriate signal to the output. R

Resistor-string DAC (cont’) Resistor-string DAC (cont’)

• Example 2︰a 3-bit DAC with digital R

資料來源：林克旯, “ADC及DAC積體電路實作,” MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫.

2-bit example： ⎝ VLSB VLSB ⎠