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Test Data Compression Techniques

for
IP Core Based SoC
Time, Power and Area Optimization

Usha S Mehta
MOTIVATION
IP Core Based SoC

TTM COST

Test Time Design Time Design Cost Test Cost

Modular Design

IP Core
Based SoC

IP = Black Box for System Integrator


Complicated the Testing Process
Current Generation
Fabrication Testing Issues

Test
Cost

Area
To Be
Hidden Focused
Test
Structure of Power
IP
Core
Test Cost
Test Data Compression

Test Cost
Test Application Time
*Test Time will be 209.34 times in
2024 compared to 2009 [ITRS2009]

Test Data Volume


Test Data Compression
*Test data Compression104000
times in 2024 compared to 2009
[ITRS2009]
Test Power
Reduction in Switching Activity

Test Power

Dynamic Power

Scan and Capture Power


Transitions during Scan-in
and Scan-out
Reduction in Switching Activity
During Scan Operation
IP Core
Ready made Test Data (1s, 0s, Xs)
Hidden Structure of IP Core
Black Box for System Integrator

No Availability of Netlist

No Possibility of Insertion or
Modification in Internal Structure
No Possibility of Application of Test
Development Tools like ATPG or
Scan Chain Insertion
To play with Ready Made Test Data
Test Vectors Made up of “1s, 0s and Xs”
The Goal

Ready Made
Test Data

Switching
Test Data Reduction
Compression During
Scan
Test Data Compression
Reduction in Test
Algorithm Compress the Data Transfer Time Addition of
Data /per chip Decoding Time
(one time process)
/per chip

Compressed On Chip
Data Decoder
Addition
Automatic of
Test On Chip
Equipment IPCh
Core
Decoder
to be
Area
Comparator tested

Chip
Switching
Activity??
Objective
To design a test data processing (to prepare for
better compression) and test data compression
method specially for IP core based SoC which
1. does not require any insertion or modification
in internal structure of IP core
2. does not require any test development tools
like ATPG or fault simulation
3. increases the compression
4. reduces the overall test application time (TAT)
5. reduces the switching activity during scan
operation
6. does not increase the on-chip area overhead

compared to existing methods.


Adopted Methodology

In this thesis work, the methodology adopted is:


1. The need or issues related to current generation
testing is studied.
2. The existing solutions for that issue are surveyed.
3. From the available solutions, the possible
solutions for IP core based SoC are separated.
4. These solutions are implemented and analyzed.
5. The existing solutions are optimized.
6. For further improvement, new methods are
proposed which are supported by sufficient
amount of simulation results as well as proved
mathematically.
Literature Review
Test Data
Compression

Linear Broadcast Scan Code Based


Decompression Based compression Compression

Dictionary Constructive Run Length Statistical


Codes Codes Codes Codes

Publication Ref. : C-1, Euromicro Conf. on DSD,Greece


Citation by 7
Reduction in Test Power
By
Reduction in Switching Activity

Techniques Applied Techniques Applied Techniques Applied


for as for
Built-In-Self-Test Design-For-Test External Testing

Low Power
ATPG Input Reordering Don’t Care
Algorithm Controls Techniques Bit Filling

Publication Ref. J-3 VLSI Design, Hindawi Publications ,


C-8 NUiCONE
Current Approach
The Gap

Switching
Compression
Activity

Don’t Care Don’t Care


Reordering Reordering
Bit Filing Bit Filing
Scope of The Work

Don’t Care
Reordering
Bit Filing

Compression
Switching
Compression
&
Activity
Switching Activity
Summary
of
Research Work
Run Length
Based
Test Data Compression
Analysis
Analysis of Existing run length based test data compression
codes like Golomb coding, Frequency Directed Run length
coding (FDR), extended FDR (EFDR), modified FDR (MFDR),
alternating FDR (AFDR), shifted alternating FDR (SAFDR)
for
• Compression results through implementation and
simulation of these codes using MATLAB and C
language.
• Peak power and average power (in terms of switching
activities) through implementation and simulation of
these codes using MATLAB and C language.
• On-chip decoder area overhead through implementation
in VHDL, simulation using Modelsim and synthesis
using Leonardo Spectrum.

Publication Ref. :C-4 APCCS, Kuala-Lumpur


Citation by 1
Run Based Bit Filling
• The proposed classifications of runs used in variety
of run length codes
• Instead of simply filling don’t care bits with ‘0’, in the
proposed method, the don't care bits are filled
considering the type of run being used by the
applied test data compression method.
• It has been shown the compression results are
improved. Further, the entropy based maximum
data compression limit is calculated for the proposed
approach.
Publication Ref. :J-1 VLSI_Design
Citation by 4
Hamming Distance Based Reordering
Columnwise Bit Filling
Difference Vector
• A test data processing method to enhance the
compression results
• HDR-CBF-DV processing method efficiently uses
– the Hamming distance for reordering
– don't care bit filling
– difference vector
approaches to improve the compression.
• The compression has been increased largely without
any significant on-chip area overhead compared to
earlier methods proposed in literature.
Publication Ref. :C-3, VLSID-10, Bangalore
Citation by 4
2-Dimensional Reordering
• To make the test data processing power efficient
• It uses Hamming distance for
– Row wise reordering (vector reordering)
– Columnwise reordering (bit reordering)
• It reduces the peak and average power to large extent
compared to HDR-CBF-DV
• It gives nearly same compression compared to HDR-
CBF-DV.
• It gives large on-chip area overhead compared to HDR-
CBF-DV.
Publication Ref. :C-5 SoC-10, Finland,
Citation by 2
C-6 Indicon-10, Kolkatta
Weighted Transition Based Reordering
Columnwise Bit Filling
Difference Vector
• Weighted Transition Based Reordering (WTR-
CBF-DV) reorders the test vectors considering
weighted transition.
• WTR reduces peak and average power
compared to HDR-CBF-DV but not as much
as 2-D.
• This method also gives nearly same
compression compared to 2-D reordering.
• No extra area overhead HDR-CBF-DV
Publication Ref. J-5, VLSI Design, Special issue on CAD for
Gigascale SoC Design & Verification
Comparison (Ranking)
of
Proposed Test Data Processing Methods
for
Run Length Codes
Compression Peak & On-chip Computational
Average Area Complexity
Scan Overhead
Power

HDR-CBF- 1 3 1 1
DV

2-D 3 1 2 3
WTR-CBF- 2 2 1 2
DV
Statistical Code
Based
Test Data Compression
Analysis
Analysis of Existing Statistical compression codes like
selective Huffman code, optimal selective Huffman code,
Variable Length Input Huffman code (VIHC) and Split-
VIHC for
• Compression results through implementation and
simulation of these codes using MATLAB and C
language.
• Peak power and average power (in terms of switching
activities) through implementation and simulation of
these codes using MATLAB and C language.
• On-chip decoder area overhead through implementation
in VHDL, simulation using Modelsim and synthesis
using Leonardo Spectrum.
Publication Ref. J-4 IJCA,
C-7 NUiCONE
Modified Selective Huffman Code

• To further enhance the compression


• The improvement in compression and
overall test application time without any
extra area-overhead compared to
selective Huffman and optimal selective
Huffman code is proved mathematically
• Effectiveness is demonstrated with
necessary simulation results.
Publication Ref. : J-2 JETTA
Citation by 3
Frequency Dependant Bit Appending
and Filling (FDBAF)

• The proposed Frequency Dependant Bit


Appending and Filling (FDBAF) is a test
data processing method to be applied to test
data before applying statistical code to
increase the compression.

Publication Ref. : C-2 INDICON-09, Gandhinagar


Citation by 5
Comparison (Ranking)
of
Proposed Test Data Processing Methods
For
Statistical Codes
Compr Test On-chip Computational
ession Power Area Complexity
Overhead
MT Fill* 2 1 No 1
FDBAF 1 2 Negligible 2
Conclusion
% Compression

WTR-CBF-DV + FDR Coding FDBAF + MS-Huffman Coding


100
90
80
70
60
50
40
30
20
10
0
s5378 s9234 s13207 s15850 s38417 s38584
Peak Power (max # of transitions)
WTR-CBF-DV + FDR Coding FDBAF + Ms-Huffman Coding
800000

700000

600000

500000

400000

300000

200000

100000

0
s5378 s9234 s13207 s15850 s38417 s38584
Average Power
(average # of transitions)
600000 WTR-CBF-DV + FDR Coding FDBAF + MS-Huffman Coding

500000

400000

300000

200000

100000

0
s5378 s9234 s13207 s15850 s38417 s38584
On-Chip Area Overhead

Test Data Test # of # of # of Max.


Processing Data Equivalent Ports Nets Clock
Compression NAND Frequency
Gates
FDBAF MS 362 6 217 1927.2
Huffman
Code
WTR- FDR Code 1104 5 797 24.6
CBF-DV
Compression-Area Trade off

FDBAF WTR-CBF-DV
• Compression: less • Compression : more
• Area Overhead: less • Area Overhead:
• Power: comparable more
• Power: comparable
THANK YOU

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