Code No: N0203 Set No.

1
IV B.Tech I Semester Regular Examinations, November 2009
VLSI DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Instrumentation Engineering, Electronics & Control Engineering and
Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Explain the MOS Transistor operation with the help of neat sketches in the follow-
ing modes

(a) Enhancement mode

(b) Depletion mode. [8+8]

2. (a) Discuss the gate source and gate drain capacitance of an nFET.
(b) Calculate the gate capacitance of an nFET with following parameter.
W=8µm, L=0.5µm, Cox = 3.45 × 10−7 F/cm2 . [8+8]

3. Describe all the steps in VLSI design flow. [16]

4. Describe three sources of wiring capacitances. Explain the effect of wiring capaci-
tance on the performance of a VLSI circuit. [16]

5. (a) Draw the multiplier array using a square array and explain the operation of
multiplication.
(b) How is the parity generator designed as a linear column of XOR gates with a
tree routing channel and draw the layout of it. [8+8]

6. (a) Draw a self timed dynamic PLA and what are the advantages of it compared
to footed dynamic PLA.
(b) Explain the tradeoffs between using a transmission gate or a tristate buffer to
implement an FPGA routing block. [8+8]

7. (a) What is Selected Signal Assignment Statement? Write a syntax in VHDL.

(b) Explain how the timing analyzers are used to verify the functionality of CMOS
chip. [8+8]

8. (a) What are the main categories of testing? Explain these with examples.
(b) Draw the block level implementation of a polarity hold SRL and explain its
working.
(c) How ROM memories can be tested? [6+6+4]

?????

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 Code No: N0203 Set No. 2
IV B.Tech I Semester Regular Examinations, November 2009
VLSI DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Instrumentation Engineering, Electronics & Control Engineering and
Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. With neat sketches explain BICMOS fabrication process in an N well. [16]

2. (a) Why resistor pull up is not used in MOS circuits?

(b) Discuss different forms of pull up, mentioning merits and demerits of each
form.
[4+12]

3. (a) Discuss design rule for wires (orbit 2µm CMOS).

(b) Discuss the transistor related design rule (orbit 2µm CMOS). [8+8]

4. Describe three sources of wiring capacitances. Explain the effect of wiring capaci-
tance on the performance of a VLSI circuit. [16]

5. (a) Draw and explain the schematic of Pseudo-nMOS comparator.

(b) Draw and explain the structure of multiplier which computes the partial prod-
ucts in a radix-2 manner. [8+8]

6. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/O
structure.
(b) Explain any one chip architecture that used the antifuse and give its advan-
tages. [8+8]

7. (a) Write a VHDL program for 2:1 multiplexer with conditional signal assignment
statement.
(b) Explain how Net list comparison is used to test the performance of CMOS
circuits. [8+8]

8. (a) Why the chip testing is needed? At what levels testing a chip can occur?
(b) What is the drawback of serial scan ? How to overcome this?
(c) What is the percentage fault coverage? How it is calculated? [6+4+6]

?????

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 Code No: N0203 Set No. 3
IV B.Tech I Semester Regular Examinations, November 2009
VLSI DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Instrumentation Engineering, Electronics & Control Engineering and
Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. With neat sketches explain BICMOS fabrication process in a P well. [16]

2. (a) Explain briefly about MOS transistor switch.

(b) Discuss the square law model of FET. [8+8]

3. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS
inverter.
(b) What are the effects of scaling on Vt ?
(c) What are design rules? Why is metal- metal spacing larger than poly -poly
spacing. [8+4+4]

4. (a) For a 5µm technology,the standard unit of capacitances for metal 1,polysilicon
and n-diffusion are 0.0075 Cg , 0.1 Cg and 0.25 Cg respectively. Calculate
the capacitances for area shown in figure 4. Consider same area for calculation.
i. metal
ii. polysilicon
iii. n-diffusion.
(b) Impliment a 3-input NOR gate in dynamic logic and explain its operation.
[8+8]

Figure 4
5. (a) Design a comparator using XNOR and AND gate and draw its schematic.
(b) Design a zero/one detector and draw its schematic and also calculate its delay.
[8+8]

6. (a) Draw and explain the Antifuse Structure for programming the PAL device.
(b) Explain how the I/O pad is programmed in FPGA. [8+8]

7. (a) Compare the behavioral and structural styles of VHDL with example.

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 Code No: N0203 Set No. 3
(b) Explain the method of Binary composition for chip routing with suitable ex-
ample. [8+8]

8. (a) Why the chip testing is needed? At what levels testing a chip can occur?
(b) What is the drawback of serial scan ? How to overcome this?
(c) What is the percentage fault coverage? How it is calculated? [6+4+6]

?????

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 Code No: N0203 Set No. 4
IV B.Tech I Semester Regular Examinations, November 2009
VLSI DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Instrumentation Engineering, Electronics & Control Engineering and
Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Describe in detail, the diffusion process in IC fabrication. [16]

2. (a) Clearly explain the body effect of a MOS FET.

(b) Clearly explain channel length modulation of a MOS FET. [8+8]

3. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS
inverter.
(b) What are the effects of scaling on Vt ?
(c) What are design rules? Why is metal- metal spacing larger than poly -poly
spacing. [8+4+4]

4. Describe three sources of wiring capacitances. Explain the effect of wiring capaci-
tance on the performance of a VLSI circuit. [16]

5. Draw the logic diagram for a ripple-carry binary counter using T registers and ex-
plain its operation with the help of truth table and also compare it with synchronous
counters. Draw the schematic for T register. [16]

6. (a) Compare the Antifuse and Vialink programmable interconnections for PAL
devices.
(b) What are different typically available SSI Standard-cell types and compare
them. [8+8]

7. (a) Write a VHDL Program for a divide-by-3 counter with suitable state diagram.
(b) Compare all available design verification tools. [8+8]

8. (a) Explain how the cost of chip can effect with the testing levels,
(b) Explain how observability is used to test the output of a gate within a larger
circuit.
(c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5]

?????

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