94201.lecture9 12 Processor

Processor p-86 Register Set
§ Processor characterized by 16-Bit General Purpose Registers

• register set (state variables) • can access 16-bits, high (H) byte, low (L) byte
• instruction set
• includes addressing modes AX AH AL
• interrupt mechanism (not here à 94.203)
• will study p-86 processor BX BH BL
• simplified subset of Intel 80x86 family CX CH CL
• no segments – see the “ real thing ” in 94.203
DX DH DL
8 bits 8 bits
01 Oct-01 94.201 - Fall 2001: copyright ©T. Pearce, D. Hutchinson, L. Marshall Sept. 2001 1 01 Oct-01 94.201 - Fall 2001: copyright ©T. Pearce, D. Hutchinson, L. Marshall Sept. 2001 2
94201.lecture9 -12-processor 94201.lecture9 -12-processor
P-86 Register Set (contd) P-86 Register Set (contd)
16-Bit Addressing Registers (no 8-bit access) FLAGS Register (status flags – one bit/flag)
IP Instruction Pointer • 16-bit reg, but only 4 bits have meaning
SP Stack Pointer • treat as individual bits, not 16-bit value
BP Base Pointer • ignore unused bits
– CF Carry Flag
SI Source Index
– SF Sign Flag data
DI Destination Index – OF Overflow Flag manipulation
– IF Interrupt Flag & conditional
control flow
P-86 Register Set (contd) P-86 Execution Cycle
Other Registers in Programmer’s Model Processor executes instructions by repeating:

• support the execution of instructions do {
• cannot be accessed directly by programmers IR := mem[ IP ] & adjust IP to point to next
• often larger than 16-bits sequential instruction
• temporary reg’s (scratchpad values)
Execute instruction in IR
IR Instruction Register
} until HLT instruction has been executed
1
P-86 Execution Cycle (contd) P86 Instruction Cycle (contd)
§ IP contains address of next instruction to execute Before Fetch: Memory

0000
§ IR holds instruction in processor Processor
§ instruction fetch from memory 4B 3C08 3 bytes of
36 3C09
§ load 1st byte; from encoding: decide how many FF 3C0A
3C0B
instruction
4 bytes
more are needed (may need 2nd byte too!) IP 3C08 of next
§ IP is adjusted as bytes are loaded IR 07 43 A6 12

3C0E instruction
FFFF
P86 Instruction Cycle (contd) Instruction Operations, Operands
After Fetch: 0000

operation: how to use state variable values
Processor operands : which state variables to use
4B 3C08 3 bytes of
36 3C09 e.g. C=A+B
FF 3C0A instruction
3C0B 4 bytes operations: addition (+) and assignment (=)
IP 3C0B of next operands: state variables A, B & C
3C0E instruction
IR 4B 36 FF source operands: provide values to use (inputs)
C = A + B; A= A + A
destination operands: receive results (outputs)
FFFF
C = A + B; A = A + A
Instruction Operations, Operands (contd) Instruction Categories

§ human-oriented mnemonics for operations e.g.: § data transfer: copies data among state
• MOV (move)
variables
• SUB (subtract)
• do not modify FLAGS
• JMP (jump)
§ addressing modes: ways to specify operands § data manipulation: modify state variable
• simple modes: register, immediate, direct values – including FLAGS
• more powerful: indirect § control-flow: determine “next” instruction
§ instruction encoding includes both operation and to execute – allow non-sequential execution
operand information
2
Data Transfer Example Register Addressing Mode
MOV (Move) Instruction § allows a register to be an operand

• as source: copy register value
syntax: MOV dest , src
• as destination: write value to register
semantics: dest := src e.g. MOV AX, DX ; value in DX is copied to AX
§ copy src value to dest state variable à AX := DX
§ register addressing mode for both dest and src
§ register and memory operands only (I/O ??)
§ dest and src must be compatible (same size)
• MOV AH, CL ; This is OK
• MOV AL, CX ; This is not OK
Immediate Addressing Mode Direct Addressing Mode

§ allows constant to be specified as source § specify the address of a memory operand
• specify address as a constant value
• source value assembled into the instruction
• loaded into IR as part of instruction • address gets encoded as part of instruction
• must be known when program is assembled !
• value obtained from IR as instruction executed
e.g. MOV AL, 5 ; AL is 8 bit dest § potential ambiguity? MOV AX, 3FC0H
• instruction encoding includes 8 -bit value 05h • is 3FC0H an immediate constant or address?
• need syntax to clarify intention!
§ what about: MOV AX, 5
• use square brackets “[” and “]”
• 16-bit dest: encoding includes 16-bit value 0005h
§ what about MOV 4, BH ;lets be ridiculous § [A] means A is the address of the operand
• dest as immediate value ? MOV AX, 3FC0H ;AX := 3FC0H
MOV AX, [ 3FC0H ] ;AX:= contents of cell 3FC0H
Indirect Addressing Mode Indirect Addressing Mode (contd)
§ simple form : use current contents of a register as § potential ambiguity?

the address of an operand more complex MOV CX, [ BX ] v.s. MOV CX, BX
• only these registers can be used: forms later! • register, immediate and direct are static modes
• for memory operands: BX, BP, SI, DI • operand bound to instruction at assemble-time
• for I/O operands: DX • indirect is a dynamic mode
e.g. MOV CX, [ BX ] • operand bound to instruction at run-time
• contents of BX are used as the memory address of • depends on values at time instruction executed
value (16-bit, little endian) to load into CX • more powerful! J more complicated! L
• only makes any sense if earlier instruction(s) put a
useful address into BX!
3
Manipulating I/O Ports I/O Port Example
§ MOV allows only register and memory § For now: OUT [DX], AL
operands • the 8 -bit value in AL is written to the I/O port
addressed by the contents of DX (indirect mode!)
§ so . . . what accesses I/O ports? § Display character at the “current” cursor position:
• IN read a value from a port
• write 7-bit ASCII encoded char to port 04E9H
• OUT write a value to a port
• must set up DX to point to I/O port
§ IN / OUT: always use AL (or AX) and [DX] • must set up AL to contain char
• write: display char and “ advance” cursor
comments start with “ ; ”

I/O Example (contd) Assembler Program
label definition
§ MOV DX, 04E9H ; set display port address § ; simple program that displays 'Hi'
§ MOV AL, 30H ; char = ‘0’ § start:
§ mov dx, 04E9H ; get display port address
§ OUT [DX], AL ; put char on display
§ mov al, 'H' ; display 'H'
(whew!)
§ out [dx], al
§ Enough for a simple program? § ;
MOV and OUT § mov al, 'i' ; display 'i'
§ out [dx], al
§ hlt ; STOP!
§ end start Where pgm starts
Assembler Program Operand Compatibility
§ above is “source” code – human-oriented § operands must have compatible sizes

§ must be converted to binary values for § if register mode is used, then no ambiguity
loading into memory à operand size = register size
§ But no register operands à potential ambiguity!
§ ASSEMBLER is a program that encodes /
translates this sort of repr. of a program into § Consider:
16-bit operand
the internal repr. required to run it. MOV AX, 1 no ambiguity!
MOV [ BX ], 1
§ CROSS ASSEMBLERS translate into 8-bit or 16 -bit moves?
MOV [1234H], 0
internal repr. for different machines default?
4
Operand Compatibility (contd) Data Manipulation Instructions
§ need syntax to remove ambiguity § use state variable values to compute new values
§ qualify off-processor access using: § modify state variables to hold results (incl FLAGS)
WORD PTR word pointer – 16-bit operand ADD dest, src
BYTE PTR byte pointer – 8-bit operand à dest := dest + src (bitwise add)
e.g. no ambiguity with: § dest is both a source and destination operand
MOV BYTE PTR [ BX ], 1 ;8 bit dest § also modifies FLAGS as part of instruction execution:
§ ZF := 1 if-and-only-if (iff) result = 0
MOV WORD PTR [1234H], 0 ;16 bit dest
§ SF := 1 iff msbit of result = 1 (sign = negative)
§ CF := 1 iff carry out of msbit
§ OF := 1 iff result overflowed signed capacity
Data Manipulation Example More Data Manipulation Instructions
§ Suppose that AH contains 73H, when SUB dest, src (Subtract)

IP à ADD AH, 40H à dest := dest – src
results: AH := 0B3H • like ADD, but bitwise subtract
ZF := 0 result ≠ 0 • modifies flags as in ADD, except:
SF := 1 result is negative (signed) CF := 1 iff borrow into msbit
CF := 0 (no carry out of msbit)
OF := 1 +ve + +ve = −ve
CMPdest, src (Compare)
• like SUB, except dest is not modified
• modifies FLAGS ONLY !
More Data Manipulation Instructions More Data Manipulation Instructions

16-bit dividend
DIV src (Unsigned Integer Divide) DIV src 8-bit divisor (src)
where src may be specified using:
• register, direct or indirect mode, NOT immediate § for 8-bit src: divide src into 16-bit value in AX
mode! • two 8-bit results
• size of divisor (8-bit or 16-bit) is determined by size • AL := AX ÷ src (unsigned divide)
of src • AH := AX mod src ( unsigned modulus)
• if direct or indirect used for src, must clarify size § flags are undefined after DIV (values may have
using BYTE PTR or WORD PTR changed, no meaning)
e.g. DIV WORD PTR [BX ]
5
More Data Manipulation Instructions Control Flow Instructions
32-bit dividend See Instruction Reference (posted) for more complete list
DIV src 16-bit divisor (src)
§ for 16-bit src: of instructions – includes effects on FLAGS !!
• divide src into 32-bit value obtained by concatenating § execution may change value in IP
DX and AX (written DX:AX) § changes address for fetch of next instruction
• AX := DX:AX ÷ src (unsigned divide)
• DX := DX:AX mod src (unsigned modulus)
• flags are undefined after DIV
§ what if result is too big to fit in destination?

e.g. AX ÷ 1 ?? AL = ?? overflow trap – more later!
§ in assignment 2: use 16-bit source form. Why?
High Level Language Example JMP Instruction
§ Why is C++ called a structured language? JMP target (Unconditional JUMP)

e.g.: C++ control flow May use data manipulation à IP := IP + target
if ( condition ) to decide condition § control is always transferred to the specified target
{ block T: do this if condition true; } § target operand is assembled as an immediate, 16-bit,
else { block F: do this if condition false;} signed value
next_statement; Need control flow instructions to ‘skip’ § relative offset (in bytes) from the end of the JMP
instruction to the start of the next instruction to be fetched
§ if condition is true à continue sequentially into block T, at end
of block T, must skip to next_statement • 16-bit signed value
§ if condition false à skip past block T to block F, then continue • +ve allows JMP forward (to higher address)
sequentially through block F and on to next_statement • –ve allows jump backwards (to lower address) e.g.
loop back
Execution of JMP Conditional Jumps

§ specify condition in terms of FLAG values
Address Contents 16-bit relative offset
e.g. JZ JumpZero
0034H 0E9H à if ZF==1: then jump to JumpZero else continue
0035H 10H JMP 0010H § e.g.: looping example

MOV CX,5 ;loop 5 times
0036H 00H DoLoop:
start of fetch : IP = 0034H IR = ???????? . . . label: identifies an address
after fetch : IP = 0037H IR = E9 0010 SUB CX, 1
after execute : IP = 0047H IR = E9 0010 JNZ DoLoop
§ many possible conditions - see Instruction Reference
6
Conditional Jumps (contd) Conditional Jumps (contd)
CMP dest, src (Compare)
§ often condition and “not” condition are valid instr § performs dest – src and sets FLAGS
§ e.g. JZ dest (Jump Zero) § often useful to think of combination as:
JNZ dest (Jump Not Zero) CMP dest, src
JC dest (Jump Carry) Jxx jmpdest
• more too! (Instruction Reference!) § jump is taken if “ dest xx src” condition holds
§ Conditional Jump often follows CMP § Some conditions for xx:
CMP AL, 10 § JE Jump Equal (opposite is JNE)
JL LessThanTen § JL Jump Less Than (JNL)
. . . ; some code here § JLE Jump Less Than or Equal (JNLE)
LessThanTen: § JG Jump Greater Than
§ processor provides FLAGS to reflect results of Suppose AX contains 7FFFH:

(binary) manipulation under both signed and Scenario 1 Scenario 2
unsigned interpretations
CMP AX, 8000H CMP AX, 8000H
§ instructions for different interpretations! JA Bigger JG Bigger
Unsigned Signed
§ In each scenario, is the jump taken? Why?
JA Above JG Greater
JAE Above or Equal JGE Greater or Equal
§ Programmer MUST know how binary values are
JB Below JL Less
to be interpreted! (e.g. value in AX above)
JBE Below or Equal JLE Less or Equal
§ (instructions for Not conditions too!)
§ Conditional jump limitation: uses 8-bit signed § One possible workaround if distance is
relative offset! 8 bits, ‘sign extended to greater than 127 bytes (but not the only
16 bits’
IP := IP + offset one!):
§ can’t jump very far! – 128 ßà +127 bytes JNL Continue 16-bit relative offset
§ example: JL Less JMP Less
some code maximum possible Continue: lots of distance >> 127 bytes
here distance = 127 bytes code here
Less: Less:
MOV . . . MOV . . .

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Processor p-86 Register Set

§ Processor characterized by 16-Bit General Purpose Registers

P-86 Register Set (contd) P-86 Register Set (contd)

P-86 Register Set (contd) P-86 Execution Cycle

Other Registers in Programmer’s Model Processor executes instructions by repeating:

§ IP contains address of next instruction to execute Before Fetch: Memory

§ IP is adjusted as bytes are loaded IR 07 43 A6 12

P86 Instruction Cycle (contd) Instruction Operations, Operands

After Fetch: 0000

Instruction Operations, Operands (contd) Instruction Categories

MOV (Move) Instruction § allows a register to be an operand

Immediate Addressing Mode Direct Addressing Mode

Indirect Addressing Mode Indirect Addressing Mode (contd)

§ simple form : use current contents of a register as § potential ambiguity?

comments start with “ ; ”

Assembler Program Operand Compatibility

§ above is “source” code – human-oriented § operands must have compatible sizes

Data Manipulation Example More Data Manipulation Instructions

§ Suppose that AH contains 73H, when SUB dest, src (Subtract)

More Data Manipulation Instructions More Data Manipulation Instructions

§ what if result is too big to fit in destination?

High Level Language Example JMP Instruction

§ Why is C++ called a structured language? JMP target (Unconditional JUMP)

Execution of JMP Conditional Jumps

0035H 10H JMP 0010H § e.g.: looping example

Conditional Jumps (contd) Conditional Jumps (contd)

§ processor provides FLAGS to reflect results of Suppose AX contains 7FFFH:

Conditional Jumps (contd) Conditional Jumps (contd)

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