Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
R E L I O N ® 670 SERIES
The software and hardware described in this document is furnished under a license
and may be used or disclosed only in accordance with the terms of such license.
This product includes software developed by the OpenSSL Project for use in the
OpenSSL Toolkit. (http://www.openssl.org/) This product includes cryptographic
software written/developed by: Eric Young (eay@cryptsoft.com) and Tim Hudson
(tjh@cryptsoft.com).
Trademarks
ABB and Relion are registered trademarks of the ABB Group. All other brand or
product names mentioned in this document may be trademarks or registered
trademarks of their respective holders.
Warranty
Please inquire about the terms of warranty from your nearest ABB representative.
Disclaimer
The data, examples and diagrams in this manual are included solely for the concept
or product description and are not to be deemed as a statement of guaranteed
properties. All persons responsible for applying the equipment addressed in this
manual must satisfy themselves that each intended application is suitable and
acceptable, including that any applicable safety or other operational requirements
are complied with. In particular, any risks in applications where a system failure
and/or product failure would create a risk for harm to property or persons
(including but not limited to personal injuries or death) shall be the sole
responsibility of the person or entity applying the equipment, and those so
responsible are hereby requested to ensure that all measures are taken to exclude or
mitigate such risks.
This document has been carefully checked by ABB but deviations cannot be
completely ruled out. In case any errors are detected, the reader is kindly requested
to notify the manufacturer. Other than under explicit contractual commitments, in
no event shall ABB be responsible or liable for any loss or damage resulting from
the use of this manual or the application of the equipment.
Conformity
This product complies with the directive of the Council of the European
Communities on the approximation of the laws of the Member States relating to
electromagnetic compatibility (EMC Directive 2004/108/EC) and concerning
electrical equipment for use within specified voltage limits (Low-voltage directive
2006/95/EC). This conformity is the result of tests conducted by ABB in
accordance with the product standard EN 60255-26 for the EMC directive, and
with the product standards EN 60255-1 and EN 60255-27 for the low voltage
directive. The product is designed in accordance with the international standards of
the IEC 60255 series.
Table of contents
Table of contents
Section 1 Introduction.....................................................................47
This manual...................................................................................... 47
Presumptions for Technical Data................................................ 47
Intended audience............................................................................ 48
Product documentation.....................................................................48
Product documentation set..........................................................48
Document revision history........................................................... 50
Related documents......................................................................50
Document symbols and conventions................................................51
Symbols.......................................................................................51
Document conventions................................................................ 52
IEC 61850 edition 1 / edition 2 mapping...........................................52
Settings........................................................................................95
Local HMI signals............................................................................. 95
Identification................................................................................ 95
Function block............................................................................. 96
Signals.........................................................................................96
Basic part for LED indication module............................................... 97
Identification................................................................................ 97
Function block............................................................................. 97
Signals.........................................................................................97
Settings........................................................................................98
LCD part for HMI function keys control module................................99
Identification................................................................................ 99
Function block............................................................................. 99
Signals.........................................................................................99
Settings........................................................................................99
Operation principle......................................................................... 101
Local HMI.................................................................................. 101
Keypad................................................................................. 102
Display..................................................................................104
LEDs.....................................................................................107
LED configuration alternatives...................................................109
Functionality ........................................................................ 109
Status LEDs......................................................................... 109
Indication LEDs.................................................................... 109
Function keys............................................................................ 118
Functionality ........................................................................ 118
Operation principle............................................................... 118
Monitored data...........................................................................149
Operation principle.................................................................... 153
Frequency reporting............................................................. 154
Reporting filters.................................................................... 156
Scaling Factors for ANALOGREPORT channels................. 157
Technical data........................................................................... 159
Settings......................................................................................435
Monitored data...........................................................................442
Operation principle.................................................................... 444
Filtering.................................................................................444
Distance measuring zones................................................... 444
Phase-selection element...................................................... 445
Directional criteria.................................................................446
Fuse failure...........................................................................447
Power swings....................................................................... 447
Measurement principles....................................................... 447
Load encroachment..............................................................459
Simplified logic schemes...................................................... 460
Measurement....................................................................... 466
Technical data........................................................................... 471
Power swing detection ZMRPSB ...................................................472
Identification.............................................................................. 472
Functionality.............................................................................. 472
Function block........................................................................... 472
Signals.......................................................................................472
Settings......................................................................................473
Operation principle.................................................................... 474
Resistive reach in forward direction..................................... 475
Resistive reach in reverse direction..................................... 476
Reactive reach in forward and reverse direction.................. 477
Basic detection logic.............................................................477
Operating and inhibit conditions........................................... 479
Technical data........................................................................... 480
Automatic switch onto fault logic ZCVPSOF ................................. 480
Identification.............................................................................. 480
Functionality.............................................................................. 481
Function block........................................................................... 481
Signals.......................................................................................481
Settings......................................................................................482
Monitored data...........................................................................482
Operation principle.................................................................... 483
Technical data........................................................................... 484
Power swing logic PSLPSCH ........................................................ 484
Identification.............................................................................. 485
Functionality.............................................................................. 485
Function block........................................................................... 485
Signals.......................................................................................485
Settings......................................................................................486
Operation principle.................................................................... 487
Signals.......................................................................................561
Settings......................................................................................562
Monitored data...........................................................................562
Operation principle.................................................................... 562
Technical data........................................................................... 563
Directional residual overcurrent protection, four steps EF4PTOC .564
Identification.............................................................................. 564
Functionality.............................................................................. 564
Function block........................................................................... 565
Signals.......................................................................................565
Settings......................................................................................566
Monitored data...........................................................................572
Operation principle.................................................................... 573
Operating quantity within the function.................................. 573
Internal polarizing................................................................. 574
External polarizing for earth-fault function............................576
Directional detection for earth fault function......................... 576
Base quantities within the protection....................................576
Internal earth-fault protection structure................................ 577
Four residual overcurrent steps............................................577
Directional supervision element with integrated
directional comparison function............................................578
Second harmonic blocking element..................................... 581
Switch on to fault feature......................................................583
Technical data........................................................................... 585
Four step directional negative phase sequence overcurrent
protection NS4PTOC .....................................................................586
Identification.............................................................................. 586
Functionality.............................................................................. 586
Function block........................................................................... 587
Signals.......................................................................................587
Settings......................................................................................588
Monitored data...........................................................................593
Operation principle.................................................................... 593
Operating quantity within the function.................................. 593
Internal polarizing facility of the function.............................. 594
External polarizing for negative sequence function..............595
Internal negative sequence protection structure.................. 595
Four negative sequence overcurrent stages........................ 595
Directional supervision element with integrated
directional comparison function............................................596
Technical data........................................................................... 599
Sensitive directional residual overcurrent and power protection
SDEPSDE ..................................................................................... 599
Identification.............................................................................. 600
Functionality.............................................................................. 600
Function block........................................................................... 602
Signals.......................................................................................602
Settings......................................................................................603
Monitored data...........................................................................605
Operation principle.................................................................... 605
Function inputs..................................................................... 605
Technical data........................................................................... 612
Thermal overload protection, one time constant, Celsius/
Fahrenheit LCPTTR/LFPTTR.........................................................613
Identification.............................................................................. 613
Functionality.............................................................................. 614
Function block........................................................................... 614
Signals.......................................................................................614
Settings......................................................................................616
Monitored data...........................................................................617
Operation principle.................................................................... 618
Technical data........................................................................... 621
Thermal overload protection, two time constants TRPTTR ........... 621
Identification.............................................................................. 621
Functionality.............................................................................. 621
Function block........................................................................... 622
Signals.......................................................................................622
Settings......................................................................................623
Monitored data...........................................................................624
Operation principle.................................................................... 624
Technical data........................................................................... 628
Breaker failure protection CCRBRF............................................... 628
Identification.............................................................................. 628
Functionality.............................................................................. 628
Function block........................................................................... 629
Signals.......................................................................................629
Settings......................................................................................630
Monitored data...........................................................................631
Operation principle.................................................................... 631
Technical data........................................................................... 634
Stub protection STBPTOC ............................................................ 635
Identification.............................................................................. 635
Functionality.............................................................................. 635
Function block........................................................................... 635
Signals.......................................................................................636
Settings......................................................................................636
Monitored data...........................................................................637
Operation principle.................................................................... 637
Technical data........................................................................... 638
Pole discordance protection CCPDSC........................................... 638
Identification.............................................................................. 638
Functionality.............................................................................. 638
Function block........................................................................... 639
Signals.......................................................................................639
Settings......................................................................................640
Monitored data...........................................................................640
Operation principle.................................................................... 640
Pole discordance signaling from circuit breaker...................643
Unsymmetrical current detection..........................................643
Technical data........................................................................... 644
Directional underpower protection GUPPDUP............................... 644
Identification.............................................................................. 644
Functionality.............................................................................. 644
Function block........................................................................... 645
Signals.......................................................................................645
Settings......................................................................................646
Monitored data...........................................................................648
Operation principle.................................................................... 648
Low pass filtering..................................................................650
Calibration of analog inputs..................................................650
Technical data........................................................................... 651
Directional overpower protection GOPPDOP ................................652
Identification.............................................................................. 652
Functionality.............................................................................. 652
Function block........................................................................... 653
Signals.......................................................................................653
Settings......................................................................................654
Monitored data...........................................................................656
Operation principle.................................................................... 656
Low pass filtering..................................................................658
Calibration of analog inputs..................................................658
Technical data........................................................................... 659
Broken conductor check BRCPTOC ............................................. 660
Identification.............................................................................. 660
Functionality.............................................................................. 660
Function block........................................................................... 660
Signals.......................................................................................660
Settings......................................................................................661
Monitored data...........................................................................661
Functionality.............................................................................. 729
Function block........................................................................... 729
Signals.......................................................................................730
Settings......................................................................................730
Monitored data...........................................................................731
Operation principle.................................................................... 731
Measured voltage.................................................................734
Operate time of the overexcitation protection.......................735
Cooling................................................................................. 738
Overexcitation protection function measurands................... 738
Overexcitation alarm............................................................ 739
Logic diagram.......................................................................740
Technical data........................................................................... 740
Voltage differential protection VDCPTOV ......................................741
Identification.............................................................................. 741
Functionality.............................................................................. 741
Function block........................................................................... 741
Signals.......................................................................................741
Settings......................................................................................742
Monitored data...........................................................................743
Operation principle.................................................................... 743
Technical data........................................................................... 744
Loss of voltage check LOVPTUV .................................................. 745
Identification.............................................................................. 745
Functionality.............................................................................. 745
Function block........................................................................... 745
Signals.......................................................................................745
Settings......................................................................................746
Operation principle.................................................................... 746
Technical data........................................................................... 748
Section 15 Control..........................................................................823
Signals..................................................................................861
Interlocking for 1 1/2 CB BH ..................................................... 864
Identification......................................................................... 864
Functionality......................................................................... 864
Function blocks.................................................................... 865
Logic diagrams..................................................................... 867
Signals..................................................................................872
Interlocking for double CB bay DB ........................................... 876
Identification......................................................................... 876
Functionality......................................................................... 876
Logic diagrams..................................................................... 878
Function block...................................................................... 881
Signals..................................................................................883
Interlocking for line bay ABC_LINE .......................................... 886
Identification......................................................................... 886
Functionality......................................................................... 886
Function block...................................................................... 887
Logic diagram.......................................................................888
Signals..................................................................................893
Interlocking for transformer bay AB_TRAFO ............................ 895
Identification......................................................................... 895
Functionality......................................................................... 896
Function block...................................................................... 897
Logic diagram.......................................................................898
Signals..................................................................................899
Position evaluation POS_EVAL.................................................901
Identification......................................................................... 901
Functionality......................................................................... 901
Function block...................................................................... 901
Logic diagram.......................................................................902
Signals..................................................................................902
Apparatus control APC................................................................... 902
Functionality.............................................................................. 902
Operation principle.................................................................... 903
Error handling............................................................................ 904
Bay control QCBAY................................................................... 908
Functionality......................................................................... 908
Function block...................................................................... 908
Signals..................................................................................908
Settings................................................................................ 909
Operation principle............................................................... 909
Local/Remote switch LOCREM................................................. 911
Function block...................................................................... 911
Signals..................................................................................912
Settings................................................................................ 913
Operation principle............................................................... 913
Switch controller SCSWI........................................................... 914
Functionality ........................................................................ 915
Function block...................................................................... 915
Signals..................................................................................915
Settings................................................................................ 917
Operation principle............................................................... 917
Interaction with switch on process bus.................................924
Circuit breaker SXCBR..............................................................925
Functionality ........................................................................ 925
Function block...................................................................... 926
Signals..................................................................................926
Settings................................................................................ 927
Operation principle............................................................... 927
Circuit switch SXSWI.................................................................932
Functionality ........................................................................ 932
Function block...................................................................... 932
Signals..................................................................................932
Settings................................................................................ 933
Operation principle............................................................... 934
Proxy for signals from switching device via GOOSE
XLNPROXY .............................................................................. 938
Functionality......................................................................... 938
Function block...................................................................... 938
Signals..................................................................................938
Settings................................................................................ 940
Operation principle............................................................... 940
Position supervision............................................................. 940
Command response evaluation............................................940
Bay reserve QCRSV..................................................................942
Functionality......................................................................... 942
Function block...................................................................... 943
Signals..................................................................................943
Settings................................................................................ 944
Operation principle............................................................... 944
Reservation input RESIN...........................................................946
Functionality......................................................................... 947
Function block...................................................................... 947
Signals..................................................................................947
Settings................................................................................ 948
Operation principle............................................................... 949
Voltage control................................................................................950
Identification.............................................................................. 950
Functionality.............................................................................. 951
Automatic voltage control for tap changer TR1ATCC and
TR8ATCC ................................................................................. 951
Operation principle............................................................... 951
Tap changer control and supervision, 6 binary inputs
TCMYLTC and TCLYLTC .........................................................962
Operation principle............................................................... 962
Connection between TR1ATCC or TR8ATCC and
TCMYLTCor TCLYLTC............................................................. 966
Function block........................................................................... 970
Signals.......................................................................................973
Settings......................................................................................980
Monitored data...........................................................................988
Operation principle.................................................................... 990
Technical data........................................................................... 991
Logic rotating switch for function selection and LHMI
presentation SLGAPC.................................................................... 992
Identification.............................................................................. 992
Functionality.............................................................................. 992
Function block........................................................................... 993
Signals.......................................................................................993
Settings......................................................................................994
Monitored data...........................................................................995
Operation principle.................................................................... 995
Graphical display..................................................................995
Selector mini switch VSGAPC........................................................996
Identification.............................................................................. 997
Functionality.............................................................................. 997
Function block........................................................................... 997
Signals.......................................................................................997
Settings......................................................................................998
Operation principle.................................................................... 998
Generic communication function for Double Point indication
DPGAPC........................................................................................ 999
Identification.............................................................................. 999
Functionality.............................................................................. 999
Function block........................................................................... 999
Signals.....................................................................................1000
Settings....................................................................................1000
Operation principle.................................................................. 1000
Single point generic control 8 signals SPC8GAPC...................... 1001
Identification............................................................................ 1001
Functionality............................................................................ 1001
Function block......................................................................... 1001
Signals.....................................................................................1002
Settings....................................................................................1002
Operation principle.................................................................. 1003
AutomationBits, command function for DNP3.0 AUTOBITS........ 1003
Identification............................................................................ 1003
Functionality............................................................................ 1003
Function block......................................................................... 1004
Signals.....................................................................................1004
Settings....................................................................................1005
Operation principle.................................................................. 1006
Single command, 16 signals SINGLECMD.................................. 1006
Identification............................................................................ 1006
Functionality............................................................................ 1006
Function block......................................................................... 1007
Signals.....................................................................................1007
Settings....................................................................................1008
Operation principle.................................................................. 1008
Identification............................................................................ 1040
Functionality............................................................................ 1041
Function block......................................................................... 1041
Signals.....................................................................................1042
Settings....................................................................................1042
Operation principle.................................................................. 1043
Directional comparison logic function.................................1043
Fault current reversal logic................................................. 1043
Weak-end infeed logic........................................................1044
Technical data......................................................................... 1046
Section 17 Logic...........................................................................1047
Tripping logic SMPPTRC .............................................................1047
Identification............................................................................ 1047
Functionality............................................................................ 1047
Function block......................................................................... 1048
Signals.....................................................................................1048
Settings....................................................................................1049
Operation principle.................................................................. 1050
Logic diagram.....................................................................1054
Technical data......................................................................... 1056
General start matrix block SMAGAPC..........................................1057
Identification............................................................................ 1057
Functionality............................................................................ 1057
Function block......................................................................... 1057
Signals.....................................................................................1057
Settings....................................................................................1058
Operation principle.................................................................. 1058
Trip matrix logic TMAGAPC......................................................... 1064
Identification............................................................................ 1064
Functionality............................................................................ 1064
Function block......................................................................... 1065
Signals.....................................................................................1065
Settings....................................................................................1067
Operation principle.................................................................. 1067
Technical data......................................................................... 1068
Logic for group alarm ALMCALH..................................................1068
Identification............................................................................ 1068
Functionality............................................................................ 1069
Function block......................................................................... 1069
Signals.....................................................................................1069
Settings....................................................................................1070
Operation principle.................................................................. 1070
Technical data......................................................................... 1070
Signals................................................................................1095
Technical data.................................................................... 1095
Pulse timer function block PULSETIMERQT...........................1095
Function block.................................................................... 1096
Signals................................................................................1096
Settings.............................................................................. 1096
Technical data.................................................................... 1097
Reset/Set function block RSMEMORYQT...............................1097
Function block.................................................................... 1097
Signals................................................................................1097
Settings.............................................................................. 1098
Technical data.................................................................... 1098
Set/Reset function block SRMEMORYQT...............................1098
Function block.................................................................... 1099
Signals................................................................................1099
Settings.............................................................................. 1099
Technical data.................................................................... 1099
Settable timer function block TIMERSETQT........................... 1099
Function block.................................................................... 1100
Signals................................................................................1100
Settings.............................................................................. 1100
Technical data.................................................................... 1100
Exclusive OR function block XORQT...................................... 1101
Function block.................................................................... 1101
Signals................................................................................1101
Technical data.................................................................... 1102
Extension logic package...............................................................1102
Fixed signals FXDSIGN................................................................1103
Identification............................................................................ 1103
Functionality............................................................................ 1103
Function block......................................................................... 1103
Signals.....................................................................................1103
Settings....................................................................................1104
Operation principle.................................................................. 1104
Boolean 16 to Integer conversion B16I........................................ 1104
Identification............................................................................ 1104
Functionality............................................................................ 1104
Function block......................................................................... 1105
Signals.....................................................................................1105
Monitored data.........................................................................1106
Settings....................................................................................1106
Operation principle.................................................................. 1106
Technical data......................................................................... 1107
Monitored data.........................................................................1122
Operation principle.................................................................. 1122
Technical data......................................................................... 1123
Comparator for real inputs REALCOMP.......................................1123
Identification............................................................................ 1123
Functionality............................................................................ 1123
Function block......................................................................... 1123
Signals.....................................................................................1124
Settings....................................................................................1124
Operation principle.................................................................. 1124
Technical data......................................................................... 1126
Section 18 Monitoring...................................................................1127
Measurements..............................................................................1127
Identification............................................................................ 1127
Functionality............................................................................ 1127
Function block......................................................................... 1129
Signals.....................................................................................1131
Settings....................................................................................1134
Monitored data.........................................................................1146
Operation principle.................................................................. 1148
Measurement supervision.................................................. 1148
Measurements CVMMXN...................................................1154
Phase current measurement CMMXU............................... 1159
Phase-phase and phase-neutral voltage measurements
VMMXU, VNMMXU............................................................ 1160
Voltage and current sequence measurements VMSQI,
CMSQI................................................................................1160
Technical data......................................................................... 1160
Gas medium supervision SSIMG................................................. 1162
Identification............................................................................ 1162
Functionality............................................................................ 1162
Function block......................................................................... 1163
Signals.....................................................................................1163
Settings....................................................................................1164
Monitored data.........................................................................1164
Operation principle.................................................................. 1164
Technical data......................................................................... 1165
Liquid medium supervision SSIML............................................... 1166
Identification............................................................................ 1166
Functionality............................................................................ 1166
Function block......................................................................... 1166
Signals.....................................................................................1166
Settings....................................................................................1167
Monitored data.........................................................................1168
Operation principle.................................................................. 1168
Technical data......................................................................... 1169
Breaker monitoring SSCBR..........................................................1169
Identification............................................................................ 1169
Functionality............................................................................ 1170
Function block......................................................................... 1170
Signals.....................................................................................1170
Settings....................................................................................1171
Monitored data.........................................................................1173
Operation principle.................................................................. 1173
Circuit breaker contact travel time......................................1175
Circuit breaker status......................................................... 1176
Remaining life of circuit breaker......................................... 1177
Accumulated energy...........................................................1178
Circuit breaker operation cycles......................................... 1179
Circuit breaker operation monitoring.................................. 1180
Circuit breaker spring charge monitoring........................... 1181
Circuit breaker gas pressure indication.............................. 1182
Technical data......................................................................... 1182
Event function EVENT..................................................................1183
Identification............................................................................ 1183
Functionality............................................................................ 1183
Function block......................................................................... 1184
Signals.....................................................................................1184
Settings....................................................................................1185
Operation principle.................................................................. 1187
Disturbance report DRPRDRE..................................................... 1188
Identification............................................................................ 1188
Functionality............................................................................ 1188
Function block......................................................................... 1189
Signals.....................................................................................1191
Settings....................................................................................1193
Monitored data.........................................................................1203
Operation principle.................................................................. 1207
Technical data......................................................................... 1215
Logical signal status report BINSTATREP................................... 1216
Identification............................................................................ 1216
Functionality............................................................................ 1216
Function block......................................................................... 1216
Signals.....................................................................................1217
Settings....................................................................................1218
Operation principle.................................................................. 1218
Functionality............................................................................ 1237
Function block......................................................................... 1238
Signals.....................................................................................1239
Settings....................................................................................1239
Monitored data.........................................................................1243
Operation principle.................................................................. 1243
Hot spot temperature calculation........................................1244
Top oil temperature calculation.......................................... 1246
Transformer parameters selection..................................... 1247
Calculation of constants and losses................................... 1248
Load factor calculation....................................................... 1250
Function handling with less CT’s........................................1250
Temperature unit selection.................................................1251
Insulation loss of life calculation......................................... 1251
Warning and alarm............................................................. 1252
Blocking the function.......................................................... 1253
Technical data......................................................................... 1254
Section 20 Ethernet......................................................................1269
Access point................................................................................. 1269
Introduction..............................................................................1269
Settings....................................................................................1269
Access point diagnostics.............................................................. 1271
Functionality............................................................................ 1271
Function block......................................................................... 1272
Signals.....................................................................................1272
Monitored data.........................................................................1273
Redundant communication...........................................................1273
Identification............................................................................ 1273
Functionality............................................................................ 1274
Operation principle.................................................................. 1274
Merging unit..................................................................................1276
Introduction..............................................................................1276
Settings....................................................................................1277
Monitored data.........................................................................1277
Routes.......................................................................................... 1282
Introduction..............................................................................1282
Settings....................................................................................1283
Monitored data.........................................................................1283
Identification....................................................................... 1293
Functionality....................................................................... 1293
Function block.................................................................... 1293
Signals................................................................................1293
Settings.............................................................................. 1294
Operation principle ............................................................ 1294
GOOSE function block to receive an integer value
GOOSEINTRCV...................................................................... 1295
Identification....................................................................... 1295
Functionality....................................................................... 1295
Function block.................................................................... 1295
Signals................................................................................1296
Settings.............................................................................. 1296
Operation principle ............................................................ 1296
GOOSE function block to receive a measurand value
GOOSEMVRCV...................................................................... 1297
Identification....................................................................... 1297
Functionality....................................................................... 1297
Function block.................................................................... 1298
Signals................................................................................1298
Settings.............................................................................. 1298
Operation principle ............................................................ 1298
GOOSE function block to receive a single point value
GOOSESPRCV....................................................................... 1299
Identification....................................................................... 1299
Functionality....................................................................... 1300
Function block.................................................................... 1300
Signals................................................................................1300
Settings.............................................................................. 1300
Operation principle ............................................................ 1301
GOOSE VCTR configuration for send and receive
GOOSEVCTRCONF............................................................... 1302
Identification....................................................................... 1302
Functionality....................................................................... 1302
Settings.............................................................................. 1302
GOOSE voltage control receiving block GOOSEVCTRRCV...1303
Identification....................................................................... 1303
Functionality....................................................................... 1303
Function block.................................................................... 1303
Signals................................................................................1304
Horizontal communication via GOOSE for interlocking
GOOSEINTLKRCV..................................................................1304
Functionality....................................................................... 1304
Function block.................................................................... 1305
Signals................................................................................1305
Settings.............................................................................. 1308
Operation principle............................................................. 1308
GOOSE binary receive GOOSEBINRCV................................ 1309
Function block.................................................................... 1309
Signals................................................................................1309
Settings.............................................................................. 1311
Operation principle............................................................. 1311
GOOSE function block to receive a switching device
GOOSEXLNRCV ....................................................................1312
Identification....................................................................... 1312
Functionality....................................................................... 1312
Function block.................................................................... 1313
Signals................................................................................1313
Settings.............................................................................. 1315
Operation principle............................................................. 1315
IEC/UCA 61850-9-2LE communication protocol.......................... 1315
Introduction..............................................................................1315
Function block......................................................................... 1315
Signals.....................................................................................1316
Output signals.................................................................... 1316
Settings....................................................................................1317
Monitored data.........................................................................1317
Operation principle.................................................................. 1322
IEC 61850 quality expander QUALEXP............................. 1326
Technical data......................................................................... 1327
LON communication protocol....................................................... 1327
Functionality............................................................................ 1327
Settings....................................................................................1328
Operation principle.................................................................. 1328
Technical data......................................................................... 1347
SPA communication protocol....................................................... 1348
Functionality............................................................................ 1348
Design..................................................................................... 1348
Settings....................................................................................1348
Operation principle.................................................................. 1349
Communication ports......................................................... 1357
Technical data......................................................................... 1358
IEC 60870-5-103 communication protocol................................... 1359
Introduction..............................................................................1359
Measurands for IEC 60870-5-103 I103MEAS......................... 1359
Functionality....................................................................... 1359
Identification....................................................................... 1359
Identification....................................................................... 1370
Function block.................................................................... 1371
Signals................................................................................1371
Settings.............................................................................. 1372
Function commands for IEC 60870-5-103 I103CMD.............. 1373
Functionality....................................................................... 1373
Identification....................................................................... 1373
Function block.................................................................... 1373
Signals................................................................................1374
Settings.............................................................................. 1374
IED commands for IEC 60870-5-103 I103IEDCMD................ 1374
Functionality....................................................................... 1374
Identification....................................................................... 1374
Function block.................................................................... 1375
Signals................................................................................1375
Settings.............................................................................. 1375
Function commands user defined for IEC 60870-5-103
I103USRCMD..........................................................................1375
Functionality....................................................................... 1375
Identification....................................................................... 1376
Function block.................................................................... 1376
Signals................................................................................1376
Settings.............................................................................. 1377
Function commands generic for IEC 60870-5-103
I103GENCMD..........................................................................1377
Functionality....................................................................... 1377
Identification....................................................................... 1377
Function block.................................................................... 1378
Signals................................................................................1378
Settings.............................................................................. 1378
IED commands with position and select for IEC
60870-5-103 I103POSCMD.................................................... 1378
Functionality....................................................................... 1378
Identification....................................................................... 1379
Function block.................................................................... 1379
Signals................................................................................1379
Settings.............................................................................. 1380
IED commands with position for IEC 60870-5-103
I103POSCMDV....................................................................... 1380
Functionality....................................................................... 1380
Identification....................................................................... 1380
Function block.................................................................... 1381
Signals................................................................................1381
Settings.............................................................................. 1381
Settings....................................................................................1419
FTP access with password FTPACCS......................................... 1419
Identification............................................................................ 1419
FTP access with TLS, FTPACCS............................................1419
Settings....................................................................................1420
Authority status ATHSTAT........................................................... 1420
Identification............................................................................ 1420
Functionality............................................................................ 1420
Function block......................................................................... 1421
Signals.....................................................................................1421
Settings....................................................................................1421
Operation principle ................................................................. 1421
Self supervision with internal event list INTERRSIG.................... 1422
Functionality............................................................................ 1422
Function block......................................................................... 1422
Signals.....................................................................................1422
Settings....................................................................................1422
Operation principle.................................................................. 1422
Internal signals................................................................... 1424
Supervision of analog inputs.............................................. 1426
Technical data......................................................................... 1426
ChangeLock function CHNGLCK................................................. 1427
Functionality............................................................................ 1427
Function block......................................................................... 1427
Signals.....................................................................................1427
Operation principle ................................................................. 1427
Denial of service DOS.................................................................. 1428
Functionality ........................................................................... 1428
Operation principle.................................................................. 1428
Signals.....................................................................................1447
Settings....................................................................................1448
Operation principle.................................................................. 1448
Test mode functionality TESTMODE............................................1449
Functionality............................................................................ 1449
Function block......................................................................... 1450
Signals.....................................................................................1450
Settings....................................................................................1451
Operation principle ................................................................. 1451
IED identifiers TERMINALID........................................................ 1452
Functionality............................................................................ 1452
Settings ...................................................................................1452
Product information PRODINF..................................................... 1452
Functionality............................................................................ 1452
Settings ...................................................................................1453
Factory defined settings.......................................................... 1453
Signal matrix for binary inputs SMBI............................................ 1454
Functionality............................................................................ 1454
Function block......................................................................... 1454
Signals.....................................................................................1454
Operation principle.................................................................. 1455
Signal matrix for binary outputs SMBO ....................................... 1455
Functionality............................................................................ 1455
Function block......................................................................... 1456
Signals.....................................................................................1456
Operation principle.................................................................. 1456
Signal matrix for mA inputs SMMI................................................ 1457
Functionality............................................................................ 1457
Function block......................................................................... 1457
Signals.....................................................................................1457
Operation principle.................................................................. 1458
Signal matrix for analog inputs SMAI........................................... 1458
Functionality............................................................................ 1458
Function block......................................................................... 1458
Signals.....................................................................................1459
Settings....................................................................................1460
Operation principle ................................................................. 1462
Frequency values............................................................... 1463
Summation block 3 phase 3PHSUM............................................ 1464
Functionality............................................................................ 1464
Function block......................................................................... 1464
Signals.....................................................................................1464
Settings....................................................................................1465
Section 26 Labels.........................................................................1549
44 Transformer protection RET670 2.2 IEC
Technical manual
Table of contents
Section 1 Introduction
The technical manual contains operation principle descriptions, and lists function
blocks, logic diagrams, input and output signals, setting parameters and technical
data, sorted per function. The manual can be used as a technical reference during
the engineering phase, installation and commissioning phase, and during normal
service.
The technical data stated in this document are only valid under the following
circumstances:
Decommissioning
Commissioning
Maintenance
Engineering
Operation
Installing
Engineering manual
Installation manual
Commissioning manual
Operation manual
Application manual
Technical manual
Communication
protocol manual
Cyber security
deployment guideline
IEC07000220-4-en.vsd
IEC07000220 V4 EN-US
The engineering manual contains instructions on how to engineer the IEDs using
the various tools available within the PCM600 software. The manual provides
instructions on how to set up a PCM600 project and insert IEDs to the project
structure. The manual also recommends a sequence for the engineering of
protection and control functions, LHMI functions as well as communication
engineering for IEC 60870-5-103, IEC 61850, DNP3, LON and SPA.
The installation manual contains instructions on how to install the IED. The
manual provides procedures for mechanical and electrical installation. The chapters
are organized in the chronological order in which the IED should be installed.
The operation manual contains instructions on how to operate the IED once it has
been commissioned. The manual provides instructions for the monitoring,
controlling and setting of the IED. The manual also describes how to identify
disturbances and how to view calculated and measured power grid data to
determine the cause of a fault.
The technical manual contains operation principle descriptions, and lists function
blocks, logic diagrams, input and output signals, setting parameters and technical
data, sorted per function. The manual can be used as a technical reference during
the engineering phase, installation and commissioning phase, and during normal
service.
The point list manual describes the outlook and properties of the data points
specific to the IED. The manual should be used in conjunction with the
corresponding communication protocol manual.
The cyber security deployment guideline describes the process for handling cyber
security when communicating with the IED. Certification, Authorization with role
based access control, and product engineering for cyber security related events are
described and sorted by function. The guideline can be used as a technical
reference during the engineering phase, installation and commissioning phase, and
during normal service.
The tip icon indicates advice on, for example, how to design your
project or how to use a certain function.
• Abbreviations and acronyms in this manual are spelled out in the glossary. The
glossary also contains definitions of important terms.
• Push button navigation in the LHMI menu structure is presented by using the
push button icons.
For example, to navigate between the options, use and .
• HMI menu paths are presented in bold.
For example, select Main menu/Settings.
• LHMI messages are shown in Courier font.
For example, to save the changes in non-volatile memory, select Yes and
press .
• Parameter names are shown in italics.
For example, the function can be enabled and disabled with the Operation
setting.
• Each function block symbol shows the available input/output signal.
• the character ^ in front of an input/output signal name indicates that the
signal name may be customized using the PCM600 software.
• the character * after an input signal name indicates that the signal must
be connected to another function block in the application configuration
to achieve a valid application configuration.
• Logic diagrams describe the signal logic inside the function block and are
bordered by dashed lines.
• Signals in frames with a shaded area on their right hand side represent
setting parameter signals that are only settable via the PST, ECT or
LHMI.
• If an internal signal path cannot be drawn with a continuous line, the
suffix -int is added to the signal name to indicate where the signal starts
and continues.
• Signal paths that extend beyond the logic diagram and continue in
another diagram have the suffix ”-cont.”
Function block names are used in ACT and PST to identify functions. Respective
function block names of Edition 1 logical nodes and Edition 2 logical nodes are
shown in the table below.
GUID-F5776DD1-BD04-4872-BB89-A0412B4B5CC3 v1
The following tables list all the functions available in the IED.
Those functions that are not exposed to the user or do not need to
be configured are not described in this manual.
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670 (Customized)
Differential protection
T2WPDIF 87T Transformer differential 1-3 1
protection, two winding
T3WPDIF 87T Transformer differential 1-3 1
protection, three winding
HZPDIF 87 High impedance differential 0-6 1 3-A02 3-A02
protection, single phase
REFPDIF 87N Restricted earth fault protection, 0-3 1 2 2B
low impedance 1-A01
LDRGFC 11RE Additional security logic for 0-1
L differential protection
Impedance protection
ZMQPDIS, 21 Distance protection zone, 0-5
ZMQAPDIS quadrilateral characteristic
ZDRDIR 21D Directional impedance 0-2
quadrilateral
ZMCPDIS, 21 Distance measuring zone, 0-5
ZMCAPDIS quadrilateral characteristic for
series compensated lines
Table continues on next page
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670 (Customized)
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670 (Customized)
Current protection
PHPIOC 50 Instantaneous phase 0-8 3 2 3 2-C19
overcurrent protection
OC4PTOC 51_671) Directional phase overcurrent 0-8 3 2 3 2-C19
protection, four steps
EFPIOC 50N Instantaneous residual 0-8 3 2 3 2-C19
overcurrent protection
EF4PTOC 51N Directional residual overcurrent 0-8 3 3 3 2-C19
67N2) protection, four steps
NS4PTOC 46I2 Four step directional negative 0-8 2-C42 2-C42 3-C43 2-C19
phase sequence overcurrent
protection
SDEPSDE 67N Sensitive directional residual 0-3 1 1-C16 1-C16 1-C16
overcurrent and power
protection
LCPTTR 26 Thermal overload protection, 0-2
one time constant, Celsius
LFPTTR 26 Thermal overload protection, 0-2
one time constant, Fahrenheit
TRPTTR 49 Thermal overload protection, 0-6 1 1B 2B
two time constants 1-C05 1-C05
CCRBRF 50BF Breaker failure protection 0-6 3 4 6
STBPTOC 50STB Stub protection 0-3 3-B26 3-B26 3-B26
CCPDSC 52PD Pole discordance protection 0-6 3 4 6
GUPPDUP 37 Directional underpower 0-2 1-C35 1-C35 1-C35
protection
GOPPDOP 32 Directional overpower protection 0-2 1-C35 1-C35 1-C35
BRCPTOC 46 Broken conductor check 1 1 1 1 1
CBPGAPC Capacitor bank protection 0-6
NS2PTOC 46I2 Negative sequence time 0-2
overcurrent protection for
machines
VRPVOC 51V Voltage restrained overcurrent 0-3 1-C35 1-C35 1-C35
protection
Table continues on next page
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670 (Customized)
Voltage protection
UV2PTUV 27 Two step undervoltage 0-3 1-D01 1B 1B 2-D02
protection 1-D01 2-D02
OV2PTOV 59 Two step overvoltage protection 0-3 1-D01 1B 1B 2-D02
1-D01 2-D02
ROV2PTOV 59N Two step residual overvoltage 0-3 1-D01 1B 1B 2-D02
protection 1-D01 2-D02
OEXPVPH 24 Overexcitation protection 0-2 2-D04 1-D03 2-D04
VDCPTOV 60 Voltage differential protection 0-2 2 2 2 2
LOVPTUV 27 Loss of voltage check 1 1 1 1 1
Frequency protection
SAPTUF 81 Underfrequency protection 0-6 6-E01 6-E01 6-E01
SAPTOF 81 Overfrequency protection 0-6 6-E01 6-E01 6-E01
SAPFRC 81 Rate-of-change of frequency 0-6 6-E01 6-E01 6-E01
protection
Multipurpose protection
CVGAPC General current and voltage 0-9 6-F02 6-F02
protection
General calculation
SMAIHPAC Multipurpose filter 0-6
1) 67 requires voltage
2) 67N requires voltage
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670
(Customized)
Control
SESRSYN 25 Synchrocheck, energizing 0-6 1 1B 1B
check and synchronizing 2-H01 4-H03
APC30 3 Control functionality for up to 0-1 1-H39 1-H39 1-H39
6 bays, max 30 objects
(6CBs), including interlocking
(see Table 4)
QCBAY Bay control 1+5/APC30 1 1+5/ 1+5/ 1+5/
APC30 APC30 APC30
LOCREM Handling of LR-switch 1+5/APC30 1 1+5/ 1+5/ 1+5/
positions APC30 APC30 APC30
LOCREMCTRL LHMI control of PSTO 1 1 1 1 1
SXCBR Circuit breaker 18 12 18 18 18
TR1ATCC 90 Automatic voltage control for 0-4 1 2 2B
tap changer, single control 2-H16
TR8ATCC 90 Automatic voltage control for 0-4 1-H15 1-H15 2B
tap changer, parallel control 2-H18 2-H18
TCMYLTC 84 Tap changer control and 0-4 4 4 4
supervision, 6 binary inputs
TCLYLTC 84 Tap changer control and 0-4 4 4 4
supervision, 32 binary inputs
SLGAPC Logic rotating switch for 15 15 15 15 15
function selection and LHMI
presentation
VSGAPC Selector mini switch 30 30 30 30 30
DPGAPC Generic communication 16 16 16 16 16
function for Double Point
indication
SPC8GAPC Single point generic control 5 5 5 5 5
function 8 signals
AUTOBITS Automation bits, command 3 3 3 3 3
function for DNP3.0
SINGLECMD Single command, 16 signals 4 4 4 4 4
I103CMD Function commands for IEC 1 1 1 1 1
60870-5-103
I103GENCMD Function commands generic 50 50 50 50 50
for IEC 60870-5-103
Table continues on next page
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670
(Customized)
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670
(Customized)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670
(Customized)
Monitoring
CVMMXN Power system measurement 6 6 6 6 6
CMMXU Current measurement 10 10 10 10 10
VMMXU Voltage measurement phase- 6 6 6 6 6
phase
CMSQI Current sequence 6 6 6 6 6
measurement
VMSQI Voltage sequence 6 6 6 6 6
measurement
VNMMXU Voltage measurement phase- 6 6 6 6 6
earth
AISVBAS General service value 1 1 1 1 1
presentation of analog inputs
EVENT Event function 20 20 20 20 20
DRPRDRE, Disturbance report 1 1 1 1 1
A4RADR,
SPGAPC Generic communication 64 64 64 64 64
function for Single Point
indication
SP16GAPC Generic communication 16 16 16 16 16
function for Single Point
indication 16 inputs
MVGAPC Generic communication 24 24 24 24 24
function for measured values
Table continues on next page
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670
(Customized)
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670
(Customized)
Station communication
LONSPA, SPA SPA communication protocol 1 1 1 1 1
ADE LON communication protocol 1 1 1 1 1
HORZCOMM Network variables via LON 1 1 1 1 1
RS485GEN RS485 1 1 1 1 1
DNPGEN DNP3.0 communication general 1 1 1 1 1
protocol
CHSERRS485 DNP3.0 for EIA-485 1 1 1 1 1
communication protocol
CH1TCP, CH2TCP, DNP3.0 for TCP/IP 1 1 1 1 1
CH3TCP, CH4TCP communication protocol
CHSEROPT DNP3.0 for TCP/IP and EIA-485 1 1 1 1 1
communication protocol
MSTSER DNP3.0 serial master 1 1 1 1 1
MST1TCP, DNP3.0 for TCP/IP 1 1 1 1 1
MST2TCP, communication protocol
MST3TCP,
MST4TCP
DNPFREC DNP3.0 fault records for TCP/IP 1 1 1 1 1
and EIA-485 communication
protocol
IEC 61850-8-1 IEC 61850 1 1 1 1 1
GOOSEINTLKRCV Horizontal communication via 59 59 59 59 59
GOOSE for interlocking
GOOSEBINRCV GOOSE binary receive 16 16 16 16 16
GOOSEDPRCV GOOSE function block to receive 64 64 64 64 64
a double point value
GOOSEINTRCV GOOSE function block to receive 32 32 32 32 32
an integer value
GOOSEMVRCV GOOSE function block to receive 60 60 60 60 60
a measurand value
GOOSESPRCV GOOSE function block to receive 64 64 64 64 64
a single point value
VCTRSEND Horizontal communication via 1 1 1 1 1
GOOSE for VCTR
GOOSEVCTRRCV Horizontal communication via 7 7 7 7 7
GOOSE for VCTR
Table continues on next page
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670
(Customized)
RET670 (A10)
RET670 (B30)
RET670 (B40)
RET670 (A25)
RET670
(Customized)
Analog input channels must be configured and set properly in order to get correct
measurement results and correct protection operations. For power measuring, all
directional and differential functions, the directions of the input currents must be
defined in order to reflect the way the current transformers are installed/connected
in the field ( primary and secondary connections ). Measuring and protection
algorithms in the IED use primary system quantities. Setting values are in primary
quantities as well and it is important to set the data about the connected current and
voltage transformers properly.
The IED has the ability to receive analog values from primary
equipment, that are sampled by Merging units (MU) connected to a
process bus, via the IEC 61850-9-2 LE protocol.
The hardware channels appear in the signal matrix tool (SMT) and
in ACT when a TRM is included in the configuration with the
hardware configuration tool. In the SMT or the ACT, they can be
mapped to the desired virtual input (SMAI) of the IED and used
internally in the configuration.
3.3 Signals
PID-3920-OUTPUTSIGNALS v6
PID-3921-OUTPUTSIGNALS v7
PID-3922-OUTPUTSIGNALS v6
PID-3923-OUTPUTSIGNALS v7
PID-3924-OUTPUTSIGNALS v7
PID-6598-OUTPUTSIGNALS v6
3.4 Settings
SEMOD129840-4 v2
PID-4153-SETTINGS v7
PID-3920-SETTINGS v7
PID-3921-SETTINGS v7
PID-3922-SETTINGS v7
PID-3923-SETTINGS v7
PID-3924-SETTINGS v7
PID-6598-SETTINGS v6
PID-3920-MONITOREDDATA v6
PID-3921-MONITOREDDATA v6
PID-3922-MONITOREDDATA v6
PID-3923-MONITOREDDATA v6
PID-3924-MONITOREDDATA v6
PID-6598-MONITOREDDATA v6
The direction of a measured current depends on the connection of the CT. The main
CTs are typically star connected and can be connected with the star point towards
the object or away from the object. This information must be set in the IED.
Once the CT direction settings is correctly entered the internal IED convention of
the directionality is defined as follows:
• Positive value of current or power means that the quantity has the direction
into the protected object.
• Negative value of current or power means that the quantity has the direction
out from the protected object.
For directional functions the directional conventions are defined as follows (see
Figure 2)
en05000456.vsd
IEC05000456 V1 EN-US
The settings of the IED is performed in primary values. The ratios of the main CTs
and VTs are, therefore, basic data for the IED. The user has to set the rated
secondary and primary currents and voltages of the CTs and VTs to provide the
IED with their rated ratios.
The CT and VT ratio and the name on respective channel is done under Main
menu/Hardware/Analog modules in the Parameter Settings tool or on the HMI.
M16988-1 v11
Table 30: TRM - Energizing quantities, rated values and limits for protection transformer
Description Value
Frequency
Rated frequency fr 50/60 Hz
Current inputs
Rated current Ir 1 or 5 A
Table 31: TRM - Energizing quantities, rated values and limits for measuring transformer
Description Value
Frequency
Rated frequency fr 50/60 Hz
Description Value
Current inputs
Rated current Ir 1A 5A
Voltage inputs *)
Rated voltage Ur 110 or 220 V
SEMOD53376-2 v6
The debounce filter eliminates bounces and short disturbances on a binary input.
A time counter is used for filtering. The time counter is increased once in a
millisecond when a binary input is high, or decreased when a binary input is low. A
new debounced binary input signal is forwarded when the time counter reaches the
set DebounceTime value and the debounced input value is high or when the time
counter reaches 0 and the debounced input value is low. The default setting of
DebounceTime is 1 ms.
The binary input ON-event gets the time stamp of the first rising edge, after which
the counter does not reach 0 again. The same happens when the signal goes down
to 0 again.
Binary input wiring can be very long in substations and there are electromagnetic
fields from for example nearby breakers. An oscillation filter is used to reduce the
disturbance from the system when a binary input starts oscillating.
An oscillation counter counts the debounced signal state changes during 1 s. If the
counter value is greater than the set value OscBlock, the input signal is blocked.
The input signal is ignored until the oscillation counter value during 1 s is below
the set value OscRelease.
4.1.3 Settings
GUID-07348953-4A72-444B-A31A-030ABEA8E0C4 v1
5.1.1 Identification
GUID-84392EFF-4D3F-4A67-A6ED-34C6E98574D6 v1
5.1.2 Settings
PID-6451-SETTINGS v1
5.2.1 Identification
GUID-03AB7AEE-87D3-4F3C-B6B9-B1EB1B538E38 v1
LHMICTRL
CLRLEDS HMI-ON
RED-S
YELLOW-S
YELLOW-F
CLRPULSE
LEDSCLRD
IEC09000320-1-en.vsd
IEC09000320 V1 EN-US
5.2.3 Signals
PID-3992-INPUTSIGNALS v6
PID-3992-OUTPUTSIGNALS v6
5.3.1 Identification
GUID-6E36C0BC-F284-4C88-A4A8-9535D3BE8B14 v2
GRP2_LED1 -
GRP2_LED15
GRP3_LED1 -
GRP3_LED15
LEDGEN
BLOCK NEWIND
RESET ACK
IEC09000321-1-en.vsd
IEC09000321 V1 EN-US
GRP1_LED1
^HM1L01R
^HM1L01Y
^HM1L01G
IEC09000322 V1 EN-US
The GRP1_LED1 function block is an example. The 15 LEDs in each of the three
groups have a similar function block.
5.3.3 Signals
PID-4114-INPUTSIGNALS v5
PID-4114-OUTPUTSIGNALS v5
PID-1697-INPUTSIGNALS v18
5.3.4 Settings
PID-4114-SETTINGS v6
PID-1697-SETTINGS v18
5.4 LCD part for HMI function keys control module GUID-EECAE7FA-7078-472C-A429-F7607DB884EB v2
5.4.1 Identification
GUID-E6611022-5EA3-420D-ADCD-9D1E7604EFEB v1
FNKEYMD1
^LEDCTL1 ^FKEYOUT1
IEC09000327 V1 EN-US
Only the function block for the first button is shown above. There is a similar block
for every function key button.
5.4.3 Signals
PID-1657-INPUTSIGNALS v18
PID-1657-OUTPUTSIGNALS v19
5.4.4 Settings
PID-1657-SETTINGS v19
PID-6452-SETTINGS v2
GUID-BCE87D54-C836-40EE-8DA7-779B767059AB v1
IEC13000239-3-en.vsd
IEC13000239 V3 EN-US
The LHMI keypad contains push-buttons which are used to navigate in different
views or menus. The push-buttons are also used to acknowledge alarms, reset
indications, provide help and switch between local and remote control mode.
The keypad also contains programmable push-buttons that can be configured either
as menu shortcut or control buttons.
24
1
23
2
18
3
19
4
6 20
21
7 22
8 9 10 11 12 13 14 15 16 17
IEC15000157-2-en.vsd
IEC15000157 V2 EN-US
Figure 8: LHMI keypad with object control, navigation and command push-
buttons and RJ-45 communication port
20 Clear
21 Help
22 Communication port
23 Programmable indication LEDs
24 IED status LEDs
The LHMI includes a graphical monochrome liquid crystal display (LCD) with a
resolution of 320 x 240 pixels. The character size can vary. The amount of
characters and rows fitting the view depends on the character size and the view that
is shown.
IEC15000270-1-en.vsdx
IEC15000270 V1 EN-US
1 Path
2 Content
3 Status
4 Scroll bar (appears when needed)
• The path shows the current location in the menu structure. If the path is too
long to be shown, it is truncated from the beginning, and the truncation is
indicated with three dots.
• The content area shows the menu content.
• The status area shows the current IED time, the user that is currently logged in
and the object identification string which is settable via the LHMI or with
PCM600.
• If text, pictures or other items do not fit in the display, a vertical scroll bar
appears on the right. The text in content area is truncated from the beginning if
it does not fit in the display horizontally. Truncation is indicated with three
dots.
IEC15000138-1-en.vsdx
IEC15000138 V1 EN-US
The number after : (colon sign) at the end of the function instance, for example, 1
in SMAI1:1, indicates the number of that function instance.
The function key button panel shows on request what actions are possible with the
function buttons. Each function button has a LED indication that can be used as a
feedback signal for the function button control action. The LED is connected to the
required signal with PCM600.
IEC13000281-1-en.vsd
GUID-C98D972D-D1D8-4734-B419-161DBC0DC97B V1 EN-US
The indication LED panel shows on request the alarm text labels for the indication
LEDs. Three indication LED pages are available.
IEC13000240-1-en.vsd
GUID-5157100F-E8C0-4FAB-B979-FD4A971475E3 V1 EN-US
The function button and indication LED panels are not visible at the same time.
Each panel is shown by pressing one of the function buttons or the Multipage
button. Pressing the ESC button clears the panel from the display. Both panels have
a dynamic width that depends on the label string length.
The LHMI includes three status LEDs above the display: Ready, Start and Trip.
There are 15 programmable indication LEDs on the front of the LHMI. Each LED
can indicate three states with the colors: green, yellow and red. The texts related to
each three-color LED are divided into three panels.
There are 3 separate panels of LEDs available. The 15 physical three-color LEDs
in one LED group can indicate 45 different signals. Altogether, 135 signals can be
indicated since there are three LED groups. The LEDs are lit according to priority,
with red being the highest and green the lowest priority. For example, if on one
panel there is an indication that requires the green LED to be lit, and on another
panel there is an indication that requires the red LED to be lit, the red LED takes
priority and is lit. The LEDs can be configured with PCM600 and the operation
mode can be selected with the LHMI or PCM600.
Information panels for the indication LEDs are shown by pressing the Multipage
button. Pressing that button cycles through the three pages. A lit or un-
acknowledged LED is indicated with a highlight. Such lines can be selected by
using the Up/Down arrow buttons. Pressing the Enter key shows details about the
selected LED. Pressing the ESC button exits from information pop-ups as well as
from the LED panel as such.
The Multipage button has a LED. This LED is lit whenever any LED on any panel
is lit. If there are un-acknowledged indication LEDs, then the Multipage LED
blinks. To acknowledge LEDs, press the Clear button to enter the Reset menu
(refer to description of this menu for details).
There are two additional LEDs which are next to the control buttons and
. These LEDs can indicate the status of two arbitrary binary signals by
configuring the OPENCLOSE_LED function block. For instance,
OPENCLOSE_LED can be connected to a circuit breaker to indicate the breaker
open/close status on the LEDs.
IEC16000076-1-en.vsd
IEC16000076 V1 EN-US
Each indication LED on local HMI can be set individually to operate in 6 different
sequences; two as follow type and four as latch type. Two of the latching sequence
types are intended to be used as a protection indication system, either in collecting
or restarting mode, with reset functionality. The other two are intended to be used
as signalling system in collecting mode with acknowledgment functionality.
There are three status LEDs above the LCD in front of the IED: green, yellow and
red.
The green LED has a fixed function that presents the healthy status of the IED. The
yellow and red LEDs are user configured. The yellow LED can be used to indicate
that a disturbance report is triggered (steady) or that the IED is in test mode
(flashing). The red LED can be used to indicate a trip command.
The yellow and red status LEDs are configured in the disturbance recorder
function, DRPRDRE, by connecting a start or trip signal from the actual function
to a BxRBDR binary input function block using the PCM600, and configuring the
setting to Off, Start or Trip for that particular signal.
Collecting mode
• LEDs that are used in the collecting mode of operation are accumulated
continuously until the unit is acknowledged manually. This mode is suitable
when the LEDs are used as a simplified alarm system. When all three inputs
(red, yellow and green) are connected to different sources of events for the
same function block, collecting mode shows the highest priority LED color
that was activated since the latest acknowledgment was made. If a number of
different indications were made since the latest acknowledgment, it is not
possible to get a clear view of what triggered the latest event without looking
at the sequence of events list. A condition for getting the sequence of events is
that the signals have been engineered in the disturbance recorder.
Re-starting mode
• In the re-starting mode of operation each new start resets all previous active
LEDs and activates only those which appear during one disturbance. Only
LEDs defined for re-starting mode with the latched sequence type 6
(LatchedReset-S) will initiate a reset and a restart at a new disturbance. A
disturbance is defined to end a settable time after the reset of the activated
input signals or when the maximum time limit has elapsed. In sequence 6, the
restarting or reset mode means that upon occurrence of any new event, all
previous indications will be reset. This facilitates that only the LED
indications related to the latest event is shown.
Acknowledgment/reset GUID-E6727E8F-C28B-4295-AE21-BC5643363805 v3
• Automatic reset
• The automatic reset can only be performed for LED indications defined
for re-starting mode with the latched sequence type 6 (LatchedReset-S).
When the automatic reset of the LEDs has been performed, still
persisting indications will be indicated with a steady light.
The sequences can be of type Follow or Latched. For the Follow type, the LED
follows the input signal completely. For the Latched type, each LED latches to the
corresponding input signal until it is reset.
The figures below show the function of available sequences selectable for each
LED separately. The following 6 sequences are available:
• Sequence 1: Follow-S
• Sequence 2: Follow-F
• Sequence 3: LatchedAck-F-S
• Sequence 4: LatchedAck-S-F
• Sequence 5: LatchedColl-S
• Sequence 6: LatchedReset-S
For sequence 1 and 2, which are of the Follow type, the acknowledgment (Ack ) /
reset function is not applicable because the indication shown by the LED follows
its input signal. Sequence 3 and 4, which are of the Latched type with
acknowledgement, are only working in collecting (Coll) mode. Sequence 5 is
working according to Latched type and collecting mode while Sequence 6 is
working according to Latched type and re-starting (Reset) mode. The letters S and
F in the sequence names have the meaning S = Steady and F = Flash.
At the activation of the input signal to any LED, the indication on the
corresponding LED obtains a color that corresponds to the activated input, and
operates according to the selected sequence diagrams shown below.
In the sequence diagrams the different statuses of the LEDs are shown using the
following symbols:
This sequence follows the corresponding input signals all the time with a steady
light. It does not react on acknowledgment or reset. Every LED is independent of
the other LEDs in its operation.
Activating
signal
LED
IEC01000228_2_en.vsd
IEC01000228 V2 EN-US
If inputs for two or more colors are active at the same time to the same LED, the
priority color it shows is in accordance with the color described above. An example
of the operation when two colors are activated in parallel to the same LED is
shown in figure16.
Activating
signal GREEN
Activating
signal RED
LED G G R G
IEC09000312_1_en.vsd
IEC09000312 V1 EN-US
This sequence is the same as Sequence 1, Follow-S, but the LEDs are flashing
instead of showing steady light.
This sequence has a latched function and works in collecting mode. Every LED is
independent of the other LEDs in its operation. At the activation of the input signal,
the indication starts flashing. After acknowledgment the indication disappears if
the signal is not present any more. If the signal is still present after
acknowledgment it gets a steady light.
Activating
signal
LED
Acknow.
en01000231.vsd
IEC01000231 V1 EN-US
Activating
signal GREEN
Activating
signal RED
R R G
LED
Acknow
IEC09000313_1_en.vsd
IEC09000313 V1 EN-US
If all three signals are activated the order of priority is still maintained.
Acknowledgment of indications with higher priority will acknowledge also low
priority indications, which are not visible according to figure 19.
Activating
signal GREEN
Activating
signal YELLOW
Activating
signal RED
LED G Y R R Y
Acknow.
IEC09000314-1-en.vsd
IEC09000314 V1 EN-US
Activating
signal GREEN
Activating
signal YELLOW
Activating
signal RED
LED G G R R Y
Acknow.
IEC09000315-1-en.vsd
IEC09000315 V1 EN-US
This sequence has the same functionality as sequence 3, but steady and flashing
light have been alternated.
This sequence has a latched function and works in collecting mode. At the
activation of the input signal, the indication will light up with a steady light. The
difference to sequence 3 and 4 is that indications that are still activated will not be
affected by the reset that is, immediately after the positive edge of the reset has
been executed a new reading and storing of active signals is performed. Every LED
is independent of the other LEDs in its operation.
Activating
signal
LED
Reset
IEC01000235_2_en.vsd
IEC01000235 V2 EN-US
That means if an indication with higher priority has reset while an indication with
lower priority still is active at the time of reset, the LED will change color
according to figure22.
Activating
signal GREEN
Activating
signal RED
R G
LED
Reset
IEC09000316_1_en.vsd
IEC09000316 V1 EN-US
In this mode all activated LEDs, which are set to Sequence 6 (LatchedReset-S), are
automatically reset at a new disturbance when activating any input signal for other
LEDs set to Sequence 6 LatchedReset-S. Also in this case indications that are still
activated will not be affected by manual reset, that is, immediately after the
positive edge of that the manual reset has been executed a new reading and storing
of active signals is performed. LEDs set for sequence 6 are completely independent
in its operation of LEDs set for other sequences.
Figure 23 shows the timing diagram for two indications within one disturbance.
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000239_2-en.vsd
IEC01000239 V2 EN-US
Figure 24 shows the timing diagram for a new indication after tRestart time has
elapsed.
Disturbance Disturbance
tRestart tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000240_2_en.vsd
IEC01000240 V2 EN-US
Figure 25 shows the timing diagram when a new indication appears after the first
one has reset but before tRestart has elapsed.
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000241_2_en.vsd
IEC01000241 V2 EN-US
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000242_2_en.vsd
IEC01000242 V2 EN-US
When used as a menu shortcut, a function button provides a fast way to navigate
between default nodes in the menu tree. When used as a control, the button can
control a binary signal.
The operation mode is set individually for each output, either OFF, TOGGLE or
PULSED.
Setting OFF
Input value
Output value
IEC09000330-2-en.vsd
IEC09000330 V2 EN-US
Setting TOGGLE
In this mode the output toggles each time the function key has been pressed for
more than 500ms. Note that the input attribute is reset each time the function block
executes. The function block execution is marked with a dotted line below.
Input value
500ms 500ms 500ms
Output value
IEC09000331_1_en.vsd
IEC09000331 V2 EN-US
Setting PULSED
In this mode the output sets high (1) when the function key has been pressed for
more than 500ms and remains high according to set pulse time. After this time the
output will go back to 0. The input attribute is reset when the function block detects
it being high and there is no output pulse.
Note that the third positive edge on the input attribute does not cause a pulse, since
the edge was applied during pulse output. A new pulse can only begin when the
output is zero; else the trigger edge is lost.
Input value
500ms 500ms 500ms 500ms
IEC09000332_2_en.vsd
IEC09000332 V2 EN-US
All function keys work the same way: When the LHMI is configured so that a
certain function button is of type CONTROL, then the corresponding input on this
function block becomes active, and will light the yellow function button LED when
high. This functionality is active even if the function block operation setting is set
to off. It has been implemented this way for safety reasons; the idea is that the
function key LEDs should always reflect the actual status of any primary
equipment monitored by these LEDs.
6.1.1 Identification
GUID-1E140EA0-D198-443A-B445-47CEFD2E6134 v1
PMUCONF contains the PMU configuration parameters for both IEEE C37.118
and IEEE 1344 protocols. This means all the required settings and parameters in
order to establish and define a number of TCP and/or UDP connections with one or
more PDC clients (synchrophasor client). This includes port numbers, TCP/UDP IP
addresses, and specific settings for IEEE C37.118 as well as IEEE 1344 protocols.
information is available in the sections Short guidance for the use of TCP and Short
guidance for the use of UDP.
IED
PMU ID
1344/C37.118
PMUREPORT: 1 PMUREPORT: 2 TCP Client_1
1344/C37.118
TCP Client_2
1344/C37.118
TCP Client_3
PMU ID: X
1344/C37.118
TCP IP TCP Client_4
PMU ID: Y 1344/C37.118
TCP Port TCP Client_5
1344/C37.118 TCP Client_6
1344/C37.118 TCP Client_7
1344/C37.118 TCP Client_8
PMU ID
IEC140000117-1.en.vsd
IEC140000117 V2 EN-US
Four message types are defined in IEEE C37.118 standard: data, configuration,
header, and command frames. The first three message types are transmitted from
the PMU/PDC that serves as the data source, and the last one (command frame) is
received by the PMU/PDC.
These four message types are defined in IEEE C37.118 standard as follows:
If the user-defined (updated) header file is larger than 1400 bytes, then it will be
truncated to 1400 bytes in both IEEE C37.118 and IEEE1344 protocols.
Both PMU reporting instances are using the same header file (ieee1344header.txt)
and this header file is used for both IEEE C37.118 and IEEE1344 protocols.
Port 7001 is used by the SPA on TCP/IP (field service tool). If the
port is used for any other protocol, for example C37.118, the SPA
on TCP/IP stops working.
The IED supports 8 concurrent TCP connections using IEEE1344 and/or C37.118
protocol. The following parameters are used to define the TCP connection between
the IED and the TCP clients:
1. 1344TCPport– TCP port for control of IEEE 1344 data for TCP clients
2. C37.118TCPport – TCP port for control of IEEE C37.118 data for TCP clients
As can be seen, there are two separate parameters in the IED for selecting port
numbers for TCP connections; one for IEEE1344 protocol (1344TCPport) and
another one for C37.118 protocol (C37.118 TCPport). Client can communicate
with the IED over IEEE1344 protocol using the selected TCP port defined in
1344TCPport, and can communicate with the IED over IEEE C37.118 protocol
using the selected TCP port number in C37.118TCPport.
All the frames (the header frame, configuration frame, command frame and data
frame) are communicated over the same TCP port. The client can request (by
sending a command frame) a configuration and/or header via the TCP channel and
the requested configuration and/or header will be sent back to the client (as
Configuration frame/Header frame) over the same TCP channel.
Once the TCP client connects to the IED, the client has to necessarily send a
command frame to start a communication. As shown in Figure 30, the IED can
support 2 PMUREPORT instances and the client has to specify the PMU ID Code
in order to know which PMUREPORT data needs to be sent out to that client. In
this figure, X and Y are referring to the user-defined PMU ID Codes for
PMUREPORT instances 1 or 2, respectively. It is up to the TCP client to decide
which PMUREPORT function block shall communicate with that client. Upon
successful reception of the first command by the IED, the PMU ID will be
extracted out of the command; if there is a PMUREPORT instance configured in
the IED with matching PMU ID, then the client connection over TCP with the IED
will be established and further communication will take place. Otherwise, the
connection will be terminated and the TCPCtrlCfgErrCnt is incremented in the
PMU Diagnostics on the Local HMI under Main menu/Diagnostics/
Communication/PMU diagnostics/PMUSTATUS:1
At any given point of time maximum of 8 TCP clients can be connected to the IED
for IEEE1344/C37.118 protocol. If there is an attempt made by the 9th client, the
connection to the new client will be terminated without influencing the connection
of the other clients already connected. A list of active clients can be seen on the
Local HMI in the diagnostics menu under Main menu/Diagnostics/
Communication/PMU diagnostics/PMUSTATUS:1
It is possible to turn off/on the UDP data communication either by setting the
parameter SendDataUDP[x] to Off/On locally in the PMU or by sending a C37.118
or IEEE1344 command frame (RTDOFF/RTDON) remotely from the client to the
PMU as defined in IEEE 1344/C37.118 standard.
However, such a remote control to stop the streams from the client is only possible
when the parameter SendDataUDP[x] is set to SetByProtocol. The command
RTDOFF/RTDON sent by the client is stored in the IED, i.e. if the IED is rebooted
for some reason, the state of the stream will remain the same.
The UDP implementation in the IED is a UDP_TCP. This means that by default,
only the data frames are sent out on UDP stream and the header frame,
configuration frame and command frame are sent over TCP. This makes the
communication more reliable especially since commands are sent over TCP which
performs request/acknowledgment exchange to ensure that no data (command in
this case) is lost.
The data streams in the IED can be sent as unicast or as multicast. The user-defined
IP address set in the parameter UDPDestAddress[x] for each UDP stream defines if
it is a Unicast or Multicast. The address range 224.0.0.0 to 239.255.255.255 (Class
D IP addresses) is treated as multicast. Any other IP address outside this range is
treated as unicast and the UDP data will be only sent to that specific unicast IP
address. In addition to UDPDestAddress[x] parameter, UDPDestPort[x] parameter
is used to define the UDP destination port number for UDP client group[x].
In case of multicast IP, it will be the network switches and routers that take care of
replicating the packet to reach multiple receivers. Multicast mechanism uses
network infrastructure efficiently by requiring the IED to send a packet only once,
even if it needs to be delivered to a large number of receivers.
If there are more than one UDP client group defined as multicast, the user shall set
different multicast IP addresses for each UDP group.
The PMU clients receiving the UDP frames can also connect to the IED to request
(command frame) config frame 1, config frame 2, config frame 3, or header frame,
and to disable/enable real time data. This can be done by connecting to the TCP
port selected in TCPportUDPdataCtrl[x] for each UDP group. This connection is
done using TCP. The IED allows 4 concurrent client connections for every
TCPportUDPdataCtrl[x] port (for each UDP client group[x]).
Even if the parameter SendDataUDP[x] is set to Off it is still possible for the
clients to connect on the TCP port and request the configuration frames.
PID-6710-SETTINGS v4
6.2.1 Identification
GUID-0090956B-48F1-4E8B-9A40-90044C71DF20 v1
The phasor measurement reporting block moves the phasor calculations into an
IEEE C37.118 and/or IEEE 1344 synchrophasor frame format. The PMUREPORT
block contains parameters for PMU performance class and reporting rate, the
IDCODE and Global PMU ID, format of the data streamed through the protocol,
the type of reported synchrophasors, as well as settings for reporting analog and
digital signals.
There are settings for Phasor type (positive sequence, negative sequence or zero
sequence in case of 3-phase phasor and L1, L2 or L3 in case of single phase
phasor), PMU's Service class (Protection or Measurement), Phasor representation
(polar or rectangular) and the data types for phasor data, analog data and frequency
data.
Multiple PMU functionality can be configured in the IED, which can stream out
same or different data at different reporting rates or different performance (service)
classes. There are 2 instances of PMU functionality available in the IED. Each
Figure 31 shows both instances of the PMUREPORT function block. As seen, each
PMUREPORT instance has 4 predefined binary input signals corresponding to the
Bits 03-00: Trigger Reason defined in STAT field of the Data frame in IEEE
C37.118.2 standard. These are predefined inputs for Frequency Trigger, Rate of
Change of Frequency trigger, Magnitude High and Magnitude Low triggers.
IEC140000118-2-en.vsd
IEC140000118 V2 EN-US
IEC140000119-2-en.vsd
IEC140000119 V2 EN-US
IEC140000120-2-en.vsd
IEC140000120 V2 EN-US
IEC140000121-2-en.vsd
IEC140000121 V2 EN-US
PMUREPORT
BLOCK TIMESTAT
^FREQTRIG
^DFDTTRIG
^MAGHIGHTRIG
^MAGLOWTRIG
IEC140000102-1_en.vsd
IEC140000102 V1 EN-US
ANALOGREPORT1
^ANALOG1
^ANALOG2
^ANALOG3
^ANALOG4
^ANALOG5
^ANALOG6
^ANALOG7
^ANALOG8
IEC140000107-1_en.vsd
IEC140000107 V1 EN-US
ANALOGREPORT2
^ANALOG9
^ANALOG10
^ANALOG11
^ANALOG12
^ANALOG13
^ANALOG14
^ANALOG15
^ANALOG16
IEC140000108-1_en.vsd
IEC140000108 V1 EN-US
ANALOGREPORT3
^ANALOG17
^ANALOG18
^ANALOG19
^ANALOG20
^ANALOG21
^ANALOG22
^ANALOG23
^ANALOG24
IEC140000109-1_en.vsd
IEC140000109 V1 EN-US
BINARYREPORT1
^BINARY1
^BINARY2
^BINARY3
^BINARY4
^BINARY5
^BINARY6
^BINARY7
^BINARY8
IEC140000110-1_en.vsd
IEC140000110 V1 EN-US
BINARYREPORT2
^BINARY9
^BINARY10
^BINARY11
^BINARY12
^BINARY13
^BINARY14
^BINARY15
^BINARY16
IEC140000111-1_en.vsd
IEC140000111 V1 EN-US
BINARYREPORT3
^BINARY17
^BINARY18
^BINARY19
^BINARY20
^BINARY21
^BINARY22
^BINARY23
^BINARY24
IEC140000112-1_en.vsd
IEC140000112 V1 EN-US
PHASORREPORT1
^PHASOR1
^PHASOR2
^PHASOR3
^PHASOR4
^PHASOR5
^PHASOR6
^PHASOR7
^PHASOR8
IEC140000103-1_en.vsd
IEC140000103 V1 EN-US
PHASORREPORT2
^PHASOR9
^PHASOR10
^PHASOR11
^PHASOR12
^PHASOR13
^PHASOR14
^PHASOR15
^PHASOR16
IEC140000104-1_en.vsd
IEC140000104 V1 EN-US
PHASORREPORT3
^PHASOR17
^PHASOR18
^PHASOR19
^PHASOR20
^PHASOR21
^PHASOR22
^PHASOR23
^PHASOR24
IEC140000105-1_en.vsd
IEC140000105 V1 EN-US
PHASORREPORT4
^PHASOR25
^PHASOR26
^PHASOR27
^PHASOR28
^PHASOR29
^PHASOR30
^PHASOR31
^PHASOR32
IEC140000106-1_en.vsd
IEC140000106 V1 EN-US
PID-6244-INPUTSIGNALS v2
PID-6244-OUTPUTSIGNALS v2
PID-6238-INPUTSIGNALS v2
PID-6239-INPUTSIGNALS v2
PID-6240-INPUTSIGNALS v2
PID-6241-INPUTSIGNALS v3
PID-6242-INPUTSIGNALS v2
PID-6243-INPUTSIGNALS v2
PID-6252-INPUTSIGNALS v3
PID-6253-INPUTSIGNALS v2
PID-6254-INPUTSIGNALS v2
PID-6255-INPUTSIGNALS v2
PID-6244-SETTINGS v2
PID-6238-SETTINGS v2
PID-6239-SETTINGS v2
PID-6240-SETTINGS v2
PID-6252-SETTINGS v2
PID-6253-SETTINGS v2
PID-6254-SETTINGS v2
PID-6255-SETTINGS v2
PID-6238-MONITOREDDATA v2
PID-6239-MONITOREDDATA v2
PID-6240-MONITOREDDATA v2
PID-6241-MONITOREDDATA v2
PID-6242-MONITOREDDATA v2
PID-6243-MONITOREDDATA v2
PID-6252-MONITOREDDATA v3
PID-6253-MONITOREDDATA v2
PID-6254-MONITOREDDATA v2
PID-6255-MONITOREDDATA v2
The Phasor Measurement Unit (PMU) features three main functional principles:
The C37.118 standard imposes requirements on the devices and describes the
communication message structure and data. The PMU complies with all the
standard requirements with a specific attention to the Total Vector Error (TVE)
requirement. The TVE is calculated using the following equation:
2
( X r ( n ) - X r )2 + ( X i ( n ) - X i )
TVE =
X r2 + X i2
GUID-80D9B1EA-A770-4F50-9530-61644B4DEBBE V1 EN-US (Equation 1)
where,
state and dynamic requirements which are fulfilled in the IED with the help of high
accuracy measurements and advanced filtering techniques.
U/I samples
PMUREPORT1
MU PHASOR1
PHASOR2 8 TCP
U IEEEC37.118 / 1344
TRM SMAI messages NUM
I
U 6 UDC
TRM PHASOR32
I
ANALOG1
I/P MIM SMMI ANALOG2
MEAS. ANALOG24
BINARY1
BINARY2
BIM
OR
BINARY24
PROTECTION
GPS / OP
IRIG-B FREQTRIG
UP
DFDTTRIG
OC
PPS time data MAGHIGHTRIG
MAGLOWTRIG
UV
IEC140000146-1-en.vsd
IEC140000146 V2 EN-US
The TRM modules are individually AC-calibrated in the factory. The calibration
data is stored in the prepared area of the TRM EEProm. The pre-processor block is
extended with calibration compensation and a new angle reference method based
on timestamps. The AI3P output of the preprocessor block is used to provide the
required information for each respective PMUREPORT phasor channel. More
information about preprocessor block is available in the section Signal matrix for
analog inputs SMAI.
By using patented algorithm the IED can track the power system frequency in quite
wide range from 9 Hz to 95 Hz. In order to do that, the three-phase voltage signal
shall be connected to the IED. Then IED can adapt its filtering algorithm in order
to properly measure phasors of all current and voltage signals connected to the
IED. This feature is essential for proper operation of the PMUREPORT function or
for protection during generator start-up and shut-down procedure.
As a result, the first voltage phasor is always the one delivering the system
frequency to the PDC client and if, by any reason, this voltage gets disconnected
then the next available voltage phasor is automatically used as the frequency source
and so on. If the first voltage phasor comes back, since it has a higher priority
compare to the currently selected phasor channel, after 500 ms it will be
automatically selected again as the frequency source. There is also an output
available on the component which shows if the reference frequency is good, error
or reference channel unavailable.
PID-6244-MONITOREDDATA v2
Fs
f0 ±
2
IECEQUATION2418 V1 EN-US (Equation 2)
where,
The internal calculation of analog values in the IED is based on 32 bit floating
point. Therefore, if the user selects to report the analog data (AnalogDataType) as
Integer, there will be a down-conversion of a 32 bit floating value to a new 16 bit
integer value. In such a case, in order to optimize the resolution of the reported
analog data, the user-defined analog scaling is implemented in the IED.
The analog scaling in the IED is automatically calculated by use of the user-defined
parameters AnalogXRange for the respective analog channel X. The analog data
value on the input X will have a range between -AnalogXRange and
+AnalogXRange. The resulting scale factor will be applied to the reported analog
data where applicable.
AnalogXRange ´ 2
S calefactor =
65535.0
offset = 0.0
65535.0 = 16 bit integer range
IECEQUATION2443 V1 EN-US
According to the IEEE C37.118.2 standard, the scale factors (conversion factor) for
analog channels are defined in configuration frame 2 (CFG-2) and configuration
frame 3 (CFG-3) frames as follows:
• CFG-2 frame: The field ANUNIT (4 bytes) specifies the conversion factor as
a signed 24 bit word for user defined scaling. Since it is a 24 bit integer, in
order to support the floating point scale factor, the scale factor itself is
multiplied in 10, so that a minimum of 0.1 scale factor can be sent over the
CFG-2 frame. The resulting scale factor is rounded to the nearest decimal
value. The clients receiving the Analog scale factor over CFG-2 should divide
the received scale factor by 10 and then apply it to the corresponding analog
data value.
• CFG-3 frame: The field ANSCALE (8 bytes) specifies the conversion factor
as X’ = M * X + B where; M is magnitude scaling in 32 bit floating point (first
4 bytes) and B is the offset in 32 bit floating point (last 4 bytes).
The server uses CFG-3 scale factor to scale the analog data values. As a result, the
clients which use scale factors in CFG-3 in order to recalculate analog values, will
get a better resolution than using the scale factors in CFG-2.
Example 1:
AnalogXRange = 3277.0
IECEQUATION2446 V1 EN-US
(3277.0 ´ 2.0 )
sc alefactor = = 0.1 a nd offset = 0.0
65535.0
IECEQUATION2447 V1 EN-US
Example 2:
AnalogXRange = 4915.5
IECEQUATION2448 V1 EN-US
(4915.5 ´ 2.0 )
s c alefac tor = = 0.15 a nd offse t = 0.0
65535.0
IECEQUATION2449 V1 EN-US
Example 3:
(10000000000 ´ 2.0)
sc alefac tor = = 305180.43 and offse t = 0.0
65535.5
IECEQUATION2451 V1 EN-US
The scale factor will be sent as 3051804 on configuration frame 2, and 305180.43
on configuration frame 3. The range of analog values that can be transmitted in this
case is -305181 to -10000000000 and +305181 to +10000000000.
GUID-F0BAEBD8-E361-4D50-9737-7DF8B043D66A v4
Signal magnitude:
Voltage phasor (0.1–1.2) x Ur
Current phasor (0.5–2.0) x Ir
7.1.1 Identification
M15074-1 v5
SYMBOL-BB V1 EN-US
SYMBOL-BB V1 EN-US
The function can be provided with up to six three-phase sets of current inputs if
enough HW is available. All current inputs are provided with percentage bias
restraint features, making the IED suitable for two- or three-winding transformer in
multi-breaker station arrangements.
Two-winding applications
two-winding power
transformer
xx05000048.vsd
IEC05000048 V1 EN-US
two-winding power
transformer with
unconnected delta
xx05000049.vsd tertiary winding
IEC05000049 V1 EN-US
two-winding power
transformer with two
circuit breakers and
xx05000050.vsd two CT-sets on one
IEC05000050 V1 EN-US
side
two-winding power
transformer with two
circuit breakers and
two CT-sets on both
sides
xx05000051.vsd
IEC05000051 V1 EN-US
Three-winding applications
three-winding power
transformer with all
three windings
connected
xx05000052.vsd
IEC05000052 V1 EN-US
three-winding power
transformer with two
circuit breakers and
two CT-sets on one
side
xx05000053.vsd
IEC05000053 V1 EN-US
Autotransformer with
two circuit breakers
and two CT-sets on
two out of three sides
xx05000057.vsd
IEC05000057 V1 EN-US
The setting facilities cover the application of the differential protection to all types
of power transformers and auto-transformers with or without load tap changer as
well as shunt reactors and local feeders within the station. An adaptive stabilizing
feature is included for heavy through-fault currents.By introducing the load tap
changer position, the differential protection pick-up can be set to optimum
sensitivity thus covering internal faults with low fault current level.
differential current protection element is included for a very high speed tripping at
high internal fault currents.
SEMOD54397-4 v5
T2WPDIF
I3PW1CT1* TRIP
I3PW1CT2* TRIPRES
I3PW2CT1* TRIPUNRE
I3PW2CT2* TRNSUNR
TAPOLTC1 TRNSSENS
OLTC1AL START
BLOCK STL1
BLKRES STL2
BLKUNRES STL3
BLKNSUNR BLK2H
BLKNSSEN BLK2HL1
BLK2HL2
BLK2HL3
BLK5H
BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
IDALARM
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
IDNSMAG
IEC06000249_2_en.vsd
IEC06000249 V2 EN-US
SEMOD54551-4 v5
T3WPDIF
I3PW1CT1* TRIP
I3PW1CT2* TRIPRES
I3PW2CT1* TRIPUNRE
I3PW2CT2* TRNSUNR
I3PW3CT1* TRNSSENS
I3PW3CT2* START
TAPOLTC1 STL1
TAPOLTC2 STL2
OLTC1AL STL3
OLTC2AL BLK2H
BLOCK BLK2HL1
BLKRES BLK2HL2
BLKUNRES BLK2HL3
BLKNSUNR BLK5H
BLKNSSEN BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
IDALARM
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
IDNSMAG
IEC06000250_2_en.vsd
IEC06000250 V2 EN-US
7.1.4 Signals
PID-6758-INPUTSIGNALS v1
PID-6758-OUTPUTSIGNALS v1
PID-6757-INPUTSIGNALS v1
PID-6757-OUTPUTSIGNALS v1
7.1.5 Settings
PID-6758-SETTINGS v1
PID-6757-SETTINGS v1
PID-3713-MONITOREDDATA v6
The main CTs are normally supposed to be star connected. The main CTs can be
earthed in anyway (that is, either "ToObject" or "FromObject"). However internally
the differential function will always use reference directions towards the protected
transformer as shown in Figure 39. Thus the IED will always internally measure
the currents on all sides of the power transformer with the same reference direction
towards the power transformer windings as shown in Figure 39. For more
information see the Application manual.
IW1 IW2
Z1S1 Z1S2
E1S1 E1S2
IW1 IW2
IED
en05000186.vsd
IEC05000186 V1 EN-US
Even in a healthy power transformer, the currents are generally not equal when
they flow through it. This is due to the ratio of the number of turns of the windings
and the connection group of the protected transformer. Therefore the differential
protection must first correlate all currents to each other before any calculation can
be performed.
Before any differential current can be calculated, the power transformer phase shift,
and its transformation ratio, must be accounted for. Conversion of all currents to a
common reference is performed in two steps:
• all current phasors are phase-shifted to (referred to) the phase-reference side,
(whenever possible the first winding with star connection)
• all currents magnitudes are always referred to the first winding of the power
transformer (typically transformer high-voltage side)
The two steps of conversion are made simultaneously on-line by the pre-
programmed coefficient matrices, as shown in equation 3 for a two-winding power
transformer, and in equation 4 for a three-winding power transformer.
1 2 3
EQUATION1880 V1 EN-US (Equation 3)
where:
1. is the resulting Differential Currents
2. is the current contribution from the W1 side
3. is the current contribution from the W2 side
1 2 3 4
EQUATION1556 V2 EN-US (Equation 4)
where:
1. is the resulting Differential Currents
2. is the current contribution from the W1 side
3. is the current contribution from the W2 side
4. is the current contribution from the W3 side
1. The Power transformer winding connection type, such as star (Y/y) or delta
(D/d)
2. The Transformer vector group such as Yd1, Dy11, YNautod5, Yy0d5 and so
on, which introduce phase displacement between individual windings currents
in multiples of 30°.
3. The Settings for elimination of zero sequence currents for the individual
windings.
When the end user enters all these parameters, transformer differential function
automatically calculates the matrix coefficients. During this calculations the
following rules are used:
For the phase reference, the first winding with set star (Y) connection is always
used. For example, if the power transformer is a Yd1 power transformer, the HV
winding (Y) is taken as the phase reference winding. If the power transformer is a
Dy1, then the LV winding (y) is taken for the phase reference. If there is no star
connected winding, such as in Dd0 type of power transformers, then the HV delta
winding (D) is automatically chosen as the phase reference winding.
As it can be seen from equation 3 and equation 4 the first entered winding (W1) is
always taken for ampere level reference (current magnitudes from all other sides
are always transferred to W1 side). In other words, within the differential
protection function, all differential currents and bias current are always expressed
in HV side primary Amperes.
It can be shown that the values of the matrix A, B & C coefficients (see equation 3
and equation 4) can be pre-calculated in advance depending on the relative phase
shift between the reference winding and other power transformer windings.
Table 93 summarizes the values of the matrices for all standard phase shifts
between windings.
Table 93: Matrices for differential current calculation
Matrix with Zero Sequence Matrix with Zero Sequence
Reduction set to On Reduction set to Off
Matrix for Reference Winding
é 2 -1 -1ù é1 0 0 ù
1 ê
× -1 2 -1ú ê0 1 0 ú
3 ê ú ê ú
ëê -1 -1 2 ûú êë0 0 1 úû
EQUATION1227 V1 EN-US (Equation 5) EQUATION1228 V1 EN-US (Equation 6)
Matrix for winding with 30° Not applicable. Matrix on the
lagging é 1 -1 0 ù left used.
1 ê
× 0 1 -1ú
3 ê ú
êë -1 0 1 úû
EQUATION1229 V1 EN-US (Equation 7)
Matrix for winding with 60°
lagging é1 -2 1ù é 0 -1 0 ù
1 ê
× 1 1 -2 ú ê 0 0 -1ú
3 ê ú ê ú
êë -2 1 1 úû êë -1 0 0 úû
EQUATION1230 V1 EN-US (Equation 8) EQUATION1231 V1 EN-US (Equation 9)
Matrix for winding with 90° Not applicable. Matrix on the
lagging é 0 -1 1 ù left used.
1
× ê 1 0 -1ú
3 ê ú
êë -1 1 0 úû
EQUATION1232 V1 EN-US (Equation 10)
Matrix for winding with 120°
lagging é -1 -1 2 ù é0 0 1 ù
1 ê
× 2 -1 -1ú ê1 0 0 ú
3 ê ú ê ú
êë -1 2 -1úû ëê0 1 0 úû
EQUATION1233 V1 EN-US (Equation 11) EQUATION1234 V1 EN-US (Equation 12)
Matrix for winding with 150° Not applicable. Matrix on the
lagging é-1 0 1 ù left used.
1
× ê 1 -1 0 ú
3 ê ú
ëê 0 1 -1ûú
EQUATION1235 V1 EN-US (Equation 13)
Matrix for winding which is in
opposite phase é -2 1 1ù é -1 0 0 ù
1 ê
× 1 -2 1 ú ê 0 -1 0 ú
3 ê ú ê ú
ëê 1 1 -2 ûú ëê 0 0 -1ûú
EQUATION1236 V1 EN-US (Equation 14) EQUATION1237 V1 EN-US (Equation 15)
Matrix for winding with 150° Not applicable. Matrix on the
leading é-1 1 0 ù left used.
1 ê
× 0 -1 1 ú
3 ê ú
ëê 1 0 -1ûú
EQUATION1238 V1 EN-US (Equation 16)
Table continues on next page
1. The HV star (Y) connected winding will be used as the reference winding and
zero sequence currents shall be subtracted on that side
2. The LV winding is lagging for 150°
With the help of table 93, the following matrix equation can be written for this
power transformer:
where:
IDL1 is the fundamental frequency differential current in phase L1 (in W1 side primary
amperes)
IDL2 is the fundamental frequency differential current in phase L2 (in W1 side primary
amperes)
Table continues on next page
IDL3 is the fundamental frequency differential current in phase L3 (in W1 side primary
amperes)
IL1_W1 is the fundamental frequency phase current in phase L1 on the W1 side
IL2_W1 is the fundamental frequency phase current in phase L2 on the W1 side
IL3_W1 is the fundamental frequency phase current in phase L3 on the W1 side
IL1_W2 is the fundamental frequency phase current in phase L1 on the W2 side
IL2_W2 is the fundamental frequency phase current in phase L2 on the W2 side
IL3_W2 is the fundamental frequency phase current in phase L3 on the W2 side
Ur_W1 is transformer rated phase-to-phase voltage on the W1 side (setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on the W2 side (setting parameter)
As marked in equation 3 and equation 4, the first term on the right hand side of the
equation, represents the total contribution from the individual phase currents from
the W1 side to the fundamental frequency differential currents, compensated for
eventual power transformer phase shift. The second term on the right hand side of
the equation, represents the total contribution from the individual phase currents
from the W2 side to the fundamental frequency differential currents, compensated
for eventual power transformer phase shift and transferred to the power transformer
W1 side. The third term on the right hand side of the equation, represents the total
contribution from the individual phase currents from the W3 side to the
fundamental frequency differential currents, compensated for eventual power
transformer phase shift and transferred to the power transformer W1 side. These
current contributions are important, because they are used for calculation of
common bias current.
the no-load voltage Vn_W1 will be treated as a function of the actual load tap
changer position in equation and equation . Thus for every load tap changer
position a corresponding value for Ur_W1 will be calculated and used in the above
mentioned equations. By doing this, complete on-line compensation for load tap
changer movement is achieved. Differential protection will be ideally balanced for
every load tap changer position and no false differential current will appear
irrespective of actual load tap changer position.
Typically the minimum differential protection pickup for power transformer with
load tap changer is set between 30% to 40%. However with this load tap changer
compensation feature it is possible to set the differential protection in the IED more
sensitive with a pickup value of 15% to 20%.
Load tap changer position is measured within the IED by Tap changer control and
supervision, (TCLYLTC). Within this function block, the load tap changer position
value is continuously monitored to insure its integrity.
When any error in the load tap changer position is detected an alarm is given. This
signal shall be connected to the OLTCxAL input of the differential function block.
While OLTCxAL input has a logical value of one the differential protection
minimum pickup, originally defined by setting parameter IdMin, will be increased
by the set range of the load tap changer. Alternatively the differential current alarm
feature can be used to alarm for any problems in the whole load tap changer
compensation chain.
• two-winding differential protection in the IED can on-line compensate for one
load tap changer within the protected power transformer
• three-winding differential protection in the IED can on-line compensate for up
to two load tap changers within the protected power transformer
Fundamental frequency differential current level is monitored all the time within
the differential function. As soon as all three fundamental frequency differential
currents are above the set threshold defined by setting parameter IDiffAlarm a
delay on pickup timer is started. When the pre-set time, defined by setting
parameter tAlarmDelay, has expired the differential current alarm is generated and
output signal IDALARM is set to logical value one. This feature can be effectively
used to provide alarm when load tap changer position compensation is used and
something in the whole compensation chain goes wrong. This alarm can be as well
used with some additional IED configuration logic to desensitize the differential
function.
The bias current is calculated as the highest current amongst all individual winding
current contributions to the total fundamental frequency differential currents, as
shown in equation and equation . All individual winding current contributions are
already referred to the power transformer winding one side (power transformer HV
winding) and therefore they can be compared regarding their magnitudes. There are
six (or nine in the case of a three-winding transformer) contributions to the total
fundamental differential currents, which are the candidates for the common bias
current. The highest individual current contribution is taken as a common bias
(restrain) current for all three phases. This "maximum principle" makes the
differential protection more secure, with less risk to operate for external faults and
in the same time brings more meaning to the breakpoint settings of the operate -
restrain characteristic.
It shall be noted that if the zero-sequence currents are subtracted from the separate
contributions to the total differential current, then the zero-sequence component is
automatically eliminated from the bias current as well. This ensures that for
secondary injection from just one power transformer side the bias current is always
equal to the highest differential current regardless of the fault type. During normal
through-load operation of the power transformer, the bias current is equal to the
maximum load current from two (three) -power transformer windings.
For application with so called "T" configuration, that is, two restraint CT inputs
from one side of the protected power transformer, such as in the case of breaker-
and-a-half schemes the primary CT ratings can be much higher than the rating of
the protected power transformer. In order to determine the bias current for such T
configuration, the two separate currents flowing in the T-side are scaled down to
the protected power transform level by means of additional settings. This is done in
order to prevent unwanted de-sensitizing of the overall differential protection. In
addition to that, the resultant currents (the sum of two currents) into the protected
power transformer winding, which is not directly measured is calculated, and
included in the common bias calculation. The rest of the bias calculation procedure
is the same as in protection schemes without breaker-and-a-half arrangements.
To avoid unwanted trips for external earth-faults, the zero sequence currents should
be subtracted on the side of the protected power transformer, where the zero
sequence currents can flow at external earth -faults.
The zero sequence currents can be explicitly eliminated from the differential
currents and common bias current calculation by special, dedicated parameter
settings, which are available for every individual winding.
• the protected power transformer cannot transform the zero sequence currents
to the other side.
• the zero sequence currents can only flow on one side of the protected power
transformer.
In most cases, power transformers do not properly transform the zero sequence
current to the other side. A typical example is a power transformer of the star-delta
type, for example YNd1. Transformers of this type do not transform the zero
sequence quantities, but zero sequence currents can flow in the earthed star-
connected winding. In such cases, an external earth-fault on the star-side causes
zero sequence current to flow on the star-side of the power transformer, but not on
the other side. This results in false differential currents - consisting exclusively of
the zero sequence currents. If high enough, these false differential currents can
cause an unwanted disconnection of the healthy power transformer. They must
therefore be subtracted from the fundamental frequency differential currents if an
unwanted trip is to be avoided.
For delta windings this feature shall be enabled only if an earthing transformer
exists within the differential zone on the delta side of the protected power
transformer.
Removing the zero sequence current from the differential currents decreases to
some extent the sensitivity of the differential protection for internal earth -faults. In
order to counteract this effect to some degree, the zero sequence current is
subtracted not only from the three fundamental frequency differential currents, but
from the bias current as well.
The power transformer differential protection function uses two limits, to which
actual magnitudes of the three fundamental frequency differential currents are
compared at each execution of the function.
1. IdMin
2. EndSection1
3. EndSection2
4. SlopeSection2
5. SlopeSection3
operate current
[ times IBase ]
Operate
5
unconditionally
UnrestrainedLimit
4
Operate
3
conditionally
2
Section 1 Section 2 Section 3
SlopeSection3
1
IdMin
SlopeSection2 Restrain
0
0 1 2 3 4 5
en05000187-2.vsd
IEC05000187 V2 EN-US
where:
Section 1: This is the most sensitive part on the characteristic. In section 1, normal
currents flow through the protected circuit and its current transformers, and risk for
higher false differential currents is relatively low. An un-compensated on-load tap-
changer is a typical reason for existence of the false differential currents in this
section. The slope in section 1 is always zero percent.
• for internal faults, the operate (differential) currents are always with a good
margin above the operate - restrain characteristic
• for external faults, the false (spurious) operate currents are with a good margin
below the operate - restrain characteristic
• The external fault signal disappears and no DC components exist in the phase
currents.
• The differential currents become higher than the bias current.
external disturbance. Finally, the negative sequence currents are not affected by
symmetrical through-load currents.
1 2 3
where:
1. is the Negative Sequence Differential Currents
2. is the Negative Sequence current contribution from the W1 side
3. is the Negative Sequence current contribution from the W2 side
and where:
IDL1_NS is the negative sequence differential current in phase L1 (in
W1 side primary amperes)
IDL2_NS is the negative sequence differential current in phase L2 (in
W1 side primary amperes)
IDL3_NS is the negative sequence differential current in phase L3 (in
W1 side primary amperes)
INS_W1 is the negative sequence current on the W1 side in primary
amperes (phase L1 reference)
INS_W2 is the negative sequence current on the W2 side in primary
amperes (phase L1 reference)
Ur_W1 is the transformer rated phase-to-phase voltage on the W1
side (setting parameter)
Ur_W2 is the transformer rated phase-to-phase voltage on W2
side (setting parameter)
j ×120
o 1 3
a=e =- + j×
2 2
EQUATION1248 V1 EN-US (Equation 26)
Because the negative sequence currents always form the symmetrical three phase
current system on each transformer side (that is, negative sequence currents in
every phase will always have the same magnitude and be phase displaced for 120
electrical degrees from each other), it is only necessary to calculate the first
negative sequence differential current that is, IDL1_NS.
As marked in equation 25, the first term on the right hand side of the equation,
represents the total contribution of the negative sequence current from the W1 side
compensated for eventual power transformer phase shift. The second term on the
right hand side of the equation, represents the total contribution of the negative
sequence current from the W2 side compensated for eventual power transformer
phase shift and transferred to the power transformer W1 side. These negative
sequence current contributions are phasors, which are further used in directional
comparisons, to characterize a fault as internal or external. See section "Internal/
external fault discriminator" for more information.
1. IMinNegSeq
2. NegSeqROA
90 deg
120 deg
If one or the Internal/external
other of fault boundary
currents is too
low, then no
measurement
NegSeqROA
is done, and
(Relay
120 degrees
Operate
is mapped
Angle)
IMinNegSeq
External Internal
fault fault
region region
• If the negative sequence current contributions from the W1 and the W2 sides
are in phase, the fault is internal (that is, both phasors are within protected
zone)
• If the negative sequence currents contributions from W1 and W2 sides are 180
degrees out of phase, the fault is external (that is, W1 phasors is outside
protected zone)
For example, for any unsymmetrical external fault, ideally the respective negative
sequence current contributions from the W1 and W2 power transformer sides will
be exactly 180 degrees apart and equal in magnitude, regardless the power
transformer turns ratio and phase displacement. An example is shown in figure 42,
which shows trajectories of the two separate phasors representing the negative
sequence current contributions from the HV and LV sides of an Yd5 power
transformer (after compensation of the transformer turns ratio and phase
displacement) by using equation ) for an unsymmetrical external fault. Observe that
the relative phase angle between these two phasors is 180 electrical degrees at any
point in time. No current transformer saturation was assumed for this case.
"steady state"
for HV side 90
neg. seq. phasor
60
150 30
10
ms
180 0
0.1 kA
0.2 kA
0.3 kA
10 0.4 kA
ms
210 330
"steady state"
240 for LV side
270 neg. seq. phasor
en05000189.vsd
IEC05000189 V1 EN-US
Under external fault conditions, the relative angle is theoretically equal to 180
degrees. During internal faults, the angle shall ideally be 0 degrees, but due to
Dire ctiona l Compa ris on Crite rion: Inte rna l fa ult a s s e e n from the HV s ide
90
e xcurs ion
120 60
from 0 de gre e s
35 ms due to CT
s a tura tion
150 30
de finite ly
a n inte rna l
fa ult
180 0
trip c o mmand
in 12 ms
e xte rna l
fa ult Inte rna l fa ult
0.5 kA de cla re d 7 ms
re gion
210 330 a fte r inte rna l
fa ult occure d
1.0 kA
240 300
1.5 kA
270
HV s ide contribution to the tota l ne ga tive s e que nce diffe re ntia l curre nt in kA
Dire ctiona l limit (within the re gion de limite d by ± 60 de gre e s is inte rna l fa ult)
en05000190.vsd
IEC05000190 V1 EN-US
It shall be noted that additional security measures are implemented in the internal/
external fault discriminator algorithm in order to guarantee proper operation with
heavily saturated current transformers. The trustworthy information on whether a
fault is internal or external is typically obtained in about 10ms after the fault
inception, depending on the setting IminNegSeq, and the magnitudes of the fault
currents. During heavy faults, approximately 5ms time to full saturation of the
main CT is sufficient in order to produce a correct discrimination between internal
and external faults.
Two sub functions, which are based on the internal/external fault discriminator
with the ability to trip a faulty power transformer, are parts of the traditional power
transformer differential protection.
If the same fault has been positively recognized as internal, then the unrestrained
negative sequence differential protection places its own trip request.
Any block signals by the harmonic and/or waveform criteria, which can block the
traditional differential protection are overridden, and the differential protection
operates quickly without any further delay.
This logic guarantees a fast disconnection of a faulty power transformer for any
internal fault.
If the same fault has been classified as external, then generally, but not
unconditionally, a trip command is prevented. If a fault is classified as external, the
further analysis of the fault conditions is initiated. If all the instantaneous
differential currents in phases where start signals have been issued are free of
harmonic pollution, then a (minor) internal fault, simultaneous with a predominant
external fault can be suspected. This conclusion can be drawn because at external
faults, major false differential currents can only exist when one or more current
transformers saturate. In this case, the false instantaneous differential currents are
polluted by higher harmonic components, the 2nd, the 5th etc.
The sensitive, negative sequence current based turn-to-turn fault protection detects
the low level faults, which are not detected by the traditional differential protection
until they develop into more severe faults, including power transformer iron core.
The sensitive protection is independent from the traditional differential protection
and is a very good complement to it. The essential part of this sensitive protection
is the internal/external fault discriminator. In order to be activated, the sensitive
protection requires no start signal from the traditional power transformer biased
differential protection. If magnitudes of HV and LV negative sequence current
contributions are above the set limit for IminNegSeq, then their relative positions
are determined. If the disturbance is characterized as an internal fault, then a
separate trip request will be placed. Any decision on the way to the final trip
request must be confirmed several times in succession in order to cope with
eventual CT transients. This causes a short additional operating time delay due to
this security count. For very low level turn-to-turn faults the overall response time
of this protection is about 30ms.
The instantaneous differential currents are calculated from the instantaneous values
of the input currents in order to perform the harmonic analysis and waveform
analysis upon each one of them (see section "Harmonic and waveform block
criteria" for more information).
The instantaneous differential currents are calculated using the same matrix
expression as shown in equation and equation . The same matrices A, B and C are
used for these calculations. The only difference is that the matrix algorithm is fed
by instantaneous values of currents, that is, samples.
The two block criteria are the harmonic restrain and the waveform restrain. These
two criteria have the power to block a trip command by the traditional differential
protection, which produces start signals by applying the differential currents, and
the bias current, to the operate - restrain characteristic.
The harmonic restrain is the classical restrain method traditionally used with power
transformer differential protections. The goal is to prevent an unwanted trip
command due to magnetizing inrush currents at switching operations, or due to
magnetizing currents at over-voltages.
The magnetizing currents of a power transformer flow only on one side of the
power transformer and are therefore always the cause of false differential currents.
The harmonic analysis (the 2nd and the 5th harmonic) is applied to the
instantaneous differential currents. Typical instantaneous differential currents
during power transformer energizing are shown in figure 44. The harmonic
analysis is only applied in those phases where start signals have been set.For
example, if the content of the 2nd harmonic in the instantaneous differential current
of phase L1 is above the setting I2/I1Ratio, then a block signal is set for that phase,
which can be read as BLK2HL1 output of the differential protection.
After the transformer has been energized (the energizing period has elapsed and the
inrush currents have disappeared), the 2nd harmonic blocking is conditionally
activated if NegSeqDiffEn is set to On. When the fault cannot be identified as
internal or external, the 2nd harmonic blocking signal is activated only if the
differential current is smaller than the bias current. If the differential current
becomes equal to or higher than the bias current, the differential function will be
released regardless of the 2nd harmonic blocking signal.
with low rate-of-change in instantaneous differential current, which are typical for
the power transformer inrush currents. Block signals BLKWAVLx are set in those
phases where such behavior is detected. The algorithm does not require any end
user settings. The waveform algorithm is automatically adapted dependent only on
the power transformer rated data.
IEC05000343 V1 EN-US
The basic definition of the cross-blocking is that one of the three phases can block
operation (that is, tripping) of the other two phases due to the harmonic pollution of
the differential current in that phase (that is, waveform, 2nd or 5th harmonic
content). In differential algorithm the user can control the cross-blocking between
the phases via the setting parameter CrossBlockEn=On.
The transformer differential function has a built-in, advanced switch onto fault
feature. This feature can be enabled or disabled by a setting parameter SOTFMode.
When enabled this feature ensures quick differential protection tripping in cases
The built-in open CT feature can be enabled or disabled by the setting parameter
OpenCTEnable (Off/On). When enabled, this feature tries to prevent mal-operation
when a loaded main CT connected to Transformer differential protection is by
mistake open circuited on the secondary side. Note that this feature can only detect
interruption of one CT phase current at a time. If two or even all three-phase
currents of one set of CTs are accidentally interrupted at precisely the same time,
this feature cannot operate. Transformer differential protection generates a trip
signal if the false differential current is sufficiently high. An open CT circuit is
typically detected in 12–14 ms, and if the load in the protected circuit is relatively
high, about the nominal load, the unwanted trip cannot always be prevented. Still,
the information about what was the cause of the open CT secondary circuit, is vital.
lower than 50% of IdMin, the open CT condition cannot be detected. Therefore, the
Open CT algorithm only detects an open CT if the load on the power transformer is
10...110% of rated load and the differential current is higher than 50% of IdMin on
that phase. The search for an open CT starts 60 seconds (50 seconds in 60 Hz
systems) after the transformer is energized. The Open CT detection feature can also
be explicitly deactivated by setting: OpenCTEnable = 0 ( Off).
If an open CT is detected and the output OPENCT set to 1, then all the differential
functions are blocked, except the unrestrained (instantaneous) differential. An
alarm signal is also produced after a settable delay (tOCTAlarmDelay) to report to
operational personnel for quick remedy actions once the open CT is detected.
When the open CT condition is removed (that is, the previously open CT is
reconnected), the functions remain blocked for a specified interval of time, which
is also defined by a setting (tOCTResetDelay). This is to prevent an eventual mal-
operation after the reconnection of the previously open CT secondary circuit.
The open CT algorithm provides detailed information about the location of the
defective CT secondary circuit. The algorithm clearly indicates the IED side, CT
input and phase in which an open CT condition has been detected. These
indications are provided via the following outputs from the Transformer differential
protection function:
Once the open CT condition is declared, the algorithm stops to search for further
open CT circuits. It waits until the first open CT circuit has been corrected. Note
that once the open CT condition has been detected, it can be reset automatically
within the differential function. It is not possible to externally reset an open CT
condition. To reset the open CT circuit alarm automatically, the following
conditions must be fulfilled:
If an open CT has been detected in a separate group of three CTs, the algorithm is
reset either when the missing current returns to the normal value, or when all three
currents become zero. After the reset, the open CT detection algorithm starts again
to search for open CT circuits within the protected zone.
The simplified internal logics, for transformer differential protection are shown in
the following figures.
IDL2
Derive equation to calculate differential currents
individual windings
Open CT logic on W2 side
phase current
IDL1MAG
Fundamental frequency (phasor
based) Diff current, phase L1 &
ratio
IDL2MAG
Fundamental frequency (phasor
based) Diff current, phase L2 &
phase current contributions from
individual windings
IDL3MAG
Fundamental frequency (phasor
based) Diff current, phase L3 &
phase current contributions from
individual windings
MAX IBIAS
en06000554-3-en.vsd
IEC06000544 V3 EN-US
Figure 45: Treatment of measured currents within IED for transformer differential function
The following currents are inputs used in the power transformer differential
protection function. They must all be expressed in power system (primary) A.
1. Instantaneous values of currents (samples) from the HV, and LV sides for two-
winding power transformers, and from the HV, the first LV, and the second LV
side for three-winding power transformers.
2. Currents from all power transformer sides expressed as fundamental frequency
phasors with their real and imaginary parts. These currents are calculated
within the protection function by the fundamental frequency Fourier filters.
3. Negative sequence currents from all power transformer sides expressed as
phasors. These currents are calculated within the protection function by the
symmetrical components module.
BLKUNRES
IdUnre a TRIPUNREL1
b>a AND
b
IDL1MAG
IBIAS STL1
AND
BLOCK
BLKRES
TRIPRESL1
AND
OR 1
IDL1
to fault logic
2nd BLK2HL1
Switch on
Harmonic
Wave BLKWAVL1
block
5th BLK5HL1
Harmonic
Cross Block
Cross Block to L2 or L3
from L2 or L3 AND
OR
AND
OpCrossBlock=On
en06000545.vsd
IEC06000545 V1 EN-US
Internal/ EXTFAULT
Neg.Seq. Diff External INTFAULT
Current Fault
Contributions discrimin
ator TRNSSENS
t
&
OpNegSeqDiff=On
IBIAS
a
b>a
b
Constant
TRNSUNR
STL1 &
STL2
>1
STL3
IEC05000167-2-en.vsd
IEC05000167-TIFF V2 EN-US
TRIPRESL1
TRIPRESL2 TRIPRES
OR
TRIPRESL3
TRIPUNREL1
TRIPUNREL2 TRIPUNRE
OR
TRIPUNREL3
TRIP
TRNSSENS OR
TRNSUNR
en05000278.vsd
IEC05000278 V1 EN-US
STL1
STL2 START
OR
STL3
BLK2HL1
BLK2HL2 BLK2H
OR
BLK2HL3
BLK5HL1
BLK5HL2 BLK5H
OR
BLK5HL3
BLKWAVL1
BLKWAVL2 BLKWAV
OR
BLKWAVL3
IEC05000279-2-en.vsd
IEC05000279-TIFF V2 EN-US
contents (see the blocks with the text inside: 2nd Harmonic; Wave block and
5th Harmonic). If there is less harmonic pollution. than allowed by the settings
I2/I1Ratio, and I5/I1Ratio, (then the outputs from the blocks 2nd harmonic and
5th harmonic is 0) then it is assumed that a minor simultaneous internal fault
must have occurred. Only under these conditions a trip command is allowed
(the signal TRIPRESL1 is = 1). The cross-block logic scheme is automatically
applied under such circumstances. (This means that the cross block signals
from the other two phases L2 and L3 is not activated to obtain a trip on the
TRIPRESL1 output signal in figure 46)
6. All start and blocking conditions are available as phase segregated as well as
common (that is three-phase) signals.
IDL1 MAG
a
a>b
I Diff Alarm b
IDL3 MAG
a
a>b
I Diff Alarm b
en06000546.vsd
IEC06000546 V1 EN-US
M13046-1 v12
SYMBOL-CC V2 EN-US
by wiring. Actually all CT secondary circuits which are involved in the differential
scheme are connected in parallel. External series resistor, and a voltage dependent
resistor which are both mounted externally to the IED, are also required.
The external resistor unit shall be ordered under IED accessories in the Product
Guide.
HZPDIF
ISI* TRIP
BLOCK ALARM
BLKTR MEASVOLT
IEC05000363-2-en.vsd
IEC05000363 V2 EN-US
PID-6990-INPUTSIGNALS v1
PID-6990-OUTPUTSIGNALS v1
PID-6990-SETTINGS v1
M13075-3 v11
High impedance protection system is a simple technique which requires that all
CTs, used in the protection scheme, have relatively high knee point voltage, similar
magnetizing characteristic and the same ratio. These CTs are installed in all ends of
the protected object. In order to make a scheme all CT secondary circuits belonging
to one phase are connected in parallel. From the CT junction points a measuring
branch is connected. The measuring branch is a series connection of one variable
setting resistor (or series resistor) RS with high ohmic value and an over-current
element. Thus, the high impedance differential protection responds to the current
flowing through the measuring branch. However, this current is result of a
differential voltage caused by this parallel CT connection across the measuring
branch. Non-linear resistor (that is, metrosil) is used in order to protect entire
scheme from high peak voltages which may appear during internal faults. Typical
high impedance differential scheme is shown in Figure 52. Note that only one
phase is shown in this figure.
RS
3 U
I
1
I> (50) 5
2
GUID-5CEAF088-D92B-45E5-B98F-3083894A694C V1 EN-US
Due to the parallel CT connections the high impedance differential relay can only
measure one current and that is the relay operating quantity. That means that there
is no any stabilizing quantity (that is, bias) in high-impedance differential
protection schemes. Therefore in order to guaranty the stability of the differential
relay during external faults the operating quantity must not exceed the set pickup
value. Thus, for external faults, even with severe saturation of some of the current
transformers, the voltage across the measuring branch shall not rise above the relay
set pickup value. To achieve that a suitable value for setting resistor RS is selected
in such a way that the saturated CT secondary winding provides a much lower
impedance path for the false differential current than the measuring branch. In case
of an external fault causing current transformer saturation, the non-saturated
current transformers drive most of the spill differential current through the
secondary winding of the saturated current transformer and not through the
measuring brunch of the relay. The voltage drop across the saturated current
transformer secondary winding appears also across the measuring brunch, however
it will typically be relatively small. Therefore, the pick-up value of the relay has to
be set above this false operating voltage.
See the application manual for operating voltage and sensitivity calculation.
The logic diagram shows the operation principles for the 1Ph High impedance
differential protection function HZPDIF, see Figure 53.
The function utilizes the raw samples from the single phase current input connected
to it. Thus the twenty samples per fundamental power system cycle are available to
the HZPDIF function. These current samples are first multiplied with the set value
for the used stabilizing resistor in order to get voltage waveform across the
measuring branch. The voltage waveform is then filtered in order to get its RMS
value. Note that used filtering is designed in such a way that it ensures complete
removal of the DC current component which may be present in the primary fault
current. The voltage RMS value is then compared with set Alarm and Trip
thresholds. Note that the TRIP signal is intentionally delayed on drop off for 30 ms
within the function. The measured RMS voltage is available as a service value
from the function. The function has block and trip block inputs available as well.
IEC05000301 V1 EN-US
Figure 53: Logic diagram for 1Ph High impedance differential protection
HZPDIF
M13081-1 v12
7.3.1 Identification
M14843-1 v6
SYMBOL-AA V1 EN-US
M13047-3 v19
REFPDIF can also protect autotransformers. Five currents are measured at the most
complicated configuration as shown in Figure 54.
CT CT
YNdx
CT CB CB
Y d
CB CB
Autotransformer
CT
IED
IEC05000058-2-en.vsd
IEC05000058-2 V1 EN-US
REFPDIF
I3P* TRIP
I3PW1CT1* START
I3PW1CT2* DIROK
I3PW2CT1* BLK2H
I3PW2CT2* IRES
BLOCK IN
IBIAS
IDIFF
ANGLE
I2RATIO
IEC06000251_2_en.vsd
IEC06000251 V2 EN-US
PID-3772-INPUTSIGNALS v5
PID-3772-OUTPUTSIGNALS v5
PID-3772-SETTINGS v5
7.3.7.1 Fundamental principles of the restricted earth fault protection M5447-3 v14
Restricted earth fault protection, low impedance function (REFPDIF) detects earth
faults on earthed power transformer windings, most often an earthed star winding.
REFPDIF is a unit protection of the differential type. Since REFPDIF is based on
the zero sequence current, which theoretically only exists in case of an earth fault,
REFPDIF can be made very sensitive regardless of normal load currents. It is the
fastest protection a power transformer winding can have. The high sensitivity and
the high speed tend to make such a protection unstable. Special measures must be
taken to make it insensitive to conditions for which it should not operate, for
example, heavy through faults of phase-to-phase type or heavy external earth
faults.
The following facts may be observed from Figure 56 and Figure 57, where the
three line CTs are shown as connected together in order to measure the residual 3Io
current, for the sake of simplicity.
Power Izs1
L2 L2
system
Izs1 L3
L3
3Izs1
zone of protection
Izs2 Izs1
L1 L1
Power Izs2 Izs1
L2 L2
system
Izs2 Izs1 L3
L3
3Izs1
1. For an external earth fault (Figure 56), the residual current 3Io and the neutral
current IN have equal magnitude, but they are seen within the IED as 180
degrees out-of-phase if the current transformers are connected as in Figure 56,
which is the ABB recommended connection. The differential current becomes
zero as both CTs ideally measure exactly the same component of the earth
fault current.
2. For an internal fault, the total earth fault current is composed generally of two
zero sequence currents. One zero sequence current (3IZS1) flows towards the
power transformer neutral point and into the earth, while the other zero
sequence current (3IZS2) flows into the connected power system. These two
primary currents can be expected to have approximately opposite directions
(about the same zero sequence impedance angle is assumed on both sides of
the earth fault). However, on the secondary CT sides of the current
transformers, they will be approximately in phase if the current transformers
are oriented as in Figure 54, which is the orientation recommended by ABB.
The magnitudes of the two currents may be different, dependent on the
magnitudes of zero sequence impedances on both sides. No current can flow
towards the power system, if the only point where the system is earthed, is at
the protected power transformer. Likewise, no current can flow into the power
system, if the winding is not connected to the power system (circuit breaker
open and power transformer energized from the other side).
3. For both internal and external earth faults, the current in the neutral connection
IN always has the same direction, which is towards the earth (except in case of
autotransformers where the direction can vary).
4. The two internally processed zero sequence currents are 3Io and IN. The
vectorial sum is the REFPDIF differential current, which is equal to Idiff = IN
+3Io .
The line zero sequence (residual) current is calculated from 3 line (terminal)
currents. A bias quantity must give stability against false operations due to high
through fault currents. To stabilize REFPDIF at external faults, a fixed bias
characteristic is implemented.
REFPDIF should also be stable against heavy phase-to-phase internal faults, not
including earth. These faults may also give false zero sequence currents due to
saturated line CTs. Such faults, however are without neutral current, and can thus
be eliminated as a source of danger.
7.3.7.2 Restricted earth fault protection, low impedance differential protection M5447-20 v13
REFPDIF has only one operate-bias characteristic, which is described in the table
106 and shown in Figure 58.
Table 106: Data of the operate-bias characteristic of REFPDIF
Default sensitivity Max. base Min. base sensitivity End of zone First slope Second
Idmin (zone 1) sensitivity Idmin Idmin (zone 1) 1 slope
(zone 1)
% IBase % IBase % IBase % IBase % %
30 4 100 125 70 100
operate current in pu
4 operate
1
minimum base sensitivity 100 %
default base sensitivity 30 % first slope block
maximum base sensitivity 4 %
0 1 2 3 4 5 6
IEC98000017-5-en.vsdx
IEC98000017 V5 EN-US
Figure 58: Operate - bias characteristic of the Restricted earth fault protection,
low impedance REFPDIF
Idiff = IN + 3 Io
EQUATION1533 V1 EN-US (Equation 27)
where:
where the signals are defined in the input and output signal tables for REFPDIF.
current transformers operate. Dependent on the magnitude of the bias current, the
corresponding zone (section) of the operate-bias characteristic is applied, when
deciding whether to trip, or not to trip. In general, the higher the bias current, the
higher the differential current required to produce a trip.
The bias current is the highest current of all separate input currents to REFPDIF,
that is, of current in phase L1, phase L2, phase L3, and the current in the neutral
point (designated as IN in Figure 56 and in Figure 57).
If there are two feeders included in the zone of protection of REFPDIF, as in case
of an auto-transformer with two feeders included on both sides, then the respective
bias current is found as the relatively highest of the following currents:
1
current[1] = max (I3PW1CT1) ×
CTFactorPri1
EQUATION1526 V1 EN-US (Equation 28)
1
current[2] = max (I3PW1CT2) ×
CTFactorPri2
EQUATION1527 V1 EN-US (Equation 29)
1
current[3] = max (I3PW2CT1) ×
CTFactorSec1
EQUATION1528 V1 EN-US (Equation 30)
1
current[4] = max (I3PW2CT2) ×
CTFactorSec2
EQUATION1529 V1 EN-US (Equation 31)
current[5] = IN
EQUATION1530 V1 EN-US (Equation 32)
The bias current is thus generally equal to none of the input currents. If all primary
ratings of the CTs were equal to IBase, then the bias current would be equal to the
highest current in Amperes. IBase shall be set equal to the rated current of the
protected winding where REFPDIF function is applied.
External faults are more common than internal earth faults for which the restricted
earth fault protection should operate. It is important that the restricted earth fault
protection remains stable during heavy external earth and phase-to-phase faults,
and also when such a heavy external fault is cleared by some other protection such
as overcurrent, or earth fault protection. The conditions during a heavy external
fault, and particularly immediately after the clearing of such a fault may be
complex. The circuit breaker’s poles may not open exactly at the same moment,
some of the CTs may still be highly saturated, and so on.
The detection of external earth faults is based on the fact that for such a fault a high
neutral current appears first, while a false differential current only appears if one or
more current transformers saturate.
An external earth fault is thus assumed to have occurred when a high neutral
current suddenly appears, while at the same time the differential current Idiff
remains low, at least for a while. This condition must be detected before a trip
request is placed within REFPDIF. Any search for external fault is aborted if a trip
request has been placed. A condition for a successful detection is that it takes not
less than 4ms for the first CT to saturate.
For an internal earth fault, a true differential current develops immediately, while
for an external fault it only develops if a CT saturates. If a trip request comes first,
before an external fault could be positively detected, then it must be an internal
fault.
If an external earth fault has been detected, then the REFPDIF is temporarily
desensitized.
For an external earth faults with no CT saturation, the residual current in the lines
(3Io) and the neutral current (IN in Figure 56) are theoretically equal in magnitude
and are 180 degrees out-of-phase. The current in the neutral (IN) serves as a
directional reference because it has the same direction for both internal and
external earth faults. The directional criterion in REFPDIF protection makes it a
current-polarized protection.
However, if one or more CTs saturate under external fault conditions, then the
measured currents 3Io and IN may no longer be equal, nor will their positions in the
complex plane be exactly 180 degrees apart. There is a risk that the resulting false
differential current Idiff enters the operate area of the operate-restrain characteristic
under external fault conditions. If this happens, a directional test may prevent a
malfunction.
1. a trip request signal has been issued (REFPDIF function START signal set to
1)
2. the residual current in lines (3Io) is at least 3% of the IBase current.
If a directional check is either unreliable or not possible to do, due to too small
currents, then the direction is cancelled as a condition for an eventual trip.
When energizing a transformer a false differential current may appear in earth fault
protection, low impedance function (REFPDIF). The phase CTs may saturate due
to a high DC component with a long duration, but the current through the neutral
CT does not have either the same DC component or the same amplitude and the
risk for saturation of this CT is not as high. As a result, the differential current due
to the saturation may be so high that it reaches the operate characteristic. A
calculation of the content of 2nd harmonic in the neutral current is made when the
neutral current, residual current and bias current are within some windows and
some timing criteria are fulfilled. If the ratio between second and fundamental
harmonic exceeds 40%, REFPDIF is blocked.
1. Check if current in the neutral Ineutral (IN) is less than 50% of the base
sensitivity Idmin. If yes, only service values are calculated, and rest of the
REFPDIF algorithm is not executed.
2. If current in the Ineutral (IN) is more than 50% of Idmin, then determine the
bias current Ibias.
3. Determine the differential (operate) current Idiff as a phasor, and calculate its
magnitude.
4. Check if the point P(Ibias, Idiff) is above the operate-bias characteristic. If yes,
increment the trip request counter by 1. If the point P(Ibias, Idiff) is found to
be below the operate-bias characteristic, then the trip request counter is reset to
zero.
5. If the trip request counter is still zero, search for an eventual heavy external
earth fault. The search is only made if the neutral current is at least 50% of the
Idmin current. If an external earth fault has been detected, a flag is set which
remains set until the external fault has been cleared. The external fault flag is
reset to zero when Ineutral falls below 50% of the base sensitivity Idmin. Any
search for an external fault is aborted if trip request counter is greater than
zero.
6. As long as the external fault persists, an additional temporary trip condition is
introduced. This means that REFPDIF is temporarily desensitized.
7. If point P(Ibias, Idiff) is found to be above the operate-bias characteristic), so
that trip request counter is greater than zero, a directional check can be made.
The directional check is made only if Iresidual (3Io) is more than 3% of the
IBase current. If the result of the check means “external fault”, then the
internal trip request is reset. If the directional check cannot be executed, then
direction is no longer a condition for a trip.
8. When neutral current, residual current and bias current are within some
windows and some timing criteria are fulfilled, the ratio of 2nd to fundamental
harmonic is calculated. If it is found to be above 60%, the trip request counter
is reset and TRIP remains zero.
9. Finally, a check is made if the trip request counter is equal to, or higher than 2.
If yes, and at the same instance of time tREFtrip, the actual bias current at this
instance of time tREFtrip is at least 50% of the highest bias current Ibiasmax
(Ibiasmax is the highest recording of any of the three phase currents measured
during the disturbance), then REFPDIF sets output TRIP to 1. If the counter is
less than 2, the TRIP signal remains zero.
M13062-1 v19
7.4.1 Identification
GUID-3081E62B-3E96-4615-97B8-2CCA92752658 v2
Additional security logic for differential protection (LDRGFC) can help the
security of the protection especially when the communication system is in
abnormal status or for example when there is unspecified asymmetry in the
communication link. It helps to reduce the probability for mal-operation of the
protection. LDRGFC is more sensitive than the main protection logic to always
release operation for all faults detected by the differential function. LDRGFC
consists of four sub functions:
Phase-to-phase current variation takes the current samples as input and it calculates
the variation using the sampling value based algorithm. Phase-to-phase current
variation function is major one to fulfill the objectives of the startup element.
Zero sequence criterion takes the zero sequence current as input. It increases the
security of protection during the high impedance fault conditions.
Low voltage criterion takes the phase voltages and phase-to-phase voltages as
inputs. It increases the security of protection when the three-phase fault occurred
on the weak end side.
Low current criterion takes the phase currents as inputs and it increases the
dependability during the switch onto fault case of unloaded line.
The differential function can be allowed to trip as no load is fed through the line
and protection is not working correctly.
Features:
LDRGFC
I3P* START
U3P* STCVL1L2
BLOCK STCVL2L3
BLKCV STCVL3L1
BLKUC STUC
BLK3I0 ST3I0
BLKUV STUV
REMSTUP
IEC14000015-1-en.vsd
IEC14000015 V1 EN-US
7.4.4 Signals
PID-3558-INPUTSIGNALS v9
PID-3558-OUTPUTSIGNALS v9
7.4.5 Settings
PID-3558-SETTINGS v9
Additional security logic for differential protection (LDRGFC) takes the current
samples, current RMS values, phase voltage values, phase-to-phase voltage values,
zero sequence current and remote side startup signals as inputs.
Startup signal becomes activated when any one of the current variation startup
signal, zero sequence current startup signal, voltage startup signal, and current
startup signal is activated.
Phase-to-phase current variation takes current samples and generates the startup
signal by comparing with the start value.
If the zero sequence current value is greater than the start value of zero sequence
current then the zero sequence current startup signal will be activated.
Voltage startup signal becomes activated when the any of phase voltage and line
voltage is less than the voltage start value and the remote startup signal has to be
activated.
Current startup signal becomes activated when the current value in all phases is
less than current start value.
Phase-to-phase current variation one is main startup element. It covers most of the
abnormal status of the system. The phase-to-phase current variation fails in high
impedance faults, three-phase fault on weak side and switch onto fault on unloaded
line because of low sensitivity in these cases.
Phase-to-phase current variation takes the current samples as input and the signal is
evaluated using the sampling value based algorithm.
Where:
ΔiФФ sampling value of phase-to-phase current variation
ΔIZD setting of fixed threshold, which corresponds to setting ICV>. The default value for
the setting is 0.2·IBase, where IBase is the base current.
ΔIT float threshold
1 2T -1
DI T = å | DiFF (t - n) |
T n =T
EQUATION2256 V1 EN-US
Where:
T count of sample values in one cycle
Di (k ) = [i ( k ) - i (k - N )] - [i (k - N ) - i (k - 2 N )]
= i ( k ) - 2i ( k - N ) + i (k - 2 N )
EQUATION2257 V1 EN-US
tCV
STCVL1L2
t
cont
OR STCV
cont
IEC10000295-1-en.vsd
IEC10000295 V1 EN-US
tCV is the time setting for the change of current criterion. Phase current samples
are included in input signal I3P.
Zero sequence criterion is mainly for detection of remote IED high resistance faults
or some gradual faults. The criterion takes the zero sequence current as input. Zero
sequence current is compared with I3I0> for the t3I0 time to generate the zero
sequence current startup signal.
I3P a
a>b t3I0
I3IO> b ST3I0
AND t
BLK3I0
BLOCK OR
IEC09000778-2-en.vsd
IEC09000778 V2 EN-US
Here I3I0> is the setting of the maximum possible non-faulted zero sequence
current for the protected line. The default value for this setting is 0.1 · IBase where
IBase is the rated current of the CT.
t3I0 is the time setting for the zero sequence current criterion.
The zero sequence current criterion can be blocked by activating the BLK3I0 input
signal.
Low voltage criterion is mainly for detection of the three phase faults occurring on
weak side with pre fault no load condition. The low voltage criterion takes the
voltage phase values, voltage phase-to-phase values and remote startup signals as
inputs. The logic for low voltage criterion is shown below:
U3P (UPhN) a
a<b
UPhN< b
OR
U3P (UPhPh) a
a<b
UPhPh< b
tUV STUV
REMSTUP (Recived)
AND t
BLKUV
BLOCK OR
IEC09000779-2-en.vsd
IEC09000779 V2 EN-US
Voltage phase value is compared with the start value of voltage phase and voltage
phase-to-phase value is compared with the start value of voltage phase-to-phase. If
any of the phase voltage or phase-to-phase voltages is below the set voltage levels
for some time duration (tUV) then the low voltage START signal becomes
activated after receiving the remote startup signal. Low voltage criterion can be
blocked by activating BLKUV input signal.
If there are more than one remote IED, all the startup signals of the remote ends are
logically OR to obtain the REMSTUP signal from the remote side as input.
The current in each phase is compared to the set current level. If all currents are
below setting IUC<, the STUC output is activated after the set delay tUC.
I3P
a
a<b tUC
IUC< b STUC
AND t
BLKUC
BLOCK OR
IEC09000780-2-en.vsd
IEC09000780 V2 EN-US
The configuration for the additional security logic for differential protection is
shown in Figure 64. The function will release tripping of the line differential
protection up to the end of timer tStUpReset.
Phase-phase STCV
i
current variation
Low current
criterion STUC
I0 <
REMSTUP
IEC10000296-2-en.vsd
IEC10000296 V2 EN-US
Figure 64: Additional security logic for differential protection. Logic diagram for
start up element.
S00346 V1 EN-US
S00346 V1 EN-US
Z<->
IEC09000167 V1 EN-US
Forward
operation
Reverse
operation
en05000034.vsd
IEC05000034 V1 EN-US
Figure 65: Typical quadrilateral distance protection zone with Phase selection
with load encroachment function FDPSPDIS activated
The independent measurement of impedance for each fault loop together with a
sensitive and reliable built-in phase selection makes the function suitable in
applications with single-phase autoreclosing.
SEMOD115983-4 v8
ZMQPDIS
I3P* TRIP
U3P* TRL1
BLOCK TRL2
VTSZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
IEC06000256-2-en.vsd
IEC06000256 V2 EN-US
ZMQAPDIS
I3P* TRIP
U3P* TRL1
BLOCK TRL2
VTSZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
IEC09000884-1-en.vsd
IEC09000884 V1 EN-US
The two inputs I3P — Three phase group signal for current and
U3P — Three phase group signal for voltage, must be connected to
non-adaptive SMAI blocks if ANY OF THE ZONES are set for
directional operation. That is, the parameter DFTReference in used
SMAI must be set to InternalDFTRef. If adaptive SMAI block is
used this might result in a wrong directional and reach evaluation.
SEMOD54537-4 v5
ZDRDIR
I3P* STDIRCND
U3P*
IEC10000007-2-en.vsd
IEC10000007 V2 EN-US
8.1.4 Signals
PID-3651-INPUTSIGNALS v6
PID-3651-OUTPUTSIGNALS v6
PID-3650-INPUTSIGNALS v6
PID-3650-OUTPUTSIGNALS v6
PID-3545-INPUTSIGNALS v6
PID-3545-OUTPUTSIGNALS v5
8.1.5 Settings
GUID-62142086-79A9-46FF-A14F-BA0CDD6B6466 v1
Signals and settings for ZMQPDIS are valid for zone 1 while
signals and settings for ZMQAPDIS are valid for zone 2 - 5
PID-3651-SETTINGS v6
PID-3650-SETTINGS v6
PID-3545-SETTINGS v6
The execution of the different fault loops within the IED are of full scheme type,
which means that each fault loop for phase-to-earth faults and phase-to-phase faults
for forward and reverse faults are executed in parallel.
IEC05000458-2-en.vsd
IEC05000458 V2 EN-US
Figure 69: The different measuring loops at phase-to-earth fault and phase-to-
phase fault.
The use of full scheme technique gives faster operation time compared to switched
schemes which mostly uses a start element to select correct voltages and current
depending on fault type. Each distance protection zone performs like one
independent distance protection IED with six measuring elements.
The distance measuring zone includes six impedance measuring loops; three
intended for phase-to-earth faults, and three intended for phase-to-phase as well as,
three-phase faults.
The distance measuring zone will essentially operate according to the non-
directional impedance characteristics presented in figure 70 and figure 71. The
phase-to-earth characteristic is illustrated with the full loop reach while the phase-
to-phase characteristic presents the per phase reach.
X (Ohm/loop)
R1+Rn
RFPE RFPE
X0-X1
Xn =
3
X1+Xn R0-R1
Rn =
3
jN jN
R (Ohm/loop)
RFPE RFPE
X1+Xn
RFPE RFPE
IEC11000427-1-en.vsd
R1+Rn
IEC11000427 V1 EN-US
X (Ohm/phase)
RFPP R1 RFPP
2 2
X 0 PE - X 1RVPE
XNRV =XX00PEPG--X31XRVPE
1RVPG
XNRV =
XNRV =
33
XX
X00PE
0PE
PG --1X
-X 11FWPE
XFWPE
FWPG
XNFW===
XNFW
XNFW
3
X1 3 3
j j
R (Ohm/phase)
RFPP RFPP
2 2
X1
RFPP R1 RFPP
2 2
IEC11000428-1-en.vsd
IEC11000428 V1 EN-US
The fault loop reach with respect to each fault type may also be presented as in
figure 72. Note in particular the difference in definition regarding the (fault)
resistive reach for phase-to-phase faults and three-phase faults.
IL1 R1 + j X1
Phase-to-earth
UL1
element
Phase-to-earth
fault in phase L1 RFPE
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 )
IL1 R1 + j X1 Phase-to-phase
UL1 element L1-L2
Phase-to-phase
fault in phase RFPP
L1-L2 IL2
UL2 (Arc resistance)
R1 + j X1
The R1 and jX1 in figure 72 represents the positive sequence impedance from the
measuring point to the fault location. The settings and RFPP are the eventual fault
resistances in the faulty place.
Regarding the illustration of three-phase fault in figure 72, there is of course fault
current flowing also in the third phase during a three-phase fault. The illustration
merely reflects the loop measurement, which is made phase-to-phase.
X X X
R R R
IEC05000182-2-en.vsdx
IEC05000182 V2 EN-US
For zone 1 with load compensation feature the additional criterion applies, that all
phase-to-earth loops will be blocked when IN < IMinOpIN, regardless of the phase
currents.
ILn is the RMS value of the current in phase Ln. IN is the RMS value of the vector
sum of the three-phase currents, that is, residual current 3I0.
ILmLn is the RMS value of the vector difference between phase currents Lm and
Ln.
Fault loop equations use the complex values of voltage, current, and changes in the
current. Apparent impedances are calculated and compared with the set limits. The
apparent impedances at phase-to-phase faults follow equation 33 (example for a
phase L1 to phase L2 fault).
UL1 – UL2
Zapp = -------------------------
I L1 – IL2
EQUATION1222 V1 EN-US (Equation 33)
Here U and I represent the corresponding voltage and current phasors in the
respective phase Ln (n = 1, 2, 3)
U L1
Z app =
I L1 + I N × KN
EQUATION1223 V2 EN-US (Equation 34)
Where:
are the phase voltage, phase current and residual current present to the IED
U L1
I L1
IN
KN
is defined as:
Z 0 - Z1
KN =
3 × Z1
EQUATION-2105 V2 EN-US
Z 0 = R 0 + jX 0
EQUATION2106 V2 EN-US
Z 1 = R1 + jX 1
EQUATION2107 V2 EN-US
Where
R0 is setting of the resistive zero sequence reach
X0 is setting of the reactive zero sequence reach
R1 is setting of the resistive positive sequence reach
Here IN is a phasor of the residual current in IED point. This results in the same
reach along the line for all types of faults.
The formula given in equation 34 is only valid for radial feeder application without
load. When load is considered in the case of single phase-to-earth fault,
conventional distance protection might overreach at exporting end and underreach
at importing end. The IED has an adaptive load compensation which increases the
security in such applications.
Measuring elements receive current and voltage information from the A/D
converter. The check sums are calculated and compared, and the information is
distributed into memory locations. For each of the six supervised fault loops,
sampled values of voltage (U), current (I), and changes in current between samples
(DI) are brought from the input memory and fed to a recursive Fourier filter.
The filter provides two orthogonal values for each input. These values are related
to the loop impedance according to equation 35,
X Di
U = R × i + ------ × -----
w 0 Dt
EQUATION1224 V1 EN-US (Equation 35)
X D Re ( I )
Re ( U ) = R × Re ( I ) + ------ × ------------------
w0 Dt
X DIm ( I )
Im ( U ) = R × Im ( I ) + ------ × -----------------
w0 Dt
with
w0 = 2 × p × f 0
EQUATION356 V1 EN-US (Equation 38)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real
value of the voltage and substitutes it in the equation for the imaginary part. The
equation for the Xm measured reactance can then be solved. The final result is
equal to:
Im ( U ) × DRe ( I ) – Re ( U ) × D Im ( I )
R m = ------------------------------------------------------------------------------------
DRe ( I ) × Im ( I ) – D Im ( I ) × Re ( I )
EQUATION357 V1 EN-US (Equation 39)
Re ( U ) × Im ( I ) – Im ( U ) × Re ( I )
Xm = w 0 × Dt × -------------------------------------------------------------------------------
DRe ( I ) × Im ( I ) – DIm ( I ) × Re ( I )
EQUATION358 V1 EN-US (Equation 40)
The calculated Rm and Xm values are updated each sample and compared with the
set zone reach. The adaptive tripping counter counts the number of permissive
tripping results. This effectively removes any influence of errors introduced by the
capacitive voltage transformers or by other factors.
For the L1-L2 element, the equation in forward direction is according to.
where:
ArgDir is the setting for the lower boundary of the forward directional characteristic, by default
set to 15 (= -15 degrees) and
ArgNegRes is the setting for the upper boundary of the forward directional characteristic, by default
set to 115 degrees, see figure 74.
is positive sequence phase voltage in phase L1
U 1L1
is positive sequence memorized phase voltage in phase L1
U 1L1M
is phase current in phase L1
I L1
is voltage difference between phase L1 and L2 (L2 lagging L1)
U 1L1L 2
is memorized voltage difference between phase L1 and L2 (L2 lagging L1)
U 1L1L 2 M
is current difference between phase L1 and L2 (L2 lagging L1)
I L1L 2
The setting of ArgDir and ArgNegRes is by default set to 15 (= -15) and 115
degrees respectively (as shown in figure 74). It should not be changed unless
system studies have shown the necessity.
ZDRDIR gives binary coded directional information per measuring loop on the
output STDIRCND.
STDIR= STFWL1*1+STFWL2*2+STFWL3*4+STFWL1L2*8+
+STFWL2L3*16+STFWL3L1*32+STRVL1*64+STRVL2*128+
+STRVL3*256+STRVL1L2*512+STRVL2L3*1024+STRVL3L1*2048
ArgNegRes
ArgDir
R
en05000722.vsd
IEC05000722 V1 EN-US
Figure 74: Setting angles for discrimination of forward and reverse fault in
Directional impedance quadrilateral function ZDRDIR
The polarizing voltage is available as long as the positive sequence voltage exceeds
5% of the set base voltage UBase. So the directional element can use it for all
unsymmetrical faults including close-in faults.
For close-in three-phase faults, the U1L1M memory voltage, based on the same
positive sequence voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is
restored.
• If the current is still above the set value of the minimum operating current
(between 10 and 30% of the set IED rated current IBase), the condition seals
in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element
in the reverse direction remains in operation.
• If the current decreases below the minimum operating value, the memory
resets until the positive sequence voltage exceeds 10% of its rated value.
The design of the distance protection zones are presented for all measuring loops:
phase-to-earth as well as phase-to-phase.
Phase-to-earth related signals are designated by L1N, L2N and L3N. The phase-to-
phase signals are designated by L1L2, L2L3, and L3L1.
Two types of function block, ZMQPDIS and ZMQAPDIS, are used in the IED.
ZMQPDIS is used for zone 1 and ZMQAPDIS for zone 2 - 5.
The STCND input signal represents a connection of six different integer values
from Phase selection with load encroachment, quadrilateral characteristic function
FDPSPDIS within the IED, which are converted within the zone measuring
function into corresponding boolean expressions for each condition separately.
Input signal STCND is connected to FDPSPDIS or FMPSPDIS function output
STCNDZ.
The input signal DIRCND is used to give condition for directionality for the
distance measuring zones. The signal contains binary coded information for both
forward and reverse direction. The zone measurement function filters out the
relevant signals depending on the setting of the parameter OperationDir. It must be
configured to the STDIR output on ZDRDIR function.
STZMPP
OR
STCND
AND STNDL1L2
L1L2
STNDL2L3
L2L3 AND
AND STNDL1N
L1N
AND STNDL2N
L2N
STNDL3N
L3N AND
OR STPE
OR
VTSZ STND
OR AND
BLOCK
BLOCFUNC BLK
99000557-2.vsd
IEC99000557-TIFF V3 EN-US
Composition of the phase start signals for a case, when the zone operates in a non-
directional mode, is presented in figure 76.
IEC00000488-TIFF V1 EN-US
Results of the directional measurement enter the logic circuits, when the zone
operates in directional (forward or reverse) mode, as shown in figure 77.
STNDL1N
AND
DIRL1N
STZMPE.
OR
STNDL2N
DIRL2N AND
STNDL3N 15 ms
OR STL1
AND AND t
DIRL3N
STNDL1L2
DIRL1L2 AND 15 ms
OR STL2
AND t
STNDL2L3
DIRL2L3 AND
15 ms
OR STL3
STNDL3L1 AND t
DIRL3L1 AND
STZMPP
OR
BLK
15 ms
OR START
AND t
IEC09000888-2-en.vsd
IEC09000888 V2 EN-US
Tripping conditions for the distance protection zone one are symbolically presented
in figure 78.
Timer tPP=On
STZMPP AND tPP
AND
t
BLOCFUNC
OR OR
tPE
t
AND
Timer tPE=On AND
STZMPE 15ms
BLKTR AND t
TRIP
BLK OR
IEC09000887-3-en.vsdx
IEC09000887 V3 EN-US
M13842-1 v15
8.2.1 Identification
SYMBOL-DD V1 EN-US
The operation of transmission networks today is in many cases close to the stability
limit. Due to environmental considerations, the rate of expansion and
reinforcement of the power system is reduced, for example, difficulties to get
permission to build new power lines. The ability to accurately and reliably classify
the different types of fault, so that single pole tripping and autoreclosing can be
used plays an important role in this matter. Phase selection, quadrilateral
characteristic with fixed angle (FDPSPDIS) is designed to accurately select the
proper fault loop in the distance function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may make
fault resistance coverage difficult to achieve. Therefore, FDPSPDIS has a built-in
algorithm for load encroachment, which gives the possibility to enlarge the
resistive setting of both the phase selection and the measuring zones without
interfering with the load.
The extensive output signals from the phase selection gives also important
information about faulty phase(s), which can be used for fault analysis.
FDPSPDIS
I3P* TRIP
U3P* START
BLOCK STFWL1
DIRCND STFWL2
STFWL3
STFWPE
STRVL1
STRVL2
STRVL3
STRVPE
STNDL1
STNDL2
STNDL3
STNDPE
STFW1PH
STFW2PH
STFW3PH
STPE
STPP
STCNDZ
STCNDLE
IEC14000047-1-en.vsd
IEC10000047 V2 EN-US
8.2.4 Signals
PID-3642-INPUTSIGNALS v7
PID-3642-OUTPUTSIGNALS v7
8.2.5 Settings
PID-3642-SETTINGS v7
The basic impedance algorithm for the operation of the phase selection measuring
elements is the same as for the distance zone measuring function. Phase selection
with load encroachment, quadrilateral characteristic FDPSPDIS includes six
impedance measuring loops; three intended for phase-to-earth faults, and three
intended for phase-to-phase faults as well as for three-phase faults.
1. Residual current criteria, that is, separation of faults with and without earth
connection
2. Regular quadrilateral impedance characteristic
3. Load encroachment characteristics is always active but can be switched off by
selecting a high setting.
These directional indications are based on the sector boundaries of the directional
function and the impedance setting of FDPSPDIS function. Their operating
characteristics are illustrated in figure 80.
X X X
R
R R
en08000286.vsd
IEC08000286 V1 EN-US
The setting of the load encroachment function may influence the total operating
characteristic, (for more information, refer to section "Load encroachment").
The input DIRCND contains binary coded information about the directional
coming from the directional function . It shall be connected to the STDIR output on
STDIR= STFWL1*1+STFWL2*2+STFWL3*4+STFWL1L2*8+
+STFWL2L3*16+STFWL3L1*32+STRVL1*64+STRVL2*128+
+STRVL3*256+STRVL1L2*512+STRVL2L3*1024+STRVL3L1*2048
The code built up for release of the measuring fault loops is as follows:
ULn
ZPHSn =
ILn
EQUATION1255 V1 EN-US (Equation 43)
where:
n corresponds to the particular phase (n=1, 2 or 3)
The resistance RN and reactance XN are the impedance in the earth-return path
defined according to equation 44 and equation 45.
R0 - R1
RN =
3
EQUATION1256 V1 EN-US (Equation 44)
X 0 - X1
XN =
3
EQUATION1257 V1 EN-US (Equation 45)
X (ohm/loop)
Kr·(X1+XN)
RFRvPE RFFwPE
X1+XN
60 deg
RFFwPE
RFRvPE R (Ohm/loop)
60 deg
X1+XN
1
Kr =
tan(60deg)
RFRvPE RFFwPE
Kr·(X1+XN)
en06000396.vsd
IEC06000396 V2 EN-US
Besides this, the 3I0 residual current must fulfil the conditions according to
equation 46 and equation 47.
3 × I0 ³ 0.5 × IMinOpPE
EQUATION2108 V1 EN-US (Equation 46)
3 × I0 ³ INReleasePE
------------------------------------ × Iphmax
100
EQUATION766 V1 EN-US (Equation 47)
where:
IMinOpPE is the minimum operation current for forward zones
INReleasePE is the setting for the minimum residual current needed to enable operation in the
phase-to-earth fault loops (in %).
Iphmax is the maximum phase current in any of three phases.
ULm - ULn
ZPHS =
-2 × ILn
EQUATION1258 V1 EN-US (Equation 48)
ULm is the leading phase voltage, ULn the lagging phase voltage and ILn the
phase current in the lagging phase n.
X (W / phase)
0.5·RFRvPP 0.5·RFFwPP
Kr·X1
X1
0.5·RFFwPP
60 deg
R (W / phase)
60 deg
0.5·RFRvPP
X1
1
Kr =
tan(60 deg)
Kr·X1
0.5·RFRvPP 0.5·RFFwPP
IEC09000047-2-en.vsd
IEC09000047 V2 EN-US
In the same way as the condition for phase-to-earth fault, there are current
conditions that have to be fulfilled in order to release the phase-to-phase loop.
Those are according to equation 49 or equation 50.
3I 0 < IMinOpPE
EQUATION2109 V1 EN-US (Equation 49)
INBlockPP
3I 0 < × Iph max
100
EQUATION2110 V1 EN-US (Equation 50)
where:
IMinOpPE is the minimum operation current for earth measuring loops,
INBlockPP is 3I0 limit for blocking phase-to-phase measuring loop and
Iphmax is maximal magnitude of the phase currents.
The operation conditions for three-phase faults are the same as for phase-to-phase
fault, that is equation , equation and equation are used to release the operation of
the function.
X (ohm/phase)
4 × X1
3
90 deg
0.5·RFFwPP·K3
X1·K3 4 × RFFwPP
6
R (ohm/phase)
0.5·RFRvPP·K3
2
K3 =
3 30 deg
IEC05000671-5-en.vsd
IEC05000671 V5 EN-US
Each of the six measuring loops has its own load encroachment characteristic based
on the corresponding loop impedance. The load encroachment functionality is
always active, but can be switched off by selecting a high setting.
RLdFw
ArgLd ArgLd
R
ArgLd ArgLd
RLdRv
IEC09000042-1-en.vsd
IEC09000042 V1 EN-US
X X
R R
STCNDZ STCNDLE
IEC10000099-1-
en.vsd
IEC10000099 V1 EN-US
When FDPSPDIS is set to operate together with a distance measuring zone the
resultant operate characteristic could look like in figure 86. The figure shows a
distance measuring zone operating in forward direction. Thus, the operating area is
highlighted in black.
"Phase selection"
"quadrilateral" zone
Load encroachment
characteristic
Directional line
en05000673.vsd
IEC05000673 V1 EN-US
Figure 86 is valid for phase-to-earth. During a three-phase fault, or load, when the
quadrilateral phase-to-phase characteristic is subject to enlargement and rotation
the operate area is transformed according to figure 87. Notice in particular what
happens with the resistive blinders of the "phase selection" "quadrilateral" zone.
Due to the 30-degree rotation, the angle of the blinder in quadrant one is now 90
degrees instead of the original 60 degrees. The blinder that is nominally located to
quadrant four will at the same time tilt outwards and increase the resistive reach
around the R-axis. Consequently, it will be more or less necessary to use the load
encroachment characteristic in order to secure a margin to the load impedance.
X (W / phase)
Phase selection
”Quadrilateral” zone
R (W / phase)
IEC09000049-1-en.vsd
IEC09000049 V1 EN-US
The result from rotation of the load characteristic at a fault between two phases is
presented in fig 88. Since the load characteristic is based on the same measurement
as the quadrilateral characteristic, it will rotate with the quadrilateral characteristic
clockwise by 30 degrees when subject to a pure phase-to-phase fault. At the same
time the characteristic will "shrink", divided by 2/√3, from the full RLdFw and
RLdRv reach, which is valid at load or three-phase fault.
IEC08000437.vsd
IEC08000437 V1 EN-US
Figure 88: Rotation of load characteristic for a fault between two phases
The operation of the Phase selection with load encroachment function (FDPSPDIS)
is blocked if the magnitude of input currents falls below certain threshold values.
LDEblock
& 15 ms
t STPE
&
INReleasePE
3I 0 ≥ ⋅ Iphmax
100 STCNDLE
Bool to &
BLOCK integer
15 ms
3I 0 < IMinOpPE & t STPP
10 ms 20 ms
OR & t t
IRELPP
INBlockPP
3I 0 < ⋅ Iphmax
100
IEC09000149_2_en.vsd
IEC09000149 V2 EN-US
INDL1N
INDL2N
INDL3N
15 ms
STNDPE
IRELPE OR t
LDEblockL1N
AND 15 ms
ZML1N STNDL1
OR t
LDEblockL2N
AND
ZML2N
15 ms
LDEblockL3N STNDL2
OR t
AND
ZML3N
LDEblockL1L2 15 ms
STNDL3
AND OR t
ZML1L2
LDEblockL2L3
AND INDL1L2
ZML2L3
LDEblockL3L1 INDL2L3
AND
ZML3L1 INDL3L1
IRELPP 15 ms
STNDPP
OR t
IEC00000545-3-en.vsd
IEC00000545-TIFF V3 EN-US
INDL1N
AND
DRVL1N
INDL1L2 15 ms STRVL1
AND OR t
DRVL1L2
INDL3L1
AND
DRVL3L1 15 ms
STRVPE
INDL2N OR t
AND
DRVL2N
INDL1L2 15 ms
STRVL2
AND OR t
INDL2L3 INDL1N
AND INDL2N
DRVL2L3
INDL3N Bool to STCNDZ
INDL3N INDL1L2 integer
AND INDL2L3
DRVL3N INDL3L1
INDL2L3 15 ms
STRVL3
AND OR t
INDL3L1
15 ms
AND STRVPP
OR t
IEC00000546_2_en.vsd
IEC00000546-TIFF V2 EN-US
AND
INDL1N
AND 15 ms 15 ms
DFWL1N STFW1PH
AND OR t t
INDL1L2
15 ms STFWL1
AND OR t
DFWL1L2
INDL3L1
AND
AND
DFWL3L1 15 ms
STFWPE
INDL2N OR t
AND
DFWL2N
AND 15 ms
INDL1L2 STFWL2
t
AND OR
15 ms 15 ms
INDL2L3 STFW2PH
AND OR t t
AND
DFWL2L3
INDL3N
AND AND
DFWL3N 15 ms
STFWL3
t
INDL2L3
AND OR
15 ms
INDL3L1 STFW3PH
AND t
AND
15 ms
STFWPP
OR t
IEC05000201_2_en.vsd
IEC05000201 V2 EN-US
Figure 93 presents the composition of output signals TRIP and START, where
internal signals STNDPP, STFWPP and STRVPP are the equivalent to internal
signals STNDPE, STFWPE and STRVPE, but for the phase-to-phase loops.
TimerPP=Off
tPP
AND AND
t
TRIP
OR OR
tPE
TimerPE=Off
t
AND AND
STNDPP
STFWPP OR
STRVPP
START
OR
STNDPE
STFWPE OR
STRVPE
IEC08000441_2_en.vsd
IEC08000441-1 V2 EN-US
8.3.1 Identification
SEMOD168165-2 v2
S00346 V1 EN-US
S00346 V1 EN-US
IEC09000167 V1 EN-US
Forward
operation
Reverse
operation
en05000034.vsd
IEC05000034 V1 EN-US
The distance protection zones can operate, independent of each other, in directional
(forward or reverse) or non-directional mode. This makes them suitable, together
with different communication schemes, for the protection of power lines and cables
in complex network configurations, such as parallel lines, multi-terminal lines.
SEMOD168198-4 v2
ZMCPDIS
I3P* TRIP
U3P* TRL1
BLOCK TRL2
VTSZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
IEC07000036-2-en.vsd
IEC07000036 V2 EN-US
ZMCAPDIS
I3P* TRIP
U3P* TRL1
BLOCK TRL2
VTSZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
IEC09000890-1-en.vsd
IEC09000890 V1 EN-US
ZDSRDIR
I3P* STFW
U3P* STRV
STDIRCND
IEC07000035-2-en.vsd
IEC07000035 V2 EN-US
Input and output signals is shown for zone 1, zone 2 - 5 are equal.
PID-3639-INPUTSIGNALS v6
PID-3639-OUTPUTSIGNALS v6
PID-3637-INPUTSIGNALS v6
PID-3637-OUTPUTSIGNALS v6
PID-3547-INPUTSIGNALS v6
PID-3547-OUTPUTSIGNALS v6
Settings for ZMCPDIS are valid for zone 1, while settings for
ZMCAPDIS are valid for zone 2 - 5
PID-3639-SETTINGS v6
PID-3637-SETTINGS v6
PID-3547-SETTINGS v6
The execution of the different fault loops within the IED are of full scheme type,
which means that earth fault loop for phase-to-earth faults and phase-to-phase
faults for forward and reverse faults are executed in parallel.
Figure 98 presents an outline of the different measuring loops for the basic five,
impedance-measuring zones.
IEC05000458-2-en.vsd
IEC05000458 V2 EN-US
Figure 98: The different measuring loops at phase-to-earth fault and phase-to-
phase fault
The use of full scheme technique gives faster operation time compared to switched
schemes which mostly uses a start element to select correct voltages and current
depending on fault type. Each distance protection zone performs like one
independent distance protection IED with six measuring elements.
X (Ohm/loop)
R1PE+RNFw
X 0 PE - X 1FwPE
RFRvPE RFFwPE XNFw =
3
PG- -
XX00PE 1RVPG 1RvPE
1XRVPE
X
XNRV XNRv
XNRV == =XXNFw
3
×
3 X 1FwPE
XX0 PE - X-1X
0 PG FWPE
1FWPG
XNFW==
XNFW
X1FwPE+XNFw 3 3 R0 PE - R1PE
RNFw =
jN jN 3
R (Ohm/loop)
RFRvPE RFFwPE
X1RvPE+XNRv
jN
RFRvPE RFFwPE
IEC09000625-1-en.vsd
IEC09000625 V1 EN-US
X (Ohm/phase)
j j
jN R (Ohm/phase)
RFRvPP RFFwPP
2 2
X1RvPP
jN
RFRvPP RFFwPP
2 2
IEC09000632-1-en.vsd
IEC09000632 V1 EN-US
The fault loop reach with respect to each fault type may also be presented as in
figure 101. Note in particular the difference in definition regarding the (fault)
resistive reach for phase-to-phase faults and three-phase faults.
IL1 R1 + j X1
Phase-to-earth
UL1
element
Phase-to-earth
fault in phase L1 RFPE
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 )
IL1 R1 + j X1 Phase-to-phase
UL1 element L1-L2
Phase-to-phase
fault in phase RFPP
L1-L2 IL2
UL2 (Arc resistance)
R1 + j X1
The R1 and jX1 in figure 101 represents the positive sequence impedance from the
measuring point to the fault location. The RFPE and RFPP is the eventual fault
resistance in the fault place.
Regarding the illustration of three-phase fault in figure 101, there is of course fault
current flowing also in the third phase during a three-phase fault. The illustration
merely reflects the loop measurement, which is made phase-to-phase.
X X X
R R R
IEC05000182-2-en.vsdx
IEC05000182 V2 EN-US
For zone 1 with load compensation feature the additional criterion applies, that all
phase-to-earth loops will be blocked when IN < IMinOpIN, regardless of the phase
currents.
ILn is the RMS value of the current in phase Ln. IN is the RMS value of the vector
sum of the three phase currents, that is, residual current 3I0.
ILmLn is the RMS value of the vector difference between phase currents Lm and
Ln.
Fault loop equations use the complex values of voltage, current, and changes in the
current. Apparent impedances are calculated and compared with the set limits. The
calculation of the apparent impedances at ph-ph faults follows equation 51
(example for a phase L1 to phase L2 fault).
UL1 – UL2
Zapp = -------------------------
I L1 – IL2
EQUATION1222 V1 EN-US (Equation 51)
Here U and I represent the corresponding voltage and current phasors in the
respective phase.
U L1
Z app =
I L1 + I N × KN
EQUATION1223 V2 EN-US (Equation 52)
Where:
UL1, IL1 and IN are the phase voltage, phase current and residual current present to the IED
KN is defined as:
Z 0 - Z1
KN =
3 × Z1
EQUATION-2105 V2 EN-US
Z 0 = R 0 + jX 0
EQUATION2106 V2 EN-US
Z 1 = R1 + jX 1
EQUATION2107 V2 EN-US
Where
R0 is setting of the resistive zero sequence reach
X0 is setting of the reactive zero sequence reach
R1 is setting of the resistive positive sequence reach
X1 is setting of the reactive positive sequence reach
Here IN is a phasor of the residual current at the IED point. This results in the same
reach along the line for all types of faults.
The formula given in equation 52 is only valid for no loaded radial feeder
applications. When load is considered in the case of single phase-to-earth fault,
conventional distance protection might overreach at exporting end and underreach
at importing end. IED has an adaptive load compensation which increases the
security in such applications.
Measuring elements receive current and voltage information from the A/D
converter. The check sums are calculated and compared, and the information is
distributed into memory locations. For each of the six supervised fault loops,
sampled values of voltage (U), current (I), and changes in current between samples
(DI) are brought from the input memory and fed to a recursive Fourier filter.
The filter provides two orthogonal values for each input. These values are related
to the loop impedance according to equation 53,
X Di
U = R × i + ------ × -----
w 0 Dt
EQUATION1224 V1 EN-US (Equation 53)
X D Re ( I )
Re ( U ) = R × Re ( I ) + ------ × ------------------
w0 Dt
X DIm ( I )
Im ( U ) = R × Im ( I ) + ------ × -----------------
w0 Dt
with
w0 = 2 × p × f 0
EQUATION356 V1 EN-US (Equation 56)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real
value of the voltage and substitute it in the equation for the imaginary part. The
equation for the Xm measured reactance can then be solved. The final result is
equal to:
Im ( U ) × DRe ( I ) – Re ( U ) × D Im ( I )
R m = ------------------------------------------------------------------------------------
DRe ( I ) × Im ( I ) – D Im ( I ) × Re ( I )
EQUATION357 V1 EN-US (Equation 57)
Re ( U ) × Im ( I ) – Im ( U ) × Re ( I )
Xm = w 0 × Dt × -------------------------------------------------------------------------------
DRe ( I ) × Im ( I ) – DIm ( I ) × Re ( I )
EQUATION358 V1 EN-US (Equation 58)
The calculated Rm and Xm values are updated each sample and compared with the
set zone reach. The adaptive tripping counter counts the number of permissive
tripping results. This effectively removes any influence of errors introduced by the
capacitive voltage transformers or by other factors.
In the basic distance protection function, the control of the memory for polarizing
voltage is performed by an undervoltage control. In case of series compensated
line, a voltage reversal can occur with a relatively high voltage also when the
memory must be locked. Thus, a simple undervoltage type of voltage memory
control can not be used in case of voltage reversal. In the option for series
compensated network the polarizing quantity and memory are controlled by an
impedance measurement criterion.
At a three phase fault when no positive sequence voltage remains (all three phases
are disconnected) the memory is used for direction polarization during 100 ms.
The memory predicts the phase of the positive sequence voltage with the pre-fault
frequency. This extrapolation is made with a high accuracy and it is not the
accuracy of the memory that limits the time the memory can be used. The network
is at a three phase fault under way to a new equilibrium and the post-fault condition
can only be predicted accurately for a limited time from the pre-fault condition.
In case of a three phase fault after 100 ms the phase of the memorized voltage can
not be relied upon and the directional measurement has to be blocked. The
This memory control allows in the time domain unlimited correct directional
measurement for all unsymmetrical faults also at voltage reversal. Only at three
phase fault within the range of the set impedance reach of the criteria for control of
the polarization voltage the memory has to be used and the measurement is limited
to 100 ms and thereafter the direction is sealed-in. The special impedance
measurement to control the polarization voltage is set separately and has only to
cover (with some margin) the impedance to fault that can cause the voltage
reversal.
U 1L1M
- ArgDir < arg < ArgNeg Re s
I L1
EQUATION2004 V2 EN-US (Equation 59)
For the L1-L2 element, the equation in forward direction is according to:
U 1L1L 2 M
- ArgDir < arg < ArgNeg Re s
I L1L 2
EQUATION2006 V2 EN-US (Equation 60)
where:
ArgDir is the setting for the lower boundary of the forward directional characteristic, by default
set to 15 (= -15 degrees) and
ArgNegRes is the setting for the upper boundary of the forward directional characteristic, by default
set to 115 degrees, see Figure 103.
U1L1M is positive sequence memorized phase voltage in phase L1
U1L1L2M is memorized voltage difference between phase L1 and L2 (L2 lagging L1)
The setting of ArgDir and ArgNegRes is by default set to 15 (= -15) and 115
degrees respectively, see Figure 103, and it should not be changed unless system
studies have shown the necessity.
ZDSRDIR generates a binary coded signal on the output STDIR depending on the
evaluation where STFWL1N=1 adds 1, STRVL1N=1 adds 2, STFWL2N=1 adds 4.
ArgNegRes
ArgDir
R
en05000722.vsd
IEC05000722 V1 EN-US
Figure 103: Setting angles for discrimination of forward and reverse fault
The design of distance protection zones are presented for all measuring loops:
phase-to-earth as well as phase-to-phase.
Two types of function block, ZMCPDIS and ZMCAPDIS, are used in the IED.
ZMCPDIS is used for zone 1 and ZMCAPDIS for zone 2 - 5.
The STCND input signal represents a connection of six different integer values
from the phase selection function within the IED, which are converted within the
zone measuring function into corresponding boolean expressions for each
condition separately. It is connected to Phase selection with load enchroachment,
quadrilateral characteristic (FDPSPDIS) function output STCNDZ.
STZMPP
OR
STCND
AND STNDL1L2
L1L2
STNDL2L3
L2L3 AND
AND STNDL1N
L1N
AND STNDL2N
L2N
STNDL3N
L3N AND
OR STPE
OR
VTSZ STND
OR AND
BLOCK
BLOCFUNC BLK
99000557-2.vsd
IEC99000557-TIFF V3 EN-US
Composition of the phase starting signals for a case, when the zone operates in a
non-directional mode, is presented in figure 105.
IEC00000488-TIFF V1 EN-US
Results of the directional measurement enter the logic circuits, when the zone
operates in directional (forward or reverse) mode, as shown in figure 106.
STNDL1N
AND
DIRL1N
STZMPE.
OR
STNDL2N
DIRL2N AND
STNDL3N 15 ms
OR STL1
AND AND t
DIRL3N
STNDL1L2
DIRL1L2 AND 15 ms
OR STL2
AND t
STNDL2L3
DIRL2L3 AND
15 ms
OR STL3
STNDL3L1 AND t
DIRL3L1 AND
STZMPP
OR
BLK
15 ms
OR START
AND t
IEC09000888-2-en.vsd
IEC09000888 V2 EN-US
Tripping conditions for the distance protection zone one are symbolically presented
in figure 107.
Timer tPP=On
STZMPP AND tPP
AND
t
BLOCFUNC
OR OR
tPE
t
AND
Timer tPE=On AND
STZMPE 15ms
BLKTR AND t
TRIP
BLK OR
IEC09000887-3-en.vsdx
IEC09000887 V3 EN-US
Figure 107: Tripping logic for the distance protection zone one
SEMOD173239-2 v10
8.4.1 Identification
SEMOD154447-2 v2
S00346 V1 EN-US
The full scheme technique provides back-up protection of power lines with high
sensitivity and low requirement on remote end communication.
The zones have fully independent measuring and settings, which gives high
flexibility for all types of lines.
The function can be used as under impedance back-up protection for transformers
and generators.
ZMHPDIS
I3P* TRIP
U3P* TRL1
CURR_INP* TRL2
VOLT_INP* TRL3
POL_VOLT* TRPE
BLOCK TRPP
BLKZ START
BLKZMTD STL1
BLKHSIR STL2
BLKTRIP STL3
BLKPE STPE
BLKPP STPP
EXTNST STTIMER
INTRNST
DIRCND
STCND*
LDCND
IEC06000423-2-en.vsd
IEC06000423 V3 EN-US
PID-3552-INPUTSIGNALS v7
PID-3552-OUTPUTSIGNALS v7
PID-3552-SETTINGS v7
The execution of the different fault loops within the IED are of full scheme type,
which means that each fault loop for phase-to-earth faults and phase-to-phase faults
are executed in parallel for all zones.
The use of full scheme technique gives faster operation time compared to switched
schemes which mostly uses a start element to select correct voltages and current
depending on fault type. So each distance protection zone performs like one
independent distance protection function with six measuring elements.
The Mho distance function ZMHPDIS is present with four instances so that four
separate zones could be designed. Each instance can be selected to be either
forward or reverse with positive sequence polarized mho characteristic;
alternatively self polarized offset mho characteristics is also available. One
example of the operating characteristic is shown in Figure 109 A) where zone 5 is
selected offset mho.
The directional mho characteristic of Figure 109 B) has a dynamic expansion due
to the source impedance. Instead of mho characteristic crossing origin, which is
only valid where the source impedance is zero, the crossing point is moved to the
coordinates of the negative source impedance giving an expansion of the circle of
Figure 109 B).
A B
jx X
Mho, zone4
Mho, zone2 R
Mho, zone1
Zs=Z1
Zs=2Z1
R
Offset mho, zone5
IEC09000143-3-en.vsd
IEC09000143 V3 EN-US
Figure 109: Mho, offset mho characteristic and the source impedance influence on the mho characteristic
The polarization quantities used for the mho circle are 100% memorized positive
sequence voltages. This will give a somewhat less dynamic expansion of the mho
circle during faults than a plain cross polarized characteristic. However, if the
source impedance is high, the dynamic expansion of the mho circle might lower the
security of the function too much with high loading and mild power swing
conditions.
The mho distance element has a load encroachment function which cuts off a
section of the characteristic when enabled. The function is enabled by setting the
setting parameter LoadEnchMode to On. Enabling of the load encroachment
function increases the possibility to detect high resistive faults without interfering
with the load impedance. The algorithm for the load encroachment is located in the
Faulty phase identification with load encroachment for mho function FMPSPDIS,
where also the relevant settings can be found. Information about the load
encroachment from FMPSPDIS to the zone measurement is given in binary format
to the input signal LDCND.
Each impedance zone can be switched On and Off by the setting parameter
Operation.
For critical applications such as for lines with high SIRs as well as CVTs, it is
possible to improve the security by setting the parameter ReachMode to
Underreach. In this mode the reach for faults close to the zone reach is reduced by
20% and the filtering is also introduced to increase the accuracy in the measuring.
If the ReachMode is set to Overreach no reduction of the reach is introduced and
no extra filtering introduced. The latter setting is recommended for overreaching
pilot zone, zone 2 or zone 3 elements and reverse zone where overreaching on
transients is not a major issue either because of less likelihood of overreach with
higher settings or the fact that these elements do not initiate tripping
unconditionally.
The zone reach for phase-to-earth fault and phase-to-phase fault is set individually
in polar coordinates.
The impedance is set by the parameters ZPE and ZPP and the corresponding
arguments by the parameters ZAngPE and ZAngPP.
Compensation for earth -return path for faults involving earth is done by setting the
parameter KNMag and KNAng where KNMag is the magnitude of the earth-return
path and KNAng is the difference of angles between KNMag and ZPE .
Z0-Z1
KNMag =
3 × Z1
EQUATION1579 V1 EN-US (Equation 61)
KNAng = arg
( Z 0 - Z1
3 × Z1
)
EQUATION1580 V1 EN-US (Equation 62)
where
Z0 is the complex zero sequence impedance of the line in Ω/phase
Z1 is the complex positive sequence impedance of the line in Ω/phase
The operate timers triggering input depends on the parameter ZnTimerSel setting.
The parameter ZnTimerSel can be set to:
The activation of input signal BLKZ can be made by external fuse failure function
or from the loss of voltage check in the Mho supervision logic (ZSMGAPC). In
both cases the output BLKZ in the Mho supervision logic shall be connected to the
input BLKZ in the Mho distance function block (ZMHPDIS)
The input signal BLKZMTD is activated during some ms after fault has been
detected by ZSMGAPC to avoid unwanted operations due to transients. It shall be
connected to the BLKZMTD output signal of ZSMGAPC function.
At SIR values >10, the use of electronic CVT might cause overreach due to the
built-in resonance circuit in the CVT, which reduce the secondary voltage for a
while. The input BLKHSIR is connected to the output signal HSIR on ZSMGAPC
for increasing of the filtering and high SIR values. This is valid only when
permissive underreach scheme is selected by setting ReachMode=Underreach.
The mho algorithm is based on the phase comparison of an operating phasor and a
polarizing phasor. When the operating phasor leads the reference polarizing phasor
by 90 degrees or more, the function operates and gives a trip output.
Mho SEMOD154224-217 v5
The plain Mho circle has the characteristic as in Figure 110. The condition for
deriving the angle β is according to equation 63.
where
IL1L2·X
Ucomp = UL1L2 - IL1L2 • ZPP
IL1L2 • ZPP
ß
Upol
UL1L2
IL1L2·R
en07000109.vsd
IEC07000109 V1 EN-US
Figure 110: Simplified mho characteristic and vector diagram for phase L1-to-
L2 fault
The characteristic for offset mho is a circle where two points on the circle are the
setting parameters ZPP and ZRevPP. The vector ZPP in the impedance plane has
the settable angle AngZPP and the angle for ZRevPP is AngZPP+180°.
The condition for operation at phase-to-phase fault is that the angle β between the
two compensated voltages Ucomp1 and Ucomp2 is greater than or equal to 90°
(figure 111). The angle will be 90° for fault location on the boundary of the circle.
The angle β for L1-to-L2 fault can be defined according to equation 64.
æ ö
U -IL1L2 × ZPP
b = arg ç ÷
è U-(-IL1L2 × ZRevPP) ø
EQUATION1792 V1 EN-US (Equation 64)
where
ZRevPP is the positive sequence impedance setting for phase-to-phase fault in reverse
direction
IL1L2jX
U
Ucomp2 = U = IF•ZF=UL1L2
IL1L2R
- IL1L2 • Z RevPP
en07000110.vsd
IEC07000110 V1 EN-US
Figure 111: Simplified offset mho characteristic and voltage vectors for phase
L1-to-L2 fault.
When forward direction has been selected for the offset mho, an extra criteria
beside the one for offset mho (90<β<270) is introduced, that is the angle φ between
the voltage and the current must lie between the blinders in second quadrant and
fourth quadrant. See figure 112. Operation occurs if 90≤β≤270 and
ArgDir≤φ≤ArgNegRes.
where
ArgDir is the setting parameter for directional line in fourth quadrant in the directional element,
ZDMRDIR.
ArgNegRes is the setting parameter for directional line in second quadrant in the directional element,
ZDMRDIR.
β is calculated according to equation
The directional information is brought to the mho distance measurement from the
mho directional element as binary coded information to the input DIRCND. See
Directional impedance element for mho characteristic (ZDMRDIR) for information
about the mho directional element.
IL1L2jX
ZPP
UL1L2
ArgNegRes f
IL1L2
ArgDir
en07000111.vsd
IEC07000111 V1 EN-US
Figure 112: Simplified offset mho characteristic in forward direction for phase
L1-to-L2 fault
The operation area for offset mho in reverse direction is according to figure 113.
The operation area in second quadrant is ArgNegRes+180°.
The β is derived according to equation for the mho circle and φ is the angle
between the voltage and current.
ZPP
ArgNegRes
ϕ
IL1L2
ArgDir R
UL1L2
ZRevPP
en06000469.eps
IEC06000469 V1 EN-US
Mho SEMOD154224-120 v5
For an earth fault in phase L1, the compensation voltage Ucomp can be derived, as
shown in Figure 114.
where
Upol is the polarizing voltage (memorized UL1 for Phase L1-to- earth
fault)
Zloop is the loop impedance, which in general terms can be expressed as
(
Z1+ZN = Z 1 × 1 + KN )
where
Z1 is the positive sequence impedance of the line (Ohm/phase)
The angle β between the Ucomp and the polarize voltage Upol for a L1-to-earth
fault is
where
UL1 is the phase voltage in faulty phase L1
KN Z0-Z1
3 × Z1
the setting parameter for the zero sequence
compensation consisting of the magnitude KN and
the angle KNAng.
Upol is the 100% of positive sequence memorized
voltage UL1
IL1·X
IL1·ZN
Ucomp
IL1 • Zloop
IL1·ZPE
Upol
f
IL1 (Ref) IL1·R
en06000472_2.vsd
IEC06000472 V2 EN-US
Figure 114: Simplified offset mho characteristic and vector diagram for phase
L1-to-earth fault
The characteristic for offset mho at earth fault is a circle containing the two vectors
from the origin ZPE and ZRevPE where ZPE and ZrevPE are the setting reach for
the positive sequence impedance in forward respective reverse direction. The
vector ZPE in the impedance plane has the settable angle AngZPE and the angle for
ZRevPP is AngZPE+180°.
The condition for operation at phase-to-earth fault is that the angle β between the
two compensated voltages Ucomp1 and Ucomp2 is greater or equal to 90° see
figure 115. The angle will be 90° for fault location on the boundary of the circle.
IL1L 2 • jX
UL1
U comp2 = UL1 - (-IL1 • ZRevPE)
IL1L2 • R
- I L1 • Z Re vPe
en 06000465.vsd
IEC06000465 V1 EN-US
Figure 115: Simplified offset mho characteristic and voltage vector for phase
L1-to-earth fault
In the same way as for phase-to-phase fault, selection of forward direction of offset
mho will introduce an extra criterion for operation. Beside the basic criteria for
offset mho according to equation and 90≤β≤270, also the criteria that the angle φ
between the voltage and the current must lie between the blinders in second and
fourth quadrant. See figure 116. Operation occurs if 90≤β≤270 and
ArgDir≤φ≤ArgNegRes.
where
ArgDir is the setting parameter for directional line in fourth quadrant in the directional element,
ZDMRDIR.
ArgNegRes is the setting parameter for directional line in second quadrant in the directional element,
ZDMRDIR.
β is calculated according to equation
IL1 jX
UL1
ArgNegRes f
IL1 IL1·R
ArgDir
en 06000466.vsd
IEC06000466 V1 EN-US
Figure 116: Simplified characteristic for offset mho in forward direction for L1-
to-earth fault
In the same way as for offset in forward direction, the selection of offset mho in
reverse direction will introduce an extra criterion for operation compare to the
normal offset mho. The extra is that the angle between the fault voltage and the
fault current shall lie between the blinders in second and fourth quadrant. The
operation area in second quadrant is limited by the blinder defined as 180° -ArgDir
and in fourth quadrant ArgNegRes+180°, see figure 117.
The conditions for operation of offset mho in reverse direction for L1-to-earth fault
is 90≤β≤270 and 180°-Argdir≤φ≤ArgNegRes+180°.
The β is derived according to equation for the offset mho circle and φ is the angle
between the voltage and current.
ZPE
ArgNegRes
ϕ
IL
1
ArgDir R
UL1
ZRevPE
en06000470.eps
IEC06000470 V1 EN-US
Figure 117: Simplified characteristic for offset mho in reverse direction for L1-
to-earth fault
Phase-to-earth related signals are designated by L1N, L2N and L3N. The phase-to-
phase signals are designated by L1L2, L2L3, and L3L1.
The ZMHPDIS function block is used in the IED for each zone.
The STCND input signal represents a connection of six different integer values
from Phase selection with load encroachment function FMPSPDIS within the IED,
which are converted within the zone measuring function into corresponding
boolean expressions for each condition separately. Input signal STCND is
connected from FMPSPDIS function output signal STCNDPHS.
The input signal DIRCND is used to give condition for directionality for the
distance measuring zones. The signal contains binary coded information for both
forward and reverse direction. The zone measurement function filters out the
relevant signals depending on the setting of the parameter DirMode. Input signal
DIRCND must be configured to the STDIRCND output signal on ZDMRDIR
function.
OffsetMhoDir=
Non-directional
AND AND
DirMode=Offset
STCND T
AND F
AND
LoadEnchMode=
On/Off
LDCND
T
True F
AND Release
DIRCND
OffsetMhoDir=
Forward/Reverse
AND
DirMode=
Forward/Reverse
BLKZ
BLOCK OR
IEC11000216-1-en.vsd
IEC11000216 V1 EN-US
Results of the directional measurement enter the logic circuits when the zone
operates in directional (forward or reverse) mode, as shown in figure 118.
Release STPE
OR
AND
STL1N STL1
OR
AND
STL2N
AND
STL3N
STL2
OR
AND
STL1L2
AND
STL2L3
STL3
OR
AND
STL3L1
START
OR
STPP
OR
IEC11000217-1-en.vsd
IEC11000217 V1 EN-US
Tripping conditions for the distance protection zone one are symbolically presented
in figure 120.
15ms
BLKTRIP AND t
TRIP
AND TRL2
STL2
IEC11000218-1-en.vsd
IEC11000218 V1 EN-US
Zone timer logic for the distance protection is symbolically presented in figure 121.
STPE
BLOCK
TRPE
&
tON
& ³1 t
a
Internal a=b
start b STTIMER
&
Internal
a
a<b
start b
tON
³1 t && TRPP
&
STPP
ZnTimerSel
FALSE 1 timers seperated
³1 2 timers linked
internalCommonStart
3 internal start
phSelStart 4 start from phSel
externalCommonStart
5 external start
IEC12000463-3-en.vsd
IEC12000463 V2 EN-US
SEMOD173242-2 v14
8.5.1 Identification
SEMOD154542-2 v2
S00346 V1 EN-US
S00346 V1 EN-US
The Full-scheme distance protection, quadrilateral for earth fault functions have
functionality for load encroachment, which increases the possibility to detect high
resistive faults on heavily loaded lines , see Figure 122.
Forward
operation
Reverse
operation
en05000034.vsd
IEC05000034 V1 EN-US
Figure 122: Typical quadrilateral distance protection zone with Phase selection,
quadrilateral characteristic with settable angle function FRPSPDIS
activated
The independent measurement of impedance for each fault loop together with a
sensitive and reliable built in phase selection makes the function suitable in
applications with single phase auto-reclosing.
The distance protection zones can operate, independent of each other, in directional
(forward or reverse) or non-directional mode. This makes them suitable, together
with different communication schemes, for the protection of power lines and cables
in complex network configurations, such as parallel lines, multi-terminal lines.
ZMMPDIS
I3P* TRIP
U3P* TRL1
BLOCK TRL2
BLKZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
IEC06000454-2-en.vsd
IEC06000454 V2 EN-US
ZMMAPDIS
I3P* TRIP
U3P* TRL1
BLOCK TRL2
BLKZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
IEC09000947-1-en.vsd
IEC09000947 V1 EN-US
8.5.4 Signals
PID-3645-INPUTSIGNALS v6
PID-3645-OUTPUTSIGNALS v6
PID-3640-INPUTSIGNALS v6
PID-3640-OUTPUTSIGNALS v6
8.5.5 Settings
PID-3645-SETTINGS v6
PID-3640-SETTINGS v6
The different fault loops within the IED are operating in parallel in the same
principle as a full scheme measurement.
Figure 125 presents an outline of the different measuring loops for the basic five,
impedance-measuring zones l.
en07000080.vsd
IEC07000080 V1 EN-US
Figure 125: The different measuring loops at line-earth fault and phase-phase
fault.
The distance measuring zone include three impedance measuring loops; one fault
loop for each phase.
The distance measuring zone will essentially operate according to the non-
directional impedance characteristics presented in Figure 126. The characteristic is
illustrated with the full loop reach.
X (Ohm/loop)
R1PE+Rn
RFPE RFPE
X0PE-X1PE
Xn =
3
X1PE+Xn R0PE-R1PE
Rn =
3
jN jN
R (Ohm/loop)
RFPE RFPE
X1PE+Xn
RFPE RFPE
en08000280-2-en.vsd
R1PE+Rn
IEC08000280 V1 EN-US
ILn R1 + j X1
Phase-to-earth
UL1
element
Phase-to-earth
fault in phase L1 RFPE
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 ) en06000412.vsd
IEC06000412 V1 EN-US
The R1 and jX1 in Figure 127 represent the positive sequence impedance from the
measuring point to the fault location. The RFPE is presented in order to “convey”
the fault resistance reach.
X X X
R R R
IEC05000182-2-en.vsdx
IEC05000182 V2 EN-US
The operation of the distance measuring zone is blocked if the magnitude of input
currents fall below certain threshold values.
For zone 1 with load compensation feature the additional criterion applies, that all
phase-to-earth loops will be blocked when IN < IMinOpIN, regardless of the phase
currents.
ILn is the RMS value of the current in phase Ln. IN is the RMS value of the vector
sum of the three phase currents, that is, residual current 3I0.
Fault loop equations use the complex values of voltage, current, and changes in the
current. Apparent impedances are calculated and compared with the set limits.
Here U and I represent the corresponding voltage and current phasors in the
respective phase Ln (n = 1, 2, 3).
U L1
Z app =
I L1 + I N × KN
EQUATION1223 V2 EN-US (Equation 68)
Where:
UL1, IL1 and IN are the phase voltage, phase current and residual current present to the IED
KN is defined as:
Z 0 - Z1
KN =
3 × Z1
EQUATION-2105 V2 EN-US
Z 0 = R 0 + jX 0
EQUATION2106 V2 EN-US
Z 1 = R1 + jX 1
EQUATION2107 V2 EN-US
Where
R0 is setting of the resistive zero sequence reach
X0 is setting of the reactive zero sequence reach
R1 is setting of the resistive positive sequence reach
X1 is setting of the reactive positive sequence reach
Here IN is a phasor of the residual current in IED point. This results in the same
reach along the line for all types of faults.
The formula given in equation 68 is only valid for no loaded radial feeder
applications. When load is considered in the case of single phase-to-earth fault,
conventional distance protection might overreach at exporting end and underreach
at importing end. IED has an adaptive load compensation which increases the
security in such applications.
Measuring elements receive current and voltage information from the A/D
converter. The check sums are calculated and compared, and the information is
distributed into memory locations. For each of the six supervised fault loops,
sampled values of voltage (U), current (I), and changes in current between samples
(DI) are brought from the input memory and fed to a recursive Fourier filter.
The filter provides two orthogonal values for each input. These values are related
to the loop impedance according to equation 69,
X Di
U = R × i + ------ × -----
w 0 Dt
EQUATION1224 V1 EN-US (Equation 69)
X D Re ( I )
Re ( U ) = R × Re ( I ) + ------ × ------------------
w0 Dt
X DIm ( I )
Im ( U ) = R × Im ( I ) + ------ × -----------------
w0 Dt
with
w0 = 2 × p × f 0
EQUATION356 V1 EN-US (Equation 72)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real
value of the voltage and substitute it in the equation for the imaginary part. The
equation for the Xm measured reactance can then be solved. The final result is equal
to:
Im ( U ) × DRe ( I ) – Re ( U ) × D Im ( I )
R m = ------------------------------------------------------------------------------------
DRe ( I ) × Im ( I ) – D Im ( I ) × Re ( I )
EQUATION357 V1 EN-US (Equation 73)
Re ( U ) × Im ( I ) – Im ( U ) × Re ( I )
Xm = w 0 × Dt × -------------------------------------------------------------------------------
DRe ( I ) × Im ( I ) – DIm ( I ) × Re ( I )
EQUATION358 V1 EN-US (Equation 74)
The calculated Rm and Xm values are updated each sample and compared with the
set zone reach. The adaptive tripping counter counts the number of permissive
tripping results. This effectively removes any influence of errors introduced by the
capacitive voltage transformers or by other factors.
where:
ArgDir is the setting for the lower boundary of the forward directional characteristic, by default
set to 15 (= -15 degrees) and
ArgNegRes is the setting for the upper boundary of the forward directional characteristic, by default
set to 115 degrees, see figure 129.
U1L1 is positive sequence phase voltage in phase L1
The setting of ArgDir and ArgNegRes is by default set to 15 (= -15) and 115
degrees respectively (see figure 129) and it should not be changed unless system
studies have shown the necessity.
ArgNegRes
ArgDir
R
en05000722.vsd
IEC05000722 V1 EN-US
Figure 129: Setting angles for discrimination of forward and reverse fault
For close-in three-phase faults, the U1L1M memory voltage, based on the same
positive sequence voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is
restored.
• If the current is still above the set value of the minimum operating current
(between 10 and 30% of the set IED rated current IBase), the condition seals
in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element
in the reverse direction remains in operation.
• If the current decreases below the minimum operating value, the memory
resets until the positive sequence voltage exceeds 10% of its rated value.
The design of distance protection zone 1 is presented for all measuring phase-to-
earth loops.
The STCND input signal represents a connection of six different integer values
from the phase selection function within the IED, which are converted within the
zone measuring function into corresponding boolean expressions for each
condition separately. It is connected to the Phase selection with load
enchroachment, quadrilateral characteristic (FDPSPDIS) function output STCNDZ.
The input signal DIRCND is used to give condition for directionality for the
distance measuring zones. The signal contains binary coded information for both
forward and reverse direction. The zone measurement function filter out the
relevant signals on the DIRCND input depending on the setting of the parameter
OperationDir. It shall be configured to the DIRCND output on the Directional
impedance element for mho characteristic (ZDMRDIR) function.
STCND
AND STNDL1N
L1N
AND STNDL2N
L2N
STNDL3N
L3N AND
OR STNDPE
OR
BLKZ STND
OR AND
BLOCK
BLK
en06000408-2.vsd
IEC06000408 V2 EN-US
Composition of the phase starting signals for a case, when the zone operates in a
non-directional mode, is presented in figure 131.
STNDL1N 15 ms
AND t STL1
STNDL2N 15 ms
AND t STL2
STNDL3N 15 ms
AND t STL3
15 ms
AND t START
OR
BLK
en06000409.vsd
IEC06000409 V1 EN-US
Results of the directional measurement enter the logic circuits, when the zone
operates in directional (forward or reverse) mode, see figure 132.
STNDL1N
DIRL1N AND
OR STZMPE.
&
STNDL2N
DIRL2N AND
STNDL3N 15 ms
STL1
& t
DIRL3N AND
15 ms
STL2
& t
15 ms
STL3
& t
BLK
15 ms
OR START
& t
en07000081.vsd
IEC07000081 V1 EN-US
Tripping conditions for the distance protection zone one are symbolically presented
in figure 133.
en07000082.vsd
IEC07000082 V1 EN-US
Figure 133: Tripping logic for the distance protection zone one
8.6.1 Identification
SEMOD155886-2 v2
S00346 V1 EN-US
GUID-39299546-12A2-4D9D-86D0-A33F423944E4 v2
S00346 V1 EN-US
ZDMRDIR
I3P* DIR_CURR
U3P* DIR_VOLT
DIR_POL
STFW
STRV
STDIRCND
IEC06000422_2_en.vsd
IEC06000422 V2 EN-US
ZDARDIR
I3P* STFWPE
U3P* STRVPE
I3PPOL* DIREFCND
DIRCND
IEC06000425-2-en.vsd
IEC06000425 V2 EN-US
8.6.4 Signals
PID-3546-INPUTSIGNALS v7
PID-3546-OUTPUTSIGNALS v7
PID-3564-INPUTSIGNALS v7
PID-3564-OUTPUTSIGNALS v7
8.6.5 Settings
PID-3546-SETTINGS v7
PID-3564-SETTINGS v7
Where:
ArgDir Setting for the lower boundary of the forward directional characteristic, by default set to
15 (= -15 degrees)
ArgNegRes Setting for the upper boundary of the forward directional characteristic, by default set to
115 degrees, see figure 136 for mho characteristics.
U1L1 Positive sequence phase voltage in phase L1
U1L1L2M Memorized voltage difference between phase L1 and L2 (L2 lagging L1)
The default settings for ArgDir and ArgNegRes are 15 (= -15) and 115 degrees
respectively (see figure 136) and they should not be changed unless system studies
show the necessity.
X
Zset reach point
ArgNegRes
-ArgDir R
-Zs
en06000416.vsd
IEC06000416 V1 EN-US
The code built up for release of the measuring fault loops is as follows:
STDIRCND = L1N*1 + L2N*2 + L3N*4 + L1L2*8 + L2L3*16 + L3L1*32
Example: If only L1Nstart, the value is 1, if start in L1N and L3N are detected, the
value is 1+4=5.
For close-in three-phase faults, the U1L1M memory voltage, based on the same
positive sequence voltage, ensures correct directional discrimination.
The memory voltage is used for 100ms or until the positive sequence voltage is
restored. After 100ms, the following occurs:
• If the current is still above the set value of the minimum operating current the
condition seals in.
• If the fault has caused tripping, the trip continues.
• If the fault was detected in the reverse direction, the measuring element
in the reverse direction remains in operation.
• If the current decreases below the minimum operate value, no directional
indications will be given until the positive sequence voltage exceeds 10% of
its rated value.
The STDIRCND output provides an integer signal that depends on the evaluation
and is derived from a binary coded signal as follows:
There are however some situations that can cause security problems like reverse
phase to phase faults and double phase-to-earth faults during high load periods. To
solve these, additional directional element is used.
For phase-to-earth faults, directional elements using sequence components are very
reliable for directional discrimination. The directional element can be based on one
of following types of polarization:
• Zero-sequence voltage
• Negative-sequence voltage
• Zero-sequence current
Zero-sequence voltage polarization is utilizing the phase relation between the zero-
sequence voltage and the zero-sequence current at the location of the protection.
The measurement principle is illustrated in figure 137.
- 3U 0
AngleOp
AngleRCA
3I 0
en06000417.vsd
IEC06000417 V1 EN-US
Zero-sequence current polarization is utilizing the phase relation between the zero-
sequence current at the location of the protection and some reference zero-
sequence current, for example, the current in the neutral of a power transformer.
Z0 SA I0 I0
Z0 Line Z0 SB
Charac te ris tic
ang le
U0 U0
K*I0
U0 + K*I0
IF
en06000418.vsd
IEC06000418 V1 EN-US
Note that the sequence based additional directional element cannot give per phase
information about direction to fault. This is why it is an AND-function with the
normal directional element that works on a per phase base. The enable signals are
per phase and to enable the measuring element in a specific phase, both the
additional directional element and the normal directional element, for that phase
must indicate correct direction.
These polarization quantities, voltage and current, are stabilized against minimum
polarizing voltage (UPOL>) and current (IPOL>). That means if polarizing voltage
is greater than UPOL> setting, and if polarizing current is greater than IPol>, then
only they are used for direction determination.
Normal
directional Release of distance
element measuring element
L1N, L2N, L3N L1N, L2N, L3N
AND
Additional
directional AND per
element phase
en06000419.vsd
IEC06000419 V1 EN-US
8.7.1 Identification
GUID-030C086A-8301-481E-BA0A-6550A9C1482E v2
The Mho impedance supervision logic (ZSMGAPC) includes features for fault
inception detection and high SIR detection. It also includes the functionality for
loss of potential logic as well as for the pilot channel blocking scheme.
ZSMGAPC
I3P* BLKZMTD
U3P* BLKCHST
BLOCK CHSTOP
REVSTART HSIR
BLOCKCS
CBOPEN
IEC06000426-2-en.vsd
IEC06000426 V2 EN-US
8.7.4 Signals
PID-6718-INPUTSIGNALS v1
PID-6718-OUTPUTSIGNALS v1
8.7.5 Settings
PID-6718-SETTINGS v1
The aim for the fault inception detector is to quickly detect that a fault has occurred
in the system. The fault detector detects a fault when there is a sufficient change in
at least one current and at the same time there is a sufficient change in at least one
voltage. A change is defined roughly by the difference between the present
instantaneous value and the one from one power system cycle before. The change
is sufficient if it exceeds the related threshold value. DeltaI and DeltaU for phase
currents and voltages. Delta3I0 and Delta3U0 for residual current and voltage.
If the setting PilotMode is set to On in blocking scheme and the fault inception
function has detected a system fault, a block signal BLKCHST is issued and send to
remote end in order to block the overreaching zones. Different criteria has to be
fulfilled for sending the BLKCHST signal:
If it is later detected that it was an internal fault that made the function issue the
BLKCHST signal, the function issues a CHSTOP signal to unblock the remote end.
The criteria that have to be fulfilled for this are:
1. The function has to be in pilot mode, that is, the setting PilotMode has to be
set to On
2. The carrier send signal should be blocked, that is, input signal BLOCKCS is On
and,
3. A reverse fault should not have been detected while the carrier send signal was
not blocked, that is, input REVSTART should not have been activated before
BLOCKCS.
If loss of voltage is detected, but not a fault inception, the distance protection
function is blocked. This is also the case if a fuse failure is detected by the external
fuse failure function and activate the input FUSEFAIL. Those blocks are generated
by activating the output BLKZ, which are connected to the input BLKZ on the
distance Mho function block.
During fault inception a lot of transients are developed which in turn might cause
the distance function to overreach. The Mho supervision logic (ZSMGAPC)
increases the filtering during the most transient period of the fault. This is done by
activating the output BLKZMTD, which is connected to the input BLKZMTD on mho
distance function block.
High SIR values increases the likelihood that CVT will introduce a prolonged and
distorted transient, increasing the risk for overreach of the distance function.
The SIR function calculates the SIR value as the source impedance divided by the
setting Zreach and activates the output signal HSIR if the calculated value for any
of the six basic shunt faults exceed the setting SIRLevel. The HSIR signal is
intended to block the delta based mho impedance function.
8.8.1 Identification
SEMOD155879-2 v3
S00346 V1 EN-US
The ability to accurately and reliably classify different types of fault so that single
phase tripping and autoreclosing can be used plays an important roll in today's
power systems.
The phase selection function is design to accurately select the proper fault loop(s)
in the distance function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may in
some cases interfere with the distance protection zone reach and cause unwanted
operation. Therefore the function has a built in algorithm for load encroachment,
which gives the possibility to enlarge the resistive setting of the measuring zones
without interfering with the load.
The output signals from the phase selection function produce important
information about faulty phase(s), which can be used for fault analysis as well.
FMPSPDIS
I3P* STL1
U3P* STL2
BLOCK STL3
ZSTART STPE
TR3PH STCNDPHS
1POLEAR STCNDPLE
STCNDLE
START
IEC06000429-2-en.vsd
IEC06000429 V2 EN-US
8.8.4 Signals
PID-3541-INPUTSIGNALS v9
PID-3541-OUTPUTSIGNALS v9
8.8.5 Settings
PID-3541-SETTINGS v9
Faulty phase identification with load encroachment for mho (FMPSPDIS) function
can be decomposed into six different parts:
The delta based fault detection function uses adaptive technique and is based on
patent US4409636.
The aim of the delta based phase selector is to provide very fast and reliable phase
selection for releasing of tripping from the high speed Mho measuring element and
is essential to Directional Comparison Blocking scheme (DCB), which uses Power
Line Carrier (PLC) communication system along the protected line.
The current and voltage samples for each phase passes through a notch filter that
filters out the fundamental components. Under steady state load conditions or when
no fault is present, the output of the filter is zero or close to zero. When a fault
occurs, currents and voltages change resulting in sudden changes in the currents
and voltages resulting in non-fundamental waveforms being introduced on the line.
At this point the notch filter produces significant non-zero output. The filter output
is processed by the delta function. The algorithm uses an adaptive relationship
between phases to determine if a fault has occurred, and determines the faulty
phases.
The current and voltage delta based phase selector gives a real output signal if the
following criterion is fulfilled (only phase L1 shown):
Max(ΔUL1,ΔUL2,ΔUL3)>DeltaUMinOp
Max(ΔIL1,ΔIL2,ΔIL3)>DeltaIMinOp
where:
ΔUL1, ΔUL2 and ΔUL3 are the voltage change between sample t and sample t-1
DeltaUMinOp and are the minimum harmonic level settings for the voltage and current
DeltaIMinOp filters to decide that a fault has occurred. A slow evolving fault may not
produce sufficient harmonics to detect the fault; however, in such a
case speed is no longer the issue and the sequence components
phase selector will operate.
The delta voltages ΔULn and delta current ΔILn (n index for phase order) are the
voltage and current between sample t and sample t-1.
The delta phase selector employs adaptive techniques to determine the fault type.
The logic determines the fault type by summing up all phase values and dividing
by the largest value. Both voltages and currents are filtered out and evaluated. The
condition for fault type classification for the voltages and currents can be expressed
as:
FaulType =
∑ ( ∆UL1, ∆UL2, ∆UL3)
MAX ( ∆UL1, ∆UL 2, ∆UL3)
EQUATION1621 V2 EN-US (Equation 78)
FaulType =
∑ ( ∆IL1, ∆IL2, ∆IL3)
MAX ( ∆IL1, ∆IL 2, ∆IL3)
EQUATION1622 V2 EN-US (Equation 79)
The output signal is 1 for single phase-to-earth fault, 2 for phase-to-phase fault and
3 for three-phase fault. At this point the filter does not know if earth was involved
or not.
Typically there are induced harmonics in the non-faulted lines that will affect the
result. This method allows for a significant tolerance in the evaluation of FaultType
over its entire range.
When a single phase-to-earth fault has been detected, the logic determines the
largest quantity, and asserts that phase. If phase-to-phase fault is detected, the two
largest phase quantities will be detected and asserted as outputs.
The faults detected by the delta based phase selector are coordinated in a separate
block. Different phases of faults may be detected at slightly different times due to
differences in the angles of incidence of fault on the wave shape. Therefore the
output is forced to wait a certain time by means of a timer. If the timer expires, and
a fault is detected in one phase only, the fault is deemed as phase-to-earth. This
way a premature single phase-to-earth fault detection is not released for a phase-to-
phase fault. If, however, earth current is detected before the timer expires, the
phase-to-earth fault is released sooner.
If another phase picks up during the time delay, the wait time is reduced by a
certain amount. Each detection of either phase-to-earth or additional phases further
reduce the initial time delay and allow the delta phase selector output to be faster.
There is no time delay if all three phases are faulty.
The delta function is released if the input DELTAREL is activated at the same time
as input DELTABLK is not activated. Activating the DELTABLK input blocks the
delta function. The release signal has an internal pulse timer of 100 ms. When the
DELTAREL signal has disappeared the delta logic is reset. In order not to get too
abrupt change, the reset is decayed in pre-defined steps.
This detection of earth fault is performed in two levels, first by evaluation of the
magnitude of zero sequence current, and secondly by the evaluation of the zero and
negative sequence voltage. It is a complement to the earth-fault signal built-in in
the Symmetrical component based phase selector.
The output from this detection is used to release the earth-fault loop.
|3I0|>maxIph × INRelPE
where:
|3I0| is the magnitude of the zero sequence current 3I0
The earth-fault loop is also released if the evaluation of the zero sequence current
by the main sequence function meets the following conditions:
|3I0|>IBase × 0.5
|3I0|>maxIph ×INRelPE
where:
maxIph is the maximal current magnitude found in any of the three phases
INRelPE is the setting of 3I0 limit for release of phase-to-earth measuring loop in % of IBase
IBase is the global setting of the base current (A)
In systems where the source impedance for zero sequence is high the change of
zero sequence current may not be significant and the above detection may fail. In
those cases the detection enters the second level, with evaluation of zero and
negative sequence voltage. The release of the earth-fault loops can then be
achieved if all of the following conditions are fulfilled:
|3U0|>|U2| × 0.5
|3U0|>|U1| × 0.2
and
3I0<0.1 × IBase
or
3I0<maxIph × INRelPE
where:
3U0 is the magnitude of the zero sequence voltage
U2 is the magnitude of the negative sequence voltage at the relay measuring point
k5 is design parameter
ILmax is the maximal phase current
IMinOp is the setting of minimum operate phase current in % of IBase
IEC06000383-2-en.vsd
IEC06000383 V2 EN-US
The phase-to-phase loop for the faulty phases will be determined if the angle
between the sequence voltages U2 and U1 lies within the sector defined according
to figure 142 and the following conditions are fulfilled:
|U1|>U1MinOP
|U2|>U2MinOp
where:
U1MinOP and U2MinOp are the setting parameters for positive sequence and negative sequence
minimum operate voltages
If there is a three-phase fault, there will not be any release of the individual phase
signals, even if the general conditions for U2 and U1 are fulfilled.
80°
200°
L1-E sector
320°
IEC06000384_2_en.vsd
IEC06000384 V3 EN-US
The angle is calculated in a directional function block and gives the angle in
radians as input to the U2 and I0 function block. The input angle is released only if
the fault is in forward direction. This is done by the directional element. The fault
is classified as forward direction if the angle between U0 and I0 lies between 20 to
200 degrees, see figure 144.
Forward 20°
200° Reverse
en06000385.vsd
IEC06000385 V1 EN-US
Figure 144: Directional element used to release the measured angle between
Uo and I0
The input radians are summarized with an offset angle and the result evaluated. If
the angle is within the boundaries for a specific sector, the phase indication for that
sector will be active see figure 143. Only one sector signal is allowed to be
activated at the same time.
The sector function for condition 1 has an internal release signal which is active if
the main sequence function has classified the angle between U0 and I0 as valid. The
following conditions must be fulfilled for activating the release signals:
|U2|>U2MinOp
|3I0|>maxIph · INRelPE
where:
U2 and IN are the magnitude of the negative sequence voltage and zero-
sequence current (3I0)
The angle difference is phase shifted by 180 degrees if the fault is in reverse
direction.
The condition 2 looks at the angle relationship between the negative sequence
voltage U2 and the positive sequence voltage U1. Since this is a phase-to-phase
voltage relationship, there is no need for shifting phases if the fault is in reverse
direction. A phase shift is introduced so that the fault sectors will have the same
angle boarders as for condition 1. If the calculated angle between U2 and U1 lies
within one sector, the corresponding phase for that sector will be activated. The
condition 2 is released if both the following conditions are fulfilled:
|U2|>U2MinOp
|U1|>U1MinOP
where:
|U1| and |U2| are the magnitude of the positive and negative sequence voltages.
U1MinOP and U2MinOp are the setting parameters for positive sequence and negative sequence
minimum operating voltages.
140°
L3-E sector
20°
U1L1
(Ref)
L1-E sector
L2-E sector
260° IEC06000413_2_en.vsd
IEC06000413 V2 EN-US
If both conditions are true and there is sector match, the fault is deemed as single
phase-to-earth. If the sectors, however, do not match the fault is determined to be
the complement of the second condition, that is, a phase-to-phase-to- earth fault.
The sequence phase selector is blocked when earth is not involved or if a three-
phase fault is detected.
Unless it has been categorized as a single or two-phase fault, the function classifies
it as a three-phase fault if the following conditions are fulfilled:
|U1|<U1Level
and
|I1|>I1LowLevel
or
|I1|>IMaxLoad
where:
|U1| and |I1| are the positive sequence voltage and current magnitude
U1Level , are the setting of limits for positive sequence voltage and current
I1LowLevel
IMaxLoad is the setting of the maximum load current
The output signal for detection of three-phase fault is only released if not earth
fault and phase-to-phase fault in the main sequence function is detected.
The conditions for not detecting earth fault are the inverse of equation 5 to 10.
1:
earth fault is detected
or
|3I0|> 0.05 · IBase
and
|3I0|>maxIph ·INRelPE
2:
phase-to-earth and phase-to-phase faults are not fulfilled
and
maxIph<0.1 · IBase
and
|I2|<0.1 · maxIph
3:
|3I0|>maxIph · INBlockPP
or
|I2|<maxIph · I2ILmax
where:
maxIph is the maximum of the phase currents IL1, IL2 and IL3
INRelPE is the setting parameter for 3I0 limit for release of phase-to-earth fault loops
|I2| is the magnitude of the negative sequence current
I2ILmax is the setting parameter for the relation between negative sequence current
to the maximum phase current in percent of IBase
INBlockPP is the setting parameter for 3I0 limit for blocking phase to phase measuring
loops
The phase selection logic has an evaluation procedure that can be simplified
according to figure 146. Only phase L1 is shown in the figure. If the internal signal
3 Phase fault is activated, all four outputs START, STL1, STL2 and STL3 gets
activated.
a a>b FaultPriority
DeltaIL1 then c=a c Adaptive release
b else c=b dependent on result
from Delta logic
DeltaUL1
Sequence based
function a<b
a
L1L2 fault
then c=b c
OR b else c=a OR
L1N fault
3 Phase fault
STL1
IL1Valid &
BLOCK
IEC06000386-2-en.vsd
IEC06000386 V2 EN-US
Each of the six measuring loops has its own load (encroachment) characteristic
based on the corresponding loop impedance. The load encroachment functionality
is always activated in faulty phase identification with load encroachment for mho
(FMPSPDIS) function but the influence on the zone measurement can be switched
On/Offin the respective impedance measuring function.
same in all four quadrants. The reach for the phase selector will be reduced by the
load encroachment function, as shown in figure 147.
Blinder
Blinder provides a mean to discriminate high load from a fault. The operating
characteristic is illustrated in figure 147. There are six individual measuring loops
with the blinder functionality. Three phase-to-earth loops which estimate the
impedance according to
Zn = Uph / Iph
The start operations from respective loop are binary coded into one word and
provides an output signal STCNDPLE.
X jX
RLd
ArgLd ArgLd
R
ArgLd R
ArgLd
RLd
Operation area
en06000414.vsd
IEC06000414 V1 EN-US
Outputs SEMOD153832-327 v7
The output of the sequence components based phase selector and the delta logic
phase selector activates the output signals STL1, STL2 and STL3. If an earth fault
is detected the signal STPE gets activated.
The phase selector also gives binary coded signals that are connected to the zone
measuring element for opening the correct measuring loop(s). This is done by the
signal STCNDPHS. If only one phase is started (L1, L2 or L3), the corresponding
phase-to-earth element is enabled. STPE is expected to be made available for two-
phase and three-phase faults for the correct output to be selected. The fault loop is
indicated by one of the decimal numbers below.
The output STCNDPHS provides release information from the phase selection part
only. STCNDLE provides release information from the load encroachment part
only. STCNDPLE provides release information from the phase selection part and
the load encroachment part combined, that is, both parts have to issue a release at
the same time (this signal is normally not used in the zone measuring element). In
these signals, each fault type has an associated value, which represents the
corresponding zone measuring loop to be released. The values are presented in
table 183.
0= no faulted phases
1= L1E
2= L2E
3= L3E
4= -L1L2E
5= -L2L3E
6= -L3L1E
7= -L1L2L3E
8= -L1L2
9= -L2L3
10= -L3L1
11= L1L2L3
An additional logic is applied to handle the cases when phase-to-earth outputs are
to be asserted when the earth input G is not asserted.
8.9.1 Identification
GUID-420DD49A-C65B-4F04-B317-9558DCCE7A52 v1
S00346 V1 EN-US
S00346 V1 EN-US
GUID-119120A5-8600-44C6-9C85-81136DBBE280 v1
The line distance protection is up to five zone full scheme protection with three
fault loops for phase-to-phase faults and three fault loops for phase-to-earth fault
for each of the independent zones. Individual settings for each zone in resistive and
reactive reach gives flexibility for use as back-up protection for transformer
connected to overhead lines and cables of different types and lengths.
The distance protection zones can operate, independent of each other, in directional
(forward or reverse) or non-directional mode.
ZMRPDIS
I3P* TRIP
U3P* TRL1
BLOCK TRL2
BLKZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
IEC08000248-1-en.vsd
IEC08000248 V1 EN-US
ZMRAPDIS
I3P* TRIP
U3P* TRL1
BLOCK TRL2
BLKZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
IEC08000290_1_en.vsd
IEC08000290 V1 EN-US
ZDRDIR
I3P* STDIRCND
U3P*
IEC10000007-2-en.vsd
IEC10000007 V2 EN-US
8.9.4 Signals
PID-3649-INPUTSIGNALS v6
PID-3649-OUTPUTSIGNALS v6
PID-3648-INPUTSIGNALS v6
PID-3648-OUTPUTSIGNALS v6
PID-726-INPUTSIGNALS v3
PID-726-OUTPUTSIGNALS v3
8.9.5 Settings
PID-3649-SETTINGS v6
PID-3648-SETTINGS v6
PID-3545-SETTINGS v6
The execution of the different fault loops within the IED are of full scheme type,
which means that each fault loop for phase-to-earth faults and phase-to-phase faults
for forward and reverse faults are executed in parallel.
Figure 150 presents an outline of the different measuring loops for up to five,
impedance-measuring zones. There are 3 to 5 zones depending on product type and
variant.
IEC05000458-2-en.vsd
IEC05000458 V2 EN-US
Figure 150: The different measuring loops at phase-to-earth fault and phase-to-
phase fault.
The use of full scheme technique gives faster operation time compared to switched
schemes which mostly uses a start element to select correct voltages and current
depending on fault type. Each distance protection zone performs like one
independent distance protection IED with six measuring elements.
The distance measuring zone includes six impedance measuring loops; three
intended for phase-to-earth faults, and three intended for phase-to-phase as well as,
three-phase faults.
The distance measuring zone will essentially operate according to the non-
directional impedance characteristics presented in figure 151 and figure 152. The
phase-to-earth characteristic is illustrated with the full loop reach while the phase-
to-phase characteristic presents the per phase reach.
X (Ohm/loop)
R1PE+Rn
RFPE RFPE
X0PE-X1PE
Xn =
3
X1PE+Xn R0PE-R1PE
Rn =
3
jN jN
R (Ohm/loop)
RFPE RFPE
X1PE+Xn
RFPE RFPE
en08000280-2-en.vsd
R1PE+Rn
IEC08000280 V1 EN-US
X (Ohm/phase)
j j
R (Ohm/phase)
RFPP RFPP
2 2
X1PP
The fault loop reach with respect to each fault type may also be presented as in
figure 153. Note in particular the difference in definition regarding the (fault)
resistive reach for phase-to-phase faults and three-phase faults.
IL1 R1 + j X1
Phase-to-earth
UL1
element
Phase-to-earth
fault in phase L1 RFPE
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 )
IL1 R1 + j X1 Phase-to-phase
UL1 element L1-L2
Phase-to-phase
fault in phase RFPP
L1-L2 IL2
UL2 (Arc resistance)
R1 + j X1
The R1 and jX1 in figure 153 represents the positive sequence impedance from the
measuring point to the fault location. The settings RFPE and RFPP are the
eventual fault resistances in the faulty place.
Regarding the illustration of three-phase fault in figure 153, there is of course fault
current flowing also in the third phase during a three-phase fault. The illustration
merely reflects the loop measurement, which is made phase-to-phase.
X X X
R R R
IEC05000182-2-en.vsdx
IEC05000182 V2 EN-US
For zone 1 with load compensation feature the additional criterion applies, that all
phase-to-earth loops can be blocked when IN < IMinOpIN, regardless of the phase
currents.
ILn is the RMS value of the current in phase Ln. IN is the RMS value of the vector
sum of the three-phase currents, that is residual current 3I0.
ILmLn is the RMS value of the vector difference between phase currents Lm and
Ln.
Fault loop equations use the complex values of voltage, current, and changes in the
current. Apparent impedances are calculated and compared with the set limits. The
apparent impedances at phase-to-phase faults follow equation 80 (example for a
phase L1 to phase L2 fault).
UL1 – UL2
Zapp = -------------------------
I L1 – IL2
EQUATION1222 V1 EN-US (Equation 80)
Here U and I represent the corresponding voltage and current phasors in the
respective phase Ln (n = 1, 2, 3)
U L1
Z app =
I L1 + I N × KN
EQUATION1223 V2 EN-US (Equation 81)
Where:
are the phase voltage, phase current and residual current present to the IED
U L1
I L1
IN
KN
is defined as:
Z 0 - Z1
KN =
3 × Z1
EQUATION-2105 V2 EN-US
Z 0 = R 0 + jX 0
EQUATION2106 V2 EN-US
Z 1 = R1 + jX 1
EQUATION2107 V2 EN-US
Where
R0 is setting of the resistive zero sequence reach
X0 is setting of the reactive zero sequence reach
R1 is setting of the resistive positive sequence reach
Here IN is a phasor of the residual current in IED point. This results in the same
reach along the line for all types of faults.
The formula given in equation 81 is only valid for radial feeder application without
load. When load is considered in the case of single phase-to-earth fault,
conventional distance protection might overreach at exporting end and underreach
at importing end. The IED has an adaptive load compensation which increases the
security in such applications.
Measuring elements receive current and voltage information from the A/D
converter. The check sums are calculated and compared, and the information is
distributed into memory locations. For each of the six supervised fault loops,
sampled values of voltage (U), current (I), and changes in current between samples
(DI) are brought from the input memory and fed to a recursive Fourier filter.
The filter provides two orthogonal values for each input. These values are related
to the loop impedance according to equation 82,
X Di
U = R × i + ------ × -----
w 0 Dt
EQUATION1224 V1 EN-US (Equation 82)
X D Re ( I )
Re ( U ) = R × Re ( I ) + ------ × ------------------
w0 Dt
X DIm ( I )
Im ( U ) = R × Im ( I ) + ------ × -----------------
w0 Dt
with
w0 = 2 × p × f 0
EQUATION356 V1 EN-US (Equation 85)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real
value of the voltage and substitutes it in the equation for the imaginary part. The
equation for the Xm measured reactance can then be solved. The final result is
equal to:
Im ( U ) × DRe ( I ) – Re ( U ) × D Im ( I )
R m = ------------------------------------------------------------------------------------
DRe ( I ) × Im ( I ) – D Im ( I ) × Re ( I )
EQUATION357 V1 EN-US (Equation 86)
Re ( U ) × Im ( I ) – Im ( U ) × Re ( I )
Xm = w 0 × Dt × -------------------------------------------------------------------------------
DRe ( I ) × Im ( I ) – DIm ( I ) × Re ( I )
EQUATION358 V1 EN-US (Equation 87)
The calculated Rm and Xm values are updated each sample and compared with the
set zone reach. The adaptive tripping counter counts the number of permissive
tripping results. This effectively removes any influence of errors introduced by the
capacitive voltage transformers or by other factors.
For the L1-L2 element, the equation in forward direction is according to.
where:
ArgDir is the setting for the lower boundary of the forward directional characteristic, by default
set to 15 (= -15 degrees) and
ArgNegRes is the setting for the upper boundary of the forward directional characteristic, by default
set to 115 degrees, see figure 155.
is positive sequence phase voltage in phase L1
U 1L1
is positive sequence memorized phase voltage in phase L1
U 1L1M
is phase current in phase L1
I L1
is voltage difference between phase L1 and L2 (L2 lagging L1)
U 1L1L 2
is memorized voltage difference between phase L1 and L2 (L2 lagging L1)
U 1L1L 2 M
is current difference between phase L1 and L2 (L2 lagging L1)
I L1L 2
The setting of ArgDir and ArgNegRes is by default set to 15 (= -15) and 115
degrees respectively (as shown in figure 155). It should not be changed unless
system studies have shown the necessity.
ZDRDIR gives binary coded directional information per measuring loop on the
output STDIRCND.
STDIR= STFWL1*1+STFWL2*2+STFWL3*4+STFWL1L2*8+
+STFWL2L3*16+STFWL3L1*32+STRVL1*64+STRVL2*128+
+STRVL3*256+STRVL1L2*512+STRVL2L3*1024+STRVL3L1*2048
ArgNegRes
ArgDir
R
en05000722.vsd
IEC05000722 V1 EN-US
Figure 155: Setting angles for discrimination of forward and reverse fault in
Directional impedance quadrilateral function ZDRDIR
The polarizing voltage is available as long as the positive sequence voltage exceeds
5% of the set base voltage UBase. So the directional element can use it for all
unsymmetrical faults including close-in faults.
For close-in three-phase faults, the U1L1M memory voltage, based on the same
positive sequence voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is
restored.
• If the current is still above the set value of the minimum operating current
(between 10 and 30% of the set IED rated current IBase), the condition seals
in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element
in the reverse direction remains in operation.
• If the current decreases below the minimum operating value, the memory
resets until the positive sequence voltage exceeds 10% of its rated value.
The design of the distance protection zones are presented for all measuring loops:
phase-to-earth as well as phase-to-phase.
Phase-to-earth related signals are designated by L1N, L2N and L3N.. The phase-to-
phase signals are designated by L1L2, L2L3, and L3L1.
The STCND input signal represents a connection of six different integer values
from Phase selection with load encroachment, quadrilateral characteristic function
FRPSPDIS within the IED, which are converted within the zone measuring
function into corresponding boolean expressions for each condition separately.
Input signal STCND is connected to FRPSPDISfunction output STCNDZ.
The input signal DIRCND is used to give condition for directionality for the
distance measuring zones. The signal contains binary coded information for both
forward and reverse direction. The zone measurement function filter out the
relevant signals depending on the setting of the parameter OperationDir. It must be
configured to the STDIRCND output on directional function ZDRDIR function.
STZMPP
OR
STCND
AND STNDL1L2
L1L2
STNDL2L3
L2L3 AND
AND STNDL1N
L1N
AND STNDL2N
L2N
STNDL3N
L3N AND
OR STPE
OR
VTSZ STND
OR AND
BLOCK
BLOCFUNC BLK
99000557-2.vsd
IEC99000557-TIFF V3 EN-US
Composition of the phase start signals for a case, when the zone operates in a non-
directional mode, is presented in figure 76.
STNDL1N
OR
STNDL2N 15 ms
AND t STL1
STNDL3N
STNDL1L2 OR 15 ms
AND t STL2
STNDL2L3
15 ms
STNDL3L1 AND t STL3
OR
15 ms
AND t START
OR
BLK
IEC09000889-1-en.vsd
IEC09000889 V1 EN-US
Results of the directional measurement enter the logic circuits, when the zone
operates in directional (forward or reverse) mode, as shown in figure 77.
STNDL1N
AND
DIRL1N
STZMPE.
OR
STNDL2N
DIRL2N AND
STNDL3N 15 ms
OR STL1
AND AND t
DIRL3N
STNDL1L2
DIRL1L2 AND 15 ms
OR STL2
AND t
STNDL2L3
DIRL2L3 AND
15 ms
OR STL3
STNDL3L1 AND t
DIRL3L1 AND
STZMPP
OR
BLK
15 ms
OR START
AND t
IEC09000888-2-en.vsd
IEC09000888 V2 EN-US
Tripping conditions for the distance protection zone one are symbolically presented
in figure 78.
Timer tPP=On
STZMPP AND tPP
AND
t
BLOCFUNC
OR OR
tPE
t
AND
Timer tPE=On AND
STZMPE 15ms
BLKTR AND t
TRIP
BLK OR
IEC09000887-3-en.vsdx
IEC09000887 V3 EN-US
8.10.1 Identification
GUID-07DB9506-656C-4E5F-A043-3DAA624313C7 v2
SYMBOL-DD V1 EN-US
The ability to accurately and reliably classify the different types of fault, so that
single pole tripping and autoreclosing can be used plays an important role in
today's power systems. Phase selection, quadrilateral characteristic with settable
angle FRPSPDIS is designed to accurately select the proper fault loop in the
distance function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may make
fault resistance coverage difficult to achieve. Therefore, FRPSPDIS has a built-in
algorithm for load encroachment, which gives the possibility to enlarge the
resistive setting of both the phase selection and the measuring zones without
interfering with the load.
The extensive output signals from the phase selection gives also important
information about faulty phase(s) which can be used for fault analysis.
FRPSPDIS
I3P* TRIP
U3P* START
BLOCK STFWL1
DIRCND STFWL2
STFWL3
STFWPE
STRVL1
STRVL2
STRVL3
STRVPE
STNDL1
STNDL2
STNDL3
STNDPE
STFW1PH
STFW2PH
STFW3PH
STPE
STPP
STCNDZ
STCNDLE
IEC08000430-2-en.vsd
IEC08000430 V2 EN-US
8.10.4 Signals
PID-3643-INPUTSIGNALS v7
PID-3643-OUTPUTSIGNALS v7
8.10.5 Settings
PID-3643-SETTINGS v7
The basic impedance algorithm for the operation of the phase selection measuring
elements is the same as for the distance zone measuring function. Phase selection,
quadrilateral characteristic with settable angle (FRPSPDIS) includes six impedance
measuring loops; three intended for phase-to-earth faults, and three intended for
phase-to-phase as well as for three-phase faults.
• Residual current criteria, that is, separation of faults with and without earth
connection
• Regular quadrilateral impedance characteristic
• Load encroachment characteristics is always active but can be switched off by
selecting a high setting.
There are output from FRPSPDIS that indicate whether a start is in forward or
reverse direction or non-directional, for example STFWL1, STRVL1 and STNDL1.
These directional indications are based on the sector boundaries of the directional
function and the impedance setting of FRPSPDIS function. Their operating
characteristics are illustrated in figure 161.
X X X
R
R R
en08000286.vsd
IEC08000286 V1 EN-US
The setting of the load encroachment function may influence the total operating
characteristic, for more information, refer to section "Load encroachment".
The input DIRCND contains binary coded information about the directional
coming from the directional function ZDRDIR. It shall be connected to the STDIR
output on ZDRDIR. This information is also transferred to the input DIRCND on
the distance measuring zones, that is, the ZMRPDIS block.
STDIR= STFWL1*1+STFWL2*2+STFWL3*4+STFWL1L2*8+
+STFWL2L3*16+STFWL3L1*32+STRVL1*64+STRVL2*128+
+STRVL3*256+STRVL1L2*512+STRVL2L3*1024+STRVL3L1*2048
The code built up for release of the measuring fault loops is as follows:
ULn
ZPHSn =
ILn
EQUATION1255 V1 EN-US (Equation 90)
where:
n corresponds to the particular phase (n=1, 2 or 3)
The resistance RN and reactance XN are the impedance in the earth-return path
defined according to equation 93 and equation 94.
R 0 PE - R1PE
RN =
3
EQUATION-2125 V1 EN-US (Equation 91)
R0 - R1
RN =
3
EQUATION1256 V1 EN-US (Equation 91)
X 0 - X1
XN =
3
EQUATION1257 V1 EN-US (Equation 92)
X (ohm/loop)
R1PE+RN
RFRvPE RFFwPE
X1+XN
RFFwPE
RFRvPE R (Ohm/loop)
X1+XN
RFRvPE RFFwPE
R1PE+RN
IEC09000633-1-en.vsd
IEC09000633 V1 EN-US
Besides this, the 3I0 residual current must fulfil the conditions according to
equation 93 and equation 94.
3 × I0 ³ 0.5 × IMinOpPE
EQUATION2108 V1 EN-US (Equation 93)
3 × I0 ³ INReleasePE
------------------------------------ × Iphmax
100
EQUATION766 V1 EN-US (Equation 94)
where:
IMinOpPE is the minimum operation current for forward zones
INReleasePE is the setting for the minimum residual current needed to enable operation in the
phase-to-earth fault loops (in %).
Iphmax is the maximum phase current in any of three phases.
ULm - ULn
ZPHS =
-2 × ILn
EQUATION1258 V1 EN-US (Equation 95)
ULm is the leading phase voltage, ULn the lagging phase voltage and ILn the
phase current in the lagging phase n.
X (ohm/phase)
0.5·FRvPP
R1PP 0.5·RFFwPP
X1
0.5·RFFwPP
R (ohm/phase)
0.5·RFRvPP
X1
R1PP
0.5·RFRvPP 0.5·RFFwPP
IEC09000634-1-en.vsd
IEC09000634 V1 EN-US
In the same way as the condition for phase-to-earth fault, there are current
conditions that have to be fulfilled in order to release the phase-to-phase loop.
Those are according to equation 96 or equation 97.
3I 0 < IMinOpPE
EQUATION2109 V1 EN-US (Equation 96)
INBlockPP
3I 0 < × Iph max
100
EQUATION2110 V1 EN-US (Equation 97)
where:
IMinOpPE is the minimum operation current for forward earth measuring loops,
INBlockPP is 3I0 limit for blocking phase-to-phase measuring loop and
Iphmax is maximal magnitude of the phase currents.
The operation conditions for three-phase faults are the same as for phase-to-phase
fault, that is equation 95, equation 96 and equation 97 are used to release the
operation of the function.
X (ohm/phase)
4 × X1PP
3
0.5·RFFwPP·K3
X1·K3 30 deg 2
RFwPP ×
3
R (ohm/phase)
0.5·RFRvPP·K3
K3 = 2 / sqrt(3)
30 deg
IEC09000635-1-en.vsd
IEC09000635 V2 EN-US
Figure 164: The characteristic of FRPSPDIS for three-phase fault (set angle
70°)
Each of the six measuring loops has its own load encroachment characteristic based
on the corresponding loop impedance. The load encroachment functionality is
always active, but can be switched off by selecting a high setting.
RLdFw
ArgLd ArgLd
R
ArgLd ArgLd
RLdRv
IEC09000042-1-en.vsd
IEC09000042 V1 EN-US
X X
R R
STCNDZ STCNDLE
IEC10000099-1-
en.vsd
IEC10000099 V1 EN-US
When FRPSPDIS is set to operate together with a distance measuring zone the
resultant operate characteristic could look like in figure 167. The figure shows a
distance measuring zone operating in forward direction. Thus, the operating area of
the zone together with the load encroachment is highlighted in black.
"Phase selection"
"quadrilateral" zone
Load encroachment
characteristic
Directional line
en05000673.vsd
IEC05000673 V1 EN-US
Figure 167 is valid for phase-to-earth. During a three-phase fault, or load, when the
quadrilateral phase-to-phase characteristic is subject to enlargement and rotation
the operate area is transformed according to figure 168. Notice in particular what
happens with the resistive blinders of the "phase selection" "quadrilateral" zone.
Due to the 30-degree rotation, the angle of the blinder in quadrant one is now 100
degrees instead of the original 70 degrees (if the angle setting is 70 degrees). The
blinder that is nominally located to quadrant four will at the same time tilt outwards
and increase the resistive reach around the R-axis. Consequently, it will be more or
less necessary to use the load encroachment characteristic in order to secure a
margin to the load impedance.
X (W / phase)
Phase selection
”Quadrilateral” zone
R (W / phase)
IEC09000049-1-en.vsd
IEC09000049 V1 EN-US
The result from rotation of the load characteristic at a fault between two phases is
presented in fig 169. Since the load characteristic is based on the same
measurement as the quadrilateral characteristic, it will rotate with the quadrilateral
characteristic clockwise by 30 degrees when subject to a pure phase-to-phase fault.
At the same time the characteristic will "shrink" by 2/√3, from the full RLdFw and
RLdRv reach, which is valid at load or three-phase fault.
IEC08000437.vsd
IEC08000437 V1 EN-US
Figure 169: Rotation of load characteristic for a fault between two phases
Figure 170 presents schematically the creation of the phase-to-phase and phase-to-
earth operating conditions. Consider only the corresponding part of measuring and
logic circuits, when only a phase-to-earth or phase-to-phase measurement is
available within the IED.
LDEblock
& 15 ms
t STPE
&
INReleasePE
3I 0 ≥ ⋅ Iphmax
100 STCNDLE
Bool to &
BLOCK integer
15 ms
3I 0 < IMinOpPE & t STPP
10 ms 20 ms
OR & t t
IRELPP
INBlockPP
3I 0 < ⋅ Iphmax
100
IEC09000149_2_en.vsd
IEC09000149 V2 EN-US
INDL1N
INDL2N
INDL3N
15 ms
STNDPE
IRELPE OR t
LDEblockL1N
AND 15 ms
ZML1N STNDL1
OR t
LDEblockL2N
AND
ZML2N
15 ms
LDEblockL3N STNDL2
OR t
AND
ZML3N
LDEblockL1L2 15 ms
STNDL3
AND OR t
ZML1L2
LDEblockL2L3
AND INDL1L2
ZML2L3
LDEblockL3L1 INDL2L3
AND
ZML3L1 INDL3L1
IRELPP 15 ms
STNDPP
OR t
IEC00000545-3-en.vsd
IEC00000545-TIFF V3 EN-US
INDL1N
AND
DRVL1N
INDL1L2 15 ms STRVL1
AND OR t
DRVL1L2
INDL3L1
AND
DRVL3L1 15 ms
STRVPE
INDL2N OR t
AND
DRVL2N
INDL1L2 15 ms
STRVL2
AND OR t
INDL2L3 INDL1N
AND INDL2N
DRVL2L3
INDL3N Bool to STCNDZ
INDL3N INDL1L2 integer
AND INDL2L3
DRVL3N INDL3L1
INDL2L3 15 ms
STRVL3
AND OR t
INDL3L1
15 ms
AND STRVPP
OR t
IEC00000546_2_en.vsd
IEC00000546-TIFF V2 EN-US
AND
INDL1N
AND 15 ms 15 ms
DFWL1N STFW1PH
AND OR t t
INDL1L2
15 ms STFWL1
AND OR t
DFWL1L2
INDL3L1
AND
AND
DFWL3L1 15 ms
STFWPE
INDL2N OR t
AND
DFWL2N
AND 15 ms
INDL1L2 STFWL2
t
AND OR
15 ms 15 ms
INDL2L3 STFW2PH
AND OR t t
AND
DFWL2L3
INDL3N
AND AND
DFWL3N 15 ms
STFWL3
t
INDL2L3
AND OR
15 ms
INDL3L1 STFW3PH
AND t
AND
15 ms
STFWPP
OR t
IEC05000201_2_en.vsd
IEC05000201 V2 EN-US
Figure174 presents the composition of output signals TRIP and START, where
internal signals STNDPP, STFWPP and STRVPP are the equivalent to internal
signals STNDPE, STFWPE and STRVPE, but for the phase-to-phase loops.
TimerPP=Off
tPP
AND AND
t
TRIP
OR OR
tPE
TimerPE=Off
t
AND AND
STNDPP
STFWPP OR
STRVPP
START
OR
STNDPE
STFWPE OR
STRVPE
IEC08000441_2_en.vsd
IEC08000441-1 V2 EN-US
S00346 V1 EN-US
The ZMFPDIS function is a six zone full scheme protection with three fault loops
for phase-to-phase faults and three fault loops for phase-to-earth faults for each of
the independent zones, which makes the function suitable in applications with
single-phase autoreclosing.
including close-in three-phase faults, simultaneous faults and faults with only zero-
sequence in-feed.
ZMFPDIS
I3P* TRIP
U3P* TRZ1
BLOCK TRL1Z1
VTSZ TRL2Z1
BLKZ1 TRL3Z1
BLKZ2 TRZ2
BLKZ3 TRL1Z2
BLKZ4 TRL2Z2
BLKZ5 TRL3Z2
BLKZRV TRZ3
BLKTRZ1 TRZ4
BLKTRZ2 TRZ5
BLKTRZ3 TRZRV
BLKTRZ4 START
BLKTRZ5 STZ1
BLKTRZRV STNDZ1
EXTNST STZ2
RELCNDZ1 STL1Z2
RELCNDZ2 STL2Z2
RELCNDZ3 STL3Z2
RELCNDZ4 STNDZ2
RELCNDZ5 STZ3
RELCNDZRV STNDZ3
STZ4
STNDZ4
STZ5
STNDZ5
STZRV
STL1ZRV
STL2ZRV
STL3ZRV
STNDZRV
STND
STNDL1
STNDL2
STNDL3
STNDPE
STFWL1
STFWL2
STFWL3
STFWPE
STRVL1
STRVL2
STRVL3
STRVP E
STFW1PH
STFW2PH
STFW3PH
STPE
STPP
IEC11000433-5-en.vsdx
IEC11000433 V5 EN-US
8.11.4 Signals
PID-6815-INPUTSIGNALS v3
PID-7066-OUTPUTSIGNALS v1
8.11.5 Settings
PID-7066-SETTINGS v2
Practically all voltage, current and impedance quantities used within the ZMFPDIS
function are derived from fundamental frequency phasors filtered by a half cycle
filter.
The phasor filter is frequency adaptive in the sense that its coefficients are changed
based on the estimated power system frequency.
A half cycle filter will not be able to reject both even and odd harmonics. So, while
odd harmonics will be completely attenuated, accuracy will be affected by even
harmonics. Even harmonics will not cause the distance zones to overreach
however; instead there will be a slightly variable underreach, on average in the
same order as the magnitude ratio between the harmonic and fundamental
component.
The different fault loops within the IED are of full scheme type, which means that
earth fault loop for phase-to-earth faults and phase-to-phase faults for forward and
reverse faults are executed in parallel.
Figure 176 presents an outline of the different measuring loops for the six distance
zones.
IEC05000458-2-en.vsd
IEC05000458 V2 EN-US
Figure 176: The different measuring loops at phase-to-earth fault and phase-to-
phase fault
Each distance protection zone performs like one independent distance protection
function with six measuring elements.
Transients from CVTs may have a significant impact on the transient overreach of
a distance protection. At the same time these transients can be very diverse in
nature from one type to the other; in fact, more diverse than can be distinguished
by the algorithm itself in the course of a few milliseconds. So, a setting (CVTtype)
is introduced in order to inform the algorithm about the type of CVT applied and
There are two types of CVTs from the function point of view, the passive and the
active type, which refers to the type of ferro-resonance suppression device that is
employed. The active type requires more rigorous filtering which will have a
negative impact on operate times. However, this will be evident primarily at higher
source impedance ratios (SIRs), SIR 5 and above, or close to the reach limit.
To avoid overreach and at the same time achieve fast operate times, a
supplementary circular characteristic is implemented. A circular characteristic
exists for every measuring loop and quadrilateral/mho characteristic. There are no
specific reach settings for this circular zone. It uses the normal quadrilateral/mho
zone settings to determine a reach that will be appropriate. This implies that the
circular characteristic will always have somewhat shorter reach than the
quadrilateral/mho zone.
This continuous criteria will, in the vast majority of cases, operate in parallel and
carry on the fault indication after the current change phase has ended. Only in some
particularly difficult faults on heavily loaded lines, the continuous criteria might
not be sufficient, for example, when the estimated fault impedance resides within
the load area defined by the load encroachment characteristic. In this case, the
indication will be restricted to a pulse lasting for one or two power system cycles.
The phase-selection element can, owing to the current change criteria, distinguish
faults with minimum influence from load and fault impedance. In other words, it is
not restricted by a load encroachment characteristic during the current change
phase. This significantly improves performance for remote phase-to-earth faults on
heavily loaded lines. One exception, however, are three-phase faults to which the
load encroachment characteristic always has to be applied in order to distinguish
fault from load.
Phase-to-phase-earth faults (also called double earth faults) will practically always
activate phase-to-phase zone measurements. Measurement in two phase-to-earth
loops at the same time is associated with so-called simultaneous faults: two earth
faults at the same time, one each on the two circuits of a double line, or when the
zero sequence current is relatively high due to a source with low Z0/Z1 ratio. In
these situations zone measurement will be released both for the related phase-to-
earth loops and the phase-to-phase loop simultaneously. On the other hand,
simultaneous faults closer to the remote bus will gradually take on the properties of
a phase-to-phase-earth fault and the function will eventually use phase-to-phase
zone measurements also here.
In cases where the fault current infeed is more or less completely of zero sequence
nature (all phase currents in phase), the measurement will be performed in the
phase-to-earth loops only for a phase-to-phase-earth fault.
Several criteria are employed when making the directional decision. The basis is
provided by comparing a positive sequence based polarizing voltage with phase
currents. For extra security, especially in making a very fast decision, this method
is complemented with an equivalent comparison where, instead of the phase
current, the change in phase current is used. Moreover, a basic negative sequence
directional evaluation is taken into account as a reliable reference during high load
condition. Finally, a zero sequence directional evaluation is used whenever there is
more or less exclusive zero sequence in-feed.
The directional sectors that represent forward direction, one per measuring loop,
are defined by the following equations.
U PolL1
−15° < arg < 120°
I L1
IECEQUATION15059 V1 EN-US (Equation 98)
U PolL1L 2
−15° < arg < 120°
I L1L 2
IECEQUATION15060 V1 EN-US (Equation 99)
Where:
UPolL1 is the polarizing voltage for phase L1.
UPolL1L2 is the polarizing voltage difference between phase L1 and L2 (L2 lagging L1).
IL1L2 is the current difference between phase L1 and L2 (L2 lagging L1).
The corresponding reverse directional sectors range from 165 to -60 degrees.
Since the polarizing voltage is also used for the Mho distance characteristics, the
magnitude of the voltage is just as interesting as the phase. If there are symmetrical
conditions and the measured per phase positive sequence voltage magnitude is
above 75% of the base voltage before the fault, the pre-fault magnitude will be
memorized and used as long as there is a fault. The phase angle however will only
be memorized (locked) for 75 ms at a time, not to lose synchronism with the real
system voltage.
Should the positive sequence voltage drop below 2% of the base voltage, it will be
considered invalid. In this situation, directional signals and starts from Mho
elements will be sealed-in and kept static as long as there is a fault.
For ZMFCPDIS, when option SeriesComp is chosen for OperationSC, the voltages
of faulty phases will be discarded in order not to affect the polarizing voltage with
voltage reversal.
The ZMFPDIS function has to be blocked by an additional function like the Fuse
failure supervision (FUFSPVC) or an equivalent external device. Typically, the
binary input VTSZ is used for this purpose.
There is need for external blocking of the ZMFPDIS function during power
swings, either from the Power Swing Blocking function (ZMRPSB) or an external
device.
ZMFPDIS implements quadrilateral and mho characteristic in all the six zones
separately. Set OpModePEZx or OpModePPZx to Quadrilateral, to choose
particular measuring loop in a zone to work as quadrilateral distance protection.
Zone 1 has individual positive sequence impedance settings for phase-to-phase and
phase-to-earth (X1PPZ1, R1PPZ1 and X1PEZ1, R1PEZ1). For the other zones, the
X (Ohm/phase)
X1Zx
R (Ohm/phase)
RFPPZx RFPPZx
2 2
X1Zx
X (Ohm/loop)
R1Zx+RNZx
RFPEZx RFPEZx
X0Zx-X1Zx
XNZx=
3
X1Zx+XNZx R0Zx-R1Zx
RNZx=
3
φN φN
R (Ohm/loop)
RFPEZx RFPEZx
X1Zx+XNZx
RFPEZx RFPEZx
R1Zx+RNZx IEC11000415-2-en.vsdx
IEC11000415 V2 EN-US
The faulty loop in relation to the fault type can be presented as in figure 179. The
main intention with this illustration is to make clear how the fault resistive reach
should be interpreted and set. Note in particular that the setting RFPPZx always
represents the total fault resistance of the loop, regardless the fact that the fault
resistance (arc) may be divided into parts like for three-phase or phase-to-phase
faults. The R1Zx + jX1Zx represent the positive sequence impedance from the
measuring point to the fault location.
Phase-to-earth
RFPEZx
fault in phase L1
(Arc + tower
resistance)
0
IN (R0Zx-R1Zx)/3 +
j (X0Zx-X1Zx)/3 )
ZMFPDIS implements quadrilateral and mho characteristic in all the six zones
separately. Set OpModePEZx or OpModePPZx setting to Mho or Offset, to choose
a particular measuring loop in a zone to work as mho (or Offset Mho) distance
protection.
X
X
Z4
Z3
ZS=0
Z2
Z1 R
Z5 R
ZS=Z1
ZRV
ZS=2Z1
IEC15000056-1-en.vsdx
IEC15000056 V1 EN-US
Figure 180: Mho, offset mho characteristics and the source impedance
influence on the mho characteristic
The mho characteristic has a dynamic expansion due to the source impedance.
Instead of crossing the origin, as for the mho to the left of figure 180, which is only
valid where the source impedance (Zs) is zero, the crossing point is moved to the
coordinates of the negative source impedance given an expansion of the circle
shown to the right of figure 180. Z1 denotes the complex positive sequence
impedance.
ZMFPDIS fixes zone 1 and 2 in Forward mode and zone RV in Reverse mode.
Zone 3-5 can be set to Non-directional, Forward or Reverse by setting the
parameter DirModeZx (where x is 3-5 depending on selected zone).
X X X
(a) Rset (b) (c) Rset
Xset Xset
R R R
Xset
(a)-(f)
Rset For phase-to-phase fault
Rset R1Zx
Forward Reverse Non-directional
Xset X 1Zx
Mho Characteristics For phase-to-earth fault
Rset R1Zx RNZx
Xset X 1Zx XNZx
(d) X
(e) X (f) X X 0 Zx X 1Zx
XNZx
3
R 0 Zx R1Zx
RNZx
Rset 3
Rset Rset
R R R
IEC15000055 V2 EN-US
For each zone, the impedance is set in cartesian coordinates (resistance and
reactance) which is the same as for quadrilateral characteristic.
The ZMFPDIS function has only one set of reach setting so the reverse will be the
same as for the forward reach, meaning that the non-directional offset mho
characteristic will always be centered around the origin. In detail, for Zone 1, the
resistive and reactance reaches for phase-to-earth fault and phase-to-phase fault are
set individually using the settings R1PPZ1, X1PPZ1, R1PEZ1, X1PEZ1, X0Z1 and
R0Z1. In Zone 2-5 and Zone RV, the same zone reach settings are used for phase-
to-earth fault and phase-to-phase (R1Zx, X1Zx, X0Zx and R0Zx, x=2-5 or RV).
The mho algorithm is based on the phase comparison of an operating phasor and a
polarizing phasor. When the operating phasor leads the reference polarizing phasor
by 90 degrees or more, the function operates and gives a trip output.
Mho GUID-D162893C-918A-4DDA-AAC2-0D0A814D85C1 v1
The plain Mho circle has the characteristic as in figure 182. The condition for
deriving the angle β is according to equation 100.
(
β = arg U L1L 2 − I L1L 2 ⋅ Z 1set − arg U pol ) ( )
IECEQUATION15027 V1 EN-US (Equation 100)
where
is the positive sequence impedance setting for phase-to-phase fault in zone direction
Z 1set
For Zone 1,
where
R1PPZ1 is the positive sequence resistive reach for phase-to-phase fault for zone 1
X1PPZ1 is the positive sequence reactance reach for phase-to-phase fault for zone 1
where
R1Zx is the positive sequence resistive reach for zone x (x=2-5 and RV)
X1Zx is the positive sequence reactance reach for zone x (x=2-5 and RV)
is the polarizing voltage
Upol
IL1L2 jX
I L1L 2 Z1set
UcompUL1L2 IL1L2 Z1set
UL1L2
U pol
I L1L 2 R
IEC15000060-1-en.vsdx
IEC15000060 V1 EN-US
Figure 182: Simplified mho characteristic and vector diagram for phase L1-to-
L2 fault
The characteristic for offset mho is a circle with origin as the center and magnitude
of Z 1set as the radius, where Z 1set is settable through the resistance and reactance
settings.
The condition for operation at phase-to-phase fault is that the angle β between the
two compensated voltages is greater than or equal to 90° (figure 183). The angle
will be 90° for fault location on the boundary of the circle.
U
L1L 2 I L1L 2 Z 1set
arg
U L1L 2 I L1L 2 Z1set
IECEQUATION15008 V2 EN-US (Equation 103)
I L1L 2 jX
I L1L 2 Z1set
U L1L 2
I L1L 2 R
I L1L 2 Z1set
IEC15000058-2-en.vsdx
IEC15000058 V2 EN-US
Figure 183: Simplified offset mho characteristic and voltage vector for phase L1
to L2 fault
Compensation for earth return path for faults involving earth is done by setting the
positive and zero sequence impedance of the line. It is known that the ground
compensation factor KN is,
Z 0set − Z 1set
KN =
3 ⋅ Z 1set
IECEQUATION15017 V1 EN-US
Z 0set = R 0Zx + j ⋅ X 0 Zx
IECEQUATION15018 V1 EN-US
For Zone 1,
Z 1set = R1PEZ 1 + j ⋅ X 1PEZ 1
IECEQUATION15019 V1 EN-US
where
is the complex zero sequence impedance of the line in Ω/phase
Z 0set
is the complex positive sequence impedance of the line in Ω/phase
Z 1set
R1PEZ1 is the positive sequence resistive reach of the line in Ω/phase for
phase-to-earth fault for zone 1
X1PEZ1 is the positive sequence reactance reach of the line in Ω/phase for
phase-to-earth fault for zone 1
R0Zx is the zero sequence resistive reach of the line in Ω/phase for zone
x (x=2-5, or RV)
X0Zx is the zero sequence reactance reach of the line in Ω/phase for
zone x (x=2-5, or RV)
For an earth fault in phase L1, the angle β between the compensation voltage and
the polarizing voltage Upol is,
where
is the phase voltage in faulty phase L1
UL1
is the phase current in faulty phase L1
IL1
3I0 is the zero-sequence current in faulty phase L1
IL1•jX
U L1
I L1 Z1set
U pol
IL1•R
IEC15000059-1-en.vsdx
IEC15000059 V1 EN-US
Figure 184: Simplified offset mho characteristic and vector diagram for phase
L1-to-earth fault
The condition for operation of offset mho at phase-to-earth fault is that the angle β
between the two compensated voltages is equal to or greater than 90°, see figure
185. The angle will be 90° for fault location on the boundary of the circle.
arg U L1 ( I L1 3I 0 K N ) Z1set arg U L1 ( I L1 3I 0 K N ) Z1set
IL1• jX
U comp1 U L1 ( I L1 3I 0 K N ) Z1set
( I L1 3I 0 K N ) Z1set
U L1
IL1• R
( I L1 3I 0 K N ) Z1set
IEC15000057-2-en.vsdx
IEC15000057 V2 EN-US
Figure 185: Simplified offset mho characteristic and voltage vector for phase
L1-to-earth fault
In some cases the measured load impedance might enter the set zone characteristic
without any fault on the protected line. This phenomenon is called load
encroachment and it might occur when an external fault is cleared and high
emergency load is transferred onto the protected line. The effect of load
encroachment is illustrated on the left in figure 186. A load impedance within the
characteristic would cause an unwanted trip. The traditional way of avoiding this
situation is to set the distance zone resistive reach with a security margin to the
minimum load impedance. The drawback with this approach is that the sensitivity
of the protection to detect resistive faults is reduced.
The IED has a built in feature which shapes the characteristic according to the
characteristic shown in figure 186. The load encroachment algorithm will increase
the possibility to detect high fault resistances, especially for phase-to-earth faults at
the remote line end. For example, for a given setting of the load angle ArgLd, the
resistive blinder for the zone measurement can be set according to figure 186
affording higher fault resistance coverage without risk for unwanted operation due
to load encroachment. Separate resistive blinder settings are available in forward
and reverse direction.
The use of the load encroachment feature is essential for long heavily loaded lines,
where there might be a conflict between the necessary emergency load transfer and
necessary sensitivity of the distance protection. The function can also preferably be
used on heavy loaded, medium long lines. For short lines, the major concern is to
get sufficient fault resistance coverage. Load encroachment is not a major
problem. .
Z1
ArgLd
[1]
RLdRv RLdFw
IEC09000248-3-en.vsdx
IEC09000248 V3 EN-US
PHSL1, PHSL2,...PHSL3L1 are internal binary logical signals from the Phase-
selection element. They correspond directly to the six loops of the distance zones
and determine which loops should be released to operate.
The internal input 'IN present' is activated if the residual current (3I0) exceeds 10%
of the maximum phase current magnitude and at the same time is above 5% of
[1] RLdRv=RLdRvFactor*RLdFw
DirModeZ3-5
TRUE (1)
FW(Ln & LmLn) Forward
RV(Ln & LmLn) Reverse
IEC12000137-2-en.vsd
IEC12000137 V3 EN-US
ZML1Zx PEZx
OR
PHSL1
AND
DIRL1Zx AND
ZML2Zx
PHSL2
AND
DIRL2Zx AND
ZML3Zx L1Zx
OR
PHSL3
AND
DIRL3Zx AND
ZML1L2Zx L2Zx
PHSL1L2 OR
AND
DIRL1L2Zx AND
ZML2L3Zx
PHSL2L3 L3Zx
AND OR
DIRL2L3Zx AND
ZML3L1Zx
PHSL3L1
AND
DIRL3L1Zx AND
L1N
PPZx
L2N OR
L3N
RELCNDZx Integer L1L2
to Bool
L2L3
NDZx
L1L3 OR
IEC12000140-2-en.vsdx
IEC12000140 V2 EN-US
TimerModeZx =
Enable PhPh or
Ph-E PhPh
PPZx AND tPPZx
OR AND
AND t
PEZx
AND tPEZx OR
OR
AND t
AND
BLOCK
VTSZ
BLKZx OR
BLKTRZx
OR TimerLinksZx
LoopLink (tPP-tPE)
ZoneLinkStart LoopLink & ZoneLink
OR
Phase Selection No Links
1st starting zone
External start FALSE (0)
LNKZ2
LNKZx
AND
OR
TimerLinksZx =
LNKZ4 LoopLink & ZoneLink
LNKZ5
EXTNST
IEC12000139-4-en.vsdx
IEC12000139 V4 EN-US
15 ms
TZx
t TRIPZx
AND
TRL1Zx
OR AND
BLOCK
VTSZ TRL2Zx
OR AND
BLKZx
TRL3Zx
AND
15 ms
L1Zx
t STL1Zx
AND
15 ms
L2Zx
t STL2Zx
AND
15 ms
t STL3Zx
AND
PPZx 15 ms
PEZx OR t STARTZx
AND
15 ms
NDZx
t STNDZx
AND
IEC12000138-2-en.vsd
IEC12000138 V2 EN-US
15 ms
OR t STPE
AND
15 ms
OR t
AND
15 ms
OR t STNDL2
PHSL1L2 AND
15 ms
OR t STNDL3
AND
15 ms
OR t STPP
AND
BLOCK STARTND
OR
VTSZ OR
STPHS
STNDPE
AND
IEC12000133-3-en.vsdx
IEC12000133 V3 EN-US
PHSL1
FWL1 AND
15 ms
FWL2 AND OR t
AND
FWL3 AND 15 ms
PHSL1L2 OR t STFWL2
AND
FWL1L2 AND
PHSL2L3 15 ms
FWL2L3 AND OR t STFWL3
AND
FWL3L1 AND
OR
STFWPE
IN present AND
STFW1PH
=1
BLOCK
VTSZ OR
STFW2PH
=2
STFW3PH
=3
IEC12000134-2-en.vsd
IEC12000134 V2 EN-US
PHSL1
RVL1 AND
15 ms
RVL2 AND OR t
AND
RVL3 AND 15 ms
PHSL1L2 OR t STRVL2
AND
RVL1L2 AND
PHSL2L3 15 ms
RVL2L3 AND OR t STRVL3
AND
RVL3L1 AND
OR
STRVPE
IN present AND
BLOCK
VTSZ OR
IEC12000141-2-en.vsdx
IEC12000141 V2 EN-US
8.11.7.10 Measurement
The protection, control, and monitoring IEDs have functionality to measure and
further process information for currents and voltages obtained from the pre-
processing blocks. The number of processed alternate measuring quantities
depends on the type of IED and built-in options.
Measured value below zero point clamping limit is forced to zero. This allows the
noise in the input signal to be ignored. The zero point clamping limit is a setting
(XZeroDb where X equals Z).
Users can continuously monitor the measured quantity available in the function
block by means of four defined operating thresholds, see figure 194. The
monitoring has two different modes of operating:
• Overfunction, when the measured quantity exceeds the High limit (XHiLim) or
High-high limit (XHiHiLim) pre-set values
• Underfunction, when the measured quantity decreases under the Low limit
(XLowLim) or Low-low limit (XLowLowLim) pre-set values.
X_RANGE = 3
High-high limit
X_RANGE= 1 Hysteresis
High limit
X_RANGE=0
X_RANGE=0 t
Low limit
X_RANGE=2
Low-low limit
X_RANGE=4
IEC05000657-3-en.vsdx
IEC05000657 V3 EN-US
The logical value of the functional output signals changes according to figure 194.
The user can set the hysteresis (XLimHyst), which determines the difference
between the operating and reset value at each operating point, in wide range for
each measuring channel separately. The hysteresis is common for all operating
values within one channel.
The actual value of the measured quantity is available locally and remotely. The
measurement is continuous for each measured quantity separately, but the reporting
of the value to the higher levels depends on the selected reporting mode. The
following basic reporting modes are available:
In addition to the normal cyclic reporting the IED also report spontaneously when
measured value passes any of the defined threshold limits.
Y
Value Reported Value Reported
Value Reported Value Reported
(1st)
Y3 Value Reported
Y2 Y4
Y1 Y5
t
Value 1
Value 2
Value 3
Value 4
Value 5
(*)Set value for t: XDbRepInt IEC05000500-2-en.vsdx
IEC05000500 V2 EN-US
If a measuring value is changed, compared to the last reported value, and the
change is larger than the ±ΔY pre-defined limits that are set by user (XDbRepInt),
then the measuring channel reports the new value to a higher level. This limits the
information flow to a minimum necessary. Figure 196 shows an example with the
amplitude dead-band supervision. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle
from each other.
Value Reported
Y
IEC99000529-2-en.vsdx
IEC99000529 V2 EN-US
After the new value is reported, the ±ΔY limits for dead-band are automatically set
around it. The new value is reported only if the measured quantity changes more
than defined by the ±ΔY set limits.
The measured value is reported if the time integral of all changes exceeds the pre-
set limit (XDbRepInt), figure 197, where an example of reporting with integral
dead-band supervision is shown. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle
from each other.
The last value reported, Y1 in figure 197 serves as a basic value for further
measurement. A difference is calculated between the last reported and the newly
measured value and is multiplied by the time increment (discrete integral). The
absolute values of these integral values are added until the pre-set value is
exceeded. This occurs with the value Y2 that is reported and set as a new base for
the following measurements (as well as for the values Y3, Y4 and Y5).
Y A1 >=
A >= pre-set value
A2 >=
pre-set value pre-set value
Y3 A3 + A4 + A5 + A6 + A7 >=
pre-set value
Y2 A1 A2
A4 A6
Value Reported Y4 A3 A5 A7
Value
(1st) Value
A Reported Y5
Reported Value
Reported Value
Y1 Reported
t
IEC99000530-2-en.vsdx
IEC99000530 V2 EN-US
The magnitude and angle of the impedance for each phase-to-earth and phase-to-
phase loop are available on local HMI, monitoring tools within PCM600 or to the
station level, for example, via IEC61850.
S00346 V1 EN-US
The ZMFCPDIS function is a six-zone full scheme protection with three fault loops
for phase-to-phase faults and three fault loops for phase-to-earth faults for each of
the independent zones, which makes the function suitable in applications with
single-phase autoreclosing.
ZMFCPDIS
I3P* TRIP
U3P* TRZ1
BLOCK TRL1Z1
VTSZ TRL2Z1
BLKZ1 TRL3Z1
BLKZ2 TRZ2
BLKZ3 TRL1Z2
BLKZ4 TRL2Z2
BLKZ5 TRL3Z2
BLKZRV TRZ3
BLKTRZ1 TRZ4
BLKTRZ2 TRZ5
BLKTRZ3 TRZRV
BLKTRZ4 START
BLKTRZ5 STZ1
BLKTRZRV STNDZ1
EXTNST STZ2
RELCNDZ1 STL1Z2
RELCNDZ2 STL2Z2
RELCNDZ3 STL3Z2
RELCNDZ4 STNDZ2
RELCNDZ5 STZ3
RELCNDZRV STNDZ3
STZ4
STNDZ4
STZ5
STNDZ5
STZRV
STL1ZRV
STL2ZRV
STL3ZRV
STNDZRV
STND
STNDL1
STNDL2
STNDL3
STNDPE
STFWL1
STFWL2
STFWL3
STFWPE
STRVL1
STRVL2
STRVL3
STRVP E
STFW1PH
STFW2PH
STFW3PH
STPE
STPP
IEC11000422-4-en.vsdx
IEC11000422 V4 EN-US
8.12.4 Signals
PID-6812-INPUTSIGNALS v4
PID-7070-OUTPUTSIGNALS v1
8.12.5 Settings
PID-7070-SETTINGS v2
Practically all voltage, current and impedance quantities used within the
ZMFCPDIS function are derived from fundamental frequency phasors filtered by a
half-cycle filter.
The phasor filter is frequency adaptive in the sense that its coefficients are changed
based on the estimated power system frequency.
A half-cycle filter will not be able to reject both even and odd harmonics. So, while
odd harmonics will be completely attenuated, accuracy will be affected by even
harmonics. Even harmonics will not cause the distance zones to overreach; instead
there will be a slightly variable underreach, on average in the same order as the
magnitude ratio between the harmonic and the fundamental component.
The different fault loops within the IED are of full scheme type, which means that
earth fault loop for phase-to-earth faults and phase-to-phase faults for forward and
reverse faults are executed in parallel.
Figure 199 presents an outline of the different measuring loops for the six distance
zones.
IEC05000458-2-en.vsd
IEC05000458 V2 EN-US
Figure 199: The different measuring loops at phase-to-earth fault and phase-to-
phase fault
Transients from CVTs may have a significant impact on the transient overreach of
a distance protection. At the same time these transients can be very diverse in
nature from one type to the other; in fact, more diverse than can be distinguished
by the algorithm itself in the course of a few milliseconds. So, a setting is
introduced in order to inform the algorithm about the type of CVT applied and thus
providing the advantage of knowing how performance should be optimized, even
during the first turbulent milliseconds of the fault period.
There are two types of CVTs from the function point of view, the passive and the
active type, which refers to the type of ferro-resonance suppression device that is
employed. The active type requires more rigorous filtering which will have a
negative impact on operate times. However, this will be evident primarily at higher
source impedance ratios (SIRs), SIR 5 and above, or close to the reach limit.
To avoid overreach and at the same time achieve fast operate times, a
supplementary circular characteristic that includes some alternative processing is
implemented. One such circular characteristic exists for every measuring loop and
quadrilateral/mho characteristic. There are no specific reach settings for this
circular zone. It uses the normal quadrilateral/mho zone settings to determine a
reach that will be appropriate. This implies that the circular characteristic will
always have somewhat shorter reach than the quadrilateral/mho zone.
The phase-selection element can, owing to the current change criteria, distinguish
faults with minimum influence from load and fault impedance. In other words, it is
not restricted by a load encroachment characteristic during the current change
phase. This significantly improves performance for remote phase-to-earth faults on
heavily loaded lines. One exception, however, is three-phase faults, for which the
load encroachment characteristic always has to be applied, in order to distinguish
fault from load.
The continuous criteria will in the vast majority of cases operate in parallel and
carry on the fault indication after the current change phase has ended. Only in some
particularly difficult faults on heavily loaded lines the continuous criteria might not
be sufficient, for example, when the estimated fault impedance resides within the
load area defined by the load encroachment characteristic. In this case, the
indication will be restricted to a pulse lasting for one or two power system cycles.
Phase-to-phase-earth faults (also called double earth faults) will practically always
activate phase-to-phase zone measurements.Measurement in two phase-to-earth
loops at the same time is associated with so-called simultaneous faults: two earth
faults at the same time, one each on the two circuits of a double line, or when the
zero sequence current is relatively high due to a source with low Z0/Z1 ratio.In
these situations zone measurement will be released both for the related phase-to-
earth loops and the phase-to-phase loop simultaneously. On the other hand,
simultaneous faults closer to the remote bus will gradually take on the properties of
a phase-to-phase-earth fault and the function will eventually use phase-to-phase
zone measurements also here.
In cases where the fault current infeed is more or less completely lack of zero
sequence nature (all phase currents in phase), the measurement will be performed
in the phase-to-earth loops only for a phase-to-phase-earth fault.
Several criteria are employed when making the directional decision. The basis is
provided by comparing a positive sequence based polarizing voltage with phase
currents. For extra security, especially in making a very fast decision, this method
is complemented with an equivalent comparison where, instead of the phase
current, the change in phase current is used. Moreover, a basic negative sequence
directional evaluation is taken into account as a reliable reference during high load
condition. Finally, a zero sequence directional evaluation is used whenever there is
more or less exclusive zero sequence in-feed.
The directional sectors that represent forward direction, one per measuring loop,
are defined by the following equations.
U PolL1
−15° < arg < 120°
I L1
IECEQUATION15059 V1 EN-US (Equation 107)
U PolL1L 2
−15° < arg < 120°
I L1L 2
IECEQUATION15060 V1 EN-US (Equation 108)
Where:
UPolL1 is the polarizing voltage for phase L1.
UPolL1L2 is the polarizing voltage difference between phase L1 and L2 (L2 lagging L1).
IL1L2 is the current difference between phase L1 and L2 (L2 lagging L1).
The corresponding reverse directional sectors range from 165 to -60 degrees.
Since the polarizing voltage is also used for the Mho distance characteristics, the
magnitude of the voltage is just as interesting as the phase. If there are symmetrical
conditions and the measured per phase positive sequence voltage magnitude is
above 75% of the base voltage before the fault, the pre-fault magnitude will be
memorized and used as long as there is a fault. The phase angle however will only
be memorized (locked) for 75 ms at a time, not to lose synchronism with the real
system voltage.
Should the positive sequence voltage drop below 2% of the base voltage, it will be
considered invalid. In this situation, directional signals and starts from Mho
elements will be sealed-in and kept static as long as there is a fault.
For ZMFCPDIS, when option SeriesComp is chosen for OperationSC, the voltages
of faulty phases will be discarded in order not to affect the polarizing voltage with
voltage reversal.
The ZMFCPDIS function has to be blocked by an additional function like the Fuse
failure supervision (FUFSPVC) or an equivalent external device. Typically, the
binary input VTSZ is used for this purpose.
However, to guarantee that also very fast operation is blocked in a fuse failure
situation, there is a built-in supervision based on change in current that will delay
operation before the FUFSPVC blocking signal is received. The delay will be
introduced if no (vector) magnitude change greater than 5% of IBase has been
detected in any of the phase currents.
There is need for external blocking of the ZMFCPDIS function during power
swings, either from the Power Swing Blocking function (ZMRPSB) or an external
device.
ZMFCPDIS implements quadrilateral and mho characteristic in all the six zones
separately. Set OpModePEZx or OpModePPZx to Quadrilateral, to choose
particular measuring loop in a zone to work as quadrilateral distance protection.
X (Ohm/loop)
X0FwPEZx X1FwPEZx
XNFwZx
R1FwPEZx+RNFwZx 3
X1RvPEZx
XNRvZx XNFwZx
RFRvPEZx RFFwPEZx X1FwPEZx
R0FwPEZx R1FwPEZx
RNFwZx
3
X1RvPEZx
RNRvZx RNFwZx
X1FwPEZx
X1RvPEZx
X1FwPEZx+XNFwZx R1RvPEZx R1FwPEZx
X1FwPEZx
N N
R (Ohm/loop)
1) 1)
RFRvPEZx RFFwPEZx
X1RvPEZx+XNRvZx
N
RFRvPEZx RFFwPEZx
R1FwPPZx
X (Ohm/phase)
RFRvPPZx RFFwPPZx
2 2
X1FwPPZx
N
R (Ohm/phase)
1) 1)
RFRvPPZx RFFwPPZx
2 2
X1RvPPZx
N
RFRvPPZx RFFwPPZx
2 2
X1RvPPZx IEC11000418-2-en.vsd
R1FwPPZx
X1FwPPZx
Note that for ZMFCPDIS, the reverse zone ZRV, as well as any of
zones 3-5, that are set to DirMode=Reverse will get their operating
impedances inverted (rotated 180 degrees) internally in order to
make use of the main settings, which are the settings designated
‘Fw’. Therefore, a reverse zone will have its Fw-settings
(RFFwPPZRV, X1FwPEZ3, and so on) applied in the third
quadrant, that is, towards the busbar instead of the line.
The fault loop reach in relation to each fault type may also be presented as in figure
202. The main intention with this illustration is to make clear how the fault
resistive reach should be interpreted. Note in particular that the setting RFPP [2]
always represents the total fault resistance of the loop, even while the fault
resistance (arc) may be divided into parts like for three-phase or phase-to-phase-to-
earth faults. R1Zx and jX1Zx represent the positive sequence impedance from the
measuring point to the fault location.
Phase-to-earth
RFPEZx
fault in phase L1
(Arc + tower
resistance)
0
IN (R0Zx-R1Zx)/3 +
j (X0Zx-X1Zx)/3 )
ZMFCPDIS implements quadrilateral and mho characteristic in all the six zones
separately. Set OpModePEZx or OpModePPZx setting to Mho or Offset, to choose
a particular measuring loop in a zone to work as mho (or Offset Mho) distance
protection.
X
X
Z4
Z3
ZS=0
Z2
Z1 R
Z5 R
ZS=Z1
ZRV
ZS=2Z1
IEC15000056-1-en.vsdx
IEC15000056 V1 EN-US
Figure 203: Mho, offset mho characteristics and the source impedance
influence on the mho characteristic
The mho characteristic has a dynamic expansion due to the source impedance.
Instead of crossing the origin, as for the mho to the left of figure 203, which is only
valid where the source impedance (Zs) is zero, the crossing point is moved to the
coordinates of the negative source impedance given an expansion of the circle
shown to the right of figure 203. Z1 denotes the complex positive sequence
impedance.
ZMFCPDIS fixes zone 1 and 2 in Forward mode and zone RV in Reverse mode.
Zone 3-5 can be set to Non-directional, Forward or Reverse by setting the
parameter DirModeZx (where x is 3-5 depending on selected zone).
X X
(a) Rset
X (c)
(b) Rset
Rset
Mho Characteristics
(a) and (c) are for Zone 1, Zone 2 and Zone 3-5 when DirModeZ3-5 = Forward
(b) and (d) are for ZoneRV and Zone 3-5 when DirModeZ3-5 = Reverse
(c) and (f) are for Zone 3-5 when DirModeZ3-5 = Non-Directional
IEC15000065‐2‐en.vsdx
IEC15000065 V2 EN-US
For each zone, the impedance is set in cartesian coordinates (resistance and
reactance) which is the same as for quadrilateral characteristic.
ZMFCPDIS function uses separate sets of reach settings in forward and reverse
directions for phase-to-earth fault and phase-to-phase fault. These settings are
R1FwPPZx, X1FwPPZx, X1RvPPZx, R1FwPEZx, X1FwPEZx, X1RvPEZx,
R0FWPEZx, X0FwPPZx (x=1-5 or RV). Thus, the center of the Non-directional
offset mho circle can be arbitrarily located in the circle (figure 204).
Note that the reverse ZoneRV, as well as any of zones 3-5, that are set to
DirModeZx=Reverse will get their operating impedances inverted (rotated 180
degrees) internally in order to make use of the main settings, which are the settings
designated ‘Fw’. Therefore, a reverse zone will have its Fw-settings (R1FwPPZRV,
X1FwPEZ3, and so on) applied in the third quadrant, that is, towards the busbar
instead of the line.
In Non-directional mode, for both Mho and Quad, the reach settings are equal to
Forward mode in this respect. The ‘Fw’ settings apply in the first quadrant and the
‘Rv’ settings apply in the third quadrant.
The mho algorithm is based on the phase comparison of an operating phasor and a
polarizing phasor. When the operating phasor leads the reference polarizing phasor
by 90 degrees or more, the function operates and gives a trip output.
The plain Mho circle has the characteristic as in figure 205. The condition for
deriving the angle β is according to equation 109.
(
β = arg U L1L 2 − I L1L 2 ⋅ Z 1set − arg U pol) ( )
IECEQUATION15027 V1 EN-US (Equation 109)
where
is the positive sequence impedance setting for phase-to-phase fault in zone direction
Z 1set
is the polarizing voltage
Upol
where:
R1FwPPZx is the positive sequence resistive reach for phase-to-phase fault in zone direction for
zone x (x=1-5 and RV)
X1FwPPZx is the positive sequence reactance reach for phase-to-phase fault in zone direction for
zone x (x=1-5 and RV)
IL1L2 jX
I L1L 2 Z1set
UcompUL1L2 IL1L2 Z1set
UL1L2
U pol
I L1L 2 R
IEC15000060-1-en.vsdx
IEC15000060 V1 EN-US
Figure 205: Simplified mho characteristic and vector diagram for phase L1-to-
L2 fault
The characteristic for offset mho is a circle where two points on the circle are given
by the two vectors Z 1set and Z 1RVset where Z 1set and Z 1RVset are settable
through the resistance and reactance settings in forward and reverse directions.
The condition for operation at phase-to-phase fault is that the angle β between the
two compensated voltages is greater than or equal to 90° (figure 206). The angle
will be 90° for fault location on the boundary of the circle.
U
L1L 2 I L1L 2 Z 1set
arg
U L1L 2 I L1L 2 Z1set
IECEQUATION15008 V2 EN-US (Equation 112)
where
is the positive sequence impedance setting for phase-to-phase fault
Z 1RVset opposite to zone direction and is defined as
where
X1RvPPZx is the positive sequence reactance reach for phase-to-phase fault
opposite to zone direction for zone x (x=1-5 and RV)
R1RvPPZx is the positive sequence resistive reach for phase-to-phase fault
opposite to zone direction for zone x (x=1-5 and RV) and is
internally calculated according to the equation below,
R1FwPPZx
R1RvPPZx = X 1RvPPZx ⋅
X 1FwPPZx
IECEQUATION15014 V1 EN-US (Equation 114)
IL1L 2 jX
IL1L 2 Z1set
UL1L 2
Ucomp 2 UL1L 2 IL1L 2 Z1RVset
IL1L 2 R
IL1L 2 Z1RVset
IEC16000207-1-en.vsdx
IEC16000207 V1 EN-US
Figure 206: Simplified offset mho characteristic and voltage vector for phase L1
to L2 fault
Compensation for earth return path for faults involving earth is done by setting the
positive and zero sequence impedance of the line. It is known that the ground
compensation factor KN is,
Z 0set − Z 1set
KN =
3 ⋅ Z 1set
IECEQUATION15017 V1 EN-US
where
is the complex zero sequence impedance of the line in Ω/phase
Z 0set
is the complex positive sequence impedance of the line in Ω/phase
Z 1set
R0FwPEZx is the zero sequence resistive reach of the line in Ω/phase for
phase-to-earth fault in zone direction for zone x (x=1-5, or RV)
X0FwPEZx is the zero sequence reactance reach of the line in Ω/phase for
phase-to-earth fault in zone direction for zone x (x=1-5, or RV)
R1FwPEZx is the positive sequence resistive reach of the line in Ω/phase for
phase-to-earth fault in zone direction for zone x (x=1-5, or RV)
X1FwPEZx is the positive sequence reactance reach of the line in Ω/phase for
phase-to-earth fault in zone direction for zone x (x=1-5, or RV)
For an earth fault in phase L1, the angle β between the compensation voltage and
the polarizing voltage Upol is,
where
is the phase voltage in faulty phase L1
UL1
is the phase current in faulty phase L1
IL1
3I0 is the zero-sequence current in faulty phase L1
IL1•jX
U L1
I L1 Z1set
U pol
IL1•R
IEC15000059-1-en.vsdx
IEC15000059 V1 EN-US
Figure 207: Simplified offset mho characteristic and vector diagram for phase
L1-to-earth fault
The condition for operation of offset mho at phase-to-earth fault is that the angle β
between the two compensated voltages is equal to or greater than 90°, see figure
208. The angle will be 90° for fault location on the boundary of the circle.
arg U L1 ( I L1 3I 0 K N ) Z1set arg U L1 ( I L1 3I 0 K N ) Z1set
where
is the complex positive sequence impedance of the line in Ω/phase
Z 1RVset for phase-to-earth fault opposite to zone direction and is defined as,
where
X1RvPEZx is the positive sequence reactance reach for phase-to-earth fault
opposite to zone direction for zone x (x=1-5 and RV)
R1RvPEZx is the positive sequence resistive reach for phase-to-earth fault
opposite to zone direction for zone x (x=1-5 and RV) and expressed
by,
R1FwPEZx
R1RvPEZx = X 1RvPEZx ⋅
X 1FwPEZx
IECEQUATION15024 V1 EN-US (Equation 119)
IL1• jX
U comp1 U L1 ( I L1 3I 0 K N ) Z1set
( I L1 3I 0 K N ) Z 1set U L1
U comp 2 U L1 ( I L1 3I 0 K N ) Z 1RVset )
( I L1 3I 0 K N ) Z 1RVset
IL1• R
IEC16000207-1-en.vsdx
IEC16000208 V1 EN-US
Figure 208: Simplified offset mho characteristic and voltage vector for phase
L1-to-earth fault
In some cases the load impedance might enter the zone characteristic without any
fault on the protected line. The phenomenon is called load encroachment and it
might occur when an external fault is cleared and high emergency load is
transferred on the protected line. The effect of load encroachment is illustrated in
the left part of figure 209. A load impedance within the characteristic would cause
an unwanted trip. The traditional way of avoiding this situation is to set the
distance zone resistive reach with a security margin to the minimum load
impedance. The drawback with this approach is that the sensitivity of the
protection to detect resistive faults is reduced.
The IED has a built-in function which shapes the characteristic according to the
right part of figure 209. The load encroachment algorithm will increase the
possibility to detect high fault resistances, especially for phase-to-earth faults at the
remote line end. For example, for a given setting of the load angle ArgLd the
resistive blinder for the zone measurement can be expanded according to the right
part of the figure 209, given higher fault resistance coverage without risk for
unwanted operation due to load encroachment. This is valid in both directions.
The use of the load encroachment feature is essential for long heavily loaded lines,
where there might be a conflict between the necessary emergency load transfer and
necessary sensitivity of the distance protection. The function can also preferably be
used on heavy loaded medium long lines. For short lines, the major concern is to
get sufficient fault resistance coverage. Load encroachment is not a major problem.
Nevertheless, always set RLdFw, RLdRv [3] and ArgLd according to the expected
maximum load since these settings are used internally in the function as reference
points to improve the performance of the phase selection.
Z1
ArgLd
[1]
RLdRv RLdFw
IEC09000248-3-en.vsdx
IEC09000248 V3 EN-US
PHSL1, PHSL2,...PHSL3L1 are internal binary logical signals from the Phase-
selection element. They correspond directly to the six loops of the distance zones
and determine which loops should be released to possibly issue a start or a trip.
The internal input 'IN present' is true if the residual current (3I0) exceeds 7% of
IBase. However, if current transformer saturation is detected, this criterion is
changed to residual voltage (3U0) exceeding 5% of UBase/sqrt(3) instead.
[3] RLdRv=RLdRvFactor*RLdFw.
DirModeZ3-5
TRUE (1)
FW(Ln & LmLn) Forward
RV(Ln & LmLn) Reverse
IEC12000137-2-en.vsd
IEC12000137 V3 EN-US
ZML1Zx PEZx
OR
PHSL1
AND
DIRL1Zx AND
ZML2Zx
PHSL2
AND
DIRL2Zx AND
ZML3Zx L1Zx
OR
PHSL3
AND
DIRL3Zx AND
ZML1L2Zx L2Zx
PHSL1L2 OR
AND
DIRL1L2Zx AND
ZML2L3Zx
PHSL2L3 L3Zx
AND OR
DIRL2L3Zx AND
ZML3L1Zx
PHSL3L1
AND
DIRL3L1Zx AND
L1N
PPZx
L2N OR
L3N
RELCNDZx Integer L1L2
to Bool
L2L3
NDZx
L1L3 OR
IEC12000140-2-en.vsdx
IEC12000140 V2 EN-US
TimerModeZx =
Enable PhPh or
Ph-E PhPh
PPZx AND tPPZx
OR AND
AND t
PEZx
AND tPEZx OR
OR
AND t
AND
BLOCK
VTSZ
BLKZx OR
BLKTRZx
OR TimerLinksZx
LoopLink (tPP-tPE)
ZoneLinkStart LoopLink & ZoneLink
OR
Phase Selection No Links
1st starting zone
External start FALSE (0)
LNKZ2
LNKZx
AND
OR
TimerLinksZx =
LNKZ4 LoopLink & ZoneLink
LNKZ5
EXTNST
IEC12000139-4-en.vsdx
IEC12000139 V4 EN-US
15 ms
TZx
t TRIPZx
AND
TRL1Zx
OR AND
BLOCK
VTSZ TRL2Zx
OR AND
BLKZx
TRL3Zx
AND
15 ms
L1Zx
t STL1Zx
AND
15 ms
L2Zx
t STL2Zx
AND
15 ms
t STL3Zx
AND
PPZx 15 ms
PEZx OR t STARTZx
AND
15 ms
NDZx
t STNDZx
AND
IEC12000138-2-en.vsd
IEC12000138 V2 EN-US
15 ms
OR t STPE
AND
15 ms
OR t
AND
15 ms
OR t STNDL2
PHSL1L2 AND
15 ms
OR t STNDL3
AND
15 ms
OR t STPP
AND
BLOCK STARTND
OR
VTSZ OR
STPHS
STNDPE
AND
IEC12000133-3-en.vsdx
IEC12000133 V3 EN-US
PHSL1
FWL1 AND
15 ms
FWL2 AND OR t
AND
FWL3 AND 15 ms
PHSL1L2 OR t STFWL2
AND
FWL1L2 AND
PHSL2L3 15 ms
FWL2L3 AND OR t STFWL3
AND
FWL3L1 AND
OR
STFWPE
IN present AND
STFW1PH
=1
BLOCK
VTSZ OR
STFW2PH
=2
STFW3PH
=3
IEC12000134-2-en.vsd
IEC12000134 V2 EN-US
PHSL1
RVL1 AND
15 ms
RVL2 AND OR t
AND
RVL3 AND 15 ms
PHSL1L2 OR t STRVL2
AND
RVL1L2 AND
PHSL2L3 15 ms
RVL2L3 AND OR t STRVL3
AND
RVL3L1 AND
OR
STRVPE
IN present AND
BLOCK
VTSZ OR
IEC12000141-2-en.vsdx
IEC12000141 V2 EN-US
8.12.7.10 Measurement
The protection, control, and monitoring IEDs have functionality to measure and
further process information for currents and voltages obtained from the pre-
processing blocks. The number of processed alternate measuring quantities
depends on the type of IED and built-in options.
Measured value below zero point clamping limit is forced to zero. This allows the
noise in the input signal to be ignored. The zero point clamping limit is a setting
(XZeroDb where X equals Z).
Users can continuously monitor the measured quantity available in the function
block by means of four defined operating thresholds, see figure 217. The
monitoring has two different modes of operating:
• Overfunction, when the measured quantity exceeds the High limit (XHiLim) or
High-high limit (XHiHiLim) pre-set values
• Underfunction, when the measured quantity decreases under the Low limit
(XLowLim) or Low-low limit (XLowLowLim) pre-set values.
X_RANGE = 3
High-high limit
X_RANGE= 1 Hysteresis
High limit
X_RANGE=0
X_RANGE=0 t
Low limit
X_RANGE=2
Low-low limit
X_RANGE=4
IEC05000657-3-en.vsdx
IEC05000657 V3 EN-US
The logical value of the functional output signals changes according to figure 217.
The user can set the hysteresis (XLimHyst), which determines the difference
between the operating and reset value at each operating point, in wide range for
each measuring channel separately. The hysteresis is common for all operating
values within one channel.
The actual value of the measured quantity is available locally and remotely. The
measurement is continuous for each measured quantity separately, but the reporting
of the value to the higher levels depends on the selected reporting mode. The
following basic reporting modes are available:
In addition to the normal cyclic reporting the IED also report spontaneously when
measured value passes any of the defined threshold limits.
Y
Value Reported Value Reported
Value Reported Value Reported
(1st)
Y3 Value Reported
Y2 Y4
Y1 Y5
t
Value 1
Value 2
Value 3
Value 4
Value 5
(*)Set value for t: XDbRepInt IEC05000500-2-en.vsdx
IEC05000500 V2 EN-US
If a measuring value is changed, compared to the last reported value, and the
change is larger than the ±ΔY pre-defined limits that are set by user (XDbRepInt),
then the measuring channel reports the new value to a higher level. This limits the
information flow to a minimum necessary. Figure 219 shows an example with the
amplitude dead-band supervision. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle
from each other.
Value Reported
Y
IEC99000529-2-en.vsdx
IEC99000529 V2 EN-US
After the new value is reported, the ±ΔY limits for dead-band are automatically set
around it. The new value is reported only if the measured quantity changes more
than defined by the ±ΔY set limits.
The measured value is reported if the time integral of all changes exceeds the pre-
set limit (XDbRepInt), figure 220, where an example of reporting with integral
dead-band supervision is shown. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle
from each other.
The last value reported, Y1 in figure 220 serves as a basic value for further
measurement. A difference is calculated between the last reported and the newly
measured value and is multiplied by the time increment (discrete integral). The
absolute values of these integral values are added until the pre-set value is
exceeded. This occurs with the value Y2 that is reported and set as a new base for
the following measurements (as well as for the values Y3, Y4 and Y5).
Y A1 >=
A >= pre-set value
A2 >=
pre-set value pre-set value
Y3 A3 + A4 + A5 + A6 + A7 >=
pre-set value
Y2 A1 A2
A4 A6
Value Reported Y4 A3 A5 A7
Value
(1st) Value
A Reported Y5
Reported Value
Reported Value
Y1 Reported
t
IEC99000530-2-en.vsdx
IEC99000530 V2 EN-US
The magnitude and angle of the impedance for each phase-to-earth and phase-to-
phase loop are available on local HMI, monitoring tools within PCM600 or to the
station level, for example, via IEC61850.
8.13.1 Identification
M14853-1 v3
Zpsb
SYMBOL-EE V1 EN-US
Power swings may occur after disconnection of heavy loads or trip of big
generation plants.
Power swing detection function (ZMRPSB ) is used to detect power swings and
initiate block of all distance protection zones. Occurrence of earth-fault currents
during a power swing inhibits the ZMRPSB function, to allow fault clearance.
ZMRPSB
I3P* START
U3P* ZOUT
BLOCK ZIN
BLKI01
BLKI02
BLK1PH
REL1PH
BLK2PH
REL2PH
I0CHECK
TRSP
EXTERNAL
IEC06000264-2-en.vsd
IEC06000264 V2 EN-US
8.13.4 Signals
PID-3663-INPUTSIGNALS v6
PID-3663-OUTPUTSIGNALS v6
8.13.5 Settings
PID-3663-SETTINGS v6
Its principle of operation is based on the measurement of the time it takes for a
power swing transient impedance to pass through the impedance area between the
outer and the inner characteristics. Power swings are identified by transition times
longer than a transition time set on corresponding timers. The impedance
measuring principle is the same as that used for the distance protection zones. The
impedance and the characteristic passing times are measured in all three phases
separately.
X1OutFw jX ZL R1LIn
X1InFw DFw
j
DRv
R1FInRv R1FInFw
DFw
ArgLd j
ArgLd
DRv
DFw
DFw
R
DFw
DRv
RLdInRv RLdInFw
DFw
DRv
RLdOutRv RLdOutFw
j DRv X1InRv
X1OutRv
IEC09000222_1_en.vsd
IEC09000222 V1 EN-US
æ ULn ö
Re çç ÷÷ £ Rset
è I Ln ø
EQUATION1183 V2 EN-US (Equation 120)
æ ULn ö
Imçç ÷÷ £ Xset
è ILn ø
EQUATION1184 V2 EN-US (Equation 121)
RLdInFw = kLdRFw·RLdOutFw
EQUATION1185 V2 EN-US (Equation 122)
where:
kLdRFw is a settable multiplication factor less than 1
The slope of the load encroachment inner and outer boundary is defined by setting
the parameter ArgLd.
The load encroachment in the fourth quadrant uses the same settings as in the first
quadrant (same ArgLd and RLdOutFw and calculated value RLdInFw).
From the setting parameter RLdOutFw and the calculated value RLdInFw a
distance between the inner and outer boundary, DFw, is calculated. This value is
valid for R direction in first and fourth quadrant and for X direction in first and
second quadrant.
RLdInRv = kLdRRv·RLdOutRv
EQUATION1187 V2 EN-US (Equation 123)
where:
kLdRRv is a settable multiplication factor less than 1
From the setting parameter RLdOutRv and the calculated value RLdInRv, a
distance between the inner and outer boundary, DRv, is calculated. This value is
valid for R direction in second and third quadrant and for X direction in third and
fourth quadrant.
The inner resistive characteristic in the second quadrant outside the load
encroachment part corresponds to the setting parameter R1FInRv for the inner
boundary. The outer boundary is internally calculated as the sum of DRv+R1FInRv.
The inner resistive characteristic in the third quadrant outside the load
encroachment zone consist of the sum of the settings R1FInRv and the line
resistance R1LIn. The argument of the tilted lines outside the load encroachment is
the same as the tilted lines in the first quadrant. The distance between the inner and
outer boundary is the same as for the load encroachment in reverse direction, that is
DRv.
The inner characteristic for the reactive reach in forward direction correspond to
the setting parameter X1InFw and the outer boundary is defined as X1InFw + DFw,
where:
DFw = RLdOutFw - KLdRFw · RLdOutFw
The inner characteristic for the reactive reach in reverse direction correspond to the
setting parameter X1InRv for the inner boundary and the outer boundary is defined
as X1InRv + DRv.
where:
DRv = RLdOutRv - KLdRRv · RLdOutRv
The operation of the Power swing detection ZMRPSB is only released if the
magnitude of the current is above the setting of the min operating current,
IMinOpPE.
Signals ZOUTLn (outer boundary) and ZINLn (inner boundary) in figure 223 are
related to the operation of the impedance measuring elements in each phase
separately (n represents the corresponding L1, L2 and L3). They are internal
signals, calculated by ZMRPSB function.
The tP1 timer in figure 223 serve as detection of initial power swings, which are
usually not as fast as the later swings are. The tP2 timer become activated for the
detection of the consecutive swings, if the measured impedance exit the operate
area and returns within the time delay, set on the tW waiting timer. The upper part
of figure 223 (internal input signal ZOUTL1, ZINL1, AND-gates and tP-timers)
are duplicated for phase L2 and L3. All tP1 and tP2 timers in the figure have the
same settings.
ZOUTL1 AND
0-tP1
ZINL1 0 OR
-loop
0-tP2
-loop
AND
0
OR DET-L1
AND AND
ZOUTL2 OR
ZOUTL3
detected 0
0-tW
IEC05000113-2-en.vsd
IEC05000113 V2 EN-US
DET-L1
DET-L2 DET1of3 - int.
>1
DET-L3
&
DET2of3 - int.
& >1
&
IEC01000057-2-en.vsd
IEC01000057-TIFF V2 EN-US
Figure 224: Detection of power swing for 1-of-3 and 2-of-3 operating mode
ZOUTL1 ZOUT
OR
ZOUTL2 ZINL1
ZIN
ZOUTL3 AND ZINL2 OR
ZINL3
tEF
TRSP
t AND
I0CHECK
10 ms
AND t
BLKI02 OR
tR1
AND t INHIBIT
OR
-loop
tR2
BLKI01 AND t
BLOCK
-loop
DET1of3 - int.
REL1PH
AND
BLK1PH
tH
DET2of3 - int. OR t
REL2PH
AND
BLK2PH OR START
AND
EXTERNAL
en05000114.vsd
IEC05000114 V1 EN-US
Figure 225 presents a simplified logic diagram for the Power swing detection
function ZMRPSB. The internal signals DET1of3 and DET2of3 relate to the
detailed logic diagrams in figure 223 and figure 224 respectively.
The load encroachment characteristic can be switched off by setting the parameter
OperationLdCh = Off, but notice that the DFw and DRv will still be calculated from
RLdOutFw and RLdOutRv. The characteristic will in this case be only
quadrilateral.
There are four different ways to form the internal INHIBIT signal:
8.14.1 Identification
SEMOD155890-2 v4
Mho distance protections cannot operate for switch onto fault conditions when the
phase voltages are close to zero. An additional logic based on UI Level is used for
this purpose.
IEC06000459 V3 EN-US
PID-3875-INPUTSIGNALS v10
PID-3875-OUTPUTSIGNALS v9
PID-3875-SETTINGS v10
The automatic switch onto fault logic ZCVPSOF can be activated externally (by
the breaker-closed input) or internally (automatically) with the dead-line detection
using the UI level-based logic. When the setting AutoInitMode is DLD disabled,
ZCVPSOF is activated by an external binary input BC. When the setting
AutoInitMode is set to Voltage, Current or Current & Voltage modes, ZCVPSOF is
activated by the dead-line detection.
The activation from the dead-line detection function is released if the internal
signal DeadLine from the UILevel Detector function is activated at the same
time as the inputs ZACC and START_DLYD are not activated at least for the
duration of tDLD. The internal signal DeadLine from the UILevel Detector
function is activated under any of the following conditions:
• If all three-phase currents are below the setting IPh< and the AutoInitMode
setting is set to Current
• If all three-phase voltages are below the setting UPh< and the AutoInitMode
setting is set to Voltage
• If all three-phase currents and voltages are below the settings IPh< and UPh<
and the AutoInitMode setting is set to Current & Voltage
Once the dead line drops off after energization or once BC drops off, the activated
signal is extended for the duration of tSOTF.
The internal signal SOTFUILevel is activated if the phase voltage is below the
set UPh< and the corresponding phase current is above the set IPh< for a time
longer than the duration set by tDuration.
To get the TRIP signal, one of the different operate modes must also be selected
with the Mode parameter:
• Mode = Impedance; TRIP is released if either the ZACC input (connected
normally to a nondirectional distance protection start zone) or the
START_DLYD input is activated. If START_DLD is activated, TRIP is
released after a delay of tOperate.
• Mode = UILevel; TRIP is released if UILevel detector is activated
• Mode = UILvl&Imp; TRIP is released based either on the impedance-
measured criteria or UILevel detection
The measured phase voltages and currents are provided as service values.
BLOCK
15ms
BC TRIP
& t
ZACC tSOTF
tDLD t
START_DLYD ≥1
& t
≥1
tOperate
t
I3P
U3P
DeadLine
IPh< UILevel tDuration
Detector t
UPh<
AutoInitMode
&
Mode = Impedance
SOTFUILevel
& ≥1
Mode = UILevel
≥1
&
Mode = UILvl&Imp
IEC07000084 V3 EN-US
Figure 227: Simplified logic diagram for Automatic switch onto fault logic
M16043-1 v12
8.15.1 Identification
SEMOD175682-2 v3
PSLPSCH
BLOCK TRIP
STZMUR STZMURPS
STZMOR BLKZMUR
STPSD BLKZMOR
STDEF CS
STZMPSD
CACC
AR1P1
CSUR
CR
IEC07000026-3-en.vsd
IEC07000026 V3 EN-US
8.15.4 Signals
PID-3664-INPUTSIGNALS v7
PID-3664-OUTPUTSIGNALS v7
8.15.5 Settings
PID-3664-SETTINGS v6
Communication and tripping logic as used by the power swing distance protection
zones is schematically presented in figure 229.
STDEF
AR1P1 &
STPSD tCS
CS
BLOCK & t &
CSUR
BLKZMPS
tBlkTr &
tTrip t
t
CACC TRIP
>1
CR &
en06000236.vsd
IEC06000236 V1 EN-US
Figure 229: Simplified logic diagram – power swing communication and tripping
logic
The complete logic remains blocked as long as there is a logical one on the
BLOCK functional input signal. Presence of the logical one on the STDEF
functional input signal also blocks the logic as long as this block is not released by
the logical one on the AR1P1 functional input signal. The functional output signal
BLKZMPS remains logical one as long as the function is not blocked externally
(BLOCK is logical zero) and the earth-fault is detected on protected line (STDEF
is logical one), which is connected in three-phase mode (AR1P1 is logical zero).
Timer tBlkTr prolongs the duration of this blocking condition, if the measured
impedance remains within the operate area of the Power Swing Detection
(ZMRPSB) function (STPSD input active). The BLKZMPS can be used to block
the operation of the power-swing zones.
Logical one on functional input CSUR, which is normally connected to the TRIP
functional output of a power swing carrier sending zone, activates functional output
CS, if the function is not blocked by one of the above conditions. It also activates
the TRIP functional output.
Initiation of the CS functional output is possible only, if the STPSD input has been
active longer than the time delay set on the security timer tCS.
blocked by one of the above conditions and the STPSD signal has been present
longer then the time delay set on the trip timer tTrip.
Figure 230 presents the logical circuits, which control the operation of the
underreaching zone (zone 1) at power swings, caused by the faults and their
clearance on the remote power lines.
&
BLKZMH
&
STZML tZL
STZMLL
BLOCK & t >1
&
STMZH tDZ
STZMPSD & t
>1
STPSD
&
-loop
en06000237.vsd
IEC06000237 V1 EN-US
The logic is disabled by a logical one on functional input BLOCK. It can start only
if the following conditions are simultaneously fulfilled:
• STPSD functional input signal must be a logical zero. This means, that Power
swing detection (ZMRPSB) function must not detect power swinging over the
protected power line.
• STZMPSD functional input must be a logical one. This means that the
impedance must be detected within the external boundary of ZMRPSB
function.
• STZMOR functional input must be a logical one. This means that the fault
must be detected by the overreaching distance protection zone, for example
zone 2.
The STZMURPS functional output, which can be used in complete terminal logic
instead of a normal distance protection zone 1, becomes active under the following
conditions:
The BLKZMOR functional output signal can be used to block the operation of the
higher distance protection zone, if the fault has moved into the zone 1 operate area
after tDZ time delay.
SEMOD171935-5 v5
8.16.1 Identification
SEMOD158949-2 v4
8.16.2 Functionality
SEMOD143246-17 v7
Sudden events in an electric power system such as large changes in load, fault
occurrence or fault clearance, can cause power oscillations referred to as power
swings. In a non-recoverable situation, the power swings become so severe that the
synchronism is lost, a condition referred to as pole slipping. The main purpose of
the pole slip protection (PSPPPAM) is to detect, evaluate, and take the required
action for pole slipping occurrences in the power system.
PSPPPAM
I3P* TRIP
U3P* TRIP1
BLOCK TRIP2
BLKGEN START
BLKMOTOR ZONE1
EXTZONE1 ZONE2
GEN
MOTOR
SFREQ
SLIPZOHM
SLIPZPER
UCOS
UCOSPER
IEC10000045-1-en.vsd
IEC10000045 V1 EN-US
8.16.4 Signals
PID-3526-INPUTSIGNALS v3
PID-3526-OUTPUTSIGNALS v3
8.16.5 Settings
PID-3526-SETTINGS v3
If the generator is faster than the power system, the rotor movement in the
impedance and voltage diagram is from right to left and generating is signaled. If
the generator is slower than the power system, the rotor movement is from left to
right and motoring is signaled (the power system drives the generator as if it were a
motor).
The movements in the impedance plane can be seen in Figure 232. The transient
behavior is described by the transient EMF's EA and EB, and by X'd, XT and the
transient system impedance ZS.
Zone 1 Zone 2
EB X’d XT XS EA
IED
B A
jX
XS
Pole slip
impedance XT
d Apparent generator
movement impedance R
X’d
IEC06000437_2_en.vsd
IEC06000437 V2 EN-US
where:
X'd = transient reactance of the generator
• the minimum current exceeds 0.10 IN (IN is IBase parameter set under general
setting).
• the maximum voltage falls below 0.92 UBase
• the voltage Ucosφ (the voltage in phase with the generator current) has an
angular velocity of 0.2...8 Hz and
• the corresponding direction is not blocked.
en07000004.vsd
IEC07000004 V1 EN-US
Figure 233: Different generator quantities as function of the angle between the
equivalent generators
An alarm is given when movement of the rotor is detected and the rotor angle
exceeds the angle set for 'WarnAngle'.
When the impedance crosses the slip line between ZB and ZC it counts as being in
zone 1 and between ZC and ZA in zone 2. The entire distance ZA-ZB becomes zone
1 when signal EXTZONE1 is high (external device detects the direction of the
centre of slipping).
After the first slip, the signals ZONE1 or ZONE2 and – depending on the direction
of slip - either GEN or MOTOR are issued.
Every time pole slipping is detected, the impedance of the point where the slip line
is crossed and the instantaneous slip frequency are displayed as measurements.
Further slips are only detected, if they are in the same direction and if the rate of
rotor movement has reduced in relation to the preceding slip or the slip line is
crossed in the opposite direction outside ZA-ZB. A further slip in the opposite
direction within ZA-ZB resets all the signals and is then signalled itself as a first
slip.
The TRIP1 tripping command and signal are generated after N1 slips in zone 1,
providing the rotor angle is less than TripAngle. The TRIP2 signal is generated
after N2 slips in zone 2, providing the rotor angle is less than TripAngle.
START
AND
0.2 Slip.Freq. 8 Hz
startAngle
ZONE1
AND
Z cross line ZC - ZB
ZONE2
AND
Z cross line ZA - ZC
Counter
a
ab
N1Limit b TRIP1
AND
tripAngle OR
TRIP
Counter
a
ab
N2Limit b TRIP2
AND
IEC07000005.vsd
IEC07000005 V2 EN-US
Figure 234: Simplified logic diagram for pole slip protection PSPPPAM
GUID-88E02516-1BFE-4075-BEEB-027484814697 v2
8.17.1 Identification
GUID-BF2F1533-BA39-48F0-A55C-0B13A393F780 v2
<
The out-of-step protection (OOSPPAM ) function in the IED can be used for both
generator protection and as well for line protection applications.
The main purpose of the OOSPPAM function is to detect, evaluate, and take the
required action during pole slipping occurrences in the power system.
The OOSPPAM function detects pole slip conditions and trips the generator as fast
as possible, after the first pole-slip if the center of oscillation is found to be in zone
1, which normally includes the generator and its step-up power transformer. If the
center of oscillation is found to be further out in the power system, in zone 2, more
than one pole-slip is usually allowed before the generator-transformer unit is
disconnected. A parameter setting is available to take into account the circuit
breaker opening time. If there are several out-of-step relays in the power system,
then the one which finds the center of oscillation in its zone 1 should operate first.
Two current channels I3P1 and I3P2 are available in OOSPPAM function to allow
the direct connection of two groups of three-phase currents; that may be needed for
very powerful generators, with stator windings split into two groups per phase,
when each group is equipped with current transformers. The protection function
performs a simple summation of the currents of the two channels I3P1 and I3P2.
OOSPPAM
I3P1* TRIP
I3P2* TRIPZ1
U3P* TRIPZ2
BLOCK START
BLKGEN GENMODE
BLKMOT MOTMODE
EXTZ1 R
X
SLIPFREQ
ROTORANG
UCOSPHI
IEC12000188-3-en.vsd
IEC12000188 V3 EN-US
8.17.4 Signals
PID-3539-INPUTSIGNALS v10
PID-3539-OUTPUTSIGNALS v10
8.17.5 Settings
PID-3539-SETTINGS v10
General
Under balanced and stable conditions, a generator operates with a constant rotor
angle (power angle), delivering active electrical power to the power system, which
is approximately equal to the input mechanical power on the generator axis.The
currents and voltages are constant and stable. An out-of-step condition is
characterized by periodic changes in the rotor angle, that leads to a wild flow of the
synchronizing power; so there are also periodic changes of rotational speed,
currents and voltages. When displayed in the complex impedance plane, these
changes are characterized by a cyclic change in the complex load impedance Z(R,
X) as measured at the terminals of the generator, or at the location of the
1.5 ← trajectory
of Z(R, X)
to the 3rd
The 2nd pole-slip
Imaginary part (X) of Z in Ohms
1 The 1st X in Ohms
pole slip
pole slip
occurred Pre-disturbance
occurred
RE normal load
- - - - -
- - - - ----------- - - - - Z(R, X)
0.5 -
3 ----
--- ---- --
Zone 2 -- - 1 ---- - 0
- 2 -- -
- --- -
^ --^ ^ ^ ^ ---^ ^ ^ ^ ^ ^ ^ --- -
-
- -- ^ ^--- ^ ^ ^ -^
Zone 1
0 -
- ---- -
-- -
-
- -
-- relay --
- -
- -
- -- - R in Ohms
limit of reach → -- --- - -
-- -- ---- -
-
--- -
lens determined - - → --- ------ 0- - - pre-disturbance Z(R, X)
-0.5 by the setting - - - -------- - - - →
- - -- - 1 → Z(R, X) under 3-phase fault
StartAngle = 120° SE 2 → Z(R, X) when fault cleared
3 → Z when pole-slip declared
-1
-1.5 -1 -0.5 0 0.5 1 1.5
Real part (R) of Z in Ohms
IEC10000109-1-en.vsd
IEC10000109 V1 EN-US
Figure 236: Loci of the complex impedance Z(R, X) for a typical case of
generator losing step after a short circuit that was not cleared fast
enough
Under typical, normal load conditions, when the protected generator supplies the
active and the reactive power to the power system, the complex impedance Z(R, X)
is in the 1st quadrant, point 0 in Figure 236. One can see that under a three-phase
fault conditions, the centre of oscillation is at the point of fault, point 1, which is
logical, as all three voltages are zero or near zero at that point. Under the fault
conditions the generator accelerated and when the fault was finally cleared, the
complex impedance Z(R, X) jumped to the point 2. By that time, the generator has
already lost its step, Z(R, X) continues its way from the right-hand side to the left-
hand side, and the 1st pole-slip cannot be avoided. If the generator is not
immediately disconnected, it will continue pole-slipping — see Figure 236, where
two pole-slips (two pole-slip cycles) are shown. Under out-of-step conditions, the
centre of oscillation is where the locus of the complex impedance Z(R, X) crosses
the (impedance) line connecting the points SE (Sending End), and RE (Receiving
End). The point on the SE – RE line where the trajectory of Z(R, X) crosses the
impedance line can change with time and is mainly a function of the internal
induced voltages at both ends of the equivalent two-machine system, that is, at
points SE and RE.
Rotor (power) angle δ can be thought of as the angle between the two lines,
connecting point 0 in Figure 236, that is, Z(R, X) under normal load, with the
points SE and RE, respectively. These two lines are not shown in Figure 236.
Normal values of the power angle, that is, under stable, steady-state, load
conditions, are from 30 to 60 electrical degrees. It can be observed in Figure 237
that the angle reaches 180 degrees when the complex impedance Z(R, X) crosses
the impedance line SE – RE. It then changes the sign, and continues from -180
degrees to 0 degrees, and so on. Figure 237 shows the rotor (power) angle and the
magnitude of Z(R, X) against time for the case from Figure 236.
4
|Z| in Ohms
rotor (power)
3 normal angle in rad
angle
Impe dance Z in Ohm and rotor a ngle in radian ®
load
Z(R, X) unde r fa ult lies |Z|
2
on the impe dance line
or nea r (for 3-ph faults )
1
0
0
fault 500 ms
-1 fa ult
occ urrs
Unde r 3-pha s e fa ult
condition rotor a ngle 3
-2
of a pp. ±180 de gre e s
is m e a s ure d ...
2
-3 Z(R,X) cros s e d
1 1 the im pe da nce line , Z-line ,
conne cting points S E - RE
-4
0 200 400 600 800 1000 1200 1400
Time in millis econds ®
IEC10000110-2-en.vsd
IEC10000110 V2 EN-US
Figure 237: Rotor (power) angle and magnitude of the complex impedance
Z(R, X) against the time
1
SE RE
G X [Ohm]
0.8 Z(R,X) 20 ms
fault
relay after line out
- - - RE - - -
0.6 - - -- -
-- ---- ----- 4 - - pre-fault
Figure 238: A stable case where the disturbance does not make the generator
to go out-of-step
It shall be observed that for a stable case, as shown in Figure 238, where the
disturbance does not cause the generator to lose step, the complex impedance Z(R,
X) exits the lens characteristic on the same side (point 4) it entered it (point 2), and
never re-enters the lens. In a stable case, where the protected generator remains in
synchronism, the complex impedance returns to quadrant 1, and, after the
oscillations fade, it returns to the initial normal load position (point 0), or near.
X
Position of the OOS
- - - RE- - -
0.6 - - - - relay is the origin of
- - --
- -- ----
- -- -the R - X plane
- - --- Ze --
---
-
- Zone 2 -- -
0.4 X-line - - - - -
ReverseZ
ReverseZ(ReverseR, ReverseX)) ForwardZ(ForwardR, ForwardX)
SE RE
IEC10000113-2-en.vsd
IEC10000113 V2 EN-US
the generator nominal voltage and nominal current. The impedances from the
position of the out-of-step protection in the direction of the normal load flow can
be taken as forward.
The out-of-step relay, as in Figure 240 looks into the system and the impedances in
that direction are forward impedances:
• ForwardX = Xtr + Xline + Xeq (All values referred to generator voltage)
• ForwardR = Rtr + Rline + Req (All values referred to generator voltage)
Resistances are much smaller than reactances, but in general can not be neglected.
The ratio (ForwardX + ReverseX) / (ForwardR + ReverseR) determines the
inclination of the Z-line, connecting the point SE (Sending End) and RE
(Receiving End), and is typically approximately 85 degrees. While the length of the
Z-line depends on the values of ForwardX, ReverseX, ForwardR, and ReverseR,
the width of the lens is a function of the setting StartAngle .The lens is broader for
smaller values of the StartAngle , and becomes a circle for StartAngle = 90 degrees.
When the complex impedance Z(R, X) enters the lens, pole slipping is imminent,
and a start signal is issued. The angle recommended to form the lens is 110 or 120
degrees, because it is this rotor (power) angle where problems with dynamic
stability usually begin. Rotor (power) angle 120 degrees is sometimes called “the
angle of no return” because if this angle is reached under generator power swings,
the generator is most likely to lose step.
the measured Z from point 1 to point 2 takes approximately 20 ms, due to Fourier
filters. The complex impedance then travels in the direction from the right to the
left, and exits the lens on the opposite side. When the complex impedance exits the
lens on the side opposite to its entrance, the 1st pole-slip has already occurred and
more pole-slips can be expected if the generator is not disconnected. Figure 236
shows two pole-slips. Figures like Figure 236 and Figure 238 are always possible
to draw by means of the analog output data from the pole-slip function, and are of
great help with eventual investigations of the performance of the out-of-step
function.
A pole-slip may be detected if it has a slip frequency lower than a maximum value
fsMax. The specific value of fsMax depends on the setting (parameter) StartAngle
(which determines the width of the lens characteristic). A parameter in this
calculation routine is the value of the minimum traverse time, traverseTimeMin.
The minimum traverse time is the minimum time that the travel of the complex
impedance Z(R, X) through the lens, from one side to the other, must last in order
to recognize that a pole-slip has occurred. The value of the internal constant
traverseTimeMin is a function of the set StartAngle.For values of StartAngle <=
110°, traverseTimeMin = 50 ms. For values StartAngle > 110°, traverseTimeMin =
40 ms. The expression which relates the maximum slip frequency fsMax and the
traverseTimeMin is as follows:
The minimum value of fsMax is 6.994 Hz. When StartAngle = 110 degrees, fsMax
= 7.777 Hz. This implies, that the default StartAngle = 110 degrees covers 90% of
cases as, the typical final slip frequency is between 2 - 5Hz. In practice, however,
before the slip frequency, for example 7.777 Hz, is reached, at least three pole-slips
have occurred. In other words, if we consider a linear increase of frequency from
50 Hz to 57.777 Hz, at least three pole-slips will occur (in fact: (57.777 - 50) / 2 =
3.889). The exact instantaneous slip-frequency expressed in Hz (corresponding to
number of pole slips per second) is difficult to calculate. The easiest and most exact
method is to measure time between two successive pole slips. This means that, the
instantaneous slip-frequency is measured only after the second pole-slip, if the
protected machine is not already disconnected after the first pole-slip. The
measured value of slipsPerSecond (SLIPFREQ) is equal to the average slip-
frequency of the machine between the last two successive pole-slips.
Although out-of-step events are relatively rare, the out-of-step protection should
take care of the circuit breaker health. The electromechanical stress to which the
breaker is exposed shall be minimized. The maximum currents flowing under out-
of-step conditions can be even greater that those for a three-phase short circuit on
generator terminals; see Figure 242. The currents flowing are highest at rotor angle
180 degrees, and smallest at 0 degrees, where relatively small currents flow. To
open the circuit breaker at 180 degrees, when not only the currents are highest, but
the two internal (that is, induced) voltages at both ends are in opposition, could be
fatal for the circuit breaker. There are two methods available in order to minimize
the stress; the second method is more advanced than the first one.
X[Ohm]
0.6 trip RE - Receiving End (infinite bus)
region
loci of Z(R, X)
0.4 3
Figure 241: The imaginary offset Mho circle represents loci of the impedance
Z(R, X) for which the rotor angle is 90 degrees
35
very high currents due
Current in kA, trip command to CB, rotor angle in rad →
← rotor angle
0
angle towards 0°
-5
0 200 400 600 800 1000 1200
Time in milliseconds →
IEC10000115-1-en.vsd
IEC10000115 V1 EN-US
Figure 242: Trip initiation when the break-time of the circuit breaker is known
If the traverse time is more than the limit 40 or 50 ms, a pole-slip is declared. If the
complex impedance Z(R, X) exits the lens on the same side it entered, then it is a
stable case and the protected machine is still in synchronism. If a pole-slip has been
detected, then it is determined in which zone the centre of oscillation is located. If
the number of actual pole-slips exceeds the maximum number of allowed pole-
slips in either of the zones, a trip command is issued taking care of the circuit
breaker safety.
R R
UPSRE Calculation of X X
UPSIM R and X parts
of the complex Z(R,X)
UPSMAG
positive-
IPSRE
sequence Z(R,X) NO
IPSIM
impedance within limit of Return
Z(R, X) reach?
YES UCOSPHI
Z(R,X) ROTORANG
within lens NO
Function alert
characteristic?
SLIPFREQ
YES GENMODE
Z(R,X) MOTMODE
LEFT Z(R,X) RIGHT NO
exited lens
entered lens
on the left- hand
from?
Motor losing Generator losing side?
step ? step ?
YES
Was
traverse time NO
more than
Calculation of 50 ms?
P
positive- sequence YES (pole- slip!)
active power P, Q TRIP
>= 1
reactive power Q, Number
ZONE 2 NO
rotor angle UCOSPHI
of pole- slips
ROTORANG exceeded in TRIPZ1
a zone? Open
and
ROTORANG circuit
UCOSPHI ZONE 1 TRIPZ2
breaker
safely
IEC10000116-3-en.vsd
IEC10000116 V3 EN-US
8.18.1 Identification
SEMOD151937-2 v2
For cross-country faults, the logic selects either the leading or lagging phase-earth
loop for measurement. It initiates operation on the preferred fault based on the
selected phase preference. A number of different phase preference combinations
are available for selection.
PPLPHIZ
I3P* START
U3P* ZREL
BLOCK
RELL1N
RELL2N
RELL3N
STCND
IEC07000029-2-en.vsd
IEC07000029 V2 EN-US
PID-6808-INPUTSIGNALS v2
PID-6808-OUTPUTSIGNALS v2
PID-6808-SETTINGS v2
ZMQAPDIS
FDPSPDIS
W2_CT_B_I3P I3P* TRIP
I3P* TRIP
W2_VT_B_U3P U3P* TRL1
U3P* START
FALSE BLOCK TRL2
BLOCK STFWL1 PHS_L1 W2_FSD1-BLKZ VTSZ TRL3
DIRCND STFWL2 PHS_L2 FALSE BLKTR START
STFWL3 PHS_L3 STCND STL1
STFWPE
DIRCND STL2
STRVL1
STL3
STRVL2
STND
STRVL3
STRVPE
STNDL1 ZMQPDIS
STNDL2 I3P* TRIP
W2_CT_B_I3P
STNDL3 U3P* TRL1
W2_VT_B_U3P
STNDPE FALSE BLOCK TRL2
STFW1PH VTSZ TRL3
W2_FSD1-BLKZ
STFW2PH
FALSE BLKTR START
STFW3PH
STCND STL1
STPE DIRCND STL2
STPP STL3
STCNDZ STND
STCNDLE
PPLPHIZ
W2_CT_B_I3P I3P* START
W2_VT_B_U3P U3P* ZREL
FALSE BLOCK
FALSE RELL1N
FALSE RELL2N
FALSE RELL3N
STCND
IEC06000552-3-en.vsd
IEC06000552 V3 EN-US
Transient residual currents associated with single phase fault inception are not
allowed to release the distance protection. This is taken care of by a time-on-delay
tIN, which should be set longer than the expected duration of the transient.
If a single phase fault remains for some time, it is possible to bypass the tIN time
delay, since the next fault event is expected to be a two-phase fault. The criterion
for this bypass is that the residual voltage is greater than setting level 3U0> for a
time longer than setting tUN. The time-off-delay tOffUN is used to make sure that
the bypass is steady during the cross-country fault.
The time delay for residual current start is also bypassed as soon as two low
voltages are detected during the cross-country fault (startUPP). See Figure 246.
startUPP
OR
tUN tOffUN
3U0 > 3U0> t t
(Non delayed IN start)
AND
tIN startIN
OR
3I0>IN> t
IEC16000018-1-en.vsdx
IEC16000018 V1 EN-US
During a cross-country fault, the phase with an external fault typically does not
carry any fault current, which will make it difficult for a conventional phase
selection function to detect the fault. Therefore, PPLPHIZ function provides an
additional phase selection based on voltage.
AND startUL1L2
OR
AND startUL2L3
OR
startUL1
OR
AND startUL3L1
ULxLy < UPP< OR
startUL2
L1L2 OR
L2L3
startUL3
L3L1 OR
IEC16000019-1-en.vsdx
IEC16000019 V1 EN-US
The voltage phase selection can be complemented with external phase selection
through inputs RELL1-3N.
startUL1
AND
startUL2
startUPP
AND OR
startUL3
AND
OperMode = No Filter
OR
AND
OperMode = NoPref
OR
RELL1N startL1
OR
OR
RELL2N startL2
OR
OR
RELL3N startL3
OR
OR
L1N
L2N
L3N
STCND Integer L1L2 zrelL1L2
to Bool
L2L3 zrelL2L3
L3L1 zrelL3L1
IEC16000105-1-en.vsdx
IEC16000105 V1 EN-US
The different operating modes (selected with OperMode setting) determine how the
internal status is used to release the phases of the connected distance protection.
In No Filter mode, all phase starts of the phase selection will be passed through
without any preference or requirement on residual current or voltage.
startL1 zrelL1
startL2 zrelL2
startL3 zrelL3
IEC16000106-1-en.vsdx
IEC16000106 V1 EN-US
The ‘NoPref’ mode uses only the residual current criteria (startIN). There is no
preference provided in this mode. All three phase-to-earth loops of the distance
protection may be released when a residual current start has occurred.
startL1
zrelL1
AND
startL2
zrelL2
AND
startL3
zrelL3
AND
startIN
IEC16000107-1-en.vsdx
IEC16000107 V1 EN-US
In the preference modes (for example, ‘1231c’), the internal under-voltage phase
selection status is filtered with the selected preference scheme to achieve the
desired phase preference. Only the preferred phase-to-earth loop of the distance
protection is released to operate. In addition to the voltage phase selection, a
residual current start is required.
A logic is also included to handle the special case where only one start (startL1-3)
is present.
The internal under-voltage phase selection always issues a release in at least two
phases, but the inputs RELL1-3N can be activated with some time apart. If no
measures are taken, the phase activated first will pass through the preference
scheme and release the distance protection. Since it could a be non-preferred phase,
a time delay of 40 ms is provided to release if only one phase is detected, in order
to wait for the second phase to be activated. If no second phase is detected within
40 ms, the single phase is released without preference.
In both cases, no release signals come from the phase preference scheme. For these
cases, an additional logic is provided that releases all phases if there is no output
from the preference scheme after 40 ms from the activation of the residual current
start.
Preference
OperMode Scheme
Sheme
startL1 prefL1
INL1 OUTL1
startL2 prefL2
INL2 OUTL2
startL3 INL3 OUTL3
prefL3
More
than
one stIN
AND
true
startIN
40 ms
stIN40ms
t
IEC16000023-1-en.vsdx
IEC16000023 V1 EN-US
prefL1
OR zrelL1
AND
prefL2
OR zrelL2
AND
prefL3
OR zrelL3
AND
OR
AND
stIN40ms
stIN OR
IEC16000024-1-en.vsdx
IEC16000024 V1 EN-US
Table 255 shows the preferred phase for each detected cross-country fault type and
operating mode (OperMode).
Table 255: Preferred phase for each cross-country fault type and operating mode
Operating mode start in L1 & L2 start in L2 & L3 start in L3 & L1
1231c L1 L2 L3
1321c L2 L3 L1
123a L1 L2 L1
132a L1 L3 L1
213a L2 L2 L1
231a L2 L2 L3
312a L1 L3 L3
321a L2 L3 L3
All loop releasing signals are gathered in the binary coded integer output ZREL.
The value of ZREL can be calculated according to Equation 125.
The BLOCK input will only block the enabling signals for phase-
to-earth loops, phase-to-phase loops are still released. The
PPLPHIZ is designed not to have any influence on the phase-to-
phase loops of the distance protection.
startU
AND
zrelL1
AND
zrelL2
AND L1N
zrelL3 L2N
AND L3N
Bool to ZREL
zrelL1L2 L1L2 Integer
zrelL2L3 L2L3
BLOCK zrelL3L1 L3L1
IEC16000108-1-en.vsdx
IEC16000108 V1 EN-US
8.19.1 Identification
GUID-850E4134-E912-45EC-981E-E1A2C12A91A8 v1
The Phase preference logic function (PPL2PHIZ) is used with the high speed
distance protection, quad and mho characteristic (ZMFPDIS). It is intended to be
used in isolated or high impedance earthed networks where there is a requirement
to operate on only one of the faulty lines during a cross-country fault. It can be
used without preference to restrain operation for single earth faults with a delayed
zero-sequence current release.
For cross-country faults, the logic selects either the leading or lagging phase-earth
loop for measurement. It initiates operation on the preferred fault based on the
selected phase preference. A number of different phase preference combinations
are available for selection.
PPL2PHIZ
I3P* START
U3P* ZREL
BLOCK
RELL1N
RELL2N
RELL3N
IEC16000016-1-en.vsdx
IEC16000016 V1 EN-US
8.19.4 Signals
PID-6809-INPUTSIGNALS v2
PID-6809-OUTPUTSIGNALS v2
8.19.5 Settings
PID-6809-SETTINGS v2
The PPL2PHIZ function releases the phase selection inside the distance protection,
see Figure 255.
The phase selection inside the distance protection has to detect the
fault before an operation from the distance zones can be achieved,
even when the distance protection is released by PPL2PHIZ.
PPL2PHIZ ZMFPDIS
Phase
Phase selection
preference
Zone1
L1N relcndphs TRZ1
L1N bitwise enable
L2N AND
L2N
L3N Zone2
L3N Bool to ZREL bitwise
TRUE L1L2 Integer AND
enable
RELCNDZ1
TRUE L2L3
Zone3
TRUE L3L1 RELCNDZ2 bitwise
enable
AND
RELCNDZ3
Zone4
RELCNDZ4 bitwise
enable
TRZ4
AND
RELCNDZ5 Zone5
bitwise
enable
TRZ5
RELCNDZRV AND
ZoneRV
bitwise
enable
TRZRV
AND
IEC16000017-1-en.vsdx
IEC16000017 V1 EN-US
Transient residual currents associated with single phase fault inception are not
allowed to release the distance protection. This is taken care of by a time-on-delay
tIN, which should be set longer than the expected duration of the transient.
If a single phase fault remains for some time, it is possible to bypass the tIN time
delay, since the next fault event is expected to be a two-phase fault. The criterion
for this bypass is that the residual voltage is greater than setting level 3U0> for a
time longer than setting tUN. The time-off-delay tOffUN is used to make sure that
the bypass is steady during the cross-country fault.
The time delay for residual current start is also bypassed as soon as two low
voltages are detected during the cross-country fault (startUPP). See Figure 256.
startUPP
OR
tUN tOffUN
3U0 > 3U0> t t
(Non delayed IN start)
AND
tIN startIN
OR
3I0>IN> t
IEC16000018-1-en.vsdx
IEC16000018 V1 EN-US
During a cross-country fault, the phase with an external fault typically does not
carry any fault current, which will make it difficult for a conventional phase
selection function to detect the fault. Therefore, PPL2PHIZ function provides an
additional phase selection based on voltage.
AND startUL1L2
OR
AND startUL2L3
OR
startUL1
OR
AND startUL3L1
ULxLy < UPP< OR
startUL2
L1L2 OR
L2L3
startUL3
L3L1 OR
IEC16000019-1-en.vsdx
IEC16000019 V1 EN-US
The voltage phase selection can be complemented with external phase selection
through inputs RELL1-3N.
startUL1
AND
startUL2
startUPP
AND OR
startUL3
AND
OperMode = No Filter
OR
OperMode = NoPref
startL1
RELL1N OR
startL2
RELL2N OR
startL3
RELL3N OR
IEC16000020-1-en.vsdx
IEC16000020 V1 EN-US
The different operating modes (selected with OperMode setting) determine how the
internal status is used to release the phases of the connected distance protection.
In No Filter mode, all distance protection phases are released constantly, leaving it
to the phase selection inside the distance protection to decide which distance zone
loops should be allowed to operate.
TRUE zrelL1
TRUE zrelL2
TRUE zrelL3
IEC16000021-1-en.vsdx
IEC16000021 V1 EN-US
The ‘NoPref’ mode uses only the residual current criteria (startIN). There is no
preference provided in this mode. All three phase-to-earth loops of the distance
protection releases when a residual current start has occurred.
TRUE
zrelL1
AND
TRUE
zrelL2
AND
TRUE
zrelL3
AND
startIN
IEC16000022-1-en.vsdx
IEC16000022 V1 EN-US
In the preference modes (for example, ‘1231c’), the internal under-voltage phase
selection status is filtered with the selected preference scheme to achieve the
desired phase preference. Only the preferred phase-to-earth loop of the distance
protection is released to operate. In addition to the voltage phase selection, a
residual current start is required.
A logic is also included to handle the special case where only one start (startL1-3)
is present.
The internal under-voltage phase selection always issues a release in at least two
phases, but the inputs RELL1-3N can be activated with some time apart. If no
measures are taken, the phase activated first will pass through the preference
scheme and release the distance protection. Since it could a be non-preferred phase,
a time delay of 40 ms is provided to release if only one phase is detected, in order
to wait for the second phase to be activated. If no second phase is detected within
40 ms, the single phase is released without preference.
In both cases, no release signals come from the phase preference scheme. For these
cases, an additional logic is provided that releases all phases if there is no output
from the preference scheme after 40 ms from the activation of the residual current
start.
Preference
OperMode Scheme
Sheme
startL1 prefL1
INL1 OUTL1
startL2 prefL2
INL2 OUTL2
startL3 INL3 OUTL3
prefL3
More
than
one stIN
AND
true
startIN
40 ms
stIN40ms
t
IEC16000023-1-en.vsdx
IEC16000023 V1 EN-US
prefL1
OR zrelL1
AND
prefL2
OR zrelL2
AND
prefL3
OR zrelL3
AND
OR
AND
stIN40ms
stIN OR
IEC16000024-1-en.vsdx
IEC16000024 V1 EN-US
Table 261 shows the preferred phase for each detected cross-country fault type and
operating mode (OperMode).
Table 261: Preferred phase for each cross-country fault type and operating mode
Operating mode start in L1 & L2 start in L2 & L3 start in L3 & L1
1231c L1 L2 L3
1321c L2 L3 L1
123a L1 L2 L1
132a L1 L3 L1
213a L2 L2 L1
231a L2 L2 L3
312a L1 L3 L3
321a L2 L3 L3
All loop releasing signals are gathered in the binary coded integer output ZREL.
The value of ZREL can be calculated according to Equation 126.
The phase-to-phase loops are always released, that is, the value of
ZREL will always be at least 8+16+32=56. For example:
If only L1N is active, then the value is 1+56=57
If start L1N and L3N are active, then the value is 1+4+56=61
The BLOCK input will only block the enabling signals for phase-
to-earth loops, phase-to-phase loops are still released. The
PPL2PHIZ is designed not to have any influence on the phase-to-
phase loops of the distance protection.
startU
AND
zrelL1
AND
zrelL2
AND L1N
zrelL3 L2N
AND L3N
Bool to ZREL
TRUE L1L2 Integer
TRUE L2L3
BLOCK TRUE L3L1
IEC16000025-1-en.vsdx
IEC16000025 V1 EN-US
S00346 V1 EN-US
The under impedance protection is a three zone full scheme impedance protection
using offset mho characteristics for detecting faults in the generator, generator-
transformer and transmission system. The three zones have fully independent
measuring loops and settings. The functionality also comprises an under voltage
seal-in feature to ensure issuing of a trip even if the current transformer goes into
saturation and, in addition, the positive-sequence-based load encroachment feature
for the second and the third impedance zone. Built-in compensation for the step-up
transformer vector group connection is available.
ZGVPDIS
I3P* TRIP
U3P* TRZ1
BLOCK TRZ2
BLKZ TRZ3
BLKUV TRUV
START
STZ1
STZ2
STZ3
STUV
IEC14000018-1-en.vsd
IEC14000018 V1 EN-US
8.20.4 Signals
PID-3587-INPUTSIGNALS v8
PID-3587-OUTPUTSIGNALS v8
8.20.5 Settings
PID-3587-SETTINGS v8
The full scheme backup distance element constitutes of three operating zones.
Zone1 has only the phase-to-phase loops enabled. Zone2 and zone3 can be selected
for phase –to-phase or Enhanced reach loop. Each measuring loop use the offset
mho characteristic
UBase
ZBase =
3 IBase
IECEQUATION1400024 V1 EN-US (Equation 127)
Where,
ZBase is the base value of impedance
UBase is the line-to-line voltage rating at the generator terminal
All the outputs will be blocked by activation of the BLOCK or BLKZ input.
jX
IEC11000294-2-en.vsd
IEC11000294 V2 EN-US
U3P STZ1
I3P ZONE 1 TRZ1
BLKZ OpModeZ1
Z1Fwd
BLOCK Z1Rev
tZ1 START
³1
ZONE 2 STZ2
OpModeZ2
Z2Fwd TRZ2
Z2Rev
tZ2
LoadEnchModZ2
OPERATE
³1
³1
STZ3
ZONE 3
OpModeZ3
Z3Fwd
Z3Rev
tZ3 TRZ3
LoadEnchModZ3
LoadEnch
RLd
ArgLd
UVSealIn TRUV
OpModeU< STUV
U<
tU<
BLCKUV
IEC11000295-3-en.vsd
IEC11000295 V2 EN-US
In general, the zone 1 must cover the generator winding, the cables or busbars and
step up transformer.
Zone 1 functionality can be set to PP Loops or Off using the setting OpModeZ1.
BLOCK
BLKZ
U3P Comparator
ZL1L2 <
I3P
OpModeZ1
Z1Fwd STZ1
Z1Rev
ImpedanceAng
tZ1
Comparator
³1 t TRZ1
ZL2L3 <
OPModeZ1
Z1Fwd
Z1Rev
ImpedanceAng
Comparator
ZL3L1 <
OpModeZ1
Z1Fwd
Z1Rev
ImpedanceAng
IEC11000297-3-en.vsd
IEC11000297 V3 EN-US
Comparator characteristics
The comparator consists of offset mho characteristics. Three individual
comparators are provided in the three phase-to-phase loops. The offset mho
characteristic is as shown in figure 268.
IL1L2 · jX
IL1L2 · Z 1Fwd
Ucomp1=UL1L2 - I L1L2 · Z1Fwd
IL1L2 · R
- IL1L2· Z1REV
IEC11000296-2-en.vsd
IEC11000296 V2 EN-US
Figure 268: Simplified offset mho characteristics for L1-L2 fault in zone 1
In the above characteristics, Z1Fwd and Z1Rev are the forward and reverse reach
percentage values and ImpedanceAng is the characteristic angle provided for the
zone 1 operation region.
Operate time
The operate time delay for zone 1 can be provided using the setting tZ1.
Figure 269 shows the function block diagram describing the functionality of zone
2.
Zero
sequence
Voltage
Compensation
U3P
Measuring Loop
I3P EnhancedReach
BLOCK OpModeZ2
Z2Fwd
Z2Rev
BLKZ ImpedanceAng
1
Measuring Loop
phase-to-phase STZ2
(ZL1L2<,ZL2L3<,ZL3L1<) &
OpModeZ2
tZ2
Z2Fwd
t TRZ2
Z2Rev
ImpedanceAng
LoadEnchModZ2
Load
Encroachment T
1 F
RLd
ArgLd
IEC11000298-3-en.vsd
IEC11000298 V3 EN-US
Zone 2 can be used to cover up to the HV side of the transformer and the HV bus
bar. It also covers to some degree, the stator winding. The time to trip is provided
in order to coordinate with the zone 1 element on the shortest outgoing line from
the bus.
Zone 2 coverage provides backup for the phase-to-phase and three-phase faults in
generator. It also protects LV winding of generator transformer and phase-to-earth,
phase-to-phase and three-phase faults in the HV side of transformer and the bus. A
separate maximum current feature is provided in phase-to-earth loop selection
which gives correct reach measurement for phase-to-phase fault on HV side. Zero
sequence compensation for the phase voltages is given in phase-to-earth measuring
loops in order to prevent operation for the stator earth faults.
Zone 2 can be selected for different measuring loops using the setting OpModeZ2.
The OpModeZ2 can be selected as Off or PP Loops or EnhancedReach. If the
OpModeZ2 is selected as EnhancedReach, the loop used for measurements is the
phase-to-earth measuring loop (L1E, L2E and L3E) which is with maximum phase
current of all the three phase currents.
Figure 270 shows the logic to detect the phase to earth loop with maximum phase
current.
A startPh1 &
i1Mag a
a==b
b
startPh2 & ³1 start
&
B
i2Mag a
a==b
b startPh3 &
&
³1
C
i3Mag a
a==b
b
MAX
IEC11000307_1_en.vsd
IEC11000307 V1 EN-US
Figure 270: Logic diagram for the selection of the maximum current loop
The reach settings for zone 2 can be provided using the Z2Fwd, Z2Rev and
ImpedanceAng settings. The Z2Fwd is forward reach setting and Z2Rev is reverse
reach setting. The offset mho characteristic for phase-to-earth loop is shown in
Figure 271. The offset mho characteristics for phase-to-phase loop is shown in
Figure 272.
IL1 jX
IL1 Z 2 Fwd
Ucomp1 UL1E U 0 IL1 Z 2 Fwd
IL1 R
IL1 Z 2 REV
IEC11000299-2-en.vsd
IEC11000299 V2 EN-US
Figure 271: Simplified offset mho characteristics for L1-to-E fault in zone 2
IL1L 2 jX
IL1L2 Z 2 Fwd
Ucomp1 UL1L2 IL1L2 Z 2 Fwd
IL1L 2 R
IL1L 2 Z 2 REV
IEC11000300-2-en.vsd
IEC11000300 V2 EN-US
Figure 272: Simplified offset mho characteristics for L1-to-L2 fault in zone 2
Impedance defined in the Figure 271 and 272 is described in equation 130.
Phase Phase:
Sl.No Measuring Loop Voltage Phasor Current Phasor
L1-L2
1 UL1L 2 IL1L 2
L2-L3
2 UL 2 L3 IL 2 L3
L3-L1
3 UL3L1 IL3L1
Enhanced Reach:
1 IL1 1)
UL1E - U 0 IL1
2 IL21)
UL 2 E - U 0 IL2
3 IL31)
UL3 E - U 0 IL3
Operate time
The operate time delay for zone 2 can be provided using the setting tZ2.
The zone 3 will provide protection from phase-to-earth, phase-phase and three-
phase faults on the HV side of the system. The zone 3 functionality is same as zone
2 hence the explanation of zone 2 applies except the zone 3 has separate reach
(Z3Fwd, Z3Rev), operate timer (tZ3) and load encroachment enable
(LoadEnchModZ3) settings.
The load encroachment characteristics can be set for zone2 and zone3. Load
encroachment can be enabled for zone 2 by setting LoadEnchModZ2 to On.
Similarly the load encroachment for zone 3 can be enabled by setting
LoadEnchModZ3 to On.
RLd is the positive sequence resistive reach value in percentage. ArgLd is angle in
degrees from the origin to the resistive axis as shown in Figure 273.
jX
ArgLd ArgLd
-RLd RLd R
ArgLd ArgLd
IEC11000304_1_en
IEC11000304 V1 EN-US
The under voltage seal-in logic ensures the trip under fault condition, where as
under impedance function will reset due to CT saturation. The start signal of zone 2
and zone 3 elements trigger the under voltage seal-in. This can be selected using
the setting OpModeU< . The setting OpModeU< can be selected as Off or Z2Start
or Z3Start. Select Z2Start to choose zone 2 for triggering the seal-in logic.
Similarly, select Z3Start to choose zone 3 for triggering the seal-in logic.
Under voltage seal-in is activated from the criterion based on line-to-line voltage
magnitude. The voltage criteria checks by comparing all three line-to-line voltage
levels with the level given by the setting parameter U<. If any loop detects lower
voltage, the under voltage seal-in logic gets triggered, provided the respective
selected zone start is also high. Once the under voltage seal-in logic is triggered,
the pick-up signal STUV becomes high. If it is constantly high for a time longer
than the setting tU<, the tripping signal TRUV is issued as a pulse signal with a
duration of one second.
Figure 274 shows the functionality of under voltage seal-in for zone 2 and zone 3.
- STUV
q1
BLOCK
BLKUV 1 tU<
TRUV
Zone 2 Start & t
tPulse = 1sec
&
OpModeU< =
10 ms -
0 = Off b0 1 q1
int 1 t
1 = Z2Start
2 = Z3Start b1
Drop-Off
& timer
Zone 3 Start
uP1P2 a
a<b
U< b
uP2P3 a
a<b 1
U< b
uP3P1 a
a< b
U< b
IEC11000306-3-en.vsd
IEC11000306 V3 EN-US
9.1.1 Identification
M14880-1 v5
SYMBOL-Z V1 EN-US
The instantaneous three phase overcurrent function has a low transient overreach
and short tripping time to allow use as a high set short-circuit protection function.
PHPIOC
I3P* TRIP
BLOCK TRL1
ENMULT TRL2
TRL3
IEC04000391-2-en.vsd
IEC04000391 V2 EN-US
PID-6914-INPUTSIGNALS v3
PID-6914-OUTPUTSIGNALS v3
PID-6914-SETTINGS v3
The sampled analogue phase currents are pre-processed in a discrete Fourier filter
(DFT) block. The RMS value of each phase current is derived from the
fundamental frequency components, as well as sampled values of each phase
current. These phase current values are fed to the instantaneous phase overcurrent
protection 3-phase output function PHPIOC. In a comparator the RMS values are
compared to the set operation current value of the function (IP>>).
If a phase current is larger than the set operation current a signal from the
comparator for this phase is set to true. This signal will, without delay, activate the
output signal TRLn (n=1,2,3) for this phase and the TRIP signal that is common
for all three phases.
There is also a possibility to activate a preset change of the set operation current
(StValMult) via a binary input (ENMULT). In some applications the operation
value needs to be changed, for example, due to transformer inrush currents.
IP>>Max
MAX hi
u y
IP>>_used
IP>>
MIN lo
IP>>Min
IEC17000016-1-en.vsdx
IEC17000016 V1 EN-US
M12336-1 v13
9.2.1 Identification
M14885-1 v6
TOC-REVA V2 EN-US
All IEC and ANSI inverse time characteristics are available together with an
optional user defined time characteristic.
The directional function needs voltage as it is voltage polarized with memory. The
function can be set to be directional or non-directional independently for each of
the steps.
A second harmonic blocking level can be set for the function and can be used to
block each step individually.
OC4PTOC
I3P* TRIP
U3P* TR1
BLOCK TR2
BLKTR TR3
BLKST1 TR4
BLKST2 TRL1
BLKST3 TRL2
BLKST4 TRL3
ENMULT1 TR1L1
ENMULT2 TR1L2
ENMULT3 TR1L3
ENMULT4 TR2L1
TR2L2
TR2L3
TR3L1
TR3L2
TR3L3
TR4L1
TR4L2
TR4L3
START
ST1
ST2
ST3
ST4
STL1
STL2
STL3
ST1L1
ST1L2
ST1L3
ST2L1
ST2L2
ST2L3
ST3L1
ST3L2
ST3L3
ST4L1
ST4L2
ST4L3
ST2NDHRM
DIRL1
DIRL2
DIRL3
STDI RCND
IEC06000187-4-en.vsdx
IEC06000187 V4 EN-US
9.2.4 Signals
PID-6973-INPUTSIGNALS v3
PID-6973-OUTPUTSIGNALS v3
9.2.5 Settings
PID-6973-SETTINGS v3
Directional phase overcurrent protection, four steps OC4PTOC is divided into four
different sub-functions. For each step x , where x is step 1, 2, 3 and 4, an operation
mode is set by DirModex: Off/Non-directional/Forward/Reverse.
4 step overcurrent
Direction dirPh1Flt element faultState
faultState
Element One element for each
dirPh2Flt step
I3P dirPh3Flt START
U3P
TRIP
Harmonic harmRestrBlock
Restraint
Element
enableDir
Mode Selection
enableStep1-4
DirectionalMode1-4
IEC05000740-3-en.vsdx
IEC05000740 V3 EN-US
A common setting for all steps, StartPhSel, is used to specify the number of phase
currents to be high to enable operation. These settings can be chosen: 1 out of 3, 2
out of 3 or 3 out of 3.
Using a parameter setting MeasType within the general settings for the function
OC4PTOC, it is possible to select the type of the measurement used for all
overcurrent stages. Either discrete Fourier filter (DFT) or true RMS filter (RMS)
can be selected.
If the DFT option is selected, only the RMS value of the fundamental frequency
component of each phase current is derived. The influence of the DC current
component and higher harmonic current components are almost completely
suppressed. If the RMS option is selected, then the true RMS value is used. The
true RMS value includes the contribution from the current DC component as well
as from the higher current harmonic in addition to the fundamental frequency
component.
In a comparator, the DFT or RMS values are compared to the set operation current
value of the function (I1>, I2>, I3> or I4>) for each phase current. If a phase
current is larger than the set operation current, outputs START, STx, STL1, STL2
and STL3 are activated without delay. Output signals STL1, STL2 and STL3 are
common for all steps. This means that the lowest set step will initiate the
activation. The START signal is common for all three phases and all steps. It shall
be noted that the selection of measured value (DFT or RMS) do not influence the
operation of directional part of OC4PTOC.
Service values for individually measured phase currents are available on the local
HMI for OC4PTOC function, which simplifies testing, commissioning and in
service operational checking of the function.
A harmonic restrain of the function can be chosen. A set 2nd harmonic current in
relation to the fundamental current is used.
The function can be directional.The direction of a fault is given as the current angle
in relation to the voltage angle. The fault current and fault voltage for the
directional function are dependent on the fault type. The selection of the measured
value (DFT or RMS) does not influence the operation of the directional part of
OC4PTOC. To enable directional measurement at close-in faults, causing a low
measured voltage, the polarization voltage is a combination of the apparent voltage
(85%) and a memory voltage (15%). The following combinations are used.
U refL1L 2 = U L1 - U L 2 I dirL1L 2 = I L1 - I L 2
EQUATION1449 V1 EN-US (Equation 131)
U refL 2 L 3 = U L 2 - U L 3 I dirL 2 L 3 = I L 2 - I L 3
EQUATION1450 V1 EN-US (Equation 132)
U refL 3 L1 = U L 3 - U L1 I dirL 3 L1 = I L 3 - I L1
EQUATION1451 V1 EN-US (Equation 133)
U refL1 = U L1 I dirL1 = I L1
EQUATION1452 V1 EN-US (Equation 134)
U refL 2 = U L 2 I dirL 2 = I L 2
EQUATION1453 V1 EN-US (Equation 135)
U refL 3 = U L 3 I dirL 3 = I L 3
EQUATION1454 V1 EN-US (Equation 136)
For close-in three-phase faults, the U1L1M memory voltage, based on the same
positive sequence voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is
restored.
• If the current is still above the set value of the minimum operating current (7%
of the set terminal rated current IBase), the condition seals in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element
in the reverse direction remains in operation.
• If the current decreases below the minimum operating value, the memory
resets until the positive sequence voltage exceeds 10% of its rated value.
The directional setting is given as a characteristic angle AngleRCA for the function
and an angle window ROADir.
Reverse
Uref
RCA
ROA
ROA Forward
Idir
en05000745.vsd
IEC05000745 V1 EN-US
The default value of AngleRCA is –55°. The parameter AngleROA gives the
angular distance from AngleRCA to define the directional borders.
A minimum current for the directional phase start current signal can be set.
IMinOpPhSel is the start level for the directional evaluation of IL1, IL2 and IL3.
The directional signals release the overcurrent measurement in the respective
phases if their current amplitudes are higher than the start level (IMinOpPhSel) and
the direction of the current is according to the set direction of the step.
If no blocking signals are active, the start signal will start the timer of the steps.
The time characteristic for each step can be chosen as definite time delay or an
inverse time delay characteristic. A wide range of standardized inverse time delay
characteristics is available. It is also possible to create a tailor made time
characteristic.
The possibilities for inverse time characteristics are described in section "Inverse
characteristics".
Characteristx=DefTime
|IOP| AND
tx TRx
a OR
a>b
Ix> b
AND
STx
txmin
BLKSTx AND
BLOCK
Inverse
Characteristx=Inverse
DirModex=Off OR STAGEx_DIR_Int
DirModex=Non-directional
DirModex=Forward
AND OR
FORWARD_Int
DirModex=Reverse
AND
REVERSE_Int
IEC12000008.vsd
IEC12000008.vsd
IEC12000008 V2 EN-US
I3P
DFWDLx
U3P DFWDLxx
DREVLx
Directional
Element
AngleRCA DREVLxx FORWARD_int
Directional
AngleROA Release REVERSE_int
Block
STLx
Greater
IMinOpPhSel Comparator
x‐ means three phases 1,2 and 3
xx – means phase to phase 12,23,31
IEC15000266-2-en.vsdx
IEC15000266 V2 EN-US
The operation current value Ix>, is limited to be between Ix>Max and Ix>Min. The
default values of the limits are the same as the setting limits for Ix>, and the limits
can only be used for reducing the allowed range of Ix>. This feature is used when
remote setting of the operation current value is allowed, making it possible to
ensure that the operation value used is reasonable. If Ix> is set outside Ix>Max and
Ix>Min, the closest of the limits to Ix> is used by the function. If Ix>Max is
smaller then Ix>Min, the limits are swapped. The principle of the limitation is
shown in Figure 282.
Ix>Max
MAX hi
u y
Ix>_used
Ix>
MIN lo
Ix>Min
IEC17000018-1-en.vsdx
IEC17000018 V1 EN-US
The STDIRCND output provides an integer signal that depends on the start and
directional evaluation and is derived from a binary coded signal as described in
Table 283.
Table 283: Code description for STDIRCND output signal
STDIRCND Description
bit 0 (1) General start
bit 1 (2) Direction detected in forward
bit 2 (4) Direction detected in reverse
bit 3 (8) Start in phase L1
bit 4 (16) Forward direction detected in phase L1
bit 5 (32) Reverse direction detected in phase L1
bit 6 (64) Start in phase L2
bit 7 (128) Forward direction detected in phase L2
bit 8 (256) Reverse direction detected in phase L2
bit 9 (512) Start in phase L3
bit 10 (1024) Forward direction detected in phase L3
bit 11 (2048) Reverse direction detected in phase L3
All four steps in OC4PTOC can be blocked from the binary input BLOCK. The
binary input BLKSTx (x=1, 2, 3 or 4) blocks the operation of the respective step.
The start signals from the function can be blocked by the binary input BLKST.The
trip signals from the function can be blocked by the binary input BLKTR.
GUID-E3980B2D-EEDA-4BF1-A07D-E7B721130554 v5
BLOCK
a
a>b
0.07*IBase b
a
a>b
b
Extract second AND
IOP
harmonic current a
a>b
component b
2ndH_BLOCK_Int
Extract
fundamental
current component
X
2ndHarmStab
IEC13000014-2-en.vsd
IEC13000014 V2 EN-US
9.3.1 Identification
M14887-1 v4
IEF V1 EN-US
EFPIOC
I3P* TRIP
BLOCK
BLKAR
ENMULT
IEC06000269-3-en.vsdx
IEC06000269 V3 EN-US
PID-6915-INPUTSIGNALS v4
PID-6915-OUTPUTSIGNALS v4
PID-6915-SETTINGS v4
The sampled analog residual currents are pre-processed in a discrete Fourier filter
(DFT) block. From the fundamental frequency components of the residual current,
as well as from the sample values the equivalent RMS value is derived. This
If the residual current is larger than the set operation current a signal from the
comparator is set to true. This signal will, without delay, activate the output signal
TRIP.
There is also a possibility to activate a preset change of the set operation current
via a binary input (enable multiplier ENMULT). In some applications the operation
value needs to be changed, for example, due to transformer inrush currents.
IN>>Max
MAX hi
u y
IN>>_used
IN>>
MIN lo
IN>>Min
IEC17000015-1-en.vsdx
IEC17000015 V1 EN-US
EFPIOC function can be blocked from the binary input BLOCK. The trip signals
from the function can be blocked from the binary input BLKAR, that can be
activated during single pole trip and autoreclosing sequences.
M12340-2 v9
9.4.1 Identification
M14881-1 v6
EF4PTOC has an inverse or definite time delay independent for each step.
All IEC and ANSI time-delayed characteristics are available together with an
optional user-defined characteristic.
IDir, UPol and IPol can be independently selected to be either zero sequence or
negative sequence.
EF4PTOC
I3P* TRIP
U3P* TRIN1
I3PPOL* TRIN2
I3PDIR* TRIN3
BLOCK TRIN4
BLKTR TRSOTF
BLKST1 START
BLKST2 STIN1
BLKST3 STIN2
BLKST4 STIN3
ENMULT1 STIN4
ENMULT2 STSOTF
ENMULT3 STFW
ENMULT4 STRV
CBPOS 2NDHARMD
CLOSECB
OPENCB
IEC06000424-5-en.vsdx
IEC06000424 V5 EN-US
PID-6967-INPUTSIGNALS v3
PID-6967-OUTPUTSIGNALS v3
PID-6967-SETTINGS v3
M13941-51 v7
This function has the following four analog inputs on its function block in the
configuration tool:
1. I3P, input used for the operating quantity. Supplies the zero-sequence
magnitude measuring functionality.
2. U3P, input used for the voltage polarizing quantity. Supplies either the zero or
the negative sequence voltage to the directional functionality
3. I3PPOL, input used for the current polarizing quantity. Provides polarizing
current to the directional functionality. This current is normally taken from the
grounding of a power transformer.
4. I3PDIR, input used for directional detection. Supplies either the zero or the
negative sequence current to the directional functionality.
These inputs are connected from the corresponding pre-processing function blocks
in the configuration tool in PCM600.
The function always uses residual current (3I0) for its operating quantity. The
residual current can be:
where:
IL1, IL2 and IL3 are fundamental frequency phasors of three individual phase currents.
The residual current is pre-processed by a discrete Fourier filter. Thus the phasor of
the fundamental frequency component of the residual current is derived. The
phasor magnitude is used within the EF4PTOC protection to compare it with the
set operation current value of the four steps (IN1>, IN2>, IN3> or IN4>).
If the residual current is larger than the set operation current and the step is used in
non-directional mode a signal from the comparator for this step is set to true. This
signal will, without delay, activate the output signal STINx (x=step 1-4) for this
step and a common START signal.
The function can be set to use voltage polarizing, current polarizing or dual
polarizing.
Voltage polarizing
When voltage polarizing is selected, the protection will use the residual voltage
-3U0 as the polarizing quantity U3P.
where:
UL1, UL2 and UL3 are fundamental frequency phasors of three individual phase voltages.
In order to use this, all three phase-to-earth voltages must be connected to three IED VT
inputs.
The residual voltage is pre-processed by a discrete fourier filter. Thus, the phasor
of the fundamental frequency component of the residual voltage is derived.
This phasor is used together with the phasor of the operating directional current, in
order to determine the direction to the earth fault (Forward/Reverse). In order to
enable voltage polarizing the magnitude of polarizing voltage shall be bigger than a
minimum level defined by setting parameter UPolMin.
It shall be noted that residual voltage (-3U0) or negative sequence voltage (-3U2) is
used to determine the location of the earth fault. This ensures the required inversion
of the polarizing voltage within the earth-fault function.
Current polarizing
When current polarizing is selected, the function will use an external residual
current (3I0) as the polarizing quantity IPol. This current can be:
where:
IL1, IL2 and IL3 are fundamental frequency phasors of three individual phase currents.
The residual current is pre-processed by a discrete fourier filter. Thus the phasor of
the fundamental frequency component of the polarizing current is derived. This
phasor is then multiplied with the pre-set equivalent zero-sequence source
impedance in order to calculate the equivalent polarizing voltage UIPol in
accordance with the following formula:
which will be then used, together with the phasor of the operating current, in order
to determine the direction to the earth fault (forward/reverse).
In order to enable current polarizing, the magnitude of the polarizing current shall
be bigger than a minimum level defined by setting parameter IPolMin.
Dual polarizing
When dual polarizing is selected, the function will use the vectorial sum of the
voltage based and current based polarizing in accordance with the following
formula:
UPol and IPol can be either zero sequence component or negative sequence
component depending upon the user selection.
Then the phasor of the total polarizing voltage UTotPol will be used, together with
the phasor of the operating current, to determine the direction of the earth fault
(forward/reverse).
The individual steps within the protection can be set as non-directional. When this
setting is selected, it is possible via the function binary input BLKSTx to provide
external directional control (that is, torque control) by, for example, using one of
the following functions if available in the IED:
Zero sequence components will be used for detecting directionality for the earth
fault function. In some cases, zero sequence quantities might detect directionality
incorrectly. In such a scenario, negative sequence quantities will be used. The user
can select either zero sequence components or negative sequence components for
detecting directionality with the parameter SeqTypeIPol. I3PDIR input is always
connected to the same source as I3P input.
The base quantities are entered as global settings for all functions in the IED. Base
current (IBase) shall be entered as rated phase current of the protected object in
primary amperes. Base voltage (UBase) shall be entered as rated phase-to-phase
voltage of the protected object in primary kV.
Each overcurrent step uses operating quantity Iop (residual current) as the
measuring quantity. Each of the four residual overcurrent steps has the following
built-in facilities:
INx>Max
MAX hi
u y
INx>_used
INx>
MIN lo
INx>Min
IEC17000017-1-en.vsdx
IEC17000017 V1 EN-US
Simplified logic diagram for one residual overcurrent step is shown in Figure 288.
BLKTR
EMULTX
IMinx Characteristx=DefTime
X T b
a>b
F a
tx TRINx
AND AND
|IOP|
a OR t
a>b
b
STINx
INxMult AND
X T
INx> F
AND Inverse
BLKSTx
AND
BLOCK Characteristx=Inverse
txmin
2ndHarm_BLOCK_Int
OR t
HarmRestrainx=Off
DirModex=Off OR STEPx_DIR_Int
DirModex=Non-directional
DirModex=Forward
AND OR
FORWARD_Int
DirModex=Reverse
AND
REVERSE_Int
IEC10000008.vsd
IEC10000008 V5 EN-US
Figure 288: Simplified logic diagram for residual overcurrent step x, where x = step 1, 2, 3 or 4
The protection can be completely blocked from the binary input BLOCK. Output
signals for respective step, and STINx and TRINx, can be blocked from the binary
input BLKSTx. The trip signals from the function can be blocked from the binary
input BLKTR.
The operating and polarizing quantity are then used inside the directional element,
as shown in Figure 289, in order to determine the direction of the earth fault.
Operating area
STRV
0.6 * IN>DIR
Characteristic for reverse
release of measuring steps
-RCA -85 deg
Characteristic
for STRV 40% of
IN>DIR RCA +85 deg
RCA
65° Upol = -3U 0
STFW
I op = 3I0
Operating area
Characteristic
for STFW IEC11000243-1-en.ai
IEC11000243 V1 EN-US
The relevant setting parameters for the directional supervision element are:
| IopDir |
a
a>b STRV
b AND
REVERSE_Int
0.6
X
a
a>b STFW
IN>Dir b AND
FORWARD_Int
X
0.4
FWD
AND FORWARD_Int
AngleRCA
polMethod=Voltage
OR
Characteristic
UPolMin
Directional
polMethod=Dual UPol IPolMin
T
I3PDIR
polMethod=Current 0.0 F
OR
UTotPol
IPol AND REVERSE_Int
T RVS
0.0 F
UIPol STAGE1_DIR_Int
RNPol Complex X T STAGE2_DIR_Int
XNPol Number 0.0 F STAGE3_DIR_Int OR
STAGE4_DIR_Int
BLOCK AND
IEC07000067-6-en.vsdx
IEC07000067 V6 EN-US
Figure 290: Simplified logic diagram for directional supervision element with integrated directional
comparison step
Blocking from the 2nd harmonic element activates if all of three criteria are
satisfied:
In addition to the basic functionality explained above, the 2nd harmonic blocking
can be set in such way to seal-in until residual current disappears. This feature
might be required to stabilize EF4PTOC during switching of parallel transformers
in the station. In case of parallel transformers there is a risk of sympathetic inrush
current. If one of the transformers is in operation, and the parallel transformer is
switched in, the asymmetric inrush current of the switched-in transformer will
cause partial saturation of the transformer already in service. This is called
transferred saturation. The 2nd harmonic of the inrush currents of the two
transformers is in phase opposition. The summation of the two currents thus gives a
small 2nd harmonic current. The residual fundamental current is however
significant. The inrush current of the transformer in service before the parallel
transformer energizing, is a little delayed compared to the first transformer.
Therefore, we have high 2nd harmonic current component initially. After a short
period this current is however small and the normal 2nd harmonic blocking resets.
If the BlkParTransf function is activated, the 2nd harmonic restrain signal is latched
as long as the residual current measured by the relay is larger than a selected step
current level by using setting UseStartValue.
This feature has been called Block for Parallel Transformers. This 2nd harmonic
seal-in feature is activated when all of the following three conditions are
simultaneously fulfilled:
Once Block for Parallel Transformers is activated, the basic 2nd harmonic blocking
signal is sealed-in until the residual current magnitude falls below a value defined
by parameter setting UseStartValue (see condition 3 above).
Simplified logic diagram for 2nd harmonic blocking feature is shown in Figure 291.
BLOCK
a
a>b
0.07*IBase b
a
a>b
b
Extract second AND
IOP
harmonic current a
a>b
component b
Extract
fundamental
current component
X
2ndHarmStab
q-1
t=70ms OR
t AND OR 2ndH_BLOCK_Int
BlkParTransf=On
a
a>b
b
UseStartValue
IN1>
IN2>
IN3>
IN4>
IEC13000015 V4 EN-US
Figure 291: Simplified logic diagram for 2nd harmonic blocking feature and Block for Parallel Transformers
feature
Integrated in the four step residual overcurrent protection are the switch on to fault
logic (SOTF) and the under-time logic. The setting parameter SOTF is set to
activate SOTF, the under-time logic or both. When the circuit breaker is closing
there is a risk to close it onto a permanent fault, for example during an
autoreclosing sequence. The SOTF logic will enable fast fault clearance during
such situations. The time during which SOTF and under-time logics will be active
after activation is defined by the setting parameter t4U.
The SOTF logic uses the start signal from step 2 or step 3 for its operation, selected
by setting parameter StepForSOTF. The setting parameter ActivationSOTF can be
set for activation of CB position open change, CB position closed change or CB
close command. In case of a residual current start from step 2 or 3 (dependent on
setting) the function will give a trip after a set delay tSOTF. This delay is normally
set to a short time (default 200 ms).
The under-time logic always uses the start signal from the step 4. The under-time
logic will normally be set to operate for a lower current level than the SOTF
function. The under-time logic can also be blocked by the 2nd harmonic restraint
feature. This enables high sensitivity even if power transformer inrush currents can
occur at breaker closing. This logic is typically used to detect asymmetry of CB
poles immediately after switching of the circuit breaker. The under-time logic is
activated either from change in circuit breaker position or from circuit breaker
close and open command pulses. This selection is done by setting parameter
ActUnderTime. In case of a start from step 4 this logic will give a trip after a set
delay tUnderTime. This delay is normally set to a relatively short time (default 300
ms).
SOTF
Open
t4U
Closed
ActivationSOTF
Close command
tSOTF
AND
AND t
STIN2
StepForSOTF
STIN3
SOTF
BLOCK
OFF
SOTF
UNDERTIME TRIP
UnderTime
tUnderTime
SOTF or
2nd Harmonic AND
HarmResSOFT t UnderTime
OR
Open
Close OR
t4U
STIN4
IEC06000643-5-en.vsdx
IEC06000643 V5 EN-US
Figure 292: Simplified logic diagram for SOTF and under-time features
M13941-3 v6
Simplified logic diagram for the complete EF4PTOC function is shown in Figure
293:
signal to
commu nica tion
sche me
Directio nal Che ck
Elemen t
harmRestrB lock
3I0 Harmonic
Restrain t 1
Elemen t
CB
DirMode pos
or cmd
ena bleDir
Mode
Sele ction ena bleStep1-4
Directio nalMode1-4
IEC06000376-2-en.vsd
IEC06000376 V3 EN-US
M15223-1 v17
9.5.1 Identification
GUID-E1720ADA-7F80-4F2C-82A1-EF2C9EF6A4B4 v1
All IEC and ANSI time delayed characteristics are available together with an
optional user defined characteristic.
NS4PTOC
I3P* TRIP
I3PDIR* TR1
U3P* TR2
BLOCK TR3
BLKTR TR4
BLKST1 START
BLKST2 ST1
BLKST3 ST2
BLKST4 ST3
ENMULT1 ST4
ENMULT2 STFW
ENMULT3 STRV
ENMULT4
IEC10000054-2-en.vsd
IEC10000054 V2 EN-US
9.5.4 Signals
PID-4151-INPUTSIGNALS v4
PID-4151-OUTPUTSIGNALS v4
9.5.5 Settings
PID-4151-SETTINGS v4
Four step negative sequence overcurrent protection NS4PTOC function has the
following three “Analog Inputs” on its function block in the configuration tool:
These inputs are connected from the corresponding pre-processing function blocks
in the Configuration Tool within PCM600.
1
I2 = (
× IL1 + a × IL 2 + a × IL 3
2
)
3
EQUATION2266 V2 EN-US (Equation 144)
where:
IL1, IL2 and IL3 are fundamental frequency phasors of three individual phase currents.
a is so called operator which gives a phase shift of 120 deg, that is, a = 1∠120 deg
a2 similarly gives a phase shift of 240 deg, that is, a2 = 1∠240 deg
The phasor magnitude is used within the NS4PTOC protection to compare it with
the set operation current value of the four steps (I1>, I2>, I3> or I4>). If the
negative sequence current is larger than the set operation current and the step is
used in non-directional mode a signal from the comparator for this step is set to
true. This signal, without delay, activates the output signal STx (x=1 - 4) for this
step and a common START signal.
A polarizing quantity is used within the protection to determine the direction to the
fault (Forward/Reverse).
Four step negative sequence overcurrent protection NS4PTOC function uses the
voltage polarizing method.
NS4PTOC uses the negative sequence voltage -U2 as polarizing quantity U3P.
This voltage is calculated from three phase voltage input within the IED. The pre-
processing block calculates -U2 from the first three inputs into the pre-processing
block by using the following formula:
1
UPol = -U 2 = - × (UL1 + a 2 × UL 2 + a × UL3 )
3
EQUATION2267 V2 EN-US
where:
UL1, UL2 and UL3 are fundamental frequency phasors of three individual phase voltages.
To use this all three phase-to-earth voltages must be connected to three IED VT inputs.
This phasor is used together with the phasor of the operating current, in order to
determine the direction to the fault (Forward/Reverse).To enable voltage polarizing
the magnitude of polarizing voltage must be bigger than a minimum level defined
by setting UpolMin.
Note that –U2 is used to determine the location of the fault. This ensures the
required inversion of the polarizing voltage within the function.
The individual steps within the protection can be set as non-directional. When this
setting is selected it is then possible via function binary input BLKSTx (where x
indicates the relevant step within the protection) to provide external directional
control (that is, torque control) by for example using one of the following functions
if available in the IED:
Simplified logic diagram for one negative sequence overcurrent stage is shown in
the following figure:
BLKTR
Characteristx=DefTime AND
TRx
|IOP| AND
tx
a OR
a>b
ENMULTx b
STx
IxMult AND
X T
Ix> F
txmin
BLKSTx AND
BLOCK
Inverse
Characteristx=Inverse
DirModex=Off OR STAGEx_DIR_Int
DirModex=Non-directional
DirModex=Forward
AND OR
FORWARD_Int
DirModex=Reverse
AND
REVERSE_Int
IEC09000683.vsd
IEC09000683 V3 EN-US
Figure 295: Simplified logic diagram for negative sequence overcurrent stage x , where x=1, 2, 3 or 4
NS4PTOC can be completely blocked from the binary input BLOCK. The start
signals from NS4PTOC for each stage can be blocked from the binary input
BLKSTx. The trip signals from NS4PTOC can be blocked from the binary input
BLKTR.
The operating and polarizing quantity are then used inside the directional element,
as shown in figure 296, to determine the direction of the fault.
Reverse
Area
AngleRCA Upol=-U2
Forward
Area
Iop = I2
IEC10000031-1-en.vsd
IEC10000031 V1 EN-US
|Iop|
a a>
STRV
b b REVERSE_Int
AND
0.6
X
a a>
STFW
I>Dir b b FORWARD_Int
AND
X
0.4
FWD
AND FORWARD_Int
AngleRCA
C h a r a c e ri s ti c
D i r e c ti o n a l
UPolMin
IPolMin
t
Iop
UPol
AND REVERSE_Int
RVS
STAGE1_DIR_Int
STAGE2_DIR_Int
STAGE3_DIR_Int OR
STAGE4_DIR_Int
BLOCK AND
IEC07000067-4.vsd
IEC07000067-4 V2 EN-US
Figure 297: Simplified logic diagram for directional supervision element with integrated directional
comparison step
GUID-E83AD807-8FE0-4244-A50E-86B9AF92469E v6
Minimum operate time for inverse curves, (0.000 - 60.000) s ±0.2% or ±35 ms
step 1 - 4 whichever is greater
Inverse time characteristics, see table 16 curve types See table 1130,
1130, table 1131 and table 1132 table 1131 and table
1132
Minimum operate current, step 1 - 4 (1.00 - 10000.00)% of IBase ±1.0% of Ir at I ≤ Ir
±1.0% of I at I > Ir
9.6.1 Identification
SEMOD172025-2 v4
Directional residual current can be used to detect and give selective trip of phase-
to-earth faults in high impedance earthed networks. The protection uses the
residual current component 3I0 · cos φ, where φ is the angle between the residual
current and the residual voltage (-3U0), compensated with a characteristic angle.
Alternatively, the function can be set to strict 3I0 level with a check of angle φ.
Directional residual power can also be used to detect and give selective trip of
phase-to-earth faults in high impedance earthed networks. The protection uses the
residual power component 3I0 · 3U0 · cos φ, where φ is the angle between the
residual current and the reference residual voltage, compensated with a
characteristic angle.
A normal non-directional residual current function can also be used with definite or
inverse time delay.
In an isolated network, that is, the network is only coupled to earth via the
capacitances between the phase conductors and earth, the residual current always
has -90º phase shift compared to the residual voltage (3U0). The characteristic
angle is chosen to -90º in such a network.
As the amplitude of the residual current is independent of the fault location, the
selectivity of the earth fault protection is achieved by time selectivity.
When should the sensitive directional residual overcurrent protection be used and
when should the sensitive directional residual power protection be used? Consider
the following:
Phase
currents
IN
Phase-
ground
voltages
UN
IEC13000013-1-en.vsd
IEC13000013 V1 EN-US
Overcurrent functionality uses true 3I0, i.e. sum of GRPxL1, GRPxL2 and
GRPxL3. For 3I0 to be calculated, connection is needed to all three phase inputs.
SDEPSDE
I3P* TRIP
U3P* TRDIRIN
BLOCK TRNDIN
BLKTR TRUN
BLKTRDIR START
BLKNDN STDIRIN
BLKUN STNDIN
STUN
STFW
STRV
STDIR
UNREL
IEC07000032-2-en.vsd
IEC07000032 V2 EN-US
9.6.4 Signals
PID-3892-INPUTSIGNALS v7
PID-3892-OUTPUTSIGNALS v7
9.6.5 Settings
PID-3892-SETTINGS v7
The function is using phasors of the residual current and voltage. Group signals I3P
and U3P containing phasors of residual current and voltage which are taken from
pre-processor blocks.
The sensitive directional earth fault protection has the following sub-functions
included:
φ is defined as the angle between the residual current 3I0 and the reference voltage
(|φ=ang(3I0)-ang(Uref)|). The reference voltage (Uref) is the polarizing quantity
which is used for directionality and is defined as Uref = -3U0 e—jRCADir, that is
-3U0 inversely rotated by the set characteristic angle RCADir. RCADir is normally
set equal to 0 in a high impedance earthed network with a neutral point resistor as
the active current component is appearing out on the faulted feeder only. RCADir is
set equal to -90° in an isolated network as all currents are mainly capacitive. The
function operates when 3I0·cos φ gets larger than the set value.
3I0
j = ang(3I0 ) - ang(3Uref )
-3U0 = Uref
3I0 × cosj
IEC06000648-4-en.vsd
IEC06000648 V4 EN-US
Uref
RCADir = −90 , ROADir = 90
3I0
3I0 ⋅ cos ϕ
−3U0
IEC06000649_3_en.vsd
IEC06000649 V3 EN-US
For trip, the operating quantity 3I0 cos φ, the residual current 3I0, and the residual
voltage 3U0 must be larger than the set levels : INCosPhi>, INRel> and UNRel>.
Refer to the simplified logical diagram in Figure 305.
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function picks up, binary output signals START and STDIRIN are
activated. If the output signals START and STDIRIN remain active for the set
delay tDef the binary output signals TRIP and TRDIRIN get activated. The trip
from this sub-function has definite time delay.
RCADir = 0o
3I0
Operate area
j
-3U0 = Uref
3I0 × cos j
ROADir
IEC06000650_2_en.vsd
IEC06000650 V2 EN-US
RCADir = 0º
Operate area
-3U0 =Uref
Instrument
transformer
angle error
RCAcomp
Characteristic after
angle compensation
IEC06000651-3-en.vsd
IEC06000651 V3 EN-US
φ is defined as the angle between the residual current 3I0 and the reference voltage
(Uref = -3U0 e-jRCA) compensated with the set characteristic angle RCADir (|
φ=ang(3I0)—ang(Uref)|). The function operates when 3I0 · 3U0 · cos φ gets larger
than the set value SN>. Refer to the simplified logical diagram in Figure 305.
For trip, the residual power 3I0 · 3U0 · cos φ, the residual current 3I0 and the
release voltage 3U0, shall be larger than the set levels (SN>, INRel> and UNRel>).
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function picks up, binary output signals START and STDIRIN are
activated. If the output signals START and STDIRIN remain active for the set
delay tDef or after the inverse time delay (setting kSN) the binary output signals
TRIP and TRDIRIN get activated.
The function shall indicate forward/reverse direction to the fault. Reverse direction
is defined as 3I0 · 3U0·cos (φ + 180°) ³ the set value.
This variant has the possibility of choice between definite time delay and inverse
time delay.
The function will operate if the residual current is larger than the set value and the
angle |φ = ang(3I0)-ang(Uref)| is within the sector RCADir ± ROADir
RCADir = 0º
ROADir = 80º
Operate area
3I0
-3U0
IEC06000652-3-en.vsd
IEC06000652 V3 EN-US
For trip, Residual current 3I0 shall be larger than both INRel> and INDir>, and
residual voltage 3U0 shall be larger than the UNRel>. In addition, the angle φ shall
be in the set area defined by ROADir and RCADir. Refer to the simplified logical
diagram in Figure 305.
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function picks up, binary output signals START and STDIRIN are
activated. If the output signals START and STDIRIN remain active for the set
delay tDef the binary output signals TRIP and TRDIRIN get activated.
For all the directional functions there are directional start signals STFW: fault in
the forward direction, and STRV: fault in the reverse direction. Even if the
directional function is set to operate for faults in the forward direction, a fault in the
reverse direction will give the start signal STRV. Also if the directional function is
set to operate for faults in the reverse direction, a fault in the forward direction will
give the start signal STFW.
This function will measure the residual current without checking the phase angle.
The function will be used to detect cross-country faults. This function can serve as
alternative or backup to distance protection with phase preference logic. To assure
selectivity the distance protection can block the non-directional earth fault current
function via the input BLKNDN.
This variant has the possibility of choice between definite time delay and inverse
time delay (TimeChar parameter). The inverse time delay shall be according to IEC
60255-3.
For trip, the residual current 3I0 shall be larger than the set level (INNonDir>).
Trip from this function can be blocked from the binary input BLKNDN.
When the function picks up, binary output signal STNDIN is activated. If the
output signal STNDIN remains active for the set delay tINNonDir or after the
inverse time delay the binary output signals TRIP and TRNDIN get activated.
All the directional functions shall be released when the residual voltage gets higher
than a set level UNRel>.
For trip, the residual voltage 3U0 shall be larger than the set level (UN>).
Trip from this function can be blocked from the binary input BLKUN.
When the function picks up, binary output signal STUN is activated. If the output
signal STUN is active for the set delay tUNNonDir, the binary output signals TRIP
and TRUN get activated. A simplified logical diagram of the total function is
shown in Figure 305.
OpINNonDir> = On
STNDIN
&
INNonDir>
t
TRNDIN
TimeChar IN
OpUN> = On
STUN
&
UN>
tUN TRUN
t
OpMode = 3I0Cosfi
INRel>
tDef ³ TRDIRIN
t 1
OpMode = 3I03U0Cosfi
& &
SN>
t
³ S
1 N
STFW
RCADir Direction &
Detection
RCAComp Logic STRV
&
ROADir
DirMode = Forward
DirMode = Reverse
IEC06000653.vsd
IEC06000653 V4 EN-US
Figure 305: Simplified logical diagram of the sensitive earth fault current protection
SEMOD173350-2 v16
Inverse characteristics, see table 1133, 16 curve types See Table 1133,
Table 1134 and Table 1135 Table 1134 and Table
1135
Relay characteristic angle (RCADir) (-179 to 180) degrees ±2.0 degrees
Relay operate angle (ROADir) (0 to 90) degrees ±2.0 degrees
9.7.1 Identification
M17106-1 v7
The increasing utilization of the power system closer to the thermal limits has
generated a need of a thermal overload protection for power lines.
A thermal overload will often not be detected by other protection functions and the
introduction of the thermal overload protection can allow the protected circuit to
operate closer to the thermal limits.
The three-phase current measuring protection has an I2t characteristic with settable
time constant and a thermal memory. The temperature is displayed in either Celsius
or Fahrenheit, depending on whether the function used is Thermal overload
protection (LCPTTR) (Celsius) or (LFPTTR) (Fahrenheit).
An alarm level gives early warning to allow operators to take action well before the
line is tripped.
Estimated time to trip before operation, and estimated time to reclose after
operation are presented.
LCPTTR
I3P* TRIP
BLOCK START
BLKTR ALARM
ENMULT LOCKOUT
AMBTEMP
SENSFLT
RESET
IEC13000199-1-en.vsd
IEC13000199 V1 EN-US
LFPTTR
I3P* TRIP
BLOCK START
BLKTR ALARM
ENMULT LOCKOUT
AMBTEMP
SENSFLT
RESET
IEC13000301-1-en.vsd
IEC13000301 V1 EN-US
9.7.4 Signals
PID-3908-INPUTSIGNALS v7
PID-3909-INPUTSIGNALS v9
PID-3908-OUTPUTSIGNALS v7
PID-3909-OUTPUTSIGNALS v8
9.7.5 Settings
PID-3908-SETTINGS v7
PID-3909-SETTINGS v8
PID-3909-MONITOREDDATA v7
The sampled analog phase currents are pre-processed and for each phase current
the RMS value is derived. These phase current values are fed to the thermal
overload protection, one time constant LCPTTR/LFPTTR function. The
temperature is displayed either in Celsius or Fahrenheit, depending on whether
LCPTTR/LFPTTR function is selected.
2
æ I ö
Q final =ç ÷÷ × Tref
ç I ref
è ø
EQUATION1167 V1 EN-US (Equation 146)
where:
I is the largest phase current,
Iref is a given reference current and
æ Dt
ö
Qn = Qn -1 + ( Q final - Q n-1 ) × ç1 - e t ÷
-
è ø
EQUATION1168 V1 EN-US (Equation 147)
where:
Qn is the calculated present temperature,
When the component temperature reaches the set alarm level AlarmTemp the
output signal ALARM is set. When the component temperature reaches the set trip
level TripTemp the output signal TRIP is set.
There is also a calculation of the present time to operate with the present current.
This calculation is only performed if the final temperature is calculated to be above
the operation temperature:
æQ - Qoperate ö
toperate = -t × ln ç final
ç Q final - Q n ÷÷
è ø
EQUATION1169 V1 EN-US (Equation 148)
After a trip, caused by the thermal overload protection, there can be a lockout to
reconnect the tripped circuit. The output lockout signal LOCKOUT is activated
when the device temperature is above the set lockout release temperature setting
ReclTemp.
The time to lockout release is calculated by the following cooling time calculation.
The thermal content of the function can be reset with input RESET.
æQ - Qlockout _ release ö
tlockout _ release = -t × ln ç final ÷÷
ç Q final - Q n
è ø
EQUATION1170 V1 EN-US (Equation 149)
In the above equation, the final temperature is equal to the set or measured ambient
temperature. The calculated time to reset of lockout is available as a real figure
signal, TENRECL. This signal is enabled when the LOCKOUT output is activated.
In some applications the measured current can involve a number of parallel lines.
This is often used where one bay connects several parallel cables. By setting the
parameter IMult to the number of parallel lines (cables) the actual current on one
line is used in the protection algorithm by dividing the measured current by the
total number of cables. To activate this option the input ENMULT must be
activated.
The protection has a reset input: RESET. By activating this input the calculated
temperature is reset to its default initial value. This is useful during testing when
secondary injected current has given a calculated “false” temperature level.
START
Final Temp > Trip Temp
TEMP
Calculation of actual
temperature
AMBTEMP ALARM
Actual Temp > Alarm Temp
I3P
Calculation of final
temperature
ENMULT
TRIP
LOCKOUT
Lockout logic
TTRIP
Calculation of time to trip
BLKTR
TENRECL
Calculation of time to reset
of lockout
IEC09000637-2-en.vsd
IEC09000637 V2 EN-US
9.8.1 Identification
M14877-1 v2
SYMBOL-A V1 EN-US
The thermal overload protection estimates the internal heat content of the
transformer (temperature) continuously. This estimation is made by using a thermal
model of the transformer with two time constants, which is based on current
measurement.
Two warning levels are available. This enables actions in the power system to be
done before dangerous temperatures are reached. If the temperature continues to
increase to the trip value, the protection initiates a trip of the protected transformer.
TRPTTR
I3P* TRIP
BLOCK START
COOLING ALARM1
ENMULT ALARM2
RESET LOCKOUT
WARNING
IEC06000272_2_en.vsd
IEC06000272 V2 EN-US
9.8.4 Signals
PID-4148-INPUTSIGNALS v4
PID-4148-OUTPUTSIGNALS v4
9.8.5 Settings
PID-4148-SETTINGS v4
The sampled analog phase currents are pre-processed and for each phase current
the true RMS value of each phase current is derived. These phase current values
are fed to the protection function.
From the largest of the three phase currents a relative final temperature (heat
content) is calculated according to the expression:
2
æ I ö
Q final =ç ÷÷
ç I ref
è ø
EQUATION1171 V1 EN-US (Equation 151)
where:
I is the largest phase current
Iref is a given reference current
If this calculated relative temperature is larger than the relative temperature level
corresponding to the set operate (trip) current, then the start output signal START
will be activated.
If Q final > Q n
EQUATION1172 V1 EN-US (Equation 152)
æ Dt
ö
Qn = Qn -1 + ( Q final - Q n-1 ) × ç1 - e t ÷
-
è ø
EQUATION1173 V1 EN-US (Equation 153)
If Q final < Qn
EQUATION1174 V1 EN-US (Equation 154)
Dt
Qn = Q final - ( Q final - Qn -1 ) × e
-
t
where:
Qn is the calculated present temperature
Qfinal is the calculated final (steady state) temperature with the actual current
Dt is the time step between calculation of the actual and final temperature
t is the thermal time constant of the protected circuit given in minutes. There are
different time constants depending on the cooling used. Please refer to
manufacturer's manuals for details
When the transformer temperature reaches any of the set alarm levels Alarm1 or
Alarm2 the corresponding output signal ALARM1 or ALARM2 is activated. When
the temperature of the object reaches the set trip level which corresponds to
continuous current equal to ITrip the output signal TRIP is activated.
There is also a calculation of the time to operation with the present current. This
calculation is only performed if the final temperature is calculated to be above the
operation temperature:
æQ - Qoperate ö
toperate = -t × ln ç final
ç Q final - Q n ÷÷
è ø
EQUATION1176 V1 EN-US (Equation 156)
The calculated time to trip can be monitored and it is exported from the function as
an integer output TTRIP.
After a trip there can be a lockout to inhibit reconnecting the tripped circuit. The
output lockout signal LOCKOUT is activated when the temperature of the object is
above the set lockout release temperature setting ResLo.
The time to lockout release is calculated by the following cooling time calculation.
æQ - Qlockout _ release ö
tlockout _ release = -t × ln ç final ÷÷
ç Q final - Q n
è ø
EQUATION1177 V1 EN-US (Equation 157)
When the current is so high that it has given a start signal START, the estimated
time to trip is continuously calculated and given as analogue output TTRIP. If this
calculated time get less than the setting time Warning, set in minutes, the output
WARNING is activated.
RESET HEATCONT
Calculation
of heat
content
I3P
Calculation
ENMULT of final
temperature
ALARM1
Actual Temp >
Alarm1,Alarm2
ALARM2
Temp
S LOCKOUT
Management of R
COOLING setting
parameters: Tau,
Actual Temp
IBase Tau used
< Recl
Temp
TTRIP
Calculation
of time to
WARNING
trip
Calculation
of time to TRESCAL
reset of
lockout
IEC05000833-2-en.vsd
IEC05000833 V2 EN-US
M13266-2 v8
Reset level temperature (10–95)% of heat content trip ±2.0% of heat content trip
9.9.1 Identification
M14878-1 v5
SYMBOL-U V1 EN-US
A current check with extremely short reset time is used as check criterion to
achieve high security against unwanted operation.
Contact check criteria can be used where the fault current through the breaker is
small.
CCRBRF can be single- or three-phase initiated to allow use with single phase
tripping applications. For the three-phase version of CCRBRF the current criteria
can be set to operate only if two out of four for example, two phases or one phase
plus the residual current start. This gives a higher security to the back-up trip
command.
CCRBRF
I3P* TRBU
BLOCK TRBU2
START TRRET
STL1 TRRETL1
STL2 TRRETL2
STL3 TRRETL3
CBCLDL1 CBALARM
CBCLDL2
CBCLDL3
CBFLT
IEC06000188-2-en.vsd
IEC06000188 V2 EN-US
9.9.4 Signals
PID-3562-INPUTSIGNALS v7
PID-3562-OUTPUTSIGNALS v7
9.9.5 Settings
PID-3562-SETTINGS v7
Breaker failure protection CCRBRF is initiated from the protection trip command,
either from protection functions within the IED or from external protection devices.
The start signal can be phase selective or general (for all three phases). Phase
selective start signals enable single pole re-trip function. This means that a second
attempt to open the breaker is done. The re-trip attempt is made after a set time
delay t1. For transmission lines, single pole trip and autoreclosing is often used.
The re-trip function can be phase selective if it is initiated from phase selective line
protection. The re-trip function can be done with or without current check. With the
current check, the re-trip is only performed if the current through the circuit
breaker is larger than the operate current level.
The re-trip function can be done with or without CB position check according to
table 337.
The start signal can be an internal or external protection trip signal. This signal will
start the back-up trip timer. The function detects the successful breaker opening,
either by detection of low current through RMS evaluation and a special adapted
current algorithm or by open contact indication. The special algorithm enables a
very fast detection of successful breaker opening, that is, fast resetting of the
current measurement. If the current and/or contact detection has not detected
breaker opening before the back-up timer has run its time a back-up trip is initiated.
• The minimum length of the re-trip pulse, the back-up trip pulse and the back-
up trip pulse 2 are settable. The re-trip pulse, the back-up trip pulse and the
back-up trip pulse 2 will however sustain as long as there is an indication of
closed breaker.
• In the current detection it is possible to use three different options: 1 out of 3
where it is sufficient to detect failure to open (high current) in one pole, 1 out
of 4 where it is sufficient to detect failure to open (high current) in one pole or
high residual current and 2 out of 4 where at least two current (phase current
and/or residual current) shall be high for breaker failure detection.
• The current detection level for the residual current can be set different from the
setting of phase current detection.
• It is possible to have different back-up time delays for single-phase faults and
for multi-phase faults.
• The back-up trip can be made without current check. It is possible to have this
option activated for small load currents only.
• It is possible to have instantaneous back-up trip function if a signal is high if
the circuit breaker is incapable to clear faults, for example at low gas pressure.
30 ms
START
STL1 OR BFP Started L1
150 ms
AND S
SR Q t
R
BLOCK
OR Retrip Time Out L1 AND
Time out L1
Reset L1
BackupTrip L1
IEC09000976-2-en.vsd
IEC09000976 V2 EN-US
IP>
a
a>b
b
FunctionMode Current
OR AND Reset L1
OR
a AND AND
a>b OR AND
I>BlkCont b
IEC09000977-2-en.vsd
IEC09000977 V2 EN-US
t1 TRRETL3
BFP Started L1 From other
t Retrip Time Out L1
phases TRRETL2 OR
TRRET
tPulse
RetripMode No CBPos Check AND
OR TRRETL1
OR
1 30ms
OR
CB Pos Check
AND
CB Closed L1
CBFLT
IEC09000978-4-en.vsd
IEC09000978 V4 EN-US
BUTripMode
1 out of 3
2 out of 4
OR
1 1 out of 4 AND
Current high L1
BFP Started L1
AND
IN
a
a>b
IN> b
Contact Closed L1
OR
OR
Current High L2
From other AND Backup Time Out L1
Current High L3
phases
Current High L1
CBFLT
AND
t2
30ms Backup Trip L1
BFP Started L1 t AND
OR
t2MPh
AND t
AND
OR OR
tPulse
From other Backup Trip L2 OR TRBU
OR
phases Backup Trip L3
From other BFP Started L2 AND
phases OR tPulse
BFP Started L3
t3
OR
TRBU2
S Q
SR
t
AND R
IEC09000979-4-en.vsd
IEC09000979 V4 EN-US
Figure 314: Simplified logic scheme of the back-up trip logic function
The internal logical signals Current High L1, Current High L2, Current High L3
have logical value 1 when the current in the respective phase has the magnitude
larger than the setting parameter IP>.
M12353-1 v14
Additional time delay for a second back-up trip at (0.000-60.000) s ±0.2% or ±20 ms
0 to 2 x Iset whichever is greater
Time delay for alarm for faulty circuit breaker (0.000-60.000) s ±0.2% or ±15 ms
whichever is greater
9.10.1 Identification
M17108-1 v2
3I>STUB
SYMBOL-T V1 EN-US
When a power line is taken out of service for maintenance and the line
disconnector is opened in multi-breaker arrangements the voltage transformers will
mostly be outside on the disconnected part. The primary line distance protection
will thus not be able to operate and must be blocked.
The stub protection (STBPTOC) covers the zone between the current transformers
and the open disconnector. The three-phase instantaneous overcurrent function is
released from a normally open, NO (b) auxiliary contact on the line disconnector.
STBPTOC
I3P* TRIP
BLOCK START
BLKTR
RELEASE
IEC05000678-2-en.vsd
IEC05000678 V2 EN-US
9.10.4 Signals
PID-6931-INPUTSIGNALS v1
PID-6931-OUTPUTSIGNALS v1
9.10.5 Settings
PID-6931-SETTINGS v1
The sampled analog phase currents are pre-processed in a discrete Fourier filter
(DFT) block. From the fundamental frequency components of each phase current
the RMS value of each phase current is derived. These phase current values are fed
to a comparator in the stub protection function STBPTOC. In a comparator the
RMS values are compared to the set operating current value of the function I>.
If a phase current is larger than the set operating current the signal from the
comparator for this phase is activated. This signal will, in combination with the
release signal from line disconnection (RELEASE input), activate the timer for the
TRIP signal. If the fault current remains during the timer delay t, the TRIP output
signal is activated. The function can be blocked by activation of the BLOCK input.
BLOCK
TRIP
STIL1 AND
STIL2 OR
STIL3
RELEASE
en05000731.vsd
IEC05000731 V1 EN-US
9.11.1 Identification
M14888-1 v4
PD
SYMBOL-S V1 EN-US
An open phase can cause negative and zero sequence currents which cause thermal
stress on rotating machines and can cause unwanted operation of zero sequence or
negative sequence current functions.
Normally the own breaker is tripped to correct such a situation. If the situation
persists the surrounding breakers should be tripped to clear the unsymmetrical load
situation.
CCPDSC
I3P* TRIP
BLOCK START
BLKDBYAR
CLOSECMD
OPENCMD
EXTPDIND
POLE1OPN
POLE1CL
POLE2OPN
POLE2CL
POLE3OPN
POLE3CL
IEC13000305-1-en.vsd
IEC13000305 V1 EN-US
9.11.4 Signals
PID-3525-INPUTSIGNALS v8
PID-3525-OUTPUTSIGNALS v8
9.11.5 Settings
PID-3525-SETTINGS v8
The detection of pole discordance can be made in two different ways. If the contact
based function is used an external logic can be made by connecting the auxiliary
contacts of the circuit breaker so that a pole discordance is indicated, see figure
318.
circuit breaker
en05000287.vsd
IEC05000287 V2 EN-US
This binary signal is connected to a binary input of the IED. The appearance of this
signal will start a timer that will give a trip signal after the set time delay.
There is also a possibility to connect all phase selective auxiliary contacts (phase
contact open and phase contact closed) to binary inputs of the IED, see figure 319.
C.B.
+
poleOneOpened from C.B.
en05000288.vsd
IEC05000288 V1 EN-US
In this case the logic is realized within the function. If the inputs are indicating pole
discordance the trip timer is started. This timer will give a trip signal after the set
delay.
The function also has a binary input that can be configured from the autoreclosing
function, so that the pole discordance function can be blocked during sequences
with a single pole open if single pole autoreclosing is used.
M13946-3 v7
The simplified block diagram of the current and contact based Pole discordance
protection function CCPDSC is shown in figure 320.
BLOCK
OR
BLKDBYAR
PolPosAuxCont
AND
POLE1OPN
POLE1CL
POLE2OPN
Discordance
POLE2CL
detection
POLE3OPN
POLE3CL t 150 ms
t TRIP
AND
OR
PD Signal from CB
AND
EXTPDIND
CLOSECMD t+200 ms
OR
OPENCMD
AND
Unsymmetry current
detection
en05000747.vsd
IEC05000747 V1 EN-US
• The IED is in TEST mode and CCPDSC has been blocked from the local HMI
• The input signal BLOCK is high
• The input signal BLKDBYAR is high
The BLOCK signal is a general purpose blocking signal of the pole discordance
protection. It can be connected to a binary input in the IED in order to receive a
block command from external devices or can be software connected to other
internal functions in the IED itself in order to receive a block command from
internal functions. Through OR gate it can be connected to both binary inputs and
internal function outputs.
The BLKDBYAR signal blocks the pole discordance operation when a single phase
autoreclosing cycle is in progress. It can be connected to the output signal 1PT1 on
SMBRRECfunction block. If the autoreclosing function is an external device, then
BLKDBYAR has to be connected to a binary input in the IED and this binary input
If the pole discordance protection is enabled, then two different criteria can
generate a trip signal TRIP:
If one or two poles of the circuit breaker have failed to open or to close the pole
discordance status, then the function input EXTPDIND is activated from the pole
discordance signal derived from the circuit breaker auxiliary contacts (one NO
contact for each phase connected in parallel, and in series with one NC contact for
each phase connected in parallel) and, after a settable time interval tTrip (0-60 s), a
150 ms trip pulse command TRIP is generated by the Polediscordance function.
• any phase current is lower than CurrUnsymLevel of the highest current in the
three phases.
• the highest phase current is greater than CurrRelLevel of IBase.
If these conditions are true, an unsymmetrical condition is detected and the internal
signal INPS is turned high. This detection is enabled to generate a trip after a set
time delay tTrip if the detection occurs in the next 200 ms after the circuit breaker
has received a command to open trip or close and if the unbalance persists. The 200
ms limitation is for avoiding unwanted operation during unsymmetrical load
conditions.
The pole discordance protection is informed that a trip or close command has been
given to the circuit breaker through the inputs CLOSECMD (for closing command
information) and OPENCMD (for opening command information). These inputs
can be connected to terminal binary inputs if the information are generated from
the field (that is from auxiliary contacts of the close and open push buttons) or may
be software connected to the outputs of other integrated functions (that is close
command from a control function or a general trip from integrated protections).
9.12.1 Identification
SEMOD158941-2 v4
Sometimes, the mechanical power from a prime mover may decrease so much that
it does not cover bearing losses and ventilation losses. Then, the synchronous
generator becomes a synchronous motor and starts to take electric power from the
rest of the power system. This operating state, where individual synchronous
machines operate as motors, implies no risk for the machine itself. If the generator
under consideration is very large and if it consumes lots of electric power, it may
be desirable to disconnect it to ease the task for the rest of the power system.
Often, the motoring condition may imply that the turbine is in a very dangerous
state. The task of the low forward power protection is to protect the turbine and not
to protect the generator itself.
Figure 321 illustrates the low forward power and reverse power protection with
underpower and overpower functions respectively. The underpower IED gives a
higher margin and should provide better dependability. On the other hand, the risk
for unwanted operation immediately after synchronization may be higher. One
should set the underpower IED to trip if the active power from the generator is less
than about 2%. One should set the overpower IED to trip if the power flow from
the network to the generator is higher than 1% depending on the type of turbine.
When IED with a metering class input CTs is used pickup can be set to more
sensitive value (e.g.0,5% or even to 0,2%).
Operate
Q Q
Operate
Line Line
Margin Margin
P P
IEC06000315-2-en.vsd
IEC06000315 V2 EN-US
GUPPDUP
I3P* TRIP
U3P* TRIP1
BLOCK TRIP2
BLOCK1 START
BLOCK2 START1
START2
P
PPERCENT
Q
QPERCENT
IEC07000027-2-en.vsd
IEC07000027 V2 EN-US
9.12.4 Signals
PID-3709-INPUTSIGNALS v6
PID-3709-OUTPUTSIGNALS v6
9.12.5 Settings
PID-3709-SETTINGS v6
Chosen current
phasors P
P = POWRE
Q = POWIM
IEC09000018-2-en.vsd
IEC09000018 V2 EN-US
The function will use voltage and current phasors calculated in the pre-processing
blocks. The apparent complex power is calculated according to chosen formula as
shown in table 358.
The active and reactive power is available from the function and can be used for
monitoring and fault recording.
low, normally down to 0.02 p.u. of rated generator power. The hysteresis should
therefore be set to a smaller value. The drop-power value of stage1 can be
calculated with the Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2) +
Hysteresis1(2)
For small power1 values the hysteresis1 may not be too big, because the drop-
power1(2) would be too small. In such cases, the hysteresis1 greater than (0.5 ·
Power1(2)) is corrected to the minimal value.
If the measured power drops under the drop-power1(2) value, the function will
reset after a set time DropDelay1(2). The reset means that the start signal will drop
out and that the timer of the stage will reset.
S = k × SOld + (1 - k ) × SCalculated
EQUATION1959 V1 EN-US (Equation 168)
Where
S is a new measured value to be used for the protection function
Sold is the measured value given from the function in previous execution cycle
k is settable parameter by the end user which influence the filter properties
TD
Default value for parameter k is 0.00. With this value the new calculated value is
immediately given out without any filtering (that is without any additional delay).
When k is set to value bigger than 0, the filtering is enabled. A typical value for
k=0.92 in case of slow operating functions.
Measured currents and voltages used in the Power function can be calibrated to get
class 0.5 measuring accuracy. This is achieved by amplitude and angle
compensation at 5, 30 and 100% of rated current and voltage. The compensation
below 5% and above 100% is constant and linear in between, see example in figure
324.
IEC05000652 V2 EN-US
The first current and voltage phase in the group signals will be used as reference
and the amplitude and angle compensation will be used for related input signals.
Analog outputs (Monitored data) from the function can be used for service values
or in the disturbance report. The active power is provided as MW value: P, or in
percent of base power: PPERCENT. The reactive power is provided as Mvar value:
Q, or in percent of base power: QPERCENT.
SEMOD175152-2 v11
S r = 1.732 × U r × I r
9.13.1 Identification
SEMOD176574-2 v4
Sometimes, the mechanical power from a prime mover may decrease so much that
it does not cover bearing losses and ventilation losses. Then, the synchronous
generator becomes a synchronous motor and starts to take electric power from the
rest of the power system. This operating state, where individual synchronous
machines operate as motors, implies no risk for the machine itself. If the generator
under consideration is very large and if it consumes lots of electric power, it may
be desirable to disconnect it to ease the task for the rest of the power system.
Often, the motoring condition may imply that the turbine is in a very dangerous
state. The task of the reverse power protection is to protect the turbine and not to
protect the generator itself.
Figure 325 illustrates the low forward power and reverse power protection with
underpower and overpower functions respectively. The underpower IED gives a
higher margin and should provide better dependability. On the other hand, the risk
for unwanted operation immediately after synchronization may be higher. One
should set the underpower IED to trip if the active power from the generator is less
than about 2%. One should set the overpower IED to trip if the power flow from
the network to the generator is higher than 1%.
When IED with a metering class input CTs is used pickup can be set to more
sensitive value (e.g.0,5% or even to 0,2%).
Operate
Q Q
Operate
Line Line
Margin Margin
P P
IEC06000315-2-en.vsd
IEC06000315 V2 EN-US
Figure 325: Reverse power protection with underpower IED and overpower
IED
GOPPDOP
I3P* TRIP
U3P* TRIP1
BLOCK TRIP2
BLOCK1 START
BLOCK2 START1
START2
P
PPERCENT
Q
QPERCENT
IEC07000028-2-en.vsd
IEC07000028 V2 EN-US
9.13.4 Signals
PID-3710-INPUTSIGNALS v7
PID-3710-OUTPUTSIGNALS v7
9.13.5 Settings
PID-3710-SETTINGS v7
Chosen current
phasors P
P = POWRE
Q = POWIM
IEC06000567-2-en.vsd
IEC06000567 V2 EN-US
The function will use voltage and current phasors calculated in the pre-processing
blocks. The apparent complex power is calculated according to chosen formula as
shown in table 366.
The active and reactive power is available from the function and can be used for
monitoring and fault recording.
For small power1 values the hysteresis1 may not be too big, because the drop-
power1(2) would be too small. In such cases, the hysteresis1 greater than (0.5 ·
Power1(2)) is corrected to the minimal value.
If the measured power drops under the drop-power1(2) value the function will reset
after a set time DropDelay1(2). The reset means that the start signal will drop out
ant that the timer of the stage will reset.
S = k × SOld + (1 - k ) × SCalculated
EQUATION1959 V1 EN-US (Equation 178)
Where
S is a new measured value to be used for the protection function
Sold is the measured value given from the function in previous execution cycle
k is settable parameter by the end user which influence the filter properties
Default value for parameter k is 0.00. With this value the new calculated value is
immediately given out without any filtering (that is, without any additional delay).
When k is set to value bigger than 0, the filtering is enabled. A typical value for k =
0.92 in case of slow operating functions.
Measured currents and voltages used in the Power function can be calibrated to get
class 0.5 measuring accuracy. This is achieved by amplitude and angle
compensation at 5, 30 and 100% of rated current and voltage. The compensation
below 5% and above 100% is constant and linear in between, see example in figure
328.
IEC05000652 V2 EN-US
The first current and voltage phase in the group signals will be used as reference
and the amplitude and angle compensation will be used for related input signals.
Analog outputs from the function can be used for service values or in the
disturbance report. The active power is provided as MW value: P, or in percent of
base power: PPERCENT. The reactive power is provided as Mvar value: Q, or in
percent of base power: QPERCENT.
SEMOD175159-2 v9
9.14.1 Identification
SEMOD172362-2 v2
BRCPTOC
I3P* TRIP
BLOCK START
BLKTR
IEC07000034-2-en.vsd
IEC07000034 V2 EN-US
9.14.4 Signals
PID-3479-INPUTSIGNALS v6
PID-3479-OUTPUTSIGNALS v7
9.14.5 Settings
PID-3479-SETTINGS v7
• The difference in currents between the phase with the lowest current and the
phase with the highest current is greater than set percentage Iub> of the
highest phase current
• The highest phase current is greater than the minimum setting value IP>.
• The lowest phase current is below 50% of the minimum setting value IP>
The simplified logic diagram of the broken conductor check function is shown in
figure 330
• The IED is in TEST status and the function has been blocked from the local
HMI test menu (BlockBRC=Yes).
• The input signal BLOCK is high.
The BLOCK input can be connected to a binary input of the IED in order to receive
a block command from external devices, or can be software connected to other
internal functions of the IED itself to receive a block command from internal
functions.
The output trip signal TRIP is a three-phase trip. It can be used to command a trip
to the circuit breaker or for alarm purpose only.
TEST
TEST-ACTIVE
and
Block BRCPTOC=Yes
START
Function Enable
BLOCK or
tOper
TRIP
and t
Unsymmetrical
Current Detection
STI
IL1<50%IP>
IL2<50%IP> or
IL3<50%IP>
IEC09000158-3-en.vsd
IEC09000158 V3 EN-US
Figure 330: Simplified logic diagram for Broken conductor check BRCPTOC
SEMOD175200-2 v7
9.15.1 Identification
GUID-67FC8DBF-4391-4562-A630-3F244CBB4A33 v2
Shunt Capacitor Banks (SCB) are used in a power system to provide reactive
power compensation and power factor correction. They are as well used as integral
parts of Static Var Compensators (SVC) or Harmonic Filters installations.
Capacitor bank protection (CBPGAPC) function is specially designed to provide
protection and supervision features for SCBs.
CBPGAPC
I3P* TRIP
BLOCK TROC
BLKTR TRUC
BLKOC TRQOL
BLKUC TRHOL
BLKUCCUT START
BLKQOL STOC
BLKHOL STUC
STQOL
STHOL
STOCL1
STOCL2
STOCL3
STUCL1
STUCL2
STUCL3
STQOLL1
STQOLL2
STQOLL3
STHDTL1
STHDTL2
STHDTL3
STHIDML1
STHIDML2
STHIDML3
RECNINH
IEC14000046-1-en.vsd
IEC08000500 V2 EN-US
9.15.4 Signals
PID-3580-INPUTSIGNALS v5
PID-3580-OUTPUTSIGNALS v5
9.15.5 Settings
PID-3580-SETTINGS v5
Three-phase input current from the SCB is connected via the preprocessing block
to CBPGAPC function. From this preprocessing block CBPGAPC function obtains
the following quantities for every phase:
• Current sample values with sampling rate of 1 kHz in 50 Hz power system and
1.2 kHz in 60 Hz power system (that is, 20 samples in fundamental power
system cycle). These samples correspond to the instantaneous current
waveform of the protected SCB and in further text will be marked with symbol
“i~”
• Equivalent RMS current value based on Peak Current measurement. This
value is obtained as maximum absolute current sample value over last power
system cycle divided by √2 and in further text will be marked with symbol
“IpeakRMS”
• Equivalent true RMS current value based on the following formula:
åi 2
~m
I TRMS = m =1
N
EQUATION2232 V1 EN-US (Equation 179)
where N is used number of samples in one power system cycle (that is, 20) and i~m
are last N samples of the current waveform. In further text this equivalent true rms
current quantity will be marked with symbol ITRMS.
Note that the measured IpeakRMS value is available as a service value in primary
amperes for every phase from the function.
From the measured SCB currents, voltage value across every SCB phase is
calculated. This is done by continuous integration of the measured current
waveform by using the following principal equation:
1
u (t ) = × i ( t ) × ¶t
ò
C
EQUATION2233 V1 EN-US (Equation 180)
Where:
u(t) is voltage waveform across capacitor
i(t) is capacitor current waveform
C is capacitance in Farads
• Voltage sample values with rate of 1 kHz in 50 Hz power system and 1.2 kHz
in 60 Hz power system (that is, 20 samples in fundamental power system
cycle). These samples correspond to the instantaneous voltage waveform
across the protected SCB and in further text will be marked with symbol u~
• Equivalent rms voltage value based on Peak Voltage measurement. This value
is obtained as maximum absolute voltage sample value over last power system
cycle divided by √2 and in further text will be marked with symbol UpeakRMS
• Equivalent true RMS voltage value based on the following formula:
åu 2
~m
U TRMS = m =1
N
EQUATION2234 V1 EN-US (Equation 181)
Where:
N is used number of samples in one power system cycle (for example, 20)
u~m are last N samples of the voltage waveform
In further text this equivalent true RMS voltage quantity will be marked with
symbol UTRMS
1000 × Q [ MVAr ]
IBase =
3 × U [ kV ]
EQUATION2235 V1 EN-US (Equation 182)
Where:
IBase is base current for the function in primary amperes
Q[MVAr] is shunt capacitor bank MVAr rating
U[kV] is shunt capacitor bank rated phase-to-phase voltage in kV
Once the base current is known the internal voltage calculations can be performed.
Note that the calculated UpeakRMS value is available as a service value in percent
for every phase from the function.
Generated reactive power (Q) by the capacitor bank is calculated within the
function for every phase as given by the following equation:
Q =U TRMS ×I TRMS
Where:
Q is generated reactive power in per-unit
UTRMS is capacitor equivalent true RMS voltage in per-unit
Simplified logic diagram about used analog quantities within one phase of the
capacitor bank protection function are shown in figure 332.
Undercurrent
I TRMS[A]
Reconnection Inhibit
IEC09000746-2-en.vsd
IEC09000746 V2 EN-US
Figure 332: Simplified logic diagram about used analog quantities within one
phase
This feature determines that capacitor banks are disconnected from the power
system and is used to prevent reconnection of a charged capacitor bank to a live
network. The IRMS values of the three phase currents are compared with the
IRecnInhibit< parameter in order to determine when the capacitor bank is
energized or disconnected. The simplified logic diagram is shown in fig 333.
currentRMS a 0.02 s
CapBank Energised
a>b t
b
IRecnInhibit<
CAPDISC
Phx
NOT
IEC08000345-1-en.vsd
IEC08000345 V1 EN-US
Figure 333: Capacitor bank energization check for one phase. Similar for all
three phases
When SCB is disconnected in all three phases, the reconnection inhibit signal will
be given. This signal will be active until the preset time elapsed and is used to
inhibit the reconnection of charged capacitor bank to live network. The internal
logic diagram for the inhibit feature is shown in figure 334.
CAPDISC
CAPDISC
_ Ph1
Z-2
en08000346.vsd
IEC08000346 V1 EN-US
The overcurrent protection feature protects the capacitor bank from excessive
current conditions. The sub function takes the current peakRMS value from the
preprocessing block in the IED as input. The peakRMS value of the current is
compared with the setting of parameter IOC>. Whenever the peakRMS value of
the current crosses the set level the function sends a START signal as output. The
signal is passed through the definite timer for giving the TRIP signal. Each phase
will have its own START and TRIP signals for overcurrent. The internal logic for
the overcurrent feature is shown in fig 335.
IPeakRMS a
a>b tOC
IOC> b TROC
AND t AND
OperationOC=On
STOC
BLKTR
BLKOC
BLOCK OR
IEC08000350-1-en.vsd
IEC08000350 V1 EN-US
Undercurrent protection feature is used to disconnect the capacitor bank from the
rest of the power system when the voltage at the capacitor bank terminals is too
low for too long period of time. This sub function uses the current peakRMS value
from the preprocessing block in the IED as input. The peakRMS value of the
current is compared to the set value of the parameter IUC<. Whenever the
peakRMS value of the current falls below the set undercurrent level, the function
will send a START signal as output. The function can be blocked when the current
falls below the cut off level. The capacitor bank disconnected signals are used for
this blocking. This feature will help to prevent trip operation when the capacitor
bank is disconnected from the power system. The TRIP output signal is delayed by
a definite timer. Each phase will have its own START and TRIP signals for
undercurrent. The internal logic for the undercurrent feature is shown in fig 336.
IPeakRMS
a
b>a
IUC< b
tUC
AND t
AND TRUC
OperationUC=On
BLKUC
STUC
BLOCK
OR
CAPDISC
BLKTR
en08000351.vsd
IEC08000351 V1 EN-US
Harmonic overload protection feature will protect the capacitor from over load
conditions caused by harmonics. The sub-function protects the capacitor in two
stages, first stage is Inverse time delay (IDMT) based and a second stage is based
on Definite Time (DT) delay.
IDMT curve has adjustable k factor and inverse time characteristic is shown in
figure 337, where k = 1. The IDMT curve starts only when the equivalent RMS
voltage value is higher than set value of parameter HOLIDMTU> and stays active
until the value falls below the reset value.
2.3
Voltage Peak RMS [pu]
2.1
1.9
1.7
1.5
1.3
1.1
0.1 1 10 100 1000 10000
Operate Time [s]
IEC08000352-1-en.vsd
IEC08000352 V1 EN-US
Main seven operating points for this IDMT curve are defined by IEC/ANSI
standards and they are shown in above figure and summarized in the following
table:
Table 380: Main operating points for IDMT curve
1. When parameter kHOLIDMT has different value from 1.0 operating time is
proportionally changed (for example, when kHOLIDMT =0.9 operating times
will be 90% of the values shown in above figure 337 and table 380)
2. Between the seven main points in table 380, the operate time is calculate by
using linear interpolation in the logarithmic scale
3. Integration process is used to calculate the operate time for varying voltage
condition
4. By setting parameter tMinHOLIDMT =0.1s standard requirements for
minimum operating time of 100ms for harmonic overload IDMT curve can be
fluffed
5. By setting parameter tMaxHOLIDMT =2000s operation for small harmonics
overload condition when UpeakRMS is in-between 1.1pu and 1.2pu is assured
Harmonic overload definite time curve has settings facilities for independent
pickup and time delay. It can be used as separate tripping stage or as an alarm
stage.
Both of these two harmonic overload stages are active during capacitor bank
energizing and are capable to properly measure and operate up to and including 9th
harmonic.
The internal logic for harmonic overload feature is shown in figure 338:
STHDTLx
UPeakRMS [pu]
a
a>b
HOLDTU> b
tHOLDT
t
OperationHOL=On AND
OR TRHOL
AND
BLKHOL
BLOCK
OR OR STHOL
BLKTR
OperationHOL=On AND
TR
UPeakRMS [pu]
a
a>b kHOLIDMT IDMT
HOLIDMTU> b
tMaxHOLIDMT
STHIDMLx
tMinHOLIDMT ST
UPeakRMS [pu]
IEC09000752-1-en.vsd
IEC09000752 V1 EN-US
Reactive power overload protection feature will protect the capacitor bank from
reactive power overload conditions.
The sub-function will use the reactive power values as input. The reactive power
input values are calculated from the true RMS value of voltage and current. The
reactive power value is compared with the QOL> setting. When the reactive power
value exceeds the QOL> setting the STQOL signal will be activated. The start
signal is delayed by the definite timer before activating the TRQOL signal. The
internal logic diagram for this feature is shown in figure 339.
Q [pu]
a
a>b
QOL> b
tQOL
t
OperationQOL=On AND
TRQOL
AND
BLKTR
BLKQOL
STQOL
BLOCK
OR
en08000353.vsd
IEC08000353 V1 EN-US
The negative sequence currents in a generator may, among others, be caused by:
• Unbalanced loads
• Line to line faults
• Line to earth faults
• Broken conductors
• Malfunction of one or more poles of a circuit breaker or a disconnector
NS2PTOC can also be used as a backup protection, that is, to protect the generator
in case line protections or circuit breakers fail to clear unbalanced system faults.
where:
I2 is negative sequence current expressed in per unit of the rated
generator current
t is operating time in seconds
K is a constant which depends of the generators size and design
NS2PTOC has a wide range of K settings and the sensitivity and capability of
detecting and tripping for negative sequence currents down to the continuous
capability of a generator.
In order to match the heating characteristics of the generator a reset time parameter
can be set.
A separate definite time delayed output is available as an alarm feature to warn the
operator of a potentially dangerous situation.
NS2PTOC
I3P* TRIP
BLOCK TR1
BLKST1 TR2
BLKST2 START
BLKTR ST1
ST2
ALARM
NSCURR
IEC08000359.vsdx
IEC08000359-1-EN V3 EN-US
9.16.4 Signals
PID-3854-INPUTSIGNALS v6
PID-3854-OUTPUTSIGNALS v6
9.16.5 Settings
PID-3854-SETTINGS v5
To avoid oscillation in the output signals, a certain hysteresis has been included.
For both steps, the reset ratio is 0.97.
Step 1 of NS2PTOC can operate in the Definite Time (DT) or Inverse Time
(IDMT) mode depending on the selected value for the CurveType1 parameter. If
CurveType1= Definite, NS2PTOC operates with a Definite Time Delay
characteristic and if CurveType1 = Inverse, NS2PTOC operates with an Inverse
Time Delay characteristic. Step 2 is operating in an analogous way as Step 1.
elapsed. Reset time in definite time mode is determined by the setting parameters
tResetDef1 or tResetDef2 respectively. If NS2PTOC has already started but not
tripped and measured negative sequence current drops below the start value, the
start outputs remains active for the time defined by the resetting parameters.
K = I 2 2t
EQUATION2112 V1 EN-US
Where:
I2 is negative sequence current expressed in per unit of the rated generator current
Operate
time
t1Max
(Default= 1000 s)
t1Min
(Default= 5 s)
K1
Current I2-1>
IEC09000691-2-en.vsd
IEC09000691 V2 EN-US
ResetTime [ s ] = ResetMultip
⋅K
I 2
NS − 1
I Start
EQUATION2111 V4 EN-US (Equation 184)
Where
INS is the measured negative sequence current
ResetMultip is multiplier of the generator capability constant K equal to setting K1 and thus
defines reset time of inverse time characteristic
The trip start levels Current I2-1> and I2-2> of NS2PTOC are freely settable over
a range of 3 to 500 % of rated generator current IBase. The wide range of start
setting is required in order to be able to protect generators of different types and
sizes.
After start, a certain hysteresis is used before resetting start levels. For both steps
the reset ratio is 0.97.
The alarm function is operated by START signal and used to warn the operator for
an abnormal situation, for example, when generator continuous negative sequence
current capability is exceeded, thereby allowing corrective action to be taken
before removing the generator from service. A settable time delay tAlarm is
provided for the alarm function to avoid false alarms during short-time unbalanced
conditions.
CurveType1=Definite
AND t1 TR1
OR
Negative sequence current a
a>b
b Inverse
I2-1>
Operation=ON AND
t1Min AND
BLKST1
BLOCK
CurveType1=Inverse
t1Max
AND
ST1
IEC080004661-4-en.vsdx
IEC08000466-1-EN V4 EN-US
Figure 342: Simplified logic diagram for step 1 of Negative sequence time
overcurrent protection for machines (NS2PTOC)
ST1
START
ST2 OR
tAlarm ALARM
TR1
TRIP
TR2 OR
IEC09000690-2-en.vsd
IEC09000690 V2 EN-US
Figure 343: Simplified logic diagram for the START, ALARM and TRIP signals
for NS2PTOC
I 22t = K
Minimum operate time for inverse (0.000-60.000) s ±0.2% or ±35 ms
time characteristic, step 1 - 2 whichever is greater
Maximum trip delay at 0.5 x Iset to 2 (0.00-6000.00) s ±0.2% or ±35 ms
x Iset, step 1 - 2 whichever is greater
The overcurrent protection feature has a settable current level that can be used
either with definite time or inverse time characteristic. Additionally, it can be
voltage controlled/restrained.
One undervoltage step with definite time characteristic is also available within the
function in order to provide functionality for overcurrent protection with
undervoltage seal-in.
VRPVOC
I3P* TRIP
U3P* TROC
BLOCK TRUV
BLKOC START
BLKUV STOC
STUV
IEC12000184-1-en.vsd
IEC12000184 V1 EN-US
9.17.4 Signals
PID-3858-INPUTSIGNALS v7
PID-3858-OUTPUTSIGNALS v8
9.17.5 Settings
PID-3858-SETTINGS v7
GlobalBaseSel defines the particular Global Base Values Group where the base
quantities of the function are set. In that Global Base Values Group:
IBase shall be entered as rated phase current of the protected object in primary
amperes.
The overcurrent step simply compares the magnitude of the measured current
quantity with the set start level. The overcurrent step starts if the magnitude of the
measured current quantity is higher than the set level.
StartCurr
VDepFact * StartCurr
0,25 UHighLimit
UBase
IEC10000123-2-en.vsd
IEC10000123 V2 EN-US
Figure 345: Example for start level of the current variation as function of
measured voltage magnitude in Slope mode of operation
StartCurr
VDepFact * StartCurr
UHighLimit UBase
IEC10000124-2-en.vsd
IEC10000124 V2 EN-US
Figure 346: Example for start level of the current variation as function of
measured voltage magnitude in Step mode of operation
DEF time
selected
TROC
OR
MaxPhCurr
a STOC
a>b
b
StartCurr
X Inverse
Inverse
Voltage time
control or selected
restraint
feature
MinPh-PhVoltage
IEC10000214-1-en.vsd
IEC10000214 V1 EN-US
DEF time
selected TRUV
MinPh-phVoltage a
b>a
b STUV
AND
StartVolt
Operation_UV=On
BLKUV
IEC10000213-1-en.vsd
IEC10000213 V1 EN-US
The undervoltage step simply compares the magnitude of the lowest measured
phase-phase voltage quantity with the set start level. The undervoltage step starts if
the magnitude of the measured voltage quantity is lower than the set level.
The start signal starts a definite time delay. If the value of the start signal is logical
TRUE for longer than the set time delay, the undervoltage step sets its trip signal to
logical TRUE.
This undervoltage functionality together with additional ACT logic can be used to
provide functionality for overcurrent protection with undervoltage seal-in.
Overcurrent: -
Critical impulse time 10 ms typically at 0 to 2 x Iset
Impulse margin time 15 ms typically
Undervoltage: -
Critical impulse time 10ms typically at 2 x Uset to 0
Impulse margin time 15 ms typically
10.1.1 Identification
M16876-1 v7
3U<
V2 EN-US
SYMBOL-R-2U-GREATER-THAN
Undervoltages can occur in the power system during faults or abnormal conditions.
The two-step undervoltage protection function (UV2PTUV) can be used to open
circuit breakers to prepare for system restoration at power outages or as a long-time
delayed back-up to the primary protection.
UV2PTUV has two voltage steps, each with inverse or definite time delay.
It has a high reset ratio to allow settings close to the system service voltage.
UV2PTUV
U3P* TRIP
BLOCK TR1
BLKTR1 TR1L1
BLKST1 TR1L2
BLKTR2 TR1L3
BLKST2 TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
IEC06000276-2-en.vsd
IEC06000276 V2 EN-US
10.1.4 Signals
PID-3586-INPUTSIGNALS v7
PID-3586-OUTPUTSIGNALS v7
10.1.5 Settings
PID-3586-SETTINGS v7
UV2PTUV has two voltage-measuring steps with separate time delays. If the
voltage remains below the set value for the chosen time delay, the corresponding
trip signal is issued. To avoid an unwanted trip due to the disconnection of the
related high-voltage equipment, a voltage-controlled blocking of the function is
available: if the voltage is lower than the set blocking level, the function is blocked
and no START or TRIP signal is generated. The time delay characteristic is
individually chosen for each step and can be either definite time delay or inverse
time delay.
To avoid oscillations of the output START signal, a hysteresis has been included.
UBase(kV )
U (%) ·
3
EQUATION1429 V3 EN-US (Equation 185)
The time delay for the two steps can be either definite time delay (DT) or inverse
time delay (IDMT). For the inverse time delay three different modes are available:
• inverse curve A
• inverse curve B
• customer programmable inverse curve
k
t=
æ Un < -U ö
ç ÷
è Un < ø
EQUATION1431 V2 EN-US (Equation 187)
where:
Un< Set value for step 1 and step 2
U Measured voltage
k × 480
t= 2.0
+ 0.055
æ Un < - U ö
ç 32 × - 0.5 ÷
è Un < ø
EQUATION1432 V2 EN-US (Equation 188)
é ù
ê ú
ê k×A ú
t=ê pú
+D
ê æ Un < - U ö ú
êçB × -C÷ ú
ëè Un < ø û
EQUATION1433 V2 EN-US (Equation 189)
When the denominator in the expression is equal to zero the time delay will be
infinity. There will be an undesired discontinuity. Therefore a tuning parameter
CrvSatn is set to compensate for this phenomenon. In the voltage interval Un<
down to Un< · (1.0 – CrvSatn/100) the used voltage will be: Un< · (1.0 – CrvSatn/
100). If the programmable curve is used this parameter must be calculated so that:
CrvSatn
B× -C > 0
100
EQUATION1435 V1 EN-US (Equation 190)
The lowest voltage is always used for the inverse time delay integration. The
details of the different inverse time characteristics are shown in section "Inverse
characteristics".
Voltage
UL1
UL2
UL3
IDMT Voltage
Time
IEC12000186-1-en.vsd
IEC12000186 V1 EN-US
Figure 350: Voltage used for the inverse time characteristic integration
Trip signal issuing requires that the undervoltage condition continues for at least
the user set time delay. This time delay is set by the parameter t1 and t2 for definite
time mode (DT) and by some special voltage level dependent time curves for the
inverse time mode (IDMT). If the start condition, with respect to the measured
voltage, ceases during the delay time, and is not fulfilled again within a user-
defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and
tIReset2 pickup for the inverse time) the corresponding start output is reset. After
leaving the hysteresis area, the start condition must be fulfilled again and it is not
sufficient for the signal to only return back to the hysteresis area. For the
undervoltage function the IDMT reset time is constant and does not depend on the
voltage fluctuations during the drop-off period. However, there are three ways to
reset the timer: the timer is reset instantaneously, the timer value is frozen during
the reset time, or the timer value is linearly decreased during the reset time. See
figure 351 and figure 352.
tIReset1
Voltage
tIReset1
Measured
START Voltage
HystAbs1
TRIP
U1<
Time
START t
TRIP
Time
Integrator Frozen Timer
Time
Linearly
Instantaneous
decreased IEC05000010-4-en.vsd
IEC05000010 V4 EN-US
Figure 351: Voltage profile not causing a reset of the START signal for step 1, and inverse time delay at
different reset types
tIReset1
Voltage
tIReset1
START
START
HystAbs1 Measured Voltage
TRIP
U1<
Time
START t
TRIP
Time
Integrator Frozen Timer
Time
Instantaneous Linearly decreased
IEC05000011-en-3.vsd
IEC05000011 V3 EN-US
Figure 352: Voltage profile causing a reset of the START signal for step 1, and inverse time delay at
different reset types
When definite time delay is selected the function will operate as shown in figure
353. Detailed information about individual stage reset/operation behavior is shown
in figure 354 and figure 355 respectively. Note that by setting tResetn = 0.0s,
instantaneous reset of the definite time delayed stage is ensured.
ST1
U t1
a tReset1
TR1
t
a<b t
U1< R
b
AND
IEC09000785-3-en.vsd
IEC09000785 V3 EN-US
U1<
ST1
TR1
tReset1
t1
IEC10000039-3-en.vsd
IEC10000039 V3 EN-US
U1<
ST1
TR1
tReset1
t1
IEC10000040-3-en.vsd
IEC10000040 V3 EN-US
If the measured voltage level decreases below the setting of IntBlkStVal1, either the
trip output of step 1, or both the trip and the START outputs of step 1, are blocked.
The characteristic of the blocking is set by the IntBlkSel1 parameter. This internal
blocking can also be set to Off resulting in no voltage based blocking.
Corresponding settings and functionality are valid also for step 2.
In case of disconnection of the high voltage component the measured voltage will
get very low. The event will START both the under voltage function and the
blocking function, as seen in figure 356. The delay of the blocking function must
be set less than the time delay of under voltage function.
U Disconnection
Normal voltage
U1<
U2<
tBlkUV1 <
t1,t1Min
IntBlkStVal1
tBlkUV2 <
t2,t2Min
IntBlkStVal2
Time
Block step 1
Block step 2
en05000466.vsd
IEC05000466 V1 EN-US
Step 1 TR1L2
Time integrator TRIP
MinVoltSelector tIReset1
ResetTypeCrv1 TR1L3
TR1
OR
Comparator ST2L1
UL1 < U2< Voltage Phase Phase 1
Selector
OpMode2 ST2L2
Comparator Phase 2
UL2 < U2< 1 out of 3
2 out of 3 Start t2 ST2L3
3 out of 3 Phase 3 t2Reset
Comparator IntBlkStVal2 &
UL3 < U2< Trip ST2
Output OR
Logic
START TR2L1
Step 2
TR2L2
Time integrator TRIP
MinVoltSelector tIReset2
ResetTypeCrv2 TR2L3
TR2
OR
START
OR
TRIP
OR
IEC05000834-2-en.vsd
IEC05000834 V2 EN-US
M13290-1 v15
10.2.1 Identification
M17002-1 v8
3U>
SYMBOL-C-2U-SMALLER-THAN V2 EN-US
Overvoltages may occur in the power system during abnormal conditions such as
sudden power loss, tap changer regulating failures, and open line ends on long
lines.
Two step overvoltage protection (OV2PTOV) function can be used to detect open
line ends, normally then combined with a directional reactive over-power function
to supervise the system voltage. When triggered, the function will cause an alarm,
switch in reactors, or switch out capacitor banks.
OV2PTOV has two voltage steps, each of them with inverse or definite time
delayed.
OV2PTOV has a high reset ratio to allow settings close to system service voltage.
OV2PTOV
U3P* TRIP
BLOCK TR1
BLKTR1 TR1L1
BLKST1 TR1L2
BLKTR2 TR1L3
BLKST2 TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
IEC06000277-2-en.vsd
IEC06000277 V2 EN-US
10.2.4 Signals
PID-3535-INPUTSIGNALS v7
PID-3535-OUTPUTSIGNALS v7
10.2.5 Settings
PID-3535-SETTINGS v7
Two step overvoltage protection OV2PTOV is used to detect high power system
voltage. OV2PTOV has two steps with separate time delays. If one-, two- or three-
phase voltages increase above the set value, a corresponding START signal is
issued. OV2PTOV can be set to START/TRIP, based on 1 out of 3, 2 out of 3 or 3
out of 3 of the measured voltages, being above the set point. If the voltage remains
above the set value for a time period corresponding to the chosen time delay, the
corresponding trip signal is issued.
The time delay characteristic is individually chosen for the two steps, and can be
either definite time or inverse time delayed.
The voltage related settings are made in percent of the global set base voltage
UBase, which is set in kV, phase-to-phase.
The setting of the analog inputs are given as primary phase-to-earth or phase-to-
phase voltage. OV2PTOV will operate if the voltage gets higher than the set
percentage of the set base voltage UBase. This means operation for phase-to-earth
voltage over:
All the three voltages are measured continuously, and compared with the set
values, U1> for Step 1 and U2> for Step 2. The parameters OpMode1 and
OpMode2 influence the requirements to activate the START outputs. Either 1 out of
3, 2 out of 3 or 3 out of 3 measured voltages have to be higher than the
corresponding set point to issue the corresponding START signal.
The time delay for the two steps can be either definite time delay (DT) or inverse
time delay (IDMT). For the inverse time delay four different modes are available:
• inverse curve A
• inverse curve B
• inverse curve C
• customer programmable inverse curve
k
t=
æ U - Un > ö
ç ÷
è Un > ø
IECEQUATION2422 V1 EN-US (Equation 193)
where:
Un> Set value for step 1 and step 2
U Measured voltage
k 480
t 2.0
0.035
U Un
32 0.5
Un
k × 480
t= 3.0
+ 0.035
æ U - Un > ö
ç 32 × - 0.5 ÷
è U n > ø
IECEQUATION2425 V1 EN-US (Equation 195)
k×A
t= p
+D
æ U -Un > ö
çB× -C÷
è Un > ø
EQUATION1439 V2 EN-US (Equation 196)
When the denominator in the expression is equal to zero the time delay will be
infinity. There will be an undesired discontinuity. Therefore, a tuning parameter
CrvSatn is set to compensate for this phenomenon. In the voltage interval Un> up
to Un> · (1.0 + CrvSatn/100) the used voltage will be: Un> · (1.0 + CrvSatn/100).
If the programmable curve is used this parameter must be calculated so that:
CrvSatn
B× -C > 0
100
EQUATION1435 V1 EN-US (Equation 197)
The highest phase (or phase-to-phase) voltage is always used for the inverse time
delay integration, see figure 359. The details of the different inverse time
characteristics are shown in section "Inverse characteristics".
Voltage
IDMT Voltage
UL1
UL2
UL3
Time
IEC05000016-2-en.vsd
IEC05000016 V2 EN-US
Figure 359: Voltage used for the inverse time characteristic integration
Operation of the trip signal requires that the overvoltage condition continues for at
least the user set time delay. This time delay is set by the parameter t1 and t2 for
definite time mode (DT) and by selected voltage level dependent time curves for
the inverse time mode (IDMT). If the START condition, with respect to the
measured voltage ceases during the delay time, and is not fulfilled again within a
user defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and
tIReset2 for the inverse time) the corresponding START output is reset, after that
the defined reset time has elapsed. Here it should be noted that after leaving the
hysteresis area, the START condition must be fulfilled again and it is not sufficient
for the signal to only return back to the hysteresis area. The hysteresis value for
each step is settable HystAbsn (where n means either 1 or 2 respectively) to allow a
high and accurate reset of the function. For OV2PTOV the IDMT reset time is
constant and does not depend on the voltage fluctuations during the drop-off
period. However, there are three ways to reset the timer: either the timer is reset
instantaneously, or the timer value is frozen during the reset time, or the timer
value is linearly decreased during the reset time.
tIReset1
tIReset1
Voltage
START
TRIP
U1>
HystAbs1 Measured
Voltage
Time
START t
TRIP
Time
Integrator Linearly decreased
Frozen Timer
t
Instantaneous Time
IEC09000055-2-en.vsd
IEC09000055 V2 EN-US
Figure 360: Voltage profile not causing a reset of the START signal for step 1, and inverse time delay at
different reset types
tIReset1
Voltage tIReset1
START TRIP
START HystAbs1
U1>
Measured
Voltage
Time
START t
TRIP
Time
Integrator Frozen Timer
Time
Linearly
Instantaneous decreased IEC05000020-3-en.vsd
IEC05000020 V3 EN-US
Figure 361: Voltage profile causing a reset of the START signal for step 1, and inverse time delay at
different reset types
When definite time delay is selected, the function will operate as shown in figure
362. Detailed information about individual stage reset/operation behavior is shown
in figure 363 and figure 364 respectively. Note that by setting tResetn = 0.0s
(where n means either 1 or 2 respectively), instantaneous reset of the definite time
delayed stage is ensured.
ST1
U tReset1 t1
a
a>b t t
TR1
U1>
b AND
OFF ON
Delay Delay
IEC10000100-2-en.vsd
IEC10000100 V2 EN-US
Figure 362: Logic diagram for step 1, definite time delay, DT operation
U1>
START
TRIP
tReset1
t1
IEC10000037-2-en.vsd
IEC10000037 V2 EN-US
Figure 363: Example for step 1, Definite Time Delay stage 1 reset
U1>
START
TRIP
tReset1
t1
IEC10000038-2-en.vsd
IEC10000038 V2 EN-US
OR TR1
Comparator ST2L1
UL1 > U2> Phase 1
Voltage Phase
Selector ST2L2
Comparator OpMode2 Phase 2
UL2 > U2> 1 out of 3
Start ST2L3
2 out of 3
Phase 3 t2
3 out of 3
Comparator t2Reset
UL3 > U2> & ST2
OR
Trip
START Output TR2L1
Logic
TR2
OR
START
OR
TRIP
OR
IEC05000013-2-en.vsd
IEC05000013-WMF V2 EN-US
M13304-1 v14
10.3.1 Identification
SEMOD54295-2 v6
IEC15000108 V1 EN-US
Residual voltages may occur in the power system during earth faults.
ROV2PTOV has two voltage steps, each with inverse or definite time delay.
ROV2PTOV
U3P* TRIP
BLOCK TR1
BLKTR1 TR2
BLKST1 START
BLKTR2 ST1
BLKST2 ST2
IEC06000278-2-en.vsd
IEC06000278 V2 EN-US
10.3.4 Signals
PID-3531-INPUTSIGNALS v5
PID-3531-OUTPUTSIGNALS v5
10.3.5 Settings
PID-3531-SETTINGS v5
The time delay characteristic is individually chosen for the two steps and can be
either definite time delay or inverse time delay.
The voltage-related settings are made in percent of the base voltage, which is set in
kV, phase-phase. The set UBase value is divided by sqrt(3) before the set value is
calculated.
The residual voltage is measured continuously, and compared with the set values,
U1> and U2>.
To avoid oscillations of the output START signal, a settable hysteresis has been
included.
The time delay for the two steps can be either definite time delay (DT) or inverse
time delay (IDMT). For the inverse time delay four different modes are available:
• inverse curve A
• inverse curve B
• inverse curve C
• customer programmable inverse curve
k
t=
æ U - Un > ö
ç ÷
è Un > ø
IECEQUATION2422 V1 EN-US (Equation 198)
where:
Un> Set value for step 1 and step 2
U Measured voltage
k 480
t 2.0
0.035
U Un
32 0.5
U n
k × 480
t= 3.0
+ 0.035
æ U - Un > ö
ç 32 × - 0.5 ÷
è U> ø
IECEQUATION2421 V1 EN-US (Equation 200)
k×A
t= p
+D
æ U -Un > ö
çB× -C÷
è Un > ø
EQUATION1439 V2 EN-US (Equation 201)
When the denominator in the expression is equal to zero, the time delay will be
infinite. There will be an undesired discontinuity. Therefore a tuning parameter
CrvSatn is set to compensate for this phenomenon. In the voltage interval Un> up
to Un> · (1.0 + CrvSatn/100) the used voltage will be: Un> · (1.0 + CrvSatn/100).
If the programmable curve is used this parameter must be calculated so that:
CrvSatn
B× -C > 0
100
EQUATION1440 V1 EN-US (Equation 202)
The details of the different inverse time characteristics are shown in section
"Inverse characteristics".
TRIP signal issuing requires that the residual overvoltage condition continues for at
least the user set time delay. This time delay is set by the parameter t1 and t2 for
definite time mode (DT) and by some special voltage level dependent time curves
for the inverse time mode (IDMT).
If the START condition, with respect to the measured voltage ceases during the
delay time, and is not fulfilled again within a user defined reset time (tReset1 and
tReset2 for the definite time and tIReset1 and tIReset2 for the inverse time) the
corresponding START output is reset, after the defined reset time has elapsed.
Here it should be noted that after leaving the hysteresis area, the START condition
must be fulfilled again and it is not sufficient for the signal to only return back to
the hysteresis area. Also, notice that for the overvoltage function, IDMT reset time
is constant and does not depend on the voltage fluctuations during the drop-off
period.
There are three ways to reset the timer: the timer is reset instantaneously, the timer
value is frozen during the reset time, or the timer value is linearly decreased during
the reset time. See figure 367 and figure 368.
tIReset1
tIReset1
Voltage
START
TRIP
U1>
HystAbs1 Measured
Voltage
Time
START t
TRIP
Time
Integrator Linearly decreased
Frozen Timer
t
Instantaneous Time
IEC09000055-2-en.vsd
IEC09000055 V2 EN-US
Figure 367: Voltage profile not causing a reset of the START signal for step 1, and inverse time delay
tIReset1
Voltage tIReset1
START TRIP
START HystAbs1
U1>
Measured
Voltage
Time
START t
TRIP
Time
Integrator Frozen Timer
Time
Linearly
Instantaneous decreased IEC05000020-3-en.vsd
IEC05000020 V3 EN-US
Figure 368: Voltage profile causing a reset of the START signal for step 1, and inverse time delay
When definite time delay is selected, the function will operate as shown in figure
369. Detailed information about individual stage reset/operation behavior is shown
in figure 370 and figure 371 respectively. Note that by setting tResetn = 0.0s,
instantaneous reset of the definite time delayed stage is ensured.
ST1
U tReset1 t1
a
a>b t t
TR1
U1>
b AND
OFF ON
Delay Delay
IEC10000100-2-en.vsd
IEC10000100 V2 EN-US
Figure 369: Logic diagram for step 1, Definite time delay, DT operation
U1<
ST1
TR1
tReset1
t1
IEC10000039-3-en.vsd
IEC10000039 V3 EN-US
U1<
ST1
TR1
tReset1
t1
IEC10000040-3-en.vsd
IEC10000040 V3 EN-US
ST2
Comparator Phase 1
UN > U2> TR2
Start
t2
START tReset2
& START
Trip OR
Time integrator Output
TRIP Logic
tIReset2
ResetTypeCrv2 TRIP
Step 2 OR
IEC05000748_2_en.vsd
IEC05000748 V2 EN-US
10.4.1 Identification
M14867-1 v3
U/f >
SYMBOL-Q V1 EN-US
OEXPVPH
I3P* TRIP
U3P* START
BLOCK ALARM
RESET
IEC05000329-2-en.vsd
IEC05000329 V3 EN-US
10.4.4 Signals
PID-3514-INPUTSIGNALS v6
PID-3514-OUTPUTSIGNALS v6
10.4.5 Settings
PID-3514-SETTINGS v6
Modern design transformers are more sensitive to overexcitation than earlier types.
This is a result of the more efficient designs and designs which rely on the
improvement in the uniformity of the excitation level of modern systems. If an
emergency that causes overexcitation does occur, transformers may be damaged
unless corrective action is taken. Transformer manufacturers recommend an
overexcitation protection as a part of the transformer protection system.
E = 4.44 × f × n × Bmax× A
EQUATION898 V2 EN-US (Equation 203)
E f
M ( p.u.) =
( Ur ) ( fr )
IECEQUATION2296 V1 EN-US (Equation 204)
possible, the power transformer can be disconnected from the source, after a delay,
by the TRIP signal.
The IEC 60076 - 1 standard requires that transformers operate continuously at not
more than 10% above rated voltage at no load, and rated frequency. At no load, the
ratio of the actual generator terminal voltage to the actual frequency should not
exceed 1.1 times the ratio of transformer rated voltage to the rated frequency on a
sustained basis, see equation 205.
E
---- £ 1.1 × Ur
------
f fr
EQUATION900 V1 EN-US (Equation 205)
E V Hz >
£
f fr
IECEQUATION2297 V2 EN-US (Equation 206)
where:
V/Hz> is the maximum continuously allowed voltage at no load, and rated frequency.
V/Hz> is a setting parameter. The setting range is 100% to 180%. If the user does
not know exactly what to set, then the default value for V/Hz> = 110 % given by
the IEC 60076-1 standard shall be used.
E f
M ( p.u.) =
Ur fr
IECEQUATION2299 V1 EN-US (Equation 207)
It is clear from the above formula that, for an unloaded power transformer, M = 1
for any E and f, where the ratio E/f is equal to Ur/fr. A power transformer is not
overexcited as long as the relative excitation is M ≤ V/Hz>, V/Hz> expressed in %
of Ur/fr.
As an example, at a transformer with a 15% short circuit impedance Xsc, the full
load, 0.8 power factor, 105% voltage on the load side, the actual flux level in the
transformer core, will not be significantly different from that at the 110% voltage,
no load, rated frequency, provided that the short circuit impedance X can be
equally divided between the primary and the secondary winding: Xleak = Xleak1 =
Xleak2 = Xsc / 2 = 0.075 pu.
OEXPVPH calculates the internal induced voltage E if Xleak (meaning the leakage
reactance of the winding where OEXPVPH is connected) is known to the user. The
assumption taken for two-winding power transformers that Xleak = Xsc / 2 is
unfortunately most often not true. For a two-winding power transformer the
leakage reactances of the two windings depend on how the windings are located on
the core with respect to each other. In the case of three-winding power transformers
the situation is still more complex. If a user has the knowledge on the leakage
reactance, then it should applied. If a user has no idea about it, Xleak can be set to
Xc/2. OEXPVPH protection will then take the given measured voltage U, as the
induced voltage E.
If, for example, voltage UL1L2 is fed to OEXPVPH, then currents IL1, and IL2
must be applied. From these two input currents, current IL1L2 = IL1 - IL2 is
calculated internally by the OEXPVPH algorithm. The phase-to-phase voltage
must be higher than 70% of the rated value, otherwise the protection algorithm
exits without calculating the excitation. ERROR output is set to 1, and the
displayed value of relative excitation V/Hz shows 0.000.
If three phase-to-earth voltages are available from the side where overexcitation is
connected, then OEXPVPH shall be set to measure positive sequence voltage and
current. In this case the positive sequence voltage and the positive sequence current
are used by OEXPVPH. A check is made if the positive sequence voltage is higher
than 70% of rated phase-to-earth voltage, when below this value, OEXPVPH exits
immediately, and no excitation is calculated. ERROR output is set to 1, and the
displayed value of relative excitation V/Hz shows 0.000.
Basically there are two different delay laws available to choose between:
The so called IEEE law approximates a square law and has been chosen based on
analysis of the various transformers’ overexcitation capability characteristics. They
can match the transformer core capability well.
0.18 × k 0.18 × k
top = 2
= 2
æ M ö overexcitation
ç V Hz> - 1 ÷
è ø
IECEQUATION2298 V2 EN-US (Equation 208)
where:
M the relative excitation
V/Hz> is maximum continuously allowed voltage at no load, and rated frequency, in pu and
k is time multiplier for inverse time functions, see figure 375.
Parameter k (“time multiplier setting”) selects one delay curve from the family of curves.
æ Umeasured ö
ç ÷ Umeasured frated
=è
fmeasured ø
M = ×
æ UBase ö UBase fmeasured
ç ÷
è frated ø
IECEQUATION2404 V1 EN-US (Equation 209)
top
A digital, numerical relay will instead look for the lowest j (that is, j = n) where it
becomes true that:
n
2
Dt × å ( M(j) – V/Hz> ) ³ 0.18 × k
j=k
EQUATION906 V1 EN-US (Equation 211)
where:
Dt is the time interval between two successive executions of OEXPVPH and
M(j) - V/Hz> is the relative excitation at (time j) in excess of the normal (rated) excitation which is
given as Ur/fr.
As long as M > V/Hz> (that is, overexcitation condition), the above sum can only
be larger with time, and if the overexcitation persists, the protected transformer will
be tripped at j = n.
Inverse delays as per figure 375, can be modified (limited) by two special definite
delay settings, namely tMax and tMin, see figure 374.
delay in s
tMax
overexcitation
tMin
0 Mmax - V/Hz> Overexcitation M-V/Hz>
99001067.vsd
IEC99001067 V1 EN-US
A definite maximum time, tMax, can be used to limit the operate time at low
degrees of overexcitation. Inverse delays longer than tMax will not be allowed. In
case the inverse delay is longer than tMax, OEXPVPH trips after tMax seconds.
A definite minimum time, tMin, can be used to limit the operate time at high
degrees of overexcitation. In case the inverse delay is shorter than tMin,
OEXPVPH function trips after tMin seconds. The inverse delay law is not valid for
values exceeding Mmax. The delay will be tMin, irrespective of the overexcitation
level, when values exceed Mmax (that is, M>V/Hz>).
1000
100
k = 60
k = 20
k = 10
10 k=9
k=8
k=7
k=6
k=5
k=4
k=3
k=2
k=1
1
1 2 3 4 5 10 20 30 40
OVEREXCITATION IN % (M-Emaxcont)*100)
en01000373.vsd
IEC01000373 V1 EN-US
(V Hz>> ) / f
M= = 1.40
Ur/fr
IECEQUATION2286 V1 EN-US (Equation 212)
delay in s
tMax
under- tMin
excitation Overexcitation M-Emaxcont
0 Mmax - Emaxcont Excitation M
Emaxcont Mmax
99001068.vsd
IEC99001068 V1 EN-US
Delays between two consecutive points, for example t3 and t4, are obtained by
linear interpolation.
Should it happen that tMax be lower than, for example, delays t1, and t2, the actual
delay would be tMax. Above Mmax, the delay can only be tMin.
If the overexcitation is so low that the valid delay is tMax, then the estimation of
the remaining time to trip is done against tMax.
The relative excitation M, shown on the local HMI and in PCM600 has a
monitored data value VPERHZ and is calculated from the expression:
E f
M ( p.u.) =
Ur fr
IECEQUATION2299 V1 EN-US (Equation 213)
If VPERHZ value is less than setting V/Hz> (in %), the power transformer is
underexcited. If VPERHZ is equal to V/Hz> (in %), the excitation is exactly equal
to the power transformer continuous capability. If VPERHZ is higher than V/Hz>,
the protected power transformer is overexcited. For example, if VPERHZ = 1.100,
while V/Hz> = 110 %, then the power transformer is exactly on its maximum
continuous excitation limit.
The monitored data value THERMSTA shows the thermal status of the protected
power transformer iron core. THERMSTA gives the thermal status in % of the trip
value which corresponds to 100%. THERMSTA should reach 100% at the same
time, as TMTOTRIP reaches 0 seconds. If the protected power transformer is then
for some reason not switched off, THERMSTA shall go over 100%.
If the delay as per IEEE law, or Tailor-made Law, is limited by tMax, and/or tMin,
then the Thermal status will generally not reach 100% at the same time, when
tTRIP reaches 0 seconds. For example, if, at low degrees of overexcitation, the
very long delay is limited by tMax, then the OEXPVPH TRIP output signal will be
set to 1 before the Thermal status reaches 100%.
BLOCK
AlarmLevel
tAlarm ALARM
&
t
M>V/Hz>
TRIP
&
V/Hz>
U3P Calculation
Ei k
M
of internal M=
I3P induced (Ei / f) IEEE law &
voltage Ei (Ur / fr) tMax ³1
M t
Tailor-made law
M>V/Hz>>
tMin
Xleak
t
V/Hz>>
Simplification of the diagram is in the way the IEEE and Tailor-made delays are
calculated. The cooling process is not shown. It is not shown that voltage and
frequency are separately checked against their respective limit values.
where M = (E/f)/(Ur/fr)
Minimum time delay for inverse (0.000–60.000) s ±1.0% or ±45 ms,
function whichever is greater
Maximum time delay for inverse (0.00–9000.00) s ±1.0% or ±45 ms,
function whichever is greater
Alarm time delay (0.00–9000.00) ±1.0% or ±45 ms,
whichever is greater
10.5.1 Identification
SEMOD167723-2 v2
VDCPTOV
U3P1* TRIP
U3P2* START
BLOCK ALARM
U1LOW
U2LOW
UL1DIFF
UL2DIFF
UL3DIFF
IEC06000528-2-en.vsd
IEC06000528 V2 EN-US
10.5.4 Signals
PID-3591-INPUTSIGNALS v6
PID-3591-OUTPUTSIGNALS v6
10.5.5 Settings
PID-3591-SETTINGS v6
Loss of all U1 or all U2 voltages will block the differential measurement. This
blocking can be switched off with setting BlkDiffAtULow = No.
VDCPTOV function can be blocked from an external condition with the binary
BLOCK input. It can, for example, be activated from Fuse failure supervision
function FUFSPVC.
UDTripL1>
AND
UDTripL3>
AND
AND START
UDAlarmL1>
AND
UDAlarmL2> O tAlarm
AND
R t AND ALARM
UDAlarmL3>
AND
U1<L1
tAlarm
U1<L2 AND t U1LOW
AND
U1<L3 AND
OR
BlkDiffAtULow
U2<L1
t1
U2<L2 AND t U2LOW
AND
U2<L3
BLOCK
en06000382-2.vsd
IEC06000382 V3 EN-US
10.6.1 Identification
SEMOD171954-2 v2
LOVPTUV
U3P* TRIP
BLOCK START
CBOPEN
VTSU
IEC07000039-2-en.vsd
IEC07000039 V2 EN-US
10.6.4 Signals
PID-3519-INPUTSIGNALS v6
PID-3519-OUTPUTSIGNALS v6
10.6.5 Settings
PID-3519-SETTINGS v6
LOVPTUV operates again only if the line has been restored to full voltage for at
least tRestore. Operation of the function is also inhibited by fuse failure and open
circuit breaker information signals, by their connection to dedicated inputs of the
function block.
The BLOCK input can be connected to a binary input of the IED in order to receive
a block command from external devices or can be software connected to other
internal functions of the IED itself in order to receive a block command from
internal functions. LOVPTUV is also blocked when the IED is in TEST status and
the function has been blocked from the HMI test menu. (Blocked=Yes).
TEST
TEST-ACTIVE
&
Blocked = Yes
START
BLOCK >1
Function Enable tTrip tPulse TRIP
STUL1N & t
STUL2N &
only 1 or 2 phases are low for
Latched at least 10 s (not three)
STUL3N Enable
&
tBlock
>1 t
IEC07000089_2_en.vsd
IEC07000089 V2 EN-US
11.1.1 Identification
M14865-1 v5
f<
SYMBOL-P V1 EN-US
The operation is based on positive sequence voltage measurement and requires two
phase-phase or three phase-neutral voltages to be connected. For information about
how to connect analog inputs, refer to Application manual/IED application/
Analog inputs/Setting guidelines.
SAPTUF
U3P* TRIP
BLOCK START
BLKTRIP RESTORE
BLKREST BLKDMAGN
FREQ
IEC06000279_2_en.vsd
IEC06000279 V2 EN-US
11.1.4 Signals
PID-6752-INPUTSIGNALS v2
PID-6752-OUTPUTSIGNALS v2
11.1.5 Settings
PID-6752-SETTINGS v2
To avoid oscillations of the output START signal, a hysteresis has been included.
The time delay for underfrequency protection SAPTUF can be either a settable
definite time delay or a voltage magnitude dependent time delay, where the time
delay depends on the voltage level; a high voltage level gives a longer time delay
and a low voltage level causes a short time delay. For the definite time delay, the
setting tDelay sets the time delay.
For the voltage dependent time delay the measured voltage level and the settings
UNom, UMin, Exponent, tMax and tMin set the time delay according to figure 383
and equation . The setting TimerMode is used to decide what type of time delay to
apply.
Trip signal issuing requires that the underfrequency condition continues for at least
the user set time delay tDelay. If the START condition, with respect to the
measured frequency ceases during this user set delay time, and is not fulfilled again
within a user defined reset time, tReset, the START output is reset, after that the
defined reset time has elapsed. Here it should be noted that after leaving the
hysteresis area, the START condition must be fulfilled again and it is not sufficient
for the signal to only return back to the hysteresis area.
The total time delay consists of the set value for time delay plus the
minimum operate time of the start function (80-90 ms).
On the RESTORE output of SAPTUF a 100ms pulse is issued, after a time delay
corresponding to the setting of tRestore, when the measured frequency returns to
the level corresponding to the setting RestoreFreq, after an issue of the TRIP
output signal. If tRestore is se to 0.000 s the restore functionality is disabled, and
no output will be given.
Since the fundamental frequency in a power system is the same all over the system,
except some deviations during power oscillations, another criterion is needed to
decide, where to take actions, based on low frequency. In many applications the
voltage level is very suitable, and in most cases is load shedding preferable in areas
with low voltage. Therefore, a voltage dependent time delay has been introduced,
to make sure that load shedding, or other actions, take place at the right location. At
constant voltage, U, the voltage dependent time delay is calculated according to
equation 215. At non-constant voltage, the actual time delay is integrated in a
similar way as for the inverse time characteristic for the undervoltage and
overvoltage functions.
Exponent
é U - UMin ù
t=ê × ( tMax - tMin ) + tMin
ë UNom - UMin úû
EQUATION1182 V1 EN-US (Equation 215)
where:
t is the voltage dependent time delay (at constant voltage),
U is the measured voltage
Exponent is a setting,
UMin, UNom are voltage settings corresponding to
tMax, tMin are time settings.
UMin = 90%
UNom = 100%
tMax = 1.0 s
tMin = 0.0 s
Exponent = 0, 1, 2, 3 and 4
1
0
1
Exponenent
TimeDlyOperate [s]
2
3
0.5 4
0
90 95 100
U [% of UBase]
en05000075.vsd
IEC05000075 V1 EN-US
If the measured voltage level decreases below the setting of IntBlockLevel, both the
START and the TRIP outputs are blocked.
BLKDMAGN
BLOCK
block START
OR
U < IntBlockLevel
Start
&
start Trip
Voltage
output
Definite timer
logic TRIP
or
Voltage based timer
Frequency
f < StartFrequency
tReset trip
tDelay RESTORE
AND
BLKTRIP
IEC16000041-1-en.vsdx
IEC16000041 V1 EN-US
Exponent
é U - UMin ù
t=ê × ( tMax - tMin ) + tMin
ë UNom - UMin úû
EQUATION1182 V1 EN-US (Equation 216)
U=Umeasured
11.2.1 Identification
M14866-1 v4
f>
SYMBOL-O V1 EN-US
Overfrequency occurs because of sudden load drops or shunt faults in the power
network. Close to the generating plant, generator governor problems can also cause
over frequency.
SAPTOF measures frequency with high accuracy, and is used mainly for
generation shedding and remedial action schemes. It is also used as a frequency
stage initiating load restoring. A definite time delay is provided for operate.
The operation is based on positive sequence voltage measurement and requires two
phase-phase or three phase-neutral voltages to be connected. For information about
SAPTOF
U3P* TRIP
BLOCK START
BLKTRIP BLKDMAGN
FREQ
IEC06000280_2_en.vsd
IEC06000280 V2 EN-US
11.2.4 Signals
PID-6751-INPUTSIGNALS v2
PID-6751-OUTPUTSIGNALS v2
11.2.5 Settings
PID-6751-SETTINGS v2
The time delay for Overfrequency protection SAPTOF is a settable definite time
delay, specified by the setting tDelay.
TRIP signal issuing requires that the overfrequency condition continues for at least
the user set time delay, tDelay. If the START condition, with respect to the
measured frequency ceases during this user set delay time, and is not fulfilled again
within a user defined reset time, tReset, the START output is reset, after that the
defined reset time has elapsed. It is to be noted that after leaving the hysteresis
area, the START condition must be fulfilled again and it is not sufficient for the
signal to only return back to the hysteresis area.
The total time delay consists of the set value for time delay plus
minimum operate time of the start function (80 - 90 ms).
If the measured voltage level decreases below the setting of IntBlockLevel, both the
START and the TRIP outputs are blocked.
BLKDMAGN
BLOCK
block START
OR
U < IntBlockLevel
Start
&
start Trip
Voltage
output
logic TRIP
Definite timer
Frequency
f > StartFrequency tReset
trip
tDelay
AND
BLKTRIP
IEC16000042-1-en.vsdx
IEC16000042 V1 EN-US
11.3.1 Identification
M14868-1 v4
df/dt >
<
SYMBOL-N V1 EN-US
SAPFRC
U3P* TRIP
BLOCK START
BLKTRIP RESTORE
BLKREST BLKDMAGN
IEC06000281-2-en.vsd
IEC06000281 V2 EN-US
11.3.4 Signals
PID-6754-INPUTSIGNALS v2
PID-6754-OUTPUTSIGNALS v2
11.3.5 Settings
PID-6754-SETTINGS v2
To avoid oscillations of the output START signal, a hysteresis has been included.
The RESTORE output of SAPFRC is set, after a time delay equal to the setting of
tDelay, when the measured frequency has returned to the level corresponding to
RestoreFreq, after an issue of the TRIP output signal. If tRestore is set to 0.000 s
the restore functionality is disabled, and no output will be given. The restore
functionality is only active for lowering frequency conditions and the restore
sequence is disabled if a new negative frequency gradient is detected during the
restore period, defined by the settings RestoreFreq and tRestore.
If the measured voltage level decreases below the setting of IntBlockLevel, both the
START and the TRIP outputs are blocked.
BLKDMAGN
BLOCK
block
OR
Voltage
U < IntBlockLevel
START
Start
Rate-of-change
&
of Frequency start
If Trip
[StartFreqGrad<0 output
AND logic
Definite timer
df/dt < StartFreqGrad]
start TRIP
OR
tReset
[StartFreqGrad>0
AND
tDelay
df/dt > StartFreqGrad]
Then
START trip
AND
BLKTRIP
RESTORE
Frequency restore
f > RestoreFreq
> tRestore
AND
BLKREST
IEC16000040-1-en.vsdx
IEC16000040 V1 EN-US
12.1.1 Identification
M14886-2 v3
12.1.2 Functionality
M13083-3 v6
The built-in overcurrent protection feature has two settable current levels. Both of
them can be used either with definite time or inverse time characteristic. The
overcurrent protection steps can be made directional with selectable voltage
polarizing quantity. Additionally they can be voltage and/or current controlled/
restrained. 2nd harmonic restraining facility is available as well. At too low
polarizing voltage the overcurrent feature can be either blocked, made non
directional or ordered to use voltage memory in accordance with a parameter
setting.
Additionally two overvoltage and two undervoltage steps, either with definite time
or inverse time characteristic, are available within each function.
CVGAPC
I3P* TRIP
U3P* TROC1
BLOCK TROC2
BLKOC1 TRUC1
BLKOC1TR TRUC2
ENMLTOC1 TROV1
BLKOC2 TROV2
BLKOC2TR TRUV1
ENMLTOC2 TRUV2
BLKUC1 START
BLKUC1TR STOC1
BLKUC2 STOC2
BLKUC2TR STUC1
BLKOV1 STUC2
BLKOV1TR STOV1
BLKOV2 STOV2
BLKOV2TR STUV1
BLKUV1 STUV2
BLKUV1TR BLK2ND
BLKUV2 DIROC1
BLKUV2TR DIROC2
UDIRLOW
CURRENT
ICOSFI
VOLTAGE
UIANGLE
IEC05000372-2-en.vsd
IEC05000372 V2 EN-US
12.1.4 Signals
PID-3857-INPUTSIGNALS v8
PID-3857-OUTPUTSIGNALS v8
12.1.5 Settings
PID-3857-SETTINGS v9
The user can select to measure one of the current quantities shown in table 457.
Table 457: Current selection for CVGAPC function
Set value for the
parameter Comment
CurrentInput
1 Phase1 CVGAPC function will measure the phase L1 current phasor
2 Phase2 CVGAPC function will measure the phase L2 current phasor
3 Phase3 CVGAPC function will measure the phase L3 current phasor
4 PosSeq CVGAPC function will measure internally calculated positive sequence
current phasor
5 NegSeq CVGAPC function will measure internally calculated negative
sequence current phasor
Table continues on next page
11 Phase2-Phase3 CVGAPC function will measure the current phasor internally calculated
as the vector difference between the phase L2 current phasor and
phase L3 current phasor (IL2-IL3)
12 Phase3-Phase1 CVGAPC function will measure the current phasor internally calculated
as the vector difference between the phase L3 current phasor and
phase L1 current phasor ( IL3-IL1)
13 MaxPh-Ph CVGAPC function will measure ph-ph current phasor with the
maximum magnitude
14 MinPh-Ph CVGAPC function will measure ph-ph current phasor with the
minimum magnitude
15 UnbalancePh-Ph CVGAPC function will measure magnitude of unbalance current, which
is internally calculated as the algebraic magnitude difference between
the ph-ph current phasor with maximum magnitude and ph-ph current
phasor with minimum magnitude. Phase angle will be set to 0° all the
time
The user can select to measure one of the voltage quantities shown in table 458:
Table 458: Voltage selection for CVGAPC function
Set value for the
parameter Comment
VoltageInput
1 Phase1 CVGAPC function will measure the phase L1 voltage phasor
2 Phase2 CVGAPC function will measure the phase L2 voltage phasor
3 Phase3 CVGAPC function will measure the phase L3 voltage phasor
4 PosSeq CVGAPC function will measure internally calculated positive sequence
voltage phasor
5 -NegSeq CVGAPC function will measure internally calculated negative
sequence voltage phasor. This voltage phasor will be intentionally
rotated for 180° in order to enable easier settings for the directional
feature when used.
6 -3ZeroSeq CVGAPC function will measure internally calculated zero sequence
voltage phasor multiplied by factor 3. This voltage phasor will be
intentionally rotated for 180° in order to enable easier settings for the
directional feature when used.
Table continues on next page
13 MaxPh-Ph CVGAPC function will measure ph-ph voltage phasor with the
maximum magnitude
14 MinPh-Ph CVGAPC function will measure ph-ph voltage phasor with the
minimum magnitude
15 UnbalancePh-Ph CVGAPC function will measure magnitude of unbalance voltage,
which is internally calculated as the algebraic magnitude difference
between the ph-ph voltage phasor with maximum magnitude and ph-
ph voltage phasor with minimum magnitude. Phase angle will be set to
0° all the time
It is important to notice that the voltage selection from table 458 is always
applicable regardless the actual external VT connections. The three-phase VT
inputs can be connected to IED as either three phase-to-ground voltages UL1, UL2
& UL3 or three phase-to-phase voltages UL1L2, UL2L3 & UL3L1). This information
about actual VT connection is entered as a setting parameter for the pre-processing
block, which will then take automatic care about it.
The user can select one of the current quantities shown in table 459 for built-in
current restraint feature:
Table 459: Restraint current selection for CVGAPC function
Set value for the
parameter RestrCurr Comment
1 PosSeq CVGAPC function will measure internally calculated positive sequence
current phasor
2 NegSeq CVGAPC function will measure internally calculated negative
sequence current phasor
3 3ZeroSeq CVGAPC function will measure internally calculated zero sequence
current phasor multiplied by factor 3
4 MaxPh CVGAPC function will measure current phasor of the phase with
maximum magnitude
The parameter settings for the base quantities, which represent the base (100%) for
pickup levels of all measuring stages, shall be entered as setting parameters for
every CVGAPC function.
1. rated phase current of the protected object in primary amperes, when the
measured Current Quantity is selected from 1 to 9, as shown in table 457.
2. rated phase current of the protected object in primary amperes multiplied by
√3 (1.732*Iphase), when the measured Current Quantity is selected from 10 to
15, as shown in table 457.
1. rated phase-to-earth voltage of the protected object in primary kV, when the
measured Voltage Quantity is selected from 1 to 9, as shown in table 458.
2. rated phase-to-phase voltage of the protected object in primary kV, when the
measured Voltage Quantity is selected from 10 to 15, as shown in table 458.
Two overcurrent protection steps are available. They are absolutely identical and
therefore only one will be explained here.
Overcurrent step simply compares the magnitude of the measured current quantity
(see table 457) with the set pickup level. Non-directional overcurrent step will
pickup if the magnitude of the measured current quantity is bigger than this set
level. However depending on other enabled built-in features this overcurrent
pickup might not cause the overcurrent step start signal. Start signal will only come
if all of the enabled built-in features in the overcurrent step are fulfilled at the same
time.
This feature will simple prevent overcurrent step start if the second-to-first
harmonic ratio in the measured current exceeds the set level.
The overcurrent protection step operation can be made dependent on the relevant
phase angle between measured current phasor (see table 457) and measured voltage
phasor (see table 458). In protection terminology it means that the General currrent
and voltage protection (CVGAPC) function can be made directional by enabling
this built-in feature. In that case overcurrent protection step will only operate if the
current flow is in accordance with the set direction (Forward, which means
towards the protected object, or Reverse, which means from the protected object).
For this feature it is of the outmost importance to understand that the measured
voltage phasor (see table 458) and measured current phasor (see table 457) will be
used for directional decision. Therefore it is the sole responsibility of the end user
to select the appropriate current and voltage signals in order to get a proper
directional decision. CVGAPC function will NOT do this automatically. It will
simply use the current and voltage phasors selected by the end user to check for the
directional criteria.
Table 460 gives an overview of the typical choices (but not the only possible ones)
for these two quantities from traditional directional relays.
Table 460: Typical current and voltage choices for directional feature
Set value for the Set value for the
parameter parameter Comment
CurrentInput VoltageInput
PosSeq PosSeq Directional positive sequence overcurrent function is
obtained. Typical setting for RCADir is from 45° to
90° depending on the power system voltage level
(X/R ratio)
NegSeq -NegSeq Directional negative sequence overcurrent function is
obtained. Typical setting for RCADir is from 45° to
90° depending on the power system voltage level
(X/R ratio)
3ZeroSeq -3ZeroSeq Directional zero sequence overcurrent function is
obtained. Typical setting for RCADir is from 0° to 90°
depending on the power system earthing (that is,
solidly earthed, earthed via resistor)
Phase1 Phase2-Phase3 Directional overcurrent function for the first phase is
obtained. Typical setting for RCADir is +30° or +45°
Phase2 Phase3-Phase1 Directional overcurrent function for the second phase
is obtained. Typical setting for RCADir is +30° or
+45°
Phase3 Phase1-Phase2 Directional overcurrent function for the third phase is
obtained. Typical setting for RCADir is +30° or +45°
Unbalance current or voltage measurement shall not be used when the directional
feature is enabled.
• the magnitude of the measured current is bigger than the set pick-up level
• the phasor of the measured current is within the operating region (defined by
the relay operate angle, ROADir parameter setting; see figure 390).
U=-3U0
RCADir
Operate region
mta line
en05000252.vsd
IEC05000252 V1 EN-US
where:
RCADir is 75°
ROADir is 50°
• that the product I·cos(Φ) is bigger than the set pick-up level, where Φ is angle
between the current phasor and the mta line
• that the phasor of the measured current is within the operating region (defined
by the I·cos(Φ) straight line and the relay operate angle, ROADir parameter
setting; see figure 390).
U=-3U0
RCADir
Operate region
mta line
en05000253.vsd
IEC05000253 V1 EN-US
where:
RCADir is 75°
ROADir is 50°
Note that it is possible to decide by a parameter setting how the directional feature
shall behave when the magnitude of the measured voltage phasor falls below the
pre-set value. User can select one of the following three options:
It shall also be noted that the memory duration is limited in the algorithm to 100
ms. After that time the current direction will be locked to the one determined
during memory time and it will re-set only if the current fails below set pickup
level or voltage goes above set voltage memory limit.
StartCurr_OC1
VDepFact_OC1 * StartCurr_OC1
ULowLimit_OC1 UHighLimit_OC1
Selected Voltage
Magnitude
en05000324.vsd
IEC05000324 V1 EN-US
Figure 392: Example for OC1 step current pickup level variation as function of
measured voltage magnitude in Slope mode of operation
StartCurr_OC1
VDepFact_OC1 * StartCurr_OC1
en05000323.vsd
IEC05000323 V1 EN-US
Figure 393: Example for OC1 step current pickup level variation as function of
measured voltage magnitude in Step mode of operation
This feature will simply change the set overcurrent pickup level in accordance with
magnitude variations of the measured voltage. It shall be noted that this feature will
as well affect the pickup current value for calculation of operate times for IDMT
curves (overcurrent with IDMT curve will operate faster during low voltage
conditions).
IMeasured
ea ain
ar tr
te es
e ra ff *Ir
Op oe
s trC
e
I>R
IsetHigh
IsetLow
atan(RestrCoeff)
Restraint
en05000255.vsd
IEC05000255 V1 EN-US
This feature will simply prevent overcurrent step to start if the magnitude of the
measured current quantity is smaller than the set percentage of the restrain current
magnitude. However this feature will not affect the pickup current value for
calculation of operate times for IDMT curves. This means that the IDMT curve
operate time will not be influenced by the restrain current magnitude.
When set, the start signal will start definite time delay or inverse (IDMT) time
delay in accordance with the end user setting. If the start signal has value one for
longer time than the set time delay, the overcurrent step will set its trip signal to
one. Reset of the start and trip signal can be instantaneous or time delay in
accordance with the end user setting.
Two undercurrent protection steps are available. They are absolutely identical and
therefore only one will be explained here. Undercurrent step simply compares the
magnitude of the measured current quantity (see table 457) with the set pickup
level. The undercurrent step will pickup and set its start signal to one if the
magnitude of the measured current quantity is smaller than this set level. The start
signal will start definite time delay with set time delay. If the start signal has value
one for longer time than the set time delay the undercurrent step will set its trip
signal to one. Reset of the start and trip signal can be instantaneous or time delay in
accordance with the setting.
Two overvoltage protection steps are available. They are absolutely identical and
therefore only one will be explained here.
Overvoltage step simply compares the magnitude of the measured voltage quantity
(see table 458) with the set pickup level. The overvoltage step will pickup if the
magnitude of the measured voltage quantity is bigger than this set level.
The start signal will start definite time delay or inverse (IDMT) time delay in
accordance with the end user setting. If the start signal has value one for longer
time than the set time delay, the overvoltage step will set its trip signal to one.
Reset of the start and trip signal can be instantaneous or time delay in accordance
with the end user setting.
Two undervoltage protection steps are available. They are absolutely identical and
therefore only one will be explained here.
The start signal will start definite time delay or inverse (IDMT) time delay in
accordance with the end user setting. If the start signal has value one for longer
time than the set time delay, the undervoltage step will set its trip signal to one.
Reset of the start and trip signal can be instantaneous or time delay in accordance
with the end user setting.
The simplified internal logics, for CVGAPC function are shown in the following
figures.
IED
ADM CVGAPC function
Phasor calculation of
scaling with CT ratio
individual currents
A/D conversion
Selection of which current Selected current
and voltage shall be given to
Phasors &
samples
the built-in protection Selected voltage
elements
Phasors &
samples
IEC05000169_2_en.vsd
IEC05000169 V2 EN-US
Figure 395: Treatment of measured currents and voltages within IED for CVGAPC function
Figure 395 shows how internal treatment of measured currents is done for
multipurpose protection function
The following currents and voltages are inputs to the multipurpose protection
function. They must all be expressed in true power system (primary) Amperes and
kilovolts.
1. Selects one current from the three-phase input system (see table 457) for
internally measured current.
2. Selects one voltage from the three-phase input system (see table 458) for
internally measured voltage.
3. Selects one current from the three-phase input system (see table 459) for
internally measured restraint current.
CURRENT
UC1
nd TRUC1
2 Harmonic
Selected current restraint
STUC2
UC2
TRUC2
2nd Harmonic
restraint
STOC1
OC1 TROC1
STOC2
OC2 TROC2
2nd Harmonic
restraint
Current restraint ³1
UDIRLOW
Directionality DIROC2
Voltage control /
restraint
STOV1
OV1 TROV1
STOV2
OV2 TROV2
STUV1
Selected voltage
UV1 TRUV1
STUV2
UV2 TRUV2
VOLTAGE
en05000170.vsd
IEC05000170 V1 EN-US
Figure 396: CVGAPC function main logic diagram for built-in protection
elements
1. The selected currents and voltage are given to built-in protection elements.
Each protection element and step makes independent decision about status of
its START and TRIP output signals.
2. More detailed internal logic for every protection element is given in the
following four figures.
3. Common START and TRIP signals from all built-in protection elements &
steps (internal OR logic) are available from multipurpose function as well.
a
a>b AND
BlkLevel2nd b
Enable
second Second harmonic
harmonic check DEF time BLKTRO C1 TROC1
selected DEF AND
OR
a
a>b
b
OC1=On STOC1
AND
StartCurr_OC1 BLKOC1
X
Inverse
Selected v oltage
Curren t
Restrai nt
Feature
Selected restrain current Imea sure d > k Irestra int
IEC05000831-2-en.vsdx
IEC05000831 V2 EN-US
Figure 397: Simplified internal logic diagram for built-in first overcurrent step that is, OC1 (step OC2 has the
same internal logic)
Operation_UC1=On
STUC1
en05000750.vsd
IEC05000750 V1 EN-US
Figure 398: Simplified internal logic diagram for built-in first undercurrent step that is, UC1 (step UC2 has
the same internal logic)
Inverse
Operation_OV1=On
Inverse time
BLKOV1 selected
en05000751.vsd
IEC05000751 V1 EN-US
Figure 399: Simplified internal logic diagram for built-in first overvoltage step OV1 (step OV2 has the same
internal logic)
Inverse
Operation_UV1=On
Inverse time
BLKUV1 selected
en05000752.vsd
IEC05000752 V1 EN-US
Figure 400: Simplified internal logic diagram for built-in first undervoltage step UV1 (step UV2 has the same
internal logic)
SMAIHPAC
BLOCK AI3P
G3P* AI1
AI2
AI3
AI4
IEC13000180-1-en.vsd
IEC13000180 V1 EN-US
PID-6733-INPUTSIGNALS v1
PID-6733-OUTPUTSIGNALS v1
PID-6733-SETTINGS v1
For all four analogue input signals into this filter (i.e. three phases and the residual
quantity) the input samples from the TRM module which are coming at rate of 20
samples per fundamental system cycle are first stored. When enough samples are
available in the internal memory, the phasor values at set frequency defined by the
setting parameter SetFrequency are calculated. The following values are internally
available for each of the calculated phasors:
• Magnitude
• Phase angle
• Exact frequency of the extracted signal
Note that the special filtering algorithm is used to extract these phasors. This
algorithm is different from the standard one-cycle Digital Fourier Filter typically
used by the numerical IEDs. This filter provides extremely good accuracy of
measurement and excellent noise rejection, but at the same time it has much slower
response time. It is capable to extract phasor (i.e. magnitude, phase angle and
actual frequency) of any signal (e.g. 37,2Hz) present in the waveforms of the
connected CTs and/or VTs. The magnitude and the phase angle of this phasor are
calculated with very high precision. For example the magnitude and phase angle of
the phasor can be estimated even if it has magnitude of one per mille (i.e. 1‰ ) in
comparison to the dominating signal (e.g. the fundamental frequency component).
Several instances of this function block are provided. These instances are fully
synchronized between each-other in respect of phase angle calculation. Thus if two
multi-purpose filters are used for some application, one for current and the second
one for the voltage signals, the power values (i.e. P & Q) at the set frequency can
be calculated from them by the over-/under-power function or CVMMXN
measurement function block.
Thus when this filter is used in conjunction with multi-purpose protection function
or overcurrent function or over-voltage function or over-power function many
different protection applications can be arranged. For example the following
protection, monitoring or measurement features can be realized:
• Sub-synchronous resonance protection for turbo generators
• Sub-synchronous protection for wind turbines/wind farms
• Detection of sub-synchronous oscillation between HVDC links and
synchronous generators
• Super-synchronous protection
• Detection of presence of the geo-magnetic induced currents
• Overcurrent or overvoltage protection at specific frequency harmonic, sub-
harmonic, inter-harmonic etc.
• Presence of special railway frequencies (e.g. 16.7Hz or 25Hz) in the three-
phase power system
The filter output can also be connected to the measurement function blocks such as
CVMMXN (Measurements), CMMXU (Phase current measurement), VMMXU
(Phase-phase voltage measurement), etc.
The filter has as well additional capability to report the exact frequency of the
extracted signal. Thus the user can check the actual frequency of some
phenomenon in the power system (e.g. frequency of the sub-synchronous currents)
and compare it with expected value obtained previously by either calculation or
simulation. For the whole three-phase filter group the frequency of the signal
connected to the first input (i.e. phase L1) is reported. This value can be then used
either by over-/under-frequency protections or reported to the built-in HMI or any
other external client via the measurement blocks such is the CVMMXN.
How many samples in the memory are used for the phasor calculation depends on
the setting parameter FilterLength. Table 465 gives overview of the used number
of samples for phasor calculation by the filter. Note that the used number of
samples is always a power of number two.
Table 465: Length of the filtering window
Value for parameter Used No of samples for Corresponding length of Corresponding length of
FilterLength calculation (fixed, the input waveform in the input waveform in
independent from rated miliseconds for 50Hz miliseconds for 60Hz
frequency) power system power system
0.1 s 128 = 27 128 ms 107 ms
Note that the selected value for the parameter FilterLength automatically defines
certain filter properties as described below:
First in order to secure proper filter operation the selected length of the filter shall
always be longer than three complete periods of the signal which shall be extracted.
Actually the best results are obtained if at least five complete periods are available
within the filtering window. Thus, this filter feature will limit which filter lengths
can be used to extract low frequency signals. For example if 16,7 Hz signal shall be
extracted the minimum filter length in milliseconds shall be:
1000
3× = 180ms
16.7
EQUATION000028 V1 EN-US (Equation 217)
Thus based on the data from Table 465 the minimum acceptable value for this
parameter would be “FilterLength = 0.2 s” but more accurate results will be
obtained by using “FilterLength = 0.5 s”
Thus the longer length of the filter the better capability it has to reject the
disturbing signals close to the required frequency component and any other noise
present in the input signal waveform. For example if 46 Hz signal wants to be
extracted in 50Hz power system, then from Table 466 it can be concluded that
“FilterLength=1,0 s” shall be selected as a minimum value. However if frequency
deviation of the fundamental frequency signal in the power system are taken into
account it may be advisable to select “FilterLength=2,0 s” for such application.
Note that in case when no clear magnitude peak exist in the set pass frequency
band the filter will return zero values for the phasor magnitude and angle while the
signal frequency will have value minus one. Finally the set value for parameter
FilterLength also defines the response time of the filter after a step change of the
measured signal. The filter will correctly estimate the new signal magnitude once
75% of the filter length has been filed with the new signal value (i.e. after the
change).
If for any reason this natural frequency band shall be extended (e.g. to get accurate
but wider filter) it is possible to increase the pass band by entering the value
different from zero for parameter FreqBandWidth. In such case the total filter pass
band can be defined as:
Example if in 60Hz system the selected values are “FilterLength =1.0 s” and
“FreqBandWidth = 5.0” the total filter pass band will be ±(3.6+5.0/2)= ± 6.1 Hz.
IEC13000178-2-en.vsd
IEC13000178 V3 EN-US
The data shown in the Figure comes from the comtrade file captured by the IED.
The following traces are presented in this Figure.
Note the very narrow scale on the y-axle for b) and c). Such small scale as well
indicates with which precision and consistency the filter calculates the phasor
magnitude and frequency of the extracted stator sub-synchronous current
component.
With above given settings the sub-synchronous current magnitude and frequency
are calculated approximately four times per second (that is, correct value is four
times per 1024 ms).
14.1.1 Identification
M14870-1 v5
Open or short circuited current transformer cores can cause unwanted operation of
many protection functions such as differential, earth-fault current and negative-
sequence current functions.
Current circuit supervision (CCSSPVC) compares the residual current from a three
phase set of current transformer cores with the neutral point current on a separate
input taken from another set of cores on the current transformer.
CCSSPVC
I3P* FAIL
IREF* ALARM
BLOCK
IEC13000304-1-en.vsd
IEC13000304 V1 EN-US
14.1.4 Signals
PID-6806-INPUTSIGNALS v2
PID-6806-OUTPUTSIGNALS v2
14.1.5 Settings
PID-6806-SETTINGS v2
Current circuit supervision CCSSPVC compares the absolute value of the vectorial
sum of the three phase currents |ΣIphase| and the absolute value of the residual
current |Iref| from another current transformer set, see figure 403.
The FAIL output will be set to high when the following criteria are fulfilled:
• The numerical value of the difference |ΣIphase| – |Iref| is higher than 80% of
the numerical value of the sum |ΣIphase| + |Iref|.
• The numerical value of the current |ΣIphase| – |Iref| is equal to or higher than
the set operate value IMinOp.
• No phase current has exceeded Ip>Block during the last 10 ms.
• CCSSPVC is enabled by setting Operation = On.
The FAIL output remains activated 100 ms after the AND-gate resets when being
activated for more than 20 ms. If the FAIL lasts for more than 150 ms an ALARM
will be issued. In this case the FAIL and ALARM will remain activated 1 s after
the AND-gate resets. This prevents unwanted resetting of the blocking function
when phase current supervision element(s) operate, for example, during a fault.
I>Ip>Block
BLOCK
IL1 IL1 I>IMinOp
IL2 +å
IL2 å
IL3 IL3 -
+å +å
I ref Iref + x -
0,8
1,5 x Ir
AND OR FAIL
10 ms
20 ms 100 ms
150 ms 1s ALARM
OPERATION
BLOCK
en05000463.tif
IEC05000463 V2 EN-US
Figure 403: Simplified logic diagram for Current circuit supervision CCSSPVC
| åI phase | - | I ref |
Slope = 1
Operation
Slope = 0.8
area
I MinOp
| åI phase | + | I ref |
99000068.vsd
IEC99000068 V1 EN-US
Due to the formulas for the axis compared, |SIphase | - |I ref | and |S
I phase | + | I ref | respectively, the slope can not be above 1.
14.2.1 Identification
M14869-1 v4
The aim of the fuse failure supervision function (FUFSPVC) is to block voltage
measuring functions at failures in the secondary circuits between the voltage
transformer and the IED in order to avoid inadvertent operations that otherwise
might occur.
The fuse failure supervision function basically has three different detection
methods, negative sequence and zero sequence based detection and an additional
delta voltage and delta current detection.
The zero sequence detection is recommended for IEDs used in directly or low
impedance earthed networks. It is based on the zero sequence measuring quantities.
A criterion based on delta current and delta voltage measurements can be added to
the fuse failure supervision function in order to detect a three phase fuse failure,
which in practice is more associated with voltage transformer switching during
station operations.
FUFSPVC
I3P* BLKZ
U3P* BLKU
BLOCK 3PH
CBCLOSED DLD1PH
MCBOP DLD3PH
DISCPOS STDI
BLKTRIP STDIL1
STDIL2
STDIL3
STDU
STDUL1
STDUL2
STDUL3
IEC14000065-1-en.vsd
IEC14000065 V1 EN-US
14.2.4 Signals
PID-3492-INPUTSIGNALS v9
PID-3492-OUTPUTSIGNALS v9
14.2.5 Settings
PID-3492-SETTINGS v9
The zero and negative sequence function continuously measures the currents and
voltages in all three phases and calculates, see figure 406:
The measured signals are compared with their respective set values 3U0> and
3I0<, 3U2> and 3I2<.
The function enable the internal signal FuseFailDetZeroSeq if the measured zero-
sequence voltage is higher than the set value 3U0> and the measured zero-
sequence current is below the set value 3I0<.
A drop out delay of 100 ms for the measured zero-sequence and negative sequence
current will prevent a false fuse failure detection at un-equal breaker opening at the
two line ends.
Sequence Detection
3I0< CurrZeroSeq
IL1
Zero 3I0
sequence
filter 100 ms CurrNegSeq
a
IL2 a>b t
b
Negative 3I2
sequence
IL3 filter FuseFailDetZeroSeq
AND
100 ms
a
a>b t
3I2< b
FuseFailDetNegSeq
AND
3U0>
VoltZeroSeq
UL1
Zero
sequence a 3U0
a>b
b
filter
UL2 VoltNegSeq
Negative
sequence a 3U2
a>b
UL3 filter b
3U2>
IEC10000036-2-en.vsd
IEC10000036 V2 EN-US
The calculated values 3U0, 3I0, 3I2 and 3U2 are available as service values on
local HMI and monitoring tool in PCM600.
The output signals 3PH, BLKU and BLKZ as well as the signals DLD1PH and
DLD3PH from dead line detections are blocked if any of the following conditions
occur:
The input BLOCK signal is a general purpose blocking signal of the fuse failure
supervision function. It can be connected to a binary input of the IED in order to
receive a block command from external devices or can be software connected to
other internal functions of the IED itself in order to receive a block command from
internal functions. Through OR gate it can be connected to both binary inputs and
internal function outputs.
The input BLKTRIP is intended to be connected to the trip output from any of the
protection functions included in the IED. When activated for more than 20 ms, the
operation of the fuse failure is blocked; a fixed drop-out timer prolongs the block
for 100 ms. The aim is to increase the security against unwanted operations during
the opening of the breaker, which might cause unbalance conditions for which the
fuse failure might operate.
The output signal BLKZ will also be blocked if the internal dead line detection is
activated. The dead line detection signal has a 200 ms drop-out time delay.
The input signal MCBOP is supposed to be connected via a terminal binary input
to the N.C. auxiliary contact of the miniature circuit breaker protecting the VT
secondary circuit. The MCBOP signal sets the output signals BLKU and BLKZ in
order to block all the voltage related functions when the MCB is open independent
of the setting of OpMode selector. The additional drop-out timer of 150 ms
prolongs the presence of MCBOP signal to prevent the unwanted operation of
voltage dependent function due to non simultaneous closing of the main contacts of
the miniature circuit breaker.
The input signal DISCPOS is supposed to be connected via a terminal binary input
to the N.C. auxiliary contact of the line disconnector. The DISCPOS signal sets the
output signal BLKU in order to block the voltage related functions when the line
disconnector is open. The impedance protection function is not affected by the
position of the line disconnector since there will be no line currents that can cause
malfunction of the distance protection. If DISCPOS=0 it signifies that the line is
connected to the system and when the DISCPOS=1 it signifies that the line is
disconnected from the system and the block signal BLKU is generated.
The output BLKU can be used for blocking the voltage related measuring functions
(undervoltage protection, energizing check and so on) except for the impedance
protection.
The function output BLKZ shall be used for blocking the impedance protection
function.
A simplified diagram for the functionality is found in figure 407. The calculation of
the changes of currents and voltages is based on a sample analysis algorithm. The
calculated delta quantities are compared with their respective set values DI< and
DU>. The algorithm detects a fuse failure if a sufficient change in voltage without
a sufficient change in current is detected in each phase separately. The following
quantities are calculated in all three phases:
• The magnitude of the phase-ground voltage has been above UPh> for more
than 1.5 cycles (i.e. 30 ms in a 50 Hz system)
• The magnitudes of DU in three phases are higher than the corresponding
setting DU>
• The magnitudes of DI in three phases are below the setting DI<
In addition to the above conditions, at least one of the following conditions shall be
fulfilled in order to activate the internal FuseFailDetDUDI signal:
• The magnitude of the phase currents in three phases are higher than the setting
IPh>
• The circuit breaker is closed (CBCLOSED = True)
The first criterion means that detection of failure in three phases together with high
current for the three phases will set the output. The measured phase current is used
to reduce the risk of false fuse failure detection. If the current on the protected line
is low, a voltage drop in the system (not caused by fuse failure) may be followed
by current change lower than the setting DI<, and therefore a false fuse failure
might occur.
The second criterion requires that the delta condition shall be fulfilled at the same
time as circuit breaker is closed. If CBCLOSED input is connected to FALSE ,
then only the first criterion can enable the delta function.If the DUDI detections of
three phases set the internal signal FuseFailDetDUDI at the level high, then the
signal FuseFailDetDUDI will remain high as long as the voltages of three phases
are lower then the setting Uph>.
In addition to fuse failure detection, two internal signals DeltaU and DeltaI are also
generated by the delta current and delta voltage DUDI detection algorithm. The
internal signals DelatU and DeltaI are activated when a sudden change of voltage,
or respectively current, is detected. The detection of the sudden change is based on
a sample analysis algorithm. In particular DelatU is activated if at least three
consecutive voltage samples are higher then the setting DU>. In a similar way
DelatI is activated if at least three consecutive current samples are higher then the
setting DI<. When DeltaU or DeltaI are active, the output signals STDUL1,
STDUL2, STDUL3 and respectively STDIL1, STDIL2, STDIL3, based on a
sudden change of voltage or current detection, are activated with a 20 ms time off
delay. The common start output signals STDU or STDI are activated with a 60 ms
time off delay, if any sudden change of voltage or current is detected.
The delta function (except the sudden change of voltage and current
detection) is deactivated by setting the parameter OpDUDI to Off.
DUDI Detection
DUDI detection Phase 1
DeltaIL1
IL1
IL2
IL3 DI detection based on sample analysis OR
DI<
UL1
IL1 DeltaIL2
IL2 DUDI detection Phase 2
DeltaUL2
IL3
UL2 Same logic as for phase 1
IL1 DeltaIL3
DUDI detection Phase 3
IL2
DeltaUL3
IL3
UL3 Same logic as for phase 1
UL1
a
a<b
b
IL1
a
a>b
IPh> b AND
OR AND
CBCLOSED AND OR
UL2
a
a<b
b
IL2
a
a>b
b AND
OR AND
AND OR
UL3
a
a<b
b
IL3
a
a>b
b AND
OR AND
AND OR FuseFailDetDUDI
AND
IEC12000166-3-en.vsd
IEC12000166 V3 EN-US
Figure 407: Simplified logic diagram for the DU/DI detection part
intBlock
STDI
AND
20 ms
DeltaIL1 STDIL1
t AND
OR
20 ms
DeltaIL2
t STDIL2
AND
20 ms
DeltaIL3
t
STDIL3
AND
STDU
AND
20 ms
DeltaUL1 STDUL1
t AND
OR
20 ms
DeltaUL2
t STDUL2
AND
20 ms
DeltaUL3
t
STDUL3
AND
IEC12000165-1-en.vsd
IEC12000165 V1 EN-US
Figure 408: Internal signals DeltaU or DeltaI and the corresponding output
signals
A simplified diagram for the functionality is found in figure 409. A dead phase
condition is indicated if both the voltage and the current in one phase is below their
respective setting values UDLD< and IDLD<. If at least one phase is considered to
be dead the output DLD1PH and the internal signal DeadLineDet1Ph is activated.
If all three phases are considered to be dead the output DLD3PH is activated
IL3
a
a<b
b
IDLD<
DeadLineDet1Ph
UL1
a AND
a<b
b OR DLD1PH
AND
UL2
a AND
a<b
b
AND DLD3PH
UL3 AND
a AND
a<b
b
UDLD<
intBlock
IEC10000035-1-en.vsd
IEC10000035 V2 EN-US
Figure 409: Simplified logic diagram for Dead Line detection part
A simplified diagram for the functionality is found in figure 410. The fuse failure
supervision function (FUFSPVC) can be switched on or off by the setting
parameter Operation to On or Off.
The delta function can be activated by setting the parameter OpDUDI to On. When
selected it operates in parallel with the sequence based algorithms.
If the fuse failure situation is present for more than 5 seconds and the setting
parameter SealIn is set to On it will be sealed in as long as at least one phase
voltages is below the set value USealIn<. This will keep the BLKU and BLKZ
signals activated as long as any phase voltage is below the set value USealIn<. If
all three phase voltages drop below the set value USealIn< and the setting
parameter SealIn is set to On the output signal 3PH will also be activated. The
signals 3PH, BLKU and BLKZ will now be active as long as any phase voltage is
below the set value USealIn<.
If SealIn is set to On the fuse failure condition lasting more then 5 seconds is stored
in the non-volatile memory in the IED. At start-up of the IED (due to auxiliary
power interruption or re-start due to configuration change) it uses the stored value
in its non-volatile memory and re-establishes the conditions that were present
before the shut down. All phase voltages must be restored above USealIn< before
fuse failure is de-activated and resets the signals BLKU, BLKZ and 3PH.
The output signal BLKU will also be active if all phase voltages have been above
the setting USealIn< for more than 60 seconds, the zero or negative sequence
voltage has been above the set value 3U0> and 3U2> for more than 5 seconds, all
phase currents are below the setting IDLD< (criteria for open phase detection) and
the circuit breaker is closed (input CBCLOSED is activated).
If a MCB is used then the input signal MCBOP is to be connected via a binary
input to the N.C. auxiliary contact of the miniature circuit breaker protecting the
VT secondary circuit. The MCBOP signal sets the output signals BLKU and BLKZ
in order to block all the voltage related functions when the MCB is open
independent of the setting of OpMode or OpDUDI. An additional drop-out timer of
150 ms prolongs the presence of MCBOP signal to prevent the unwanted operation
of voltage dependent function due to non simultaneous closing of the main contacts
of the miniature circuit breaker.
The input signal DISCPOS is supposed to be connected via a terminal binary input
to the N.C. auxiliary contact of the line disconnector. The DISCPOS signal sets the
output signal BLKU in order to block the voltage related functions when the line
disconnector is open. The impedance protection function does not have to be
affected since there will be no line currents that can cause malfunction of the
distance protection.
TEST ACTIVE
AND
BlocFuse = Yes
BLOCK intBlock
OR
BLKTRIP 20 ms 100 ms
AND t t
FusefailStarted
AND
Any UL < UsealIn<
FuseFailDetDUDI
AND 5s
OpDUDI = On
OR t
FuseFailDetZeroSeq
AND
AND
FuseFailDetNegSeq
AND
UNsINs OR
UZsIZs OR
UZsIZs OR UNsINs
OpMode
UZsIZs AND UNsINs
OptimZsNs
OR
CurrZeroSeq
a AND
CurrNegSeq a>b
b
AND
DeadLineDet1Ph 200 ms
AND BLKZ
t OR AND
150 ms
MCBOP t
AND BLKU
60 s
t OR OR
All UL > UsealIn<
AND
VoltZeroSeq 5s
VoltNegSeq OR t
AllCurrLow
CBCLOSED
DISCPOS IEC10000033-2-en.vsd
IEC10000033 V2 EN-US
Figure 410: Simplified logic diagram for fuse failure supervision function, Main
logic
Different protection functions within the protection IED operates on the basis of
measured voltage at the relay point. Some example of protection functions are:
VDSPVC
U3P1* MAINFUF
U3P2* PILOTFUF
BLOCK U1L1FAIL
U1L2FAIL
U1L3FAIL
U2L1FAIL
U2L2FAIL
U2L3FAIL
IEC14000048-1-en.vsd
IEC12000142 V2 EN-US
14.3.4 Signals
PID-3485-INPUTSIGNALS v8
PID-3485-OUTPUTSIGNALS v8
14.3.5 Settings
PID-3485-SETTINGS v8
VDSPVC requires six voltage inputs, which are the three phase voltages on main
and pilot fuse groups. The initial voltage difference between the two groups is
theoretical zero in the healthy condition. Any subsequent voltage difference will be
due to a fuse failure.
If the main fuse voltage becomes smaller than the pilot fuse voltage (vMainL1 <
vPilotL1 or vMainL2 < vPilotL2 or vMainL3 < vPilotL3) and the voltage
difference exceeds the operation level (Ud>MainBlock), a blocking signal will be
initiated to indicate the main fuse failure and block the voltage-dependent
functions. In addition, the function also indicates the phase in which the voltage
reduction has occurred.
If the pilot fuse voltage becomes smaller than the main fuse voltage (vPilotL1 <
vMainL1 or vPilotL2 < vMainL2 or vPilotL3 < vMainL3) and the voltage
difference exceeds the operation level (Ud>PilotAlarm), an alarm signal will be
initiated to indicate the pilot fuse failure and also the faulty phase where the
voltage reduction occurred.
When SealIn is set to On and the fuse failure has last for more than 5 seconds, the
blocked protection functions will remain blocked until normal voltage conditions
are restored above the USealIn setting. Fuse failure outputs are deactivated when
normal voltage conditions are restored.
5s
a
a<b AND OR t
USealIn b
SealIn=0
vPilotL1
+
vMainL1 -
å MAX a U1L1FAIL
OR
a>b AND
Ud>MainBlock b MAINFAIL
OR
0
MIN ABS a
a>b AND U2L1FAIL
Ud> PilotAlarm b
BLOCK
OR PILOTFAIL
vPilotL2 U1L2FAIL
vMainL2 Phase L2, same as Phase L1 U2L2FAIL
vPilotL3 U1L3FAIL
vMainL3 Phase L3, same as Phase L1 U2L3FAIL
IEC12000144-1-en.vsd
IEC12000144 V1 EN-US
Section 15 Control
15.1.1 Identification
M14889-1 v4
SYMBOL-M V1 EN-US
SESRSYN function includes a built-in voltage selection scheme for double bus and
1½ breaker or ring busbar arrangements.
Manual closing as well as automatic reclosing can be checked by the function and
can have different settings.
SESRSYN
U3PBB1* SYNOK
U3PBB2* AUTOSYOK
U3PLN1* AUTOENOK
U3PLN2* MANSYOK
BLOCK MANENOK
BLKSYNCH TSTSYNOK
BLKSC TSTAUTSY
BLKENERG TSTMANSY
B1QOPEN TSTENOK
B1QCLD USELFAIL
B2QOPEN B1SEL
B2QCLD B2SEL
LN1QOPEN LN1SEL
LN1QCLD LN2SEL
LN2QOPEN SYNPROGR
LN2QCLD SYNFAIL
UB1OK UOKSYN
UB1FF UDIFFSYN
UB2OK FRDIFSYN
UB2FF FRDIFFOK
ULN1OK FRDERIVA
ULN1FF UOKSC
ULN2OK UDIFFSC
ULN2FF FRDIFFA
STARTSYN PHDIFFA
TSTSYNCH FRDIFFM
TSTSC PHDIFFM
TSTENERG INADVCLS
AENMODE UDIFFME
MENMODE FRDIFFME
PHDIFFME
UBUS
ULINE
MODEAEN
MODEMEN
IEC10000046-1-en.vsd
IEC10000046 V1 EN-US
15.1.4 Signals
PID-6724-INPUTSIGNALS v1
PID-6724-OUTPUTSIGNALS v1
15.1.5 Settings
PID-6724-SETTINGS v2
The synchrocheck feature measures the conditions across the circuit breaker and
compares them to set limits. The output for closing operation is given when all
measured quantities are simultaneously within their set limits.
The energizing check feature measures the bus and line voltages and compares
them to both high and low threshold detectors. The output is given only when the
actual measured quantities match the set conditions.
The synchronizing feature measures the conditions across the circuit breaker, and
also determines the angle change occurring during the closing delay of the circuit
breaker, from the measured slip frequency. The output is given only when all
measured conditions are simultaneously within their set limits. The closing of the
output is timed to give closure at the optimal time including the time needed for the
circuit breaker and the closing circuit operation.
The voltage difference, frequency difference and phase angle difference values are
measured in the IED centrally and are available for the SESRSYN function for
evaluation. By setting the phases used for SESRSYN, with the settings
SelPhaseBus1, SelPhaseBus2, SelPhaseLine1 and SelPhaseLine2, a compensation
is made automatically for the voltage amplitude difference and the phase angle
difference caused if different setting values are selected for both sides of the
breaker. If needed, an additional phase angle adjustment can be done for selected
line voltage with the PhaseShift setting.
For double bus single circuit breaker and 1½ circuit breaker arrangements, the
SESRSYN function blocks have the capability to make the necessary voltage
selection. For double bus single circuit breaker arrangements, selection of the
correct voltage is made using auxiliary contacts of the bus disconnectors. For 1½
circuit breaker arrangements, correct voltage selection is made using auxiliary
contacts of the bus disconnectors as well as the circuit breakers.
The internal logic for each function block as well as, the input and outputs, and the
setting parameters with default setting and setting ranges is described in this
document. For application related information, please refer to the application
manual.
M14833-3 v5
The logic diagrams that follow illustrate the main principles of the SESRSYN
function components such as Synchrocheck, Synchronizing, Energizing check and
Voltage selection, and are intended to simplify the understanding of the function.
When the function is set to OperationSC = On, the measuring will start.
The function will compare the bus and line voltage values with the set values for
UHighBusSC and UHighLineSC.
If both sides are higher than the set values, the measured values are compared with
the set values for acceptable frequency, phase angle and voltage difference:
FreqDiffA, FreqDiffM, PhaseDiffA, PhaseDiffM and UDiffSC. If additional phase
angle adjustment is done with the PhaseShift setting, the adjustment factor is
deducted from the line voltage before the comparison of the phase angle values.
The frequency on both sides of the circuit breaker is also measured. The
frequencies must not deviate from the rated frequency more than ±5Hz. The
frequency difference between the bus frequency and the line frequency is measured
and may not exceed the set value FreqDiff.
Two sets of settings for frequency difference and phase angle difference are
available and used for the manual closing and autoreclose functions respectively, as
required.
The inputs BLOCK and BLKSC are available for total block of the complete
SESRSYN function and selective block of the Synchrocheck function respectively.
Input TSTSC will allow testing of the function where the fulfilled conditions are
connected to a separate test output.
The outputs MANSYOK and AUTOSYOK are activated when the actual measured
conditions match the set conditions for the respective output. The output signal can
be delayed independently for MANSYOK and AUTOSYOK conditions.
Output INADVCLS, inadvertent circuit breaker closing, indicates that the circuit
breaker has been closed at wrong phase angle by mistake. The output is activated,
if the voltage conditions are fulfilled at the same time the phase angle difference
between bus and line is suddenly changed from being larger than 60 degrees to
smaller than 5 degrees.
OperationSC = On
AND TSTAUTSY
AND
invalidSelection AND
OR AUTOSYOK
AND
0-60 s
AND t
tSCA
UDiffSC 50 ms
AND t
UHighBusSC
UOKSC
AND
UHighLineSC
UDIFFSC
1
1
FRDIFFA
FreqDiffA
1
PHDIFFA
PhaseDiffA
UDIFFME
voltageDifferenceValue
FRDIFFME
frequencyDifferenceValue
PHDIFFME
phaseAngleDifferenceValue
32 ms 100 ms
AND t INADVCLS
PhDiff > 60° AND
PhDiff < 5°
IEC07000114-6-en.vsdx
IEC07000114 V6 EN-US
Figure 414: Simplified logic diagram for the auto synchrocheck function
The function will compare the values for the bus and line voltage with the set
values for UHighBusSynch and UHighLineSynch, which is a supervision that the
voltages are both live. Also the voltage difference is checked to be smaller than the
set value for UDiffSynch, which is a p.u value of set voltage base values. If both
sides are higher than the set values and the voltage difference between bus and line
is acceptable, the measured values are compared with the set values for acceptable
frequency FreqDiffMax and FreqDiffMin, rate of change of frequency
FreqRateChange and phase angle CloseAngleMax.
The measured frequencies between the settings for the maximum and minimum
frequency will initiate the measuring and the evaluation of the angle change to
allow operation to be sent at the right moment including the set tBreaker time. The
At operation the SYNOK output will be activated with a pulse tClosePulse and the
function resets. The function will also reset if the synchronizing conditions are not
fulfilled within the set tMaxSynch time. This prevents that the function is, by
mistake, maintained in operation for a long time, waiting for conditions to be
fulfilled.
The inputs BLOCK and BLKSYNCH are available for total block of the complete
SESRSYN function and block of the Synchronizing function respectively.
TSTSYNCH will allow testing of the function where the fulfilled conditions are
connected to a separate output.
OperationSynch=On
TSTSYNCH
STARTSYN
invalidSelection
SYNPROGR
AND
BLOCK AND
S
BLKSYNCH OR
R
UDiffSynch
50 ms SYNOK
AND
UHighBusSynch AND t
UHighLineSynch OR
FreqDiffMax TSTSYNOK
AND
FreqDiffMin
tClosePulse
FreqRateChange
AND
fBus&fLine ± 5Hz
tMaxSynch
CloseAngleMax AND
SYNFAIL
FreqDiff
Close pulse
in advance
tBreaker
=IEC06000636=5=en=Original.vsd
IEC06000636 V5 EN-US
Voltage values are measured in the IED and are available for evaluation by the
Energizing check function.
The function measures voltages on the busbar and the line to verify whether they
are live or dead. This is done by comparing with the set values UHighBusEnerg
and ULowBusEnerg for bus energizing and UHighLineEnerg and ULowLineEnerg
for line energizing.
The frequency on both sides of the circuit breaker is also measured. The
frequencies must not deviate from the rated frequency more than +/-5Hz.
The Energizing direction can be selected individually for the Manual and the
Automatic functions respectively. When the conditions are met the outputs
AUTOENOK and MANENOK respectively will be activated if the fuse
supervision conditions are fulfilled. The output signal can be delayed
independently for MANENOK and AUTOENOK conditions. The Energizing
direction can also be selected by an integer input AENMODE respective
MENMODE, which for example, can be connected to a Binary to Integer function
block (B16I). Integers supplied shall be 1=Off, 2=DLLB, 3=DBLL and 4= Both.
Not connected input will mean that the setting is done from Parameter Setting tool.
The active position can be read on outputs MODEAEN resp MODEMEN. The
modes are 0=OFF, 1=DLLB, 2=DBLL and 3=Both.
The inputs BLOCK and BLKENERG are available for total block of the complete
SESRSYN function respective block of the Energizing check function.
TSTENERG will allow testing of the function where the fulfilled conditions are
connected to a separate test output.
manEnergOpenBays
MANENOK
OR
TSTENERG
BLKENERG
OR
BLOCK
selectedFuseOK
UHighBusEnerg
DLLB tManEnerg
AND
OR t
AND
OR
ULowLineEnerg AND
ManEnerg BOTH
ULowBusEnerg
DBLL
AND
UHighLineEnerg
TSTENOK
ManEnergDBDL AND AND
UMaxEnerg
fBus and fLine ±5 Hz
IEC14000031-1-en.vsd
IEC14000031 V1 EN-US
TSTENERG
BLKENERG
OR
BLOCK
selectedFuseOK
UHighBusEnerg
DLLB tAutoEnerg
AND
OR t
AND OR
AUTOENOK
ULowLineEnerg AND
AutoEnerg BOTH
ULowBusEnerg
DBLL
AND
UHighLineEnerg
TSTENOK
UMaxEnerg AND
IEC14000030-1-en.vsd
IEC14000030 V1 EN-US
BLKENERG
BLOCK OR manEnergOpenBays
AND
ManEnerg
1½ bus CB
CBConfig AND
B1QOPEN
LN1QOPEN AND
OR
B1QCLD
B2QOPEN
AND
LN2QOPEN
B2QCLD
AND
Tie CB
AND
AND
OR
AND
IEC14000032-1-en.vsd
IEC14000032 V1 EN-US
External fuse failure signals or signals from a tripped fuse switch/MCB are
connected to binary inputs that are configured to the inputs of SESRSYN function
in the IED. Alternatively, the internal signals from fuse failure supervision can be
used when available. There are two alternative connection possibilities. Inputs
labelled OK must be connected if the available contact indicates that the voltage
circuit is healthy. Inputs labelled FF must be connected if the available contact
indicates that the voltage circuit is faulty.
The UB1OK/UB2OK and UB1FF/UB2FF inputs are related to the busbar voltage
and the ULN1OK/ULN2OK and ULN1FF/ULN2FF inputs are related to the line
voltage. Configure them to the binary input or function outputs that indicate the
status of the external fuse failure of the busbar and line voltages. In the event of a
fuse failure, the energizing check function is blocked. The synchronizing and the
synchrocheck function requires full voltage on both sides, thus no blocking at fuse
failure is needed.
The voltage selection type to be used is set with the parameter CBConfig.
If No voltage sel. is set the voltages used will be U-Line1 and U-Bus1. This setting
is also used in the case when external voltage selection is provided. Fuse failure
supervision for the used inputs must also be connected.
The voltage selection function, selected voltages, and fuse conditions are used for
the Synchronizing, Synchrocheck and Energizing check inputs.
For the disconnector positions it is advisable to use (NO) a and (NC) b type
contacts to supply Disconnector Open and Closed positions but, it is also possible
to use an inverter for one of the positions.
Voltage selection for a single circuit breaker with double busbars M14838-3 v9
The setting CBConfig selected for Double Bus activates the voltage selection for
single CB and double busbars. This function uses the binary input from the
disconnectors auxiliary contacts B1QOPEN-B1QCLD for Bus 1, and B2QOPEN-
B2QCLD for Bus 2 to select between bus 1 and bus 2 voltages. If the disconnector
connected to bus 1 is closed and the disconnector connected to bus 2 is opened the
bus 1 voltage is used. All other combinations use the bus 2 voltage. The outputs
B1SEL and B2SEL respectively indicate the selected Bus voltage.
The function checks the fuse-failure signals for bus 1, bus 2 and line voltage
transformers. Inputs UB1OK-UB1FF supervise the MCB for Bus 1 and UB2OK-
UB2FF supervises the MCB for Bus 2. ULN1OK and ULN1FF supervises the
MCB for the Line voltage transformer. The inputs fail (FF) or healthy (OK) can
alternatively be used dependent on the available signal. If a VT failure is detected
in the selected voltage source an output signal USELFAIL is set. This output signal
is true if the selected bus or line voltages have a VT failure. This output as well as
the function can be blocked with the input signal BLOCK. The function logic
diagram is shown in figure 419.
B1QOPEN
B1SEL
B1QCLD AND
B2QOPEN B2SEL
AND
1
B2QCLD
invalidSelection
AND
bus1Voltage busVoltage
bus2Voltage
UB1OK AND
UB1FF OR
OR selectedFuseOK
AND
UB2OK AND
UB2FF OR USELFAIL
AND
ULN1OK
ULN1FF OR
BLOCK
en05000779-2.vsd
IEC05000779 V2 EN-US
Figure 419: Logic diagram for the voltage selection function of a single circuit breaker with double busbars
Note that with 1½ breaker schemes three Synchrocheck functions must be used for
the complete diameter. Below, the scheme for one Bus breaker and the Tie breaker
is described.
With the setting parameter CBConfig the selection of actual CB location in the 1
1/2 circuit breaker switchgear is done. The settings are: 1 1/2 Bus CB, 1 1/2 alt.
Bus CB or Tie CB.
This voltage selection function uses the binary inputs from the disconnectors and
circuit breakers auxiliary contacts to select the right voltage for the SESRSYN
function. For the bus circuit breaker one side of the circuit breaker is connected to
the busbar and the other side is connected either to line 1, line 2 or the other busbar
depending on the best selection of voltage circuit.
The tie circuit breaker is connected either to bus 1 or line 1 voltage on one side and
the other side is connected either to bus 2 or line 2 voltage. Four different output
combinations are possible, bus to bus, bus to line, line to bus and line to line.
The function also checks the fuse-failure signals for bus 1, bus 2, line 1 and line 2.
If a VT failure is detected in the selected voltage an output signal USELFAIL is
set. This output signal is true if the selected bus or line voltages have a MCB trip.
This output as well as the function can be blocked with the input signal BLOCK.
The function block diagram for the voltage selection of a bus circuit breaker is
shown in figure 420 and for the tie circuit breaker in figure 421.
LN1QOPEN
AND
LN1SEL
LN1QCLD
B1QOPEN
LN2SEL
B1QCLD AND AND
B2SEL
OR
LN2QOPEN
AND invalidSelection
LN2QCLD AND
AND
B2QOPEN
B2QCLD AND
line1Voltage lineVoltage
line2Voltage
bus2Voltage
UB1OK
UB1FF OR
OR selectedFuseOK
UB2OK AND
AND
UB2FF OR
USELFAIL
ULN1OK AND
AND
ULN1FF OR
ULN2OK
AND
ULN2FF OR
BLOCK
en05000780-2.vsd
IEC05000780 V2 EN-US
Figure 420: Simplified logic diagram for the voltage selection function for a bus circuit breaker in a 1 1/2
breaker arrangement
LN1QOPEN
AND
LN1SEL
LN1QCLD
B1SEL
1
B1QOPEN AND
AND
B1QCLD AND
line1Voltage busVoltage
bus1Voltage
LN2QOPEN
LN2SEL
LN2QCLD AND
B2SEL
1
invalidSelection
OR
B2QOPEN AND
AND
B2QCLD AND
line2Voltage lineVoltage
bus2Voltage
UB1OK AND
UB1FF OR
OR selectedFuseOK
UB2OK AND
AND
UB2FF OR
USELFAIL
ULN1OK AND
AND
ULN1FF OR
ULN2OK
AND
ULN2FF OR
BLOCK
en05000781-2.vsd
IEC05000781 V2 EN-US
Figure 421: Simplified logic diagram for the voltage selection function for the tie circuit breaker in 1 1/2
breaker arrangement.
Each control IED has interlocking functions for different switchyard arrangements,
each handling the interlocking of one bay. The interlocking functionality in each
IED is not dependent on any central function. For the station-wide interlocking, the
IEDs communicate via the station bus or by using hard wired binary inputs/outputs.
The interlocking conditions depend on the circuit configuration and status of the
system at any given time.
After the selection and reservation of an apparatus, the function has complete data
on the status of all apparatuses in the switchyard that are affected by the selection.
Other operators cannot interfere with the reserved apparatus or the status of
switching devices that may affect it.
The open or closed positions of the HV apparatuses are inputs to software modules
distributed in the control IEDs. Each module contains the interlocking logic for a
bay. The interlocking logic in a module is different, depending on the bay function
and the switchyard arrangements, that is, double-breaker or 1 1/2 breaker bays have
different modules. Specific interlocking conditions and connections between
standard interlocking modules are performed with an engineering tool. Bay-level
interlocking signals can include the following kind of information:
Apparatus control
Interlocking
modules
modules in
SCILO SCSWI
other bays SXSWI
Apparatus control
modules
Interlocking SCILO SCSWI SXCBR
module
Apparatus control
modules
en04000526.vsd SCILO SCSWI SXSWI
IEC04000526 V1 EN-US
Bays communicate via the station bus and can convey information regarding the
following:
• Unearthed busbars
• Busbars connected together
• Other bays connected to a busbar
• Received data from other bays is valid
Station bus
Disc QB1 and QB2 closed Disc QB1 and QB2 closed WA1 unearthed
WA1 unearthed
WA1 and WA2 interconn
...
WA1 not earthed WA1 not earthed
WA2 not earthed WA2 not earthed WA1 and WA2 interconn
WA1 and WA2 interconn WA1 and WA2 interconn in other bay
..
WA1
WA2
QB1 QB2 QB1 QB2 QB1 QB2 QC1 QC2
QB9 QB9
en05000494.vsd
IEC05000494 V1 EN-US
When invalid data such as intermediate position, loss of a control IED, or input
board error are used as conditions for the interlocking condition in a bay, a release
for execution of the function will not be given.
On the local HMI an override function exists, which can be used to bypass the
interlocking function in cases where not all the data required for the condition is
valid.
The input signals EXDU_xx shall be set to true if there is no transmission error at
the transfer of information from other bays. Required signals with designations
ending in TR are intended for transfer to other bays.
15.2.3.1 Identification
GUID-3EC5D7F1-FDA0-4F0E-9391-08D357689E0C v3
The Logical node for interlocking SCILO function is used to enable a switching
operation if the interlocking conditions permit. SCILO function itself does not
provide any interlocking functionality. The interlocking conditions are generated in
separate function blocks containing the interlocking logic.
SCILO
POSOPEN EN_OPEN
POSCLOSE EN_CLOSE
OPEN_EN
CLOSE_EN
IEC05000359-2-en.vsd
IEC05000359 V2 EN-US
15.2.3.4 Signals
PID-3487-INPUTSIGNALS v7
PID-3487-OUTPUTSIGNALS v7
The function contains logic to enable the open and close commands respectively if
the interlocking conditions are fulfilled. That means also, if the switch has a
defined end position for example, open, then the appropriate enable signal (in this
case EN_OPEN) is false. The enable signals EN_OPEN and EN_CLOSE can be
true at the same time only in the intermediate and bad position state and if they are
enabled by the interlocking function. The position inputs come from the logical
nodes Circuit breaker/Circuit switch (SXCBR/SXSWI) and the enable signals
come from the interlocking logic. The outputs are connected to the logical node
Switch controller (SCSWI). One instance per switching device is needed.
POSOPEN SCILO
POSCLOSE =1 1
EN_OPEN
&
>1
&
OPEN_EN
CLOSE_EN & EN_CLOSE
>1
&
en04000525.vsd
IEC04000525 V1 EN-US
15.2.4.1 Identification
GUID-F3CBAFDC-3723-429F-9183-45229A6F0A12 v3
The interlocking for busbar earthing switch (BB_ES) function is used for one
busbar earthing switch on any busbar parts according to figure 426.
QC
en04000504.vsd
IEC04000504 V1 EN-US
BB_ES
QC_OP QCREL
QC_CL QCITL
BB_DC_OP BBESOPTR
VP_BB_DC BBESCLTR
EXDU_BB
IEC05000347-2-en.vsd
IEC05000347 V2 EN-US
BB_ES
VP_BB_DC QCREL
BB_DC_OP QCITL
EXDU_BB & 1
QC_OP BBESOPTR
QC_CL BBESCLTR
en04000546.vsd
IEC04000546 V1 EN-US
15.2.4.5 Signals
PID-3494-INPUTSIGNALS v10
PID-3494-OUTPUTSIGNALS v10
15.2.5.1 Identification
GUID-29EF1F25-E10A-4C82-A6B7-FA246D9C6CD2 v3
The interlocking for bus-section breaker (A1A2_BS) function is used for one bus-
section circuit breaker between section 1 and 2 according to figure 428. The
function can be used for different busbars, which includes a bus-section circuit
breaker.
QA1
QC3 QC4
en04000516.vsd
A1A2_BS
IEC04000516 V1 EN-US
A1A2_BS
QA1_OP QA1OPREL
QA1_CL QA1OPITL
QB1_OP QA1CLREL
QB1_CL QA1CLITL
QB2_OP QB1REL
QB2_CL QB1ITL
QC3_OP QB2REL
QC3_CL QB2ITL
QC4_OP QC3REL
QC4_CL QC3ITL
S1QC1_OP QC4REL
S1QC1_CL QC4ITL
S2QC2_OP S1S2OPTR
S2QC2_CL S1S2CLTR
BBTR_OP QB1OPTR
VP_BBTR QB1CLTR
EXDU_12 QB2OPTR
EXDU_ES QB2CLTR
QA1O_EX1 VPS1S2TR
QA1O_EX2 VPQB1TR
QA1O_EX3 VPQB2TR
QB1_EX1
QB1_EX2
QB2_EX1
QB2_EX2
IEC05000348-2-en.vsd
IEC05000348 V2 EN-US
A1A2_BS
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB2_OP
QB2_CL =1 VPQB2
QC3_OP
QC3_CL =1 VPQC3
QC4_OP
QC4_CL =1 VPQC4
S1QC1_OP
S1QC1_CL =1 VPS1QC1
S2QC2_OP
S2QC2_CL =1 VPS2QC2
VPQB1
QB1_OP QA1OPREL
& >1
QA1O_EX1 QA1OPITL
1
VPQB2
QB2_OP
&
QA1O_EX2
VP_BBTR
BBTR_OP
&
EXDU_12
QA1O_EX3
VPQB1 QA1CLREL
VPQB2 & QA1CLITL
1
VPQA1
VPQC3 QB1REL
& >1
VPQC4 QB1ITL
1
VPS1QC1
QA1_OP
QC3_OP
QC4_OP
S1QC1_OP
EXDU_ES
QB1_EX1
VPQC3
VPS1QC1
&
QC3_CL
S1QC1_CL
EXDU_ES
QB1_EX2
en04000542.vsd
IEC04000542 V1 EN-US
VPQA1
VPQC3 QB2REL
VPQC4 & >1
QB2ITL
VPS2QC2 1
QA1_OP
QC3_OP
QC4_OP
S2QC2_OP
EXDU_ES
QB2_EX1
VPQC4
VPS2QC2
&
QC4_CL
S2QC2_CL
EXDU_ES
QB2_EX2
VPQB1 QC3REL
VPQB2 QC3ITL
QB1_OP & 1
QC4REL
QB2_OP
QC4ITL
1
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB1_OP S1S2OPTR
QB2_OP >1 S1S2CLTR
QA1_OP 1
VPQB1
VPS1S2TR
VPQB2 &
VPQA1
en04000543.vsd
IEC04000543 V1 EN-US
15.2.5.5 Signals
PID-3498-INPUTSIGNALS v9
PID-3498-OUTPUTSIGNALS v9
15.2.6.1 Identification
GUID-0A0229EB-5ECD-405C-B706-6A54CBBDB49D v3
The interlocking for bus-section disconnector (A1A2_DC) function is used for one
bus-section disconnector between section 1 and 2 according to figure 430.
A1A2_DC function can be used for different busbars, which includes a bus-section
disconnector.
QB
WA1 (A1) WA2 (A2)
QC1 QC2
A1A2_DC en04000492.vsd
IEC04000492 V1 EN-US
A1A2_DC
QB_OP QBOPREL
QB_CL QBOPITL
S1QC1_OP QBCLREL
S1QC1_CL QBCLITL
S2QC2_OP DCOPTR
S2QC2_CL DCCLTR
S1DC_OP VPDCTR
S2DC_OP
VPS1_DC
VPS2_DC
EXDU_ES
EXDU_BB
QBCL_EX1
QBCL_EX2
QBOP_EX1
QBOP_EX2
QBOP_EX3
IEC05000349-2-en.vsd
IEC05000349 V2 EN-US
A1A2_DC
QB_OP
VPQB VPDCTR
QB_CL =1
DCOPTR
DCCLTR
S1QC1_OP
VPS1QC1
S1QC1_CL =1
S2QC2_OP
VPS2QC2
S2QC2_CL =1
VPS1QC1
VPS2QC2
VPS1_DC & >1 QBOPREL
S1QC1_OP QBOPITL
1
S2QC2_OP
S1DC_OP
EXDU_ES
EXDU_BB
QBOP_EX1
VPS1QC1
VPS2QC2
VPS2_DC &
S1QC1_OP
S2QC2_OP
S2DC_OP
EXDU_ES
EXDU_BB
QBOP_EX2
VPS1QC1
VPS2QC2
S1QC1_CL &
S2QC2_CL
EXDU_ES
QBOP_EX3
en04000544.vsd
IEC04000544 V1 EN-US
IEC04000545 V1 EN-US
15.2.6.5 Signals
PID-3499-INPUTSIGNALS v10
PID-3499-OUTPUTSIGNALS v10
15.2.7.1 Identification
GUID-8149EE0A-E2A4-431C-9D07-D1A0BD296743 v3
The interlocking for bus-coupler bay (ABC_BC) function is used for a bus-coupler
bay connected to a double busbar arrangement according to figure 432. The
function can also be used for a single busbar arrangement with transfer busbar or
double busbar arrangement without transfer busbar.
WA1 (A)
WA2 (B)
WA7 (C)
QB1 QB2 QB20 QB7
QC1
QA1
QC2
en04000514.vsd
IEC04000514 V1 EN-US
ABC_BC
QA1_OP QA1OPREL
QA1_CL QA1OPITL
QB1_OP QA1CLREL
QB1_CL QA1CLITL
QB2_OP QB1REL
QB2_CL QB1ITL
QB7_OP QB2REL
QB7_CL QB2ITL
QB20_OP QB7REL
QB20_CL QB7ITL
QC1_OP QB20REL
QC1_CL QB20ITL
QC2_OP QC1REL
QC2_CL QC1ITL
QC11_OP QC2REL
QC11_CL QC2ITL
QC21_OP QB1OPTR
QC21_CL QB1CLTR
QC71_OP QB220OTR
QC71_CL QB220CTR
BBTR_OP QB7OPTR
BC_12_CL QB7CLTR
VP_BBTR QB12OPTR
VP_BC_12 QB12CLTR
EXDU_ES BC12OPTR
EXDU_12 BC12CLTR
EXDU_BC BC17OPTR
QA1O_EX1 BC17CLTR
QA1O_EX2 BC27OPTR
QA1O_EX3 BC27CLTR
QB1_EX1 VPQB1TR
QB1_EX2 VQB220TR
QB1_EX3 VPQB7TR
QB2_EX1 VPQB12TR
QB2_EX2 VPBC12TR
QB2_EX3 VPBC17TR
QB20_EX1 VPBC27TR
QB20_EX2
QB7_EX1
QB7_EX2
IEC05000350-2-en.vsd
IEC05000350 V2 EN-US
ABC_BC
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB20_OP
QB20_CL =1 VPQB20
QB7_OP
QB7_CL =1 VPQB7
QB2_OP
QB2_CL =1 VPQB2
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
QC71_OP
QC71_CL =1 VPQC71
VPQB1
QB1_OP QA1OPREL
& >1 QA1OPITL
QA1O_EX1 1
VPQB20
QB20_OP &
QA1O_EX2
VP_BBTR
BBTR_OP &
EXDU_12
QA1O_EX3
VPQB1 QA1CLREL
VPQB2 QA1CLITL
VPQB7 & 1
VPQB20
en04000533.vsd
IEC04000533 V1 EN-US
VPQA1
VPQB2 QB1REL
& >1
VPQC1 QB1ITL
VPQC2 1
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2
VP_BC_12
&
QB2_CL
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX3
en04000534.vsd
IEC04000534 V1 EN-US
VPQA1
VPQB1 QB2REL
& >1
VPQC1 QB2ITL
VPQC2 1
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1
VP_BC_12
&
QB1_CL
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1
VPQC21
&
QC1_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000535.vsd
IEC04000535 V1 EN-US
VPQA1
VPQB20 QB7REL
& >1
VPQC1 QB7ITL
VPQC2 1
VPQC71
QA1_OP
QB20_OP
QC1_OP
QC2_OP
QC71_OP
EXDU_ES
QB7_EX1
VPQC2
VPQC71
&
QC2_CL
QC71_CL
EXDU_ES
QB7_EX2
VPQA1
VPQB7 QB20REL
& >1
VPQC1 QB20ITL
VPQC2 1
VPQC21
QA1_OP
QB7_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB20_EX1
VPQC2
VPQC21
&
QC2_CL
QC21_CL
EXDU_ES
QB20_EX2
en04000536.vsd
IEC04000536 V1 EN-US
VPQB1 QC1REL
VPQB20 QC1ITL
& 1
VPQB7
QC2REL
VPQB2
QB1_OP QC2ITL
1
QB20_OP
QB7_OP
QB2_OP
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB20_OP QB220OTR
QB2_OP & QB220CTR
VPQB20 1
VQB220TR
VPQB2 &
QB7_OP QB7OPTR
QB7_CL QB7CLTR
VPQB7 VPQB7TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
QA1_OP BC12OPTR
QB1_OP >1 BC12CLTR
QB20_OP 1
VPQA1
VPBC12TR
VPQB1 &
VPQB20
QA1_OP BC17OPTR
QB1_OP >1 BC17CLTR
QB7_OP 1
VPQA1
VPBC17TR
VPQB1 &
VPQB7
QA1_OP BC27OPTR
QB2_OP >1 BC27CLTR
QB7_OP 1
VPQA1
VPBC27TR
VPQB2 &
VPQB7
en04000537.vsd
IEC04000537 V1 EN-US
15.2.7.5 Signals
PID-3500-INPUTSIGNALS v9
PID-3500-OUTPUTSIGNALS v9
15.2.8.1 Identification
GUID-03F1A3BB-4A1E-49E8-88C6-10B3876F64DA v4
WA1 (A)
WA2 (B)
QB1 QB2
QC1 QC1
QA1 QA1
QC2 QC2
QB6 QB6
QC3 QC3
BH_LINE_A BH_LINE_B
QB9 QB9
QC1 QC2
QC9 QC9
BH_CONN
en04000513.vsd
IEC04000513 V1 EN-US
Three types of interlocking modules per diameter are defined. BH_LINE_A and
BH_LINE_B are the connections from a line to a busbar. BH_CONN is the
connection between the two lines of the diameter in the 1 1/2 breaker switchyard
layout.
M13574-3 v6
BH_LINE_A
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB6_OP QB6REL
QB6_CL QB6ITL
QB1_OP QB1REL
QB1_CL QB1ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC3_OP QC3REL
QC3_CL QC3ITL
QB9_OP QB9REL
QB9_CL QB9ITL
QC9_OP QC9REL
QC9_CL QC9ITL
CQA1_OP QB1OPTR
CQA1_CL QB1CLTR
CQB61_OP VPQB1TR
CQB61_CL
CQC1_OP
CQC1_CL
CQC2_OP
CQC2_CL
QC11_OP
QC11_CL
VOLT_OFF
VOLT_ON
EXDU_ES
QB6_EX1
QB6_EX2
QB1_EX1
QB1_EX2
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9_EX6
QB9_EX7
IEC05000352-2-en.vsd
IEC05000352 V2 EN-US
M13578-3 v6
BH_LINE_B
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB6_OP QB6REL
QB6_CL QB6ITL
QB2_OP QB2REL
QB2_CL QB2ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC3_OP QC3REL
QC3_CL QC3ITL
QB9_OP QB9REL
QB9_CL QB9ITL
QC9_OP QC9REL
QC9_CL QC9ITL
CQA1_OP QB2OPTR
CQA1_CL QB2CLTR
CQB62_OP VPQB2TR
CQB62_CL
CQC1_OP
CQC1_CL
CQC2_OP
CQC2_CL
QC21_OP
QC21_CL
VOLT_OFF
VOLT_ON
EXDU_ES
QB6_EX1
QB6_EX2
QB2_EX1
QB2_EX2
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9_EX6
QB9_EX7
IEC05000353-2-en.vsd
IEC05000353 V2 EN-US
BH_CONN
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB61_OP QB61REL
QB61_CL QB61ITL
QB62_OP QB62REL
QB62_CL QB62ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
1QC3_OP
1QC3_CL
2QC3_OP
2QC3_CL
QB61_EX1
QB61_EX2
QB62_EX1
QB62_EX2
IEC05000351-2-en.vsd
IEC05000351 V2 EN-US
M13577-1 v5
BH_CONN
QA1_OP
QA1_CL =1 VPQA1
QB61_OP
QB61_CL =1 VPQB61
QB62_OP
QB62_CL =1 VPQB62
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
1QC3_OP
1QC3_CL =1 VP1QC3
2QC3_OP
2QC3_CL =1 VP2QC3
VPQB61 QA1CLREL
VPQB62 & QA1CLITL
1
VPQA1
VPQC1 QB61REL
& >1
VPQC2 QB61ITL
1
VP1QC3
QA1_OP
QC1_OP
QC2_OP
1QC3_OP
QB61_EX1
VPQC1
VP1QC3
&
QC1_CL
1QC3_CL
QB61_EX2
VPQA1
VPQC1 QB62REL
& >1
VPQC2 QB62ITL
1
VP2QC3
QA1_OP
QC1_OP
QC2_OP
2QC3_OP
QB62_EX1
VPQC2
VP2QC3
&
QC2_CL
2QC3_CL
QB62_EX2
VPQB61 QC1REL
VPQB62 QC1ITL
& 1
QB61_OP QC2REL
QB62_OP QC2ITL
1
en04000560.vsd
IEC04000560 V1 EN-US
BH_LINE_A
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB6_OP
QB6_CL =1 VPQB6
QC9_OP
QC9_CL =1 VPQC9
QB9_OP
QB9_CL =1 VPQB9
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
CQA1_OP
CQA1_CL =1 VPCQA1
CQC1_OP
CQC1_CL =1 VPCQC1
CQC2_OP
CQC2_CL =1 VPCQC2
CQB61_OP
CQB61_CL =1 VPCQB61
QC11_OP
QC11_CL =1 VPQC11
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQB1 QA1CLREL
VPQB6 QA1CLITL
& 1
VPQB9
VPQA1
VPQC1 QB6REL
VPQC2 & >1
QB6ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB6_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB6_EX2
en04000554.vsd
IEC04000554 V1 EN-US
VPQA1
VPQC1 QB1REL
VPQC2 & >1
QB1ITL
1
VPQC11
QA1_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX2
VPQB1 QC1REL
VPQB6 QC1ITL
QB1_OP & 1
QC2REL
QB6_OP QC2ITL
VPQB6 1
VPQB9 QC3REL
VPCQB61 &
QC3ITL
1
QB6_OP
QB9_OP
CQB61_OP
VPQA1 QB9REL
VPQB6 QB9ITL
VPQC9 & >1 1
VPQC1
VPQC2
VPQC3
VPCQA1
VPCQB61
VPCQC1
VPCQC2
QB9_EX1
QB6_OP
QB9_EX2
>1
QA1_OP
QC1_OP
QC2_OP &
QB9_EX3
en04000555.vsd
IEC04000555 V1 EN-US
CQB61_OP
QB9_EX4
>1 & >1
CQA1_OP
CQC1_OP
CQC2_OP &
QB9_EX5
QC9_OP
QC3_OP
QB9_EX6
VPQC9
VPQC3
&
QC9_CL
QC3_CL
QB9_EX7
VPQB9 QC9REL
VPVOLT QC9ITL
QB9_OP & 1
VOLT_OFF
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
en04000556.vsd
IEC04000556 V1 EN-US
BH_LINE_B
QA1_OP
QA1_CL =1 VPQA1
QB2_OP
QB2_CL =1 VPQB2
QB6_OP
QB6_CL =1 VPQB6
QC9_OP
QC9_CL =1 VPQC9
QB9_OP
QB9_CL =1 VPQB9
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
CQA1_OP
CQA1_CL =1 VPCQA1
CQC1_OP
CQC1_CL =1 VPCQC1
CQC2_OP
CQC2_CL =1 VPCQC2
CQB62_OP
CQB62_CL =1 VPCQB62
QC21_OP
QC21_CL =1 VPQC21
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQB2 QA1CLREL
VPQB6 QA1CLITL
& 1
VPQB9
VPQA1
VPQC1 QB6REL
VPQC2 & >1
QB6ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB6_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB6_EX2
en04000557.vsd
IEC04000557 V1 EN-US
VPQA1
VPQC1 QB2REL
VPQC2 & >1
QB2ITL
1
VPQC21
QA1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQC1
VPQC21
&
QC1_CL
QC21_CL
EXDU_ES
QB2_EX2
VPQB2 QC1REL
VPQB6 QC1ITL
QB2_OP & 1
QC2REL
QB6_OP QC2ITL
VPQB6 1
VPQB9 QC3REL
VPCQB62 &
QC3ITL
1
QB6_OP
QB9_OP
CQB62_OP
VPQA1 QB9REL
VPQB6 QB9ITL
VPQC9 & >1 1
VPQC1
VPQC2
VPQC3
VPCQA1
VPCQB62
VPCQC1
VPCQC2
QB9_EX1
QB6_OP
QB9_EX2
>1
QA1_OP
QC1_OP
QC2_OP &
QB9_EX3
en04000558.vsd
IEC04000558 V1 EN-US
CQB62_OP
QB9_EX4
>1 & >1
CQA1_OP
CQC1_OP
CQC2_OP &
QB9_EX5
QC9_OP
QC3_OP
QB9_EX6
VPQC9
VPQC3
&
QC9_CL
QC3_CL
QB9_EX7
VPQB9 QC9REL
VPVOLT QC9ITL
QB9_OP & 1
VOLT_OFF
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
en04000559.vsd
IEC04000559 V1 EN-US
15.2.8.5 Signals
PID-3593-INPUTSIGNALS v9
PID-3593-OUTPUTSIGNALS v9
PID-3594-INPUTSIGNALS v9
PID-3594-OUTPUTSIGNALS v9
PID-3501-INPUTSIGNALS v9
PID-3501-OUTPUTSIGNALS v9
15.2.9.1 Identification
GUID-D6D10255-2818-44E4-A44E-DF623161C486 v3
The interlocking for a double busbar double circuit breaker bay including
DB_BUS_A, DB_BUS_B and DB_LINE functions are used for a line connected to
a double busbar arrangement according to figure 438.
WA1 (A)
WA2 (B)
QB1 QB2
QC1 QC4
QA1 QA2
DB_BUS_A DB_BUS_B
QC2 QC5
QB61 QB62
QC3
QB9
DB_LINE
QC9
en04000518.vsd
IEC04000518 V1 EN-US
M15105-1 v4
DB_BUS_A
QA1_OP
QA1_CL =1 VPQA1
QB61_OP
QB61_CL =1 VPQB61
QB1_OP
QB1_CL =1 VPQB1
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
QC11_OP
QC11_CL =1 VPQC11
VPQB61 QA1CLREL
VPQB1 & QA1CLITL
1
VPQA1
VPQC1 QB61REL
& >1
VPQC2 QB61ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB61_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB61_EX2
VPQA1
VPQC1 QB1REL
& >1
VPQC2 QB1ITL
1
VPQC11
QA1_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX2
en04000547.vsd
IEC04000547 V1 EN-US
VPQB61 QC1REL
VPQB1 QC1ITL
& 1
QB61_OP QC2REL
QB1_OP QC2ITL
1
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
en04000548.vsd
IEC04000548 V1 EN-US
DB_BUS_B
QA2_OP
QA2_CL =1 VPQA2
QB62_OP
QB62_CL =1 VPQB62
QB2_OP
QB2_CL =1 VPQB2
QC4_OP
QC4_CL =1 VPQC4
QC5_OP
QC5_CL =1 VPQC5
QC3_OP
QC3_CL =1 VPQC3
QC21_OP
QC21_CL =1 VPQC21
VPQB62 QA2CLREL
VPQB2 & QA2CLITL
1
VPQA2
VPQC4 QB62REL
& >1
VPQC5 QB62ITL
1
VPQC3
QA2_OP
QC4_OP
QC5_OP
QC3_OP
QB62_EX1
VPQC5
VPQC3
&
QC5_CL
QC3_CL
QB62_EX2
VPQA2
VPQC4 QB2REL
& >1
VPQC5 QB2ITL
1
VPQC21
QA2_OP
QC4_OP
QC5_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQC4
VPQC21
&
QC4_CL
QC21_CL
EXDU_ES
QB2_EX2
en04000552.vsd
IEC04000552 V1 EN-US
VPQB62 QC4REL
VPQB2 QC4ITL
& 1
QB62_OP QC5REL
QB2_OP QC5ITL
1
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
en04000553.vsd
IEC04000553 V1 EN-US
DB_LINE
QA1_OP
QA1_CL =1 VPQA1
QA2_OP
QA2_CL =1 VPQA2
QB61_OP
QB61_CL =1 VPQB61
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QB62_OP
QB62_CL =1 VPQB62
QC4_OP
QC4_CL =1 VPQC4
QC5_OP
QC5_CL =1 VPQC5
QB9_OP
QB9_CL =1 VPQB9
QC3_OP
QC3_CL =1 VPQC3
QC9_OP
QC9_CL =1 VPQC9
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQA1
VPQA2 QB9REL
VPQC1 & >1
QB9ITL
1
VPQC2
VPQC3
VPQC4
VPQC5
VPQC9
QA1_OP
QA2_OP
QC1_OP
QC2_OP
QC3_OP
QC4_OP
QC5_OP
QC9_OP
QB9_EX1
& en04000549.vsd
IEC04000549 V1 EN-US
VPQA1
VPQC1
VPQC2 & >1
VPQC3
VPQC9
VPQB62
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QC9_OP
QB62_OP
QB9_EX2
VPQA2
VPQB61
&
VPQC3
VPQC4
VPQC5
VPQC9
QA2_OP
QB61_OP
QC3_OP
QC4_OP
QC5_OP
QC9_OP
QB9_EX3
VPQC3
VPQC9
&
VPQB61
VPQB62
QC3_OP
QC9_OP
QB61_OP
QB62_OP
QB9_EX4
VPQC3
VPQC9
&
QC3_CL
QC9_CL
QB9_EX5
en04000550.vsd
IEC04000550 V1 EN-US
VPQB61
VPQB62 QC3REL
VPQB9 &
QC3ITL
1
QB61_OP
QB62_OP
QB9_OP
VPQB9
VPVOLT QC9REL
QB9_OP &
QC9ITL
1
VOLT_OFF
en04000551.vsd
IEC04000551 V1 EN-US
M13591-3 v6
DB_BUS_A
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB1_OP QB61REL
QB1_CL QB61ITL
QB61_OP QB1REL
QB61_CL QB1ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC3_OP QB1OPTR
QC3_CL QB1CLTR
QC11_OP VPQB1TR
QC11_CL
EXDU_ES
QB61_EX1
QB61_EX2
QB1_EX1
QB1_EX2
IEC05000354-2-en.vsd
IEC05000354 V2 EN-US
M15107-3 v6
DB_LINE
QA1_OP QB9REL
QA1_CL QB9ITL
QA2_OP QC3REL
QA2_CL QC3ITL
QB61_OP QC9REL
QB61_CL QC9ITL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QB62_OP
QB62_CL
QC4_OP
QC4_CL
QC5_OP
QC5_CL
QB9_OP
QB9_CL
QC3_OP
QC3_CL
QC9_OP
QC9_CL
VOLT_OFF
VOLT_ON
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
IEC05000356-2-en.vsd
IEC05000356 V2 EN-US
DB_BUS_B
QA2_OP QA2CLREL
QA2_CL QA2CLITL
QB2_OP QB62REL
QB2_CL QB62ITL
QB62_OP QB2REL
QB62_CL QB2ITL
QC4_OP QC4REL
QC4_CL QC4ITL
QC5_OP QC5REL
QC5_CL QC5ITL
QC3_OP QB2OPTR
QC3_CL QB2CLTR
QC21_OP VPQB2TR
QC21_CL
EXDU_ES
QB62_EX1
QB62_EX2
QB2_EX1
QB2_EX2
IEC05000355-2-en.vsd
IEC05000355 V2 EN-US
15.2.9.5 Signals
PID-3598-INPUTSIGNALS v9
PID-3598-OUTPUTSIGNALS v9
PID-3601-INPUTSIGNALS v9
PID-3601-OUTPUTSIGNALS v9
PID-3508-INPUTSIGNALS v10
PID-3508-OUTPUTSIGNALS v10
15.2.10.1 Identification
GUID-BEA26EA4-F402-4385-9238-1361E862D987 v3
The interlocking for line bay (ABC_LINE) function is used for a line connected to
a double busbar arrangement with a transfer busbar according to figure 442. The
function can also be used for a double busbar arrangement without transfer busbar
or a single busbar arrangement with/without transfer busbar.
WA1 (A)
WA2 (B)
WA7 (C)
QB1 QB2 QB7
QC1
QA1
QC2
QB9
QC9
en04000478.vsd
IEC04000478 V1 EN-US
ABC_LINE
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB9_OP QB9REL
QB9_CL QB9ITL
QB1_OP QB1REL
QB1_CL QB1ITL
QB2_OP QB2REL
QB2_CL QB2ITL
QB7_OP QB7REL
QB7_CL QB7ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC9_OP QC9REL
QC9_CL QC9ITL
QC11_OP QB1OPTR
QC11_CL QB1CLTR
QC21_OP QB2OPTR
QC21_CL QB2CLTR
QC71_OP QB7OPTR
QC71_CL QB7CLTR
BB7_D_OP QB12OPTR
BC_12_CL QB12CLTR
BC_17_OP VPQB1TR
BC_17_CL VPQB2TR
BC_27_OP VPQB7TR
BC_27_CL VPQB12TR
VOLT_OFF
VOLT_ON
VP_BB7_D
VP_BC_12
VP_BC_17
VP_BC_27
EXDU_ES
EXDU_BPB
EXDU_BC
QB9_EX1
QB9_EX2
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
QB7_EX1
QB7_EX2
QB7_EX3
QB7_EX4
IEC05000357-2-en.vsd
IEC05000357 V2 EN-US
ABC_LINE
QA1_OP
QA1_CL =1 VPQA1
QB9_OP
QB9_CL =1 VPQB9
QA1CLREL
QB1_OP
QB1_CL =1 VPQB1 QA1CLITL
& 1
QB2_OP
QB2_CL =1 VPQB2
QB7_OP
QB7_CL =1 VPQB7
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC9_OP
QC9_CL =1 VPQC9
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
QC71_OP
QC71_CL =1 VPQC71
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQA1
VPQC1 QB9REL
VPQC2 & >1
QB9ITL
1
VPQC9
QA1_OP
QC1_OP
QC2_OP
QC9_OP
QB9_EX1
VPQC2
VPQC9
&
QC2_CL
QC9_CL
QB9_EX2
en04000527.vsd
IEC04000527 V1 EN-US
VPQA1 QB1REL
& ³1
VPQB2
VPQC1 1 QB1ITL
VPQC2
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2 &
VP_BC_12
QB2_CL
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1 &
VPQC11
QC1_CL
QC11_CL
EXDU_ES
QB1EX3
en04000528.vsd
IEC04000528 V1 EN-US
VPQA1 QB2REL
& ³1
VPQB1
VPQC1 1 QB2ITL
VPQC2
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1 &
VP_BC_12
QB1_CL
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1 &
VPQC21
QC1_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000529.vsd
IEC04000529 V1 EN-US
VPQC9 QB7REL
& >1
VPQC71
VP_BB7_D 1 QB7ITL
VP_BC_17
VP_BC_27
QC9_OP
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_17_OP
BC_27_OP
EXDU_BC
QB7_EX1
VPQA1
VPQB1
VPQC9
&
VPQB9
VPQC71
VP_BB7_D
VP_BC_17
QA1_CL
QB1_CL
QC9_OP
QB9_CL
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_17_CL
EXDU_BC
QB7_EX2
IEC04000530 V1 EN-US
VPQA1
VPQB2
& >1
VPQC9
VPQB9
VPQC71
VP_BB7_D
VP_BC_27
QA1_CL
QB2_CL
QC9_OP
QB9_CL
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_27_CL
EXDU_BC
QB7_EX3
VPQC9
VPQC71
&
QC9_CL
QC71_CL
EXDU_ES
QB7_EX4
VPQB1 QC1REL
VPQB2 QC1ITL
VPQB9 & 1
QC2REL
QB1_OP
QB2_OP QC2ITL
1
QB9_OP
VPQB7
VPQB9 QC9REL
VPVOLT &
QC9ITL
QB7_OP 1
QB9_OP
VOLT_OFF
en04000531.vsd
IEC04000531 V1 EN-US
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB7_OP QB7OPTR
QB7_CL QB7CLTR
VPQB7 VPQB7TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
en04000532.vsd
IEC04000532 V1 EN-US
15.2.10.5 Signals
PID-3509-INPUTSIGNALS v10
PID-3509-OUTPUTSIGNALS v10
15.2.11.1 Identification
GUID-AD839CAA-531B-43BC-B508-39AED3D0A97D v3
WA1 (A)
WA2 (B)
QB1 QB2
QC1
QA1
AB_TRAFO
QC2
QC3
QA2
QA2 and QC4 are not
QC4 used in this interlocking
QB3 QB4
en04000515.vsd
IEC04000515 V1 EN-US
AB_TRAFO
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB1_OP QB1REL
QB1_CL QB1ITL
QB2_OP QB2REL
QB2_CL QB2ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QB3_OP QB1OPTR
QB3_CL QB1CLTR
QB4_OP QB2OPTR
QB4_CL QB2CLTR
QC3_OP QB12OPTR
QC3_CL QB12CLTR
QC11_OP VPQB1TR
QC11_CL VPQB2TR
QC21_OP VPQB12TR
QC21_CL
BC_12_CL
VP_BC_12
EXDU_ES
EXDU_BC
QA1_EX1
QA1_EX2
QA1_EX3
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
IEC05000358-2-en.vsd
IEC05000358 V2 EN-US
AB_TRAFO
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB2_OP
QB2_CL =1 VPQB2
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QB3_OP
QB3_CL =1 VPQB3
QB4_OP
QB4_CL =1 VPQB4
QC3_OP
QC3_CL =1 VPQC3
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
VPQB1 QA1CLREL
VPQB2 QA1CLITL
VPQC1 & 1
VPQC2
VPQB3
VPQB4
VPQC3
QA1_EX2
QC3_OP
QA1_EX3
QC1_CL >1
QC2_CL
QC3_CL &
QA1_EX1
en04000538.vsd
IEC04000538 V1 EN-US
VPQA1
VPQB2 QB1REL
& >1
VPQC1 QB1ITL
VPQC2 1
VPQC3
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC3_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2
VPQC3
&
VP_BC_12
QB2_CL
QC3_OP
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1
VPQC2
&
VPQC3
VPQC11
QC1_CL
QC2_CL
QC3_CL
QC11_CL
EXDU_ES
QB1_EX3
en04000539.vsd
IEC04000539 V1 EN-US
VPQA1
VPQB1 QB2REL
& >1
VPQC1 QB2ITL
VPQC2 1
VPQC3
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC3_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1
VPQC3
&
VP_BC_12
QB1_CL
QC3_OP
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1
VPQC2
&
VPQC3
VPQC21
QC1_CL
QC2_CL
QC3_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000540.vsd
IEC04000540 V1 EN-US
VPQB1 QC1REL
VPQB2 QC1ITL
& 1
VPQB3
QC2REL
VPQB4
QB1_OP QC2ITL
1
QB2_OP
QB3_OP
QB4_OP
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
en04000541.vsd
IEC04000541 V1 EN-US
15.2.11.5 Signals
PID-3510-INPUTSIGNALS v10
PID-3510-OUTPUTSIGNALS v10
15.2.12.1 Identification
GUID-3C4B9379-C861-406C-9295-0309014D548E v2
Position evaluation (POS_EVAL) function converts the input position data signal
POSITION, consisting of value, time and signal status, to binary signals
OPENPOS or CLOSEPOS.
The output signals are used by other functions in the interlocking scheme.
POS_EVAL
POSITION OPENPOS
CLOSEPOS
IEC09000079_1_en.vsd
IEC09000079 V1 EN-US
POS_EVAL
Position including quality POSITION OPENPOS
Open/close position of
CLOSEPOS switch device
IEC08000469-1-en.vsd
IEC08000469-1-EN V1 EN-US
Only the value, open/close, and status is used in this function. Time information is
not used.
Input position (Value) Signal quality Output OPENPOS Output CLOSEPOS
0 (Breaker Good 0 0
intermediate)
1 (Breaker open) Good 1 0
2 (Breaker closed) Good 0 1
3 (Breaker faulty) Good 0 0
Any Invalid 0 0
Any Oscillatory 0 0
15.2.12.5 Signals
PID-3555-INPUTSIGNALS v6
PID-3555-OUTPUTSIGNALS v6
The apparatus control functions are used for control and supervision of circuit
breakers, disconnectors and earthing switches within a bay. Permission to operate
is given after evaluation of conditions from other functions such as interlocking,
synchrocheck, operator place selection and external or internal blockings.
Normal security means that only the command is evaluated and the resulting
position is not supervised. Enhanced security means that the command is evaluated
with an additional supervision of the status value of the control object. The
command sequence with enhanced security is always terminated by a
CommandTermination service primitive and an AddCause telling if the command
was successful or if something went wrong.
Control operation can be performed from the local HMI with authority control if so
defined.
A bay can handle, for example a power line, a transformer, a reactor, or a capacitor
bank. The different primary apparatuses within the bay can be controlled via the
apparatus control functions directly by the operator or indirectly by automatic
sequences.
The SCSWI function block is connected either to an SXCBR function block (for
circuit breakers) or to an SXSWI function block (for disconnectors and earthing
Four types of function blocks are available to cover most of the control and
supervision within the bay. These function blocks are interconnected to form a
control function reflecting the switchyard configuration. The total number used
depends on the switchyard configuration. These types are:
Another function block type for supervision and control is the XLNPROXY. It is
used for interfacing a switch with its primary representation in a breaker IED.
XLNPROXY facilitates a common interface with the SXCBR and SXSWI
functions towards the SCSWI function, especially for command response and error
handling.
The principles of operation, function blocks, input and output signals and setting
parameters for all these functions are described below.
Depending on the error that occurs during the command sequence the error signal
will be set with a value. Table 522 describes the cause values given on local HMI.
The translation to AddCause values specified in IEC 61850-8-1 is shown in Table
523. For IEC 61850-8-1 edition 2 only addcauses defined in the standard are used,
for edition 1 also a number of vendor specific causes are used. The values are
available in the command response to commands from IE C61850-8-1 clients. An
output L_CAUSE on the function block for Switch controller (SCSWI), Circuit
breaker (SXCBR) and Circuit switch (SXSWI) indicates the value of the cause
during the latest command if the function specific command evaluation has been
started. The causes that are not always reflected on the output L_CAUSE, with
description of the typical reason are listed in table 524.
Table 522: Values for "cause" signal
Cause Name Description Supported
number
0 None Control action successfully executed X
1 Not-supported Given for Cancel request with Direct Control in Ready X
state
2 Blocked-by- Not successful since one of the downstream Loc X
switching-hierarchy switches like in CSWI has the value TRUE
Table continues on next page
Table 523: Translation of cause values for IEC 61850 edition 2 and edition 1
Internal Cause AddCause in IEC 61850-8-1 Name
Number
Ed 2 Ed 1
0 25 0 None
1 1 1 Not-supported
2 2 2 Blocked-by-switching-hierarchy
3 3 3 Select-failed
4 4 4 Invalid-position
5 5 5 Position-reached
6 6 6 Parameter-change-in-execution
7 7 7 Step-limit
8 8 8 Blocked-by-Mode
9 9 9 Blocked-by-process
10 10 10 Blocked-by-interlocking
11 11 11 Blocked-by-synchrocheck
12 12 12 Command-already-in-execution
13 13 13 Blocked-by-health
14 14 14 1-of-n-control
15 15 1 Abortion-by-cancel
16 16 16 Time-limit-over
17 17 17 Abortion-by-trip
Table continues on next page
The Bay control (QCBAY) function is used together with Local remote and local
remote control functions to handle the selection of the operator place per bay.
QCBAY also provides blocking functions that can be distributed to different
apparatuses within the bay.
QCBAY
LR_OFF PSTO
LR_LOC UPD_BLKD
LR_REM CMD_BLKD
LR_VALID LOC
BL_UPD STA
BL_CMD REM
IEC10000048-3-en.vsdx
IEC10000048 V3 EN-US
15.3.4.3 Signals
PID-4086-INPUTSIGNALS v8
PID-4086-OUTPUTSIGNALS v8
15.3.4.4 Settings
PID-4086-SETTINGS v8
The function sends information about the Permitted Source To Operate (PSTO) and
blocking conditions to other functions within the bay for example, switch control
functions and voltage control functions. The functionality of the Bay control
(QCBAY) function is mainly described by the LLN0 node in the IEC 61850-8-1
edition 2 standard, applied to one bay. In IEC 61850 edition 1 the functionality is
not described by the LLN0 node or any other node, therefore the Bay control
function is represented as a vendor specific node in edition 1.
The local panel switch is a switch that defines the operator place selection. The
switch connected to this function can have three positions (remote/local/off). The
positions are here defined so that remote means that operation is allowed from
station and/or remote level and local means that operation is allowed from the IED
level. The local/remote switch is also on the control/protection IED itself, which
means that the position of the switch and its validity information are connected
internally, not via I/O boards. When the switch is mounted separately from the IED
the signals are connected to the function via I/O boards.
When the local panel switch (or LHMI selection, depending on the set source to
select this) is in Off position, all commands from remote and local level will be
ignored. If the position for the local/remote switch is not valid the PSTO output
will always be set to faulty state (3), which means no possibility to operate.
To adapt the signals from the local HMI or from an external local/remote switch,
the function blocks LOCREM and LOCREMCTRL are needed and connected to
QCBAY.
The actual state of the operator place is presented by the value of the Permitted
Source To Operate, PSTO signal. The PSTO value is evaluated from the local/
remote switch position according to Table 528. In addition, there are two settings
and one command that affect the value of the PSTO signal.
operate from local, station and remote level without any priority. When the external
panel switch is in Off position, the PSTO output shows the actual state of the
switch that is, 0. In this case, it is not possible to control anything. The LocSta
command value is forced to FALSE if AllPSTOValid is set to No priority.
Blockings M13446-50 v5
The blocking states for position indications and commands are intended to provide
the possibility for the user to make common blockings for the functions configured
within a complete bay.
The blocking facilities provided by the bay control function are the following:
• Blocking of position indications, BL_UPD. This input will block all inputs
related to apparatus positions for all configured functions within the bay.
• Blocking of commands, BL_CMD. This input will block all commands for all
configured functions within the bay.
The switching of the Local/Remote switch requires at least system operator level.
The password will be requested at an attempt to operate if authority levels have
been defined in the IED, otherwise the default authority level can handle the
control without LogOn. The users and passwords are defined with the IED Users
tool in PCM600.
M17086-3 v8
The signals from the local HMI or from an external local/remote switch are
connected via the function blocks LOCREM and LOCREMCTRL to the Bay
control QCBAY function block. The parameter ControlMode in function block
LOCREM is set to choose if the switch signals are coming from the local HMI or
from an external hardware switch connected via binary inputs.
LOCREM
CTRLOFF OFF
LOCCTRL LOCAL
REMCTRL REMOTE
LHMICTRL VALID
IEC05000360-3-en.vsdx
IEC05000360 V3 EN-US
LOCREMCTRL
^PSTO1 HMICTR1
^PSTO2 HMICTR2
^PSTO3 HMICTR3
^PSTO4 HMICTR4
^PSTO5 HMICTR5
^PSTO6 HMICTR6
^PSTO7 HMICTR7
^PSTO8 HMICTR8
^PSTO9 HMICTR9
^PSTO10 HMICTR10
^PSTO11 HMICTR11
^PSTO12 HMICTR12
IEC05000361-3-en.vsdx
IEC05000361 V3 EN-US
15.3.5.2 Signals
PID-3944-INPUTSIGNALS v7
PID-3944-OUTPUTSIGNALS v7
PID-3943-INPUTSIGNALS v6
PID-3943-OUTPUTSIGNALS v6
15.3.5.3 Settings
PID-3944-SETTINGS v7
PID-3943-SETTINGS v2
The function block Local remote (LOCREM) handles the signals coming from the
local/remote switch. The connections are seen in Figure 450, where the inputs on
function block LOCREM are connected to binary inputs if an external switch is
used. When the local HMI is used, the inputs are not used. The switching between
external and local HMI source is done through the parameter ControlMode. The
outputs from the LOCREM function block control the output PSTO (Permitted
Source To Operate) on Bay control (QCBAY).
LOCREM QCBAY
CTRLOFF OFF LR_ OFF PSTO
LOCCTRL LOCAL LR_ LOC UPD_ BLKD
REMCTRL REMOTE LR_ REM CMD_ BLKD
LHMICTRL VALID LR_ VALID LOC
BL_ UPD STA
BL_ CMD REM
LOCREM QCBAY
CTRLOFF OFF LR_ OFF PSTO
LOCCTRL LOCAL LR_ LOC UPD_ BLKD
REMCTRL REMOTE LR_ REM CMD_ BLKD
LHMICTRL VALID LR_ VALID LOC
BL_ UPD STA
BL_ CMD REM
LOCREMCTRL
PSTO1 HMICTR1
PSTO2 HMICTR2
PSTO3 HMICTR3
PSTO4 HMICTR4
PSTO5 HMICTR5
PSTO6 HMICTR6
PSTO7 HMICTR7
PSTO8 HMICTR8
PSTO9 HMICTR9
PSTO 10 HMICTR 10
PSTO 11 HMICTR 11
PSTO 12 HMICTR 12
IEC10000052-1-en.vsd
IEC10000052 V2 EN-US
Figure 450: Configuration for the local/remote handling for a local HMI with two
bays and two screen pages
If the IED contains control functions for several bays, the local/remote position can
be different for the included bays. When the local HMI is used the position of the
local/remote switch can be different depending on which single line diagram screen
page that is presented on the local HMI. The function block Local remote control
(LOCREMCTRL) controls the presentation of the LEDs for the local/remote
position to applicable bay and screen page.
The switching of the local/remote switch requires at least system operator level.
The password will be requested at an attempt to operate if authority levels have
been defined in the IED. Otherwise the default authority level, SuperUser, can
handle the control without LogOn. The users and passwords are defined with the
IED Users tool in PCM600.
The Switch controller (SCSWI) initializes and supervises all functions to properly
select and operate switching primary apparatuses. The Switch controller may
handle and operate on one multi-phase device or up to three one-phase devices.
SCSWI
BLOCK EXE_OP
PSTO EXE_CL
L_SEL SEL_OP
L_OPEN SEL_CL
L_CLOSE SELECTED
AU_OPEN RES_RQ
AU_CLOSE START_SY
BL_CMD CANC_SY
RES_GRT POSITION
RES_EXT OPENP OS
SY_INPRO CLOSEPOS
SYNC_OK POLEDISC
EN_OPEN CMD_BLK
EN_CLOSE L_CAUSE
XPOSL1* POS_INTR
XPOSL2* XOU T
XPOSL3*
IEC05000337-5-en-us.vsdx
IEC05000337 V5 EN-US
15.3.6.3 Signals
PID-6798-INPUTSIGNALS v3
PID-6798-OUTPUTSIGNALS v3
GUID-7DABB496-EABE-48A4-8078-7ED5D6D4FE14 v2
15.3.6.4 Settings
PID-6798-SETTINGS v3
The Switch controller (SCSWI) is provided with verification checks for the select -
execute sequence, that is, checks the conditions prior each step of the operation are
fulfilled. The involved functions for these condition verifications are interlocking,
reservation, blockings and synchrocheck.
.
Two types of control models can be used. The two control models are "direct with
normal security" and "SBO (Select-Before-Operate) with enhanced security". The
parameter CtlModel defines which one of the two control models is used. The
control model "direct with normal security" does not require a select whereas, the
"SBO with enhanced security" command model requires a select before execution.
The command sequence for a command with control mode SBO with enhanced
security is shown in figure 452, with control mode direct with normal security is
shown in figure 453.
Reservation SXCBR /
Client SCSWI
logic SXSWI
select
SEL_CL = TRUE
RES_RQ = TRUE
tReservation
Response
tSelect
RES_GRT = TRUE
SELECTED = TRUE
selectAck/AddCause = 0
requestedPosition = 10
opRcvd = TRUE
EXE_CL
RES_RQ = FALSE
RES_GRT = FALSE
IEC15000416-2-EN.vsdx
IEC15000416 V2 EN-US
requestedPosition = 10
opRcvd = TRUE
RES_RQ
tReservation
Response
RES_GRT = TRUE
EXE_CL
operateAck/AddCause = 0 operateAck/AddCause = 0
RES_RQ = FALSE
RES_GRT = FALSE
IEC15000417-1-en.vsdx
IEC15000417 V1 EN-US
Normal security means that only the command is evaluated and the resulting
position is not supervised. Enhanced security means that the command sequence is
supervised in three steps, the selection, command evaluation and the supervision of
position. Each step ends up with a pulsed signal to indicate that the respective step
in the command sequence is finished. If an error occurs in one of the steps in the
command sequence, the sequence is terminated. The last error (L_CAUSE) can be
read from the function block and used for example at commissioning.
The position output from the switches (SXCBR or SXSWI) is connected to the
switch controller SCSWI. The XPOSL1, XPOSL2 and XPOSL3 input signals
receive the position, time stamps and quality attributes of the position which is
used for further evaluation.
In the case when there are two or more one-phase switches connected to the switch
control function, the switch control will "merge" the position of the switches to the
resulting multi-phase position. In the case when the position differ between the
one-phase switches, following principles will be applied:
The time stamp of the output multi-phase position from switch control will have
the time stamp of the last changed phase when it reaches the end position. When it
goes to intermediate position or bad state, it will get the time stamp of the first
changed phase.
In addition, there is also the possibility that one of the one-phase switches will
change position at any time due to a trip. Such situation is here called pole
discordance and is supervised by this function. In case of a pole discordance
situation, that is, the positions of the one-phase switches are not equal for a time
longer than the setting tPoleDiscord, an error signal POLEDISC will be set.
In the supervision phase, the switch controller function evaluates the "cause"
values from the switch modules circuit breaker (SXCBR)/circuit switch (SXSWI).
At error the "cause" value with highest priority is shown.
The blocking signals are normally coming from the bay control function (QCBAY)
and via the IEC 61850 communication from the operator place.
The different block conditions will only affect the operation of this
function, that is, no blocking signals will be "forwarded" to other
functions. The above blocking outputs are stored in a non-volatile
memory.
For the commands from a communication protocol, such as IEC 61850-8-1 and
DNP, and through the inputs L_SEL, L_OPEN and L_CLOSE, the operator place is
evaluated, and only the commands from enabled operator places are accepted, see
Table 528. Commands through the inputs L_SEL, L_OPEN and L_CLOSE are
always from the local operator place. For commands through the inputs AU_OPEN
and AU_CLOSE, the operator place is not evaluated. If the operator place is set to
Off, the commands through the inputs AU_OPEN and AU_CLOSE are not accepted.
The Switch controller (SCSWI) works in conjunction with the synchrocheck and
the synchronizing function (SESRSYN). It is assumed that the synchrocheck
function is continuously in operation and gives the result to SCSWI. The result
from the synchrocheck function is evaluated during the close execution. If the
operator performs an override of the synchrocheck, the evaluation of the
synchrocheck state is omitted. When there is a positive confirmation from the
synchrocheck function, SCSWI will send the close signal EXE_CL to the switch
function Circuit breaker (SXCBR).
SCSWI SXCBR
EXE_CL
OR CLOSE
SYNC_OK
START_SY
CANC_SY
SY_INPRO
SESRSYN
CLOSECB
Synchro Synchronizing
check function
IEC09000209-2-en.vsd
IEC09000209 V2 EN-US
The Switch controller (SCSWI) function has timers for evaluating different time
supervision conditions. These timers are explained here.
The timer tSelect is used for supervising the time between the select and the
execute command signal, that is, the time the operator has to perform the command
execution after the selection of the object to operate.
select
execute command
tSelect
timer t1 t1>tSelect, then long-
operation-time in 'cause'
is set
en05000092.vsd
IEC05000092 V1 EN-US
The parameter tResResponse is used to set the maximum allowed time to make the
reservation, that is, the time between reservation request and the feedback
reservation granted from all bays involved in the reservation function.
select
The timer tExecutionFB supervises the time between the execute command and the
command termination, see Figure 457.
execute command
position L1 open
close
position L2 open
close
position L3 open
close
cmd termination L1
cmd termination L2
cmd termination L3
cmd termination *
position open
close
t1>tExecutionFB, then
tExecutionFB timer long-operation-time in
t1 'cause' is set
The parameter tSynchrocheck is used to define the maximum allowed time between
the execute command and the input SYNC_OK to become true. If SYNC_OK=true
at the time the execute command signal is received, the timer "tSynchrocheck" will
not start. The start signal for the synchronizing is obtained if the synchrocheck
conditions are not fulfilled.
execute command
SYNC_OK
tSynchrocheck
t1
START_SY
SY_INPRO
en05000095.vsd
IEC05000095 V1 EN-US
When the switches are modelled and controlled in a breaker IED, the information
from the switches is limited to those described in the IEC 61850 standard.
Since there is no expression for distributing the cause of failure over GOOSE, the
XLNPROXY function is used for evaluating the causes normally evaluated by the
SXCBR and SXSWI functions.
Further, in some cases selection may also be used on the model of the switch in the
breaker IED, in case multiple controllers may access it via GOOSE. In such a case,
if the input for the stSeld data attribute in the XLNPROXY function is connected,
SCSWI automatically awaits that the switch is selected before accepting the
selection. Also, if the seSeld data attribute is set before the selection is requested,
the selection request fails.
Reservation
Client SCSWI XLNPROXY XCBR/XSWI
logic
select
tReservation
Response
tSelect
RES_GRT = TRUE
SELECTED = TRUE Pos.stSeld = TRUE
SELECTED = TRUE
selectAck/AddCause = 0
requestedPosition = 10
opRcvd = TRUE
OpCls.stVal = TRUE
cmdTermination/AddCause = 0
SELECTED = FALSE
SEL_CL = FALSE
RES_RQ = FALSE
RES_GRT = FALSE
IEC16000069-1-EN.vsdx
IEC16000069 V1 EN-US
The purpose of Circuit breaker (SXCBR) is to provide the actual status of positions
and to perform the control operations, that is, pass all the commands to primary
apparatuses in the form of circuit breakers via binary output boards and to
supervise the switching operation and position.
SXCBR
BLOCK XPOS
LR_SWI EXE_OP
OPEN EXE_CL
CLOSE OP_BLKD
BL_OPEN CL_BLKD
BL_CLOSE UPD_BLKD
BL_UPD OPENP OS
POSOP EN CLOSEPOS
POSCLOSE TR_POS
CBOPCAP CNT_VAL
TR_OPEN L_CAUSE
TR_CLOSE EEHEALTH
RS_CNT CBOPCAP
EEH_WARN
EEH_ALM
XIN*
IEC05000338-4-en.vsdx
IEC05000338 V5 EN-US
15.3.7.3 Signals
PID-6799-INPUTSIGNALS v2
PID-6799-OUTPUTSIGNALS v2
15.3.7.4 Settings
PID-6799-SETTINGS v2
The circuit breaker function (SXCBR) is used by other functions such as, for
example, switch controller, protection functions, autorecloser function or an IEC
61850 client residing in another IED or the operator place. This switch function
executes commands, evaluates block conditions and evaluates different time
supervision conditions. Only if all conditions indicate a switch operation to be
SXCBR has an operation counter for closing and opening commands. The counter
value can be read remotely from the operator place. The value is reset from local
HMI, a binary input or remotely from the operator place by configuring a signal
from the Single Point Generic Control 8 signals (SPC8GAPC) for example. The
health of the external equipment, the switch, can be monitored according to IEC
61850-8-1. The operation counter functionality and the external equipment health
supervision are independent sub-functions of the circuit breaker function.
One binary input signal LR_SWI is included in SXCBR to indicate the local/
remote switch position from switchyard provided via the I/O board. If this signal is
set to TRUE it means that change of position is allowed only from switchyard
level. If the signal is set to FALSE it means that command from IED or higher
level is permitted. When the signal is set to TRUE all commands (for change of
position) are rejected, even trip commands from protection functions are rejected.
The functionality of the local/remote switch is described in Figure 461.
Local= Operation at
UE switch yard level
TR
en05000096.vsd
IEC05000096 V1 EN-US
SXCBR includes several blocking principles. The basic principle for all blocking
signals is that they will affect commands from all other clients for example, switch
controller, protection functions and autoreclosure.
• Block/deblock for open command. It is used to block operation for the open
command.
• Block/deblock for close command. It is used to block operation for the close
command.
• Update block/deblock of positions. It is used to block the updating of position
values. Other signals related to the position will be reset.
• Blocking of function, BLOCK. If BLOCK signal is set, it means that the
function is active, but no outputs are generated, no reporting, control
commands are rejected and functional and configuration data is visible.
Substitution M13487-22 v5
The substitution part in SXCBR is used for manual set of the position and quality
of the switch. The typical use of substitution is that an operator enters a manual
value because that the real process value is erroneous for some reason. SXCBR
will then use the manually entered value instead of the value for positions
determined by the process.
There are two timers for supervising of the execute phase, tStartMove and
tIntermediate. tStartMove supervises that the primary device starts moving after the
execute output pulse is sent. tIntermediate defines the maximum allowed time for
intermediate position. Figure 462 explains these two timers during the execute
phase.
OPENPOS
CLOSEPOS
en05000097.vsd
IEC05000097 V1 EN-US
The timers tOpenPulse and tClosePulse are the length of the execute output pulses
to be sent to the primary equipment. Note that the output pulses for open and close
command can have different pulse lengths. The pulses can also be set to be
adaptive with the configuration parameter AdaptivePulse. Figure 463 shows the
principle of the execute output pulse. The AdaptivePulse parameter will have effect
on both execute output pulses.
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
EXE_CL
tClosePulse
AdaptivePulse=TRUE
EXE_CL
tClosePulse
en05000098.vsd
IEC05000098 V1 EN-US
If the pulse is set to be adaptive, it is not possible for the pulse to exceed
tOpenPulse or tClosePulse.
• the new expected final position is reached and the configuration parameter
AdaptivePulse is set to true
• the timer tOpenPulse or tClosePulse has elapsed
• an error occurs due to the switch does not start moving, that is, tStartMove has
elapsed.
If the breaker reaches the final position before the execution pulse
time has elapsed, and AdaptivePulse is not true, the function waits
for the end of the execution pulse before telling the activating
function that the command is completed.
There is one exception to the first item above: if the primary device is in open
position and an open command is executed or if the primary device is in closed
position and a close command is executed. In these cases, with the additional
condition that the configuration parameter AdaptivePulse is true, the execute output
pulse is always activated and resets when tStartMove has elapsed. If the
configuration parameter AdaptivePulse is set to false, the execution output remains
active until the pulse duration timer has elapsed.
OPENPOS
CLOSEPOS
EXE_OP AdaptivePulse=FALSE
tOpenPulse
EXE_OP AdaptivePulse=TRUE
tOpenPulse
tStartMove timer
en05000099.vsd
IEC05000099 V1 EN-US
The purpose of Circuit switch (SXSWI) function is to provide the actual status of
positions and to perform the control operations, that is, pass all the commands to
primary apparatuses in the form of disconnectors or earthing switches via binary
output boards and to supervise the switching operation and position.
SXSWI
BLOCK XPOS
LR_SWI EXE_OP
OPEN EXE_CL
CLOSE OP_BLKD
BL_OPEN CL_BLKD
BL_CLOSE UPD_BLKD
BL_UPD OPENP OS
POSOP EN CLOSEPOS
POSCLOSE CNT_VAL
SWOPCAP L_CAUSE
RS_CNT EEHEALTH
EEH_WARN SWOPCAP
EEH_ALM
XIN*
IEC05000339-4-en.vsdx
IEC05000339 V4 EN-US
15.3.8.3 Signals
PID-6800-INPUTSIGNALS v3
PID-6800-OUTPUTSIGNALS v3
15.3.8.4 Settings
PID-6800-SETTINGS v3
The users of the Circuit switch (SXSWI) are other functions such as for example,
switch controller, protection functions, autorecloser function, or a 61850 client
residing in another IED or the operator place. SXSWI executes commands,
evaluates block conditions and evaluates different time supervision conditions.
Only if all conditions indicate a switch operation to be allowed, SXSWI performs
the execution command. In case of erroneous conditions, the function indicates an
appropriate "cause" value, see Table 522.
SXSWI has an operation counter for closing and opening commands. The counter
value can be read remotely from the operator place. The value is reset from a
binary input or remotely from the operator place by configuring a signal from the
Single Point Generic Control 8 signals (SPC8GAPC), for example.
Also, the health of the external equipment, the switch, can be monitored according
to IEC 61850-8-1.
One binary input signal LR_SWI is included in SXSWI to indicate the local/remote
switch position from switchyard provided via the I/O board. If this signal is set to
TRUE it means that change of position is allowed only from switchyard level. If
the signal is set to FALSE it means that command from IED or higher level is
permitted. When the signal is set to TRUE all commands (for change of position)
from internal IED clients are rejected, even trip commands from protection
functions are rejected. The functionality of the local/remote switch is described in
Figure 466.
Local= Operation at
UE switch yard level
TR
en05000096.vsd
IEC05000096 V1 EN-US
SXSWI includes several blocking principles. The basic principle for all blocking
signals is that they will affect commands from all other clients for example, switch
controller, protection functions and autorecloser.
Substitution M16494-21 v7
The substitution part in SXSWI is used for manual set of the position and quality of
the switch. The typical use of substitution is that an operator enters a manual value
because the real process value is erroneous of some reason. SXSWI will then use
the manually entered value instead of the value for positions determined by the
process.
There are two timers for supervising of the execute phase, tStartMove and
tIntermediate. tStartMove supervises that the primary device starts moving after the
execute output pulse is sent. tIntermediate defines the maximum allowed time for
intermediate position. Figure 467 explains these two timers during the execute
phase.
OPENPOS
CLOSEPOS
en05000097.vsd
IEC05000097 V1 EN-US
The timers tOpenPulse and tClosePulse are the length of the execute output pulses
to be sent to the primary equipment. Note that the output pulses for open and close
command can have different pulse lengths. The pulses can also be set to be
adaptive with the configuration parameter AdaptivePulse. Figure 468 shows the
principle of the execute output pulse. The AdaptivePulse parameter will have effect
on both execute output pulses.
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
EXE_CL
tClosePulse
AdaptivePulse=TRUE
EXE_CL
tClosePulse
en05000098.vsd
IEC05000098 V1 EN-US
If the pulse is set to be adaptive, it is not possible for the pulse to exceed
tOpenPulse or tClosePulse.
• the new expected final position is reached and the configuration parameter
AdaptivePulse is set to true
• the timer tOpenPulse or tClosePulse has elapsed
• an error occurs due to the switch does not start moving, that is, tStartMove has
elapsed.
If the controlled primary device reaches the final position before the
execution pulse time has elapsed, and AdaptivePulse is not true, the
function waits for the end of the execution pulse before telling the
activating function that the command is completed.
There is one exception from the first item above. If the primary device is in open
position and an open command is executed or if the primary device is in close
position and a close command is executed. In these cases, with the additional
condition that the configuration parameter AdaptivePulse is true, the execute output
pulse is always activated and resets when tStartMove has elapsed. If the
configuration parameter AdaptivePulse is set to false the execution output remains
active until the pulse duration timer has elapsed.
OPENPOS
CLOSEPOS
EXE_OP AdaptivePulse=FALSE
tOpenPulse
EXE_OP AdaptivePulse=TRUE
tOpenPulse
tStartMove timer
en05000099.vsd
IEC05000099 V1 EN-US
The proxy for signals from switching device via GOOSE (XLNPROXY) gives an
internal representation of the position status and control response for a switch
modelled in a breaker IED. This representation is identical to that of an SXCBR or
SXSWI function.
XLNPROXY
BEH* XPOS
BEH_VALID* SELECTED
LOC* OP_BLKD
LOC_VALID* CL_BLKD
BLKOPN* OPENPOS
BLKOPN_V* CLOSEPOS
BLKCLS* CNT_VAL
BLKCLS_V* L_CAUSE
POSVAL* EEHEALTH
POSVAL_V* OPCAP
OPCNT*
OP_CNT_V*
BLK
BLK_VAL
STSELD
STSELD_V
OPRCVD
OPRCVD_V
OPOK
OPOK_VAL
EEHEALTH
EEH_VAL
OPCAP
OPCAP_V
COMMVALID
XIN
IEC16000043-1-en.vsdx
IEC16000043 V1 EN-US
15.3.9.3 Signals
PID-6712-INPUTSIGNALS v3
PID-6712-OUTPUTSIGNALS v3
15.3.9.4 Settings
PID-6712-SETTINGS v3
GUID-A4CCC681-D4D8-4534-905D-1D8AD40E923B v1
The proxy for signals from switching device via GOOSE (XLNPROXY) is
intended to be used when the switch (XCBR/XSWI) is modelled and controlled in
a breaker IED or similar unit on the process bus. XLNPROXY packages the signals
from the GOOSE receive function, normally GOOSEXLNRCV, into the same
format as used from SXCBR and SXSWI to SCSWI. It makes a similar evaluation
of the command response as SXCBR and SXSWI when a command is issued from
the connected SCSWI.
XLNPROXY has two outputs for position indication: OPENPOS and CLOSEPOS.
Position is a double point indication and the OPENPOS and CLOSEPOS are binary
outputs intended to be used for condition logics to protection and control functions
Normally, the position outputs, OPENPOS and CLOSEPOS, follow the value of
the input POSVAL. However, if the POSVAL_V input is FALSE, the
communication is lost (COMMVALID = FALSE), or the quality of the position
received is bad, the OPENPOS and CLOSEPOS are both set to FALSE.
The command evaluation is triggered through the group input XIN that is
connected to the SCSWI function controlling the switch.
desired position within the two time limits tStartMove and tIntermediate. The
default values for tStartMove and tIntermediate are for a breaker. The typical
values for a disconnector are:
• tStartMove = 3s
• tIntermediate = 15s
When the switch has started moving, it issues a response to the SCSWI function
that the operation has started. If it does not start moving within tStartMove, the
command is deemed as failed, and a cause is raised on the L_CAUSE output and
sent to the SCSWI. The different causes it can identify are listed in order of priority
in table 1. The detection of the different ways of blocking is done while waiting for
movement of the switch, but the cause is not given until the tStartMove has
elapsed.
Table 546: Possible cause values from XLNPROXY
Cause Cause Description Conditions
No
8 Blocked-by-Mode The BEH input is 5.
2 Blocked-by-switching-hierarchy The LOC input indicates that only local commands are
allowed for the breaker IED function.
-24 Blocked-for-open-cmd The BLKOPN is active indicating that the switch is
blocked for open commands.
-25 Blocked-for-close-cmd The BLKCLS is active indicating that the switch is
blocked for close commands.
9 Blocked-by-process If the Blk input is connected and active indicating that the
switch is dynamically blocked. Or if the OPCAP input is
connected, it indicates that the operation capability of the
switch is not enough to perform the command.
5 Position-reached Switch is already in the intended position.
-31 Switch-not-start-moving Switch did not start moving within tStartMove.
-32 Persistent-intermediate-state The switch stopped in intermediate state for longer than
tIntermediate.
-33 Switch-returned-to-init-pos Switch returned to the initial position.
-34 Switch-in-bad-state Switch is in a bad position.
-35 Not-expected-final-position Switch did not reach the expected final position.
The L_CAUSE output keeps its output value until a new command sequence has
been started.
If the quality of the position or the communication becomes bad, the command
evaluation replaces the uncertain position value with intermediate position. Thus,
as long as the quality is bad, all commands will result in the cause Persistant-
intermediate-state, -32.
If the switch in the merging unit has the behaviour set to Test or Test
blocked, when the IED has the behaviour On or Blocked, all data from the
switch is regarded as invalid. Thus, any command will fail with the cause
PersistantiIntermediate-state, -32, and if selection is used for the switch, all
attempts to select the connected SCSWI will fail with the cause Select-failed, 3,
from the SCSWI.
It is possible to speed up the command response for when the command has been
started by the switch in the breaker IED by connecting the inputs OPOK and
OPOK_VAL. Then the blocking check is only done until OPOK is activated and
confirmation of that the command has been started is given to the SCSWI function.
If the inputs STSELD and STSELD_V are connected, the switch in the breaker
IED is assumed to use selection. Then the SCSWI will wait for a selected
indication, STSELD input of XLNPROXY, before accepting selection, this
information is transferred to the SCSWI function from the XLNPROXY through
the group connection XPOS. If STSELD is not activated within tSelect of the
SCSWI function, the selection is deemed failed and it gives a negative selection
acknowledgement to the command issuer with the cause Select-failed. Further, if
the communication is lost, or the data received is deemed invalid, the selection will
also fail with cause Select-failed from the SCSWI.
QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_RQ2 RES_GRT3
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6
RES_RQ6 RES_GRT7
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
BLOCK ACK_TO_B
OVERRIDE RESERVED
RES_DATA EXCH_OUT
IEC05000340-3-en.vsdx
IEC05000340 V3 EN-US
15.3.10.3 Signals
PID-3561-INPUTSIGNALS v7
PID-3561-OUTPUTSIGNALS v7
15.3.10.4 Settings
PID-3561-SETTINGS v7
The Bay reserve (QCRSV) function handles the reservation. QCRSV function
starts to operate in two ways. It starts when there is a request for reservation of the
own bay or if there is a request for reservation from another bay. It is only possible
to reserve the function if it is not currently reserved. The signal that can reserve the
own bay is the input signal RES_RQx (x=1-8) coming from switch controller
(SCWI). The signals for request from another bay are the outputs RE_RQ_B and
V_RE_RQ from function block RESIN. These signals are included in signal
EXCH_OUT from RESIN and are connected to RES_DATA in QCRSV.
The parameters ParamRequestx (x=1-8) are chosen at reservation of the own bay
only (TRUE) or other bays (FALSE). To reserve the own bay only means that no
reservation request RES_BAYS is created.
If the reservation request comes from the own bay, the function QCRSV has to
know which apparatus the request comes from. This information is available with
the input signal RES_RQx and parameter ParamRequestx (where x=1-8 is the
number of the requesting apparatus). In order to decide if a reservation request of
the current bay can be permitted QCRSV has to know whether the own bay already
is reserved by itself or another bay. This information is available in the output
signal RESERVED.
If the RESERVED output is not set, the selection is made with the output
RES_GRTx (where x=1-8 is the number of the requesting apparatus), which is
connected to switch controller SCSWI. If the bay already is reserved the command
sequence will be reset and the SCSWI will set the attribute "1-of-n-control" in the
"cause" signal.
When the function QCRSV receives a request from an apparatus in the own bay
that requires other bays to be reserved as well, it checks if it already is reserved. If
not, it will send a request to the other bays that are predefined (to be reserved) and
wait for their response (acknowledge). The request of reserving other bays is done
by activating the output RES_BAYS.
When it receives acknowledge from the bays via the input RES_DATA, it sets the
output RES_GRTx (where x=1-8 is the number of the requesting apparatus). If not
acknowledgement from all bays is received within a certain time defined in SCSWI
(tResResponse), the SCSWI will reset the reservation and set the attribute "1-of-n-
control" in the "cause" signal.
When another bay requests for reservation, the input BAY_RES in corresponding
function block RESIN is activated. The signal for reservation request is grouped
into the output signal EXCH_OUT in RESIN, which is connected to input
RES_DATA in QCRSV. If the bay is not reserved, the bay will be reserved and the
acknowledgment from output ACK_T_B is sent back to the requested bay. If the
bay already is reserved the reservation is kept and no acknowledgment is sent.
This can be set, for example, via a binary input from an external device to prevent
operations from another operator place at the same time.
The reservation function can also be overridden in the own bay with the
OVERRIDE input signal, that is, reserving the own bay without waiting for the
external acknowledge.
If only one instance of QCRSV is used for a bay that is, use of up to eight
apparatuses, the input EXCH_IN must be set to zero.
If there are more than eight apparatuses in the bay, there has to be one additional
QCRSV. The two QCRSV functions have to communicate and this is done through
the input EXCH_IN and EXCH_OUT according to Figure 472. If more than one
QCRSV are used, the execution order is very important. The execution order must
be in the way that the first QCRSV has a lower number than the next one.
QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_RQ2 RES_GRT3
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6
RES_RQ6 RES_GRT7
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
BLOCK ACK_TO_B
OVERRIDE RESERVED
RES_DATA EXCH_OUT
QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_BAYS
RES_RQ2 RES_GRT3 1
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6 ACK_TO_B
RES_RQ6 RES_GRT7 1
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
1
BLOCK ACK_TO_B RESERVED
OVERRIDE RESERVED
RES_DATA EXCH_OUT
IEC05000088-3-en.vsdx
IEC05000088 V3 EN-US
The Reservation input (RESIN) function receives the reservation information from
other bays. The number of instances is the same as the number of involved bays
(up to 60 instances are available).
RESIN1
BAY_ACK ACK_F_B
BAY_VAL ANY_ACK
BAY_RES VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
IEC05000341-2-en.vsd
IEC05000341 V2 EN-US
RESIN2
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
BAY_VAL VALID_TX
BAY_RES RE_RQ_B
V_RE_RQ
EXCH_OUT
IEC09000807_1_en.vsd
IEC09000807 V1 EN-US
15.3.11.3 Signals
PID-3629-INPUTSIGNALS v7
PID-3629-OUTPUTSIGNALS v7
PID-3630-INPUTSIGNALS v7
PID-3630-OUTPUTSIGNALS v7
15.3.11.4 Settings
PID-3629-SETTINGS v7
PID-3630-SETTINGS v7
EXCH_IN INT
BIN
ACK_F_B
&
FutureUse
³1
ANY_ACK
BAY_ACK ³1
VALID_TX
&
BAY_VAL ³1
RE_RQ_B
³1
BAY_RES &
V _RE_RQ
³1
BIN
EXCH_OUT
INT
en05000089.vsd
IEC05000089 V1 EN-US
Figure 476 describes the principle of the data exchange between all RESIN
modules in the current bay. There is one RESIN function block per "other bay"
used in the reservation mechanism. The output signal EXCH_OUT in the last
RESIN functions are connected to the module bay reserve (QCRSV) that handles
the reservation function in the own bay.
RESIN
BAY_ACK ACK_F_B
Bay 1 BAY_VAL ANY_ACK
BAY_RES VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
RESIN
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
Bay 2 BAY_VAL VALID_TX
BAY_RES RE_RQ_B
V_RE_RQ
EXCH_OUT
RESIN
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
Bay n BAY_VAL VALID_TX
BAY_RES RE_RQ_B QCRSV
V_RE_RQ
EXCH_OUT RES_DATA
en05000090.vsd
IEC05000090 V2 EN-US
15.4.1 Identification
SEMOD173054-2 v5
IEC10000165 V1 EN-US
IEC10000166 V1 EN-US
Automatic voltage control for tap changer, single control (TR1ATCC), Automatic
voltage control for tap changer, parallel control (TR8ATCC), Tap changer control
and supervision, 6 binary inputs (TCMYLTC) and Tap changer control and
supervision, 32 binary inputs (TCLYLTC) are used for control of power
transformers with an on-load tap changer. The functions provide automatic
regulation of the voltage on the secondary side of transformers or alternatively on a
load point further out in the network.
Voltage control includes many extra features such as the possibility to avoid
simultaneous tapping of parallel transformers, hot stand by regulation of a
transformer in a group which regulates it to a correct tap position even though the
LV CB is open, compensation for a possible capacitor bank on the LV side bay of a
transformer, extensive tap changer monitoring including contact wear and hunting
detection, monitoring of the power flow in the transformer so that, for example, the
voltage control can be blocked if the power reverses, etc.
SEMOD158823-5 v4
The Automatic voltage control for tap changer TR1ATCC for single control and
TR8ATCC for parallel control function controls the voltage on the LV side of a
transformer either automatically or manually. The automatic control can be either
for a single transformer, or for a group of parallel transformers.
The LV-side of the transformer is used as the voltage measuring point. If necessary,
the LV side current is used as load current to calculate the line-voltage drop to the
regulation point. This current is also used when parallel control with the circulating
current method is used.
In addition, all three-phase currents from the HV-winding (usually the winding
where the tap changer is situated) are used by the Automatic voltage control for tap
changer TR1ATCC for single control and TR8ATCC for parallel control function
for over current blocking.
side. The involved phases are also selected. Thus, single-phases as well as phase-
phase or three-phase feeding on the LV-side is possible but it is commonly selected
for current and voltage.
The analog input signals are normally common for other functions in the IED for
example, protection functions.
Automatic voltage control for tap changer, single control TR1ATCC SEMOD158887-4 v5
Automatic voltage control for tap changer, single control TR1ATCC measures the
magnitude of the busbar voltage UB. If no other additional features are enabled
(line voltage drop compensation), this voltage is further used for voltage
regulation.
TR1ATCC then compares this voltage with the set voltage, USet and decides which
action should be taken. To avoid unnecessary switching around the setpoint, a
deadband (degree of insensitivity) is introduced. The deadband is symmetrical
around USet, see figure 477, and it is arranged in such a way that there is an outer
and an inner deadband. Measured voltages outside the outer deadband start the
timer to initiate tap commands, whilst the sequence resets when the measured
voltage is once again back inside the inner deadband. One half of the outer
deadband is denoted ΔU. The setting of ΔU, setting Udeadband should be set to a
value near to the power transformer’s tap changer voltage step (typically 75–125%
of the tap changer step).
Security Range
*) *) *)
Raise Cmd DU DU Lower Cmd
DUin DUin
IEC06000489_2_en.vsd
IEC06000489 V2 EN-US
During normal operating conditions the busbar voltage UB, stays within the outer
deadband (interval between U1 and U2 in figure 477). In that case no actions will
be taken by the TR1ATCC. However, if UB becomes smaller than U1, or greater
than U2, an appropriate lower or raise timer will start. The timer will run as long as
the measured voltage stays outside the inner deadband. If this condition persists
longer than the preset time delay, TR1ATCC will initiate that the appropriate
ULOWER or URAISE command will be sent from Tap changer control and
supervision, 6 binary inputs TCMYLTC, or 32 binary inputs TCLYLTC to the
transformer load tap changer. If necessary, the procedure will be repeated until the
magnitude of the busbar voltage again falls within the inner deadband. One half of
the inner deadband is denoted ΔUin. The inner deadband ΔUin, setting
UDeadbandInner should be set to a value smaller than ΔU. It is recommended to
set the inner deadband to 25-70% of the ΔU value.
This way of working is used by TR1ATCC while the busbar voltage is within the
security range defined by settings Umin and Umax
Instead of controlling the voltage at the LV busbar in the same substation as the
transformer itself, it is possible to control the voltage at a load point out in the
network, downstream from the transformer. The Line Voltage Drop Compensation
(LDC) can be selected by a setting parameter, and it works such that the voltage
drop from the transformer location to the load point is calculated based on the
measured load current and the known line impedance.
Three alternative methods can be used for parallel control with Automatic control
for tap changer, parallel control TR8ATCC:
• master-follower method
• reverse reactance method
• circulating current method.
The followers can act in one of two alternative ways selected by a setting
parameter:
In the reverse reactance method, the LDC (Line voltage drop compensation) is
used. The purpose of which is normally to control the voltage at a load point
further out in the network. The very same function can also be used here but with a
completely different objective. Whereas the LDC, when used to control the voltage
at a load point, gives a voltage drop along a line from the busbar voltage UB to a
load point voltage UL, the LDC, when used in the reverse reactance parallel control
of transformers, gives a voltage increase (actually, by adjusting the ratio XL/RL
with respect to the power factor, the length of the vector UL will be approximately
equal to the length of UB) from UB up towards the transformer itself.
When the voltage at a load point is controlled by using LDC, the line impedance
from the transformer to the load point is defined by the setting Xline. If a negative
reactance is entered instead of the normal positive line reactance, parallel
transformers will act in such a way that the transformer with a higher tap position
will be the first to tap down when the busbar voltage increases, and the transformer
with a lower tap position will be the first to tap up when the busbar voltage
decreases. The overall performance will then be that a runaway tap situation will be
avoided and that the circulating current will be minimized.
This method requires extensive exchange of data between the TR8ATCC function
blocks (one TR8ATCC function for each transformer in the parallel group). The
TR8ATCC function block can either be located in the same IED, where they are
configured in PCM600 to co-operate, or in different IEDs. If the functions are
located in different IEDs they must communicate via GOOSE interbay
communication on the IEC 61850 communication protocol.
If the functions are located in different IEDs they must communicate via GOOSE
interbay communication on the IEC 61850 communication protocol. Complete
exchange of TR8ATCC data, analog as well as binary, via GOOSE is made
cyclically every 300 ms.
The main objectives of the circulating current method for parallel voltage control
are:
The busbar voltage UB is measured individually for each transformer in the parallel
group by its associated TR8ATCC function. These measured values will then be
exchanged between the transformers, and in each TR8ATCC block, the mean value
of all UB values will be calculated. The resulting value UBmean will then be used in
each IED instead of UB for the voltage regulation, thus assuring that the same value
is used by all TR8ATCC functions, and thereby avoiding that one erroneous
measurement in one transformer could upset the voltage regulation. At the same
time, supervision of the VT mismatch is also performed.
IT1 IT2
UB
IL IL
UL Load UL Load
IEC06000484_3_en.vsd
IEC06000484 V3 EN-US
It can be shown that the magnitude of the circulating current in this case can be
approximately calculated with the formula:
UT1 - UT 2
I cc _ T 1 = I cc _ T 2 =
ZT 1 + ZT 2
EQUATION1866 V1 EN-US (Equation 218)
UT1 CT1*ICC_T1*ZT1
UB
CT2*ICC_T2*ZT2
UT2
IL
IT2 IT1
2*Udeadband
ICC_T2 ICC_T1
T2 Receives Cir_Curr T1 Produces Cir_Curr
IL = IT1+ IT2
Icc_T1 = Imag {IT1- (ZT2/(ZT1+ZT2)) * IL}
Icc_T2 = Imag {IT2- (ZT1/(ZT1+ZT2)) * IL}
en06000525.vsd
IEC06000525 V1 EN-US
Figure 479: Vector diagram for two power transformers working in parallel
Thus, by minimizing the circulating current flow through transformers, the total
reactive power flow is optimized as well. In the same time, at this optimum state
the apparent power flow is distributed among the transformers in the group in
proportion to their rated power.
In order to calculate the circulating current, measured current values for the
individual transformers must be communicated between the participating
TR8ATCC functions. It should be noted that the Fourier filters in different IEDs
run asynchronously, which means that current and voltage phasors cannot be
exchanged and used for calculation directly between the IEDs. In order to
“synchronize” measurements within all IEDs in the parallel group, a common
reference must be chosen. The most suitable reference quantity for all transformers,
belonging to the same parallel group, is the busbar voltage. This means that the
measured busbar voltage is used as a reference phasor in all IEDs, and the position
of the current phasors in a complex plane is calculated in respect to this reference.
This is a simple and effective solution, which eliminates any additional need for
synchronization between the IEDs regarding TR8ATCC function.
At each transformer bay, the real and imaginary parts of the current on the
secondary side of the transformer are calculated from measured values, and
distributed to the TR8ATCC functions belonging to the same parallel group.
As mentioned before, only the imaginary part (reactive current component) of the
individual transformer current is needed for the circulating current calculations.
The real part of the current will, however, be used to calculate the total through
load current and will be used for the line voltage drop compensation.
The total load current is defined as the sum of all individual transformer currents:
k
I L = å Ii
i =1
where the subscript i signifies the transformer bay number and k the number of
parallel transformers in the group (k≤ 8). Next step is to extract the circulating
current Icc_i that flows in bay i. It is possible to identify a term in the bay current
which represents the circulating current. The magnitude of the circulating current
in bay i, Icc_i , can be calculated as:
I cc _ i = - Im( I i - K i ´ I L )
EQUATION1868 V1 EN-US (Equation 220)
In this way each TR8ATCC function calculates the circulating current of its own
bay.
A plus sign means that the transformer produces circulating current while, a minus
sign means that the transformer receives circulating current.
As a next step, it is necessary to estimate the value of the no-load voltage in each
transformer. To do that the magnitude of the circulating current in each bay is first
converted to a voltage deviation, Udi, with the following formula:
U di = Ci ´ I cc _ i ´ X i
EQUATION1869 V1 EN-US (Equation 221)
Now the magnitude of the no-load voltage for each transformer can be
approximated with:
U i = U Bmean + U di
EQUATION1870 V1 EN-US (Equation 222)
Generally speaking, this value for the no-load voltage can then be put into the
voltage control function in a similar way as for the single transformer described
previously. Ui would then be regarded similarly to the single transformer measured
busbar voltage, and further control actions taken.
For the transformer producing/receiving the circulating current, the calculated no-
load voltage will be greater/smaller than the measured voltage UBmean. The
calculated no-load voltage will thereafter be compared with the set voltage USet. A
steady deviation which is outside the outer deadband will result in ULOWER or
URAISE being initiated alternatively. In this way the overall control action will
always be correct since the position of a tap changer is directly related to the
transformer no-load voltage. The sequence resets when UBmean is inside the inner
deadband at the same time as the calculated no-load voltages for all transformers in
the parallel group are inside the outer deadband. The example in figure 480,is a
fabricated case and not very realistic, but it illustrates some details on how the
described regulation works.
T1 T2 T3 T4
UBmean
T1 No-load voltage
DB1
DB2
USet
DB2
DB1
IEC06000526_2_en.vsd
IEC06000526 V2 EN-US
In the figure 480, voltage is considered as increasing above the line denoted USet,
and decreasing below that line.
In the TR8ATCC function for T1 and T4, the calculated no-load voltage for T1 and
T4 respectively, is above the upper limit of DB1 and thus outside the deadband.
In the TR8ATCC function for T2, the calculated no-load voltage for T2, viewed
from the upper DB1, is not outside (above) the deadband, but as viewed from the
lower DB1 it is outside (below) the deadband. However, there is a restriction in a
situation like this, when the measured busbar voltage, UBmean, is on the opposite
side of the USet line (in figure 480), then UBmean must be inside DB1 if the
calculated no-load voltage for that transformer shall qualify as a candidate for
tapping. Thus in the example above, the calculated no-load voltage for T2,
although below DB1, would not be considered for tapping in this case.
In the TR8ATCC function for T3, the calculated no-load voltage for T3, is above
the upper limit of DB1 and thus outside the deadband. However, viewed from the
upper limit DB1, transformers with negative voltage deviation, Udi, are disregarded
and similarly, viewed from the lower limit DB1, transformers with positive voltage
deviation, Udi, are disregarded. Thus in the example above, the calculated no-load
voltage for T3, although above DB1, would not be considered in this case. Thus in
the example above, the calculated no-load voltage for T3, although above DB1,
would not be considered for tapping in this case.
AUTO
UL a
a<b
< &
U1 INNER DB b &
a
a>b
>
U2 INNER DB b &
a
a<b
>1 URAISE
<
U1 DB b
a
a>b
>1
> >1 ULOWER
U2 DB b
UB a
a>b
>
U MAX b &
FSD &
en06000509.vsd
IEC06000509 V1 EN-US
Figure 481: Simplified logic for automatic control in single mode operation
AUTO
PARALLEL START
&
OPERSIMTAP
UL a
a<b
< &
U1 INNER DB b &
&
a
a>b
>
U2 INNER DB b &
U CIRCCOMP
&
MIN a
a<b
>1 URAISE
<
U1 DB b >1
U CIRCCOMP
MAX a
a>b
>1
> >1 ULOWER
U2 DB b >1
UB a
a>b
>
U MAX b &
FSD &
en06000511.vsd
IEC06000511 V1 EN-US
Figure 482: Simplified logic for parallel control in the circulating current mode
UCCT4 a
a=b
b &
T4PG &
T4
UCCT3 a 1
a=b & ³1
b & & &
T3PG T3 SIMLOWER
³1
UCCT2 a
a=b
1 &
b & &
T2
T2PG
UCCT1 a &
a=b
1 &
& T1
b
MAX
T1PG
a
a=b
b &
&
T1
a 1
a=b & ³1
b & & &
T2PG T2 SIMRAISE
³1
a
a=b
1 &
b & &
T3
T3PG
a &
a=b
1 &
T4
b &
T4PG
MIN
ADAPT
a
³1
a=b
ActualUser S b
³1 1
³1
Udeadband S a
a=b
b
LoadVoltage
HOMING
OperSimTap
1
en06000521.vsd
IEC06000521 V1 EN-US
relativePosition a
a<b
<
raiseVoltageOut
b &
&
lowerVoltageOut
a
a>b
> =
b & URAISE
& 1
Follow Tap
&
& =
ULOWER
1 1
YLTCOUT ® ATCCIN
tapPosition &
&
tapInHighVoltPos
tapInLowVoltPos
en06000510.vsd
IEC06000510 V1 EN-US
SEMOD171466-5 v5
The Tap changer control and supervision, 6 binary inputs (TCMYLTC) and 32
binary inputs TCLYLTC gives the tap commands to the tap changer, and supervises
that commands are carried through correctly. It has built-in extensive possibilities
for tap changer position measurement, as well as supervisory and monitoring
features. This is used in the voltage control and can also give information about tap
position to the transformer differential protection.
The tap changer position can be received to the tap changer control and
supervision, 6 binary inputs TCMYLTC or 32 binary inputs TCLYLTC function
block in the following ways:
1. Via binary input signals, one per tap position (max. 6 or 32 positions).
2. Via coded binary (Binary), binary coded decimal (BCD) signals, or Gray
coded binary signals.
3. Via a mA input signal.
In this option, each tap position has a separate contact that is hard wired to a binary
input in the IED. Via the Signal Matrix tool in PCM600, the contacts on the binary
input card are then directly connected to the
• inputs B1 – B6 on TCMYLTC function
• or inputs B1 – B32 on TCLYLTC function.
Via coded binary (Binary), binary coded decimal (BCD) signals or Gray
coded binary signals SEMOD159170-24 v3
It is also possible to use even parity check of the input binary signal. Whether the
parity check shall be used or not is set with the setting parameter UseParity.
The truth table (see table 556) shows the conversion for Binary, Binary Coded
Decimal, and Gray coded signals.
IEC06000522 V1 EN-US
The Gray code conversion above is not complete and therefore the conversion from
decimal numbers to Gray code is given below.
IEC06000523 V1 EN-US
Any of the six inputs on the mA card (MIM) can be used for the purpose of tap
changer position reading connected to the Tap changer control and supervision, 6
binary inputs TCMYLTC or 32 binary inputs TCLYLTC.
The measurement of the tap changer position via MIM module is based on the
principle that the specified mA input signal range (usually 4-20 mA) is divided into
N intervals corresponding to the number of positions available on the tap changer.
All mA values within one interval are then associated with one tap changer
position value.
The two function blocks Automatic voltage control for tap changer, single control
TR1ATCC and parallel control TR8ATCC and Tap changer control and
supervision, 6 binary inputs TCMYLTC and 32 binary inputs TCLYLTC are
connected to each other according to figure 485 below.
(Rmk. In case of
parallel control,
this signal shall
TR8ATCC TCLYLTC also be connected
I3P1 ATCCOUT YLTCIN URAISE to HORIZx input of
I3P2 MAN TCINPROG ULOWER the parallel
U3P2 AUTO INERR HIPOSAL transformer
BLOCK IBLK RESETERR LOPOSAL TR8ATCC function
MANCTRL PGTFWD OUTERR POSERRAL
block)
AUTOCTRL PLTREV RS_CLCNT CMDERRAL
PSTO QGTFWD RS_OPCNT TCERRAL
RAISEV QLTREV PARITY POSOUT
LOWERV REVACBLK BIERR CONVERR
EAUTOBLK UHIGH B1 NEWPOS
DEBLKAUT ULOW B2 HIDIFPOS
LVA1 UBLK B3 INVALPOS
LVA2 HOURHUNT B4 YLTCOUT
LVA3 DAYHUNT B5
LVA4 HUNTING B6
LVARESET SINGLE B7
RSTERR PARALLEL B8
DISC HOMING B9
Q1ON ADAPT B10
Q2ON TOTBLK B11
Q3ON AUTOBLK B12
SNGLMODE MASTER B13
T1INCLD FOLLOWER B14
T2INCLD MFERR B15
T3INCLD OUTOFPOS B16
T4INCLD COMMERR B17
T5INCLD ICIRC B18
T6INCLD TRFDISC B19
T7INCLD VTALARM B20
T8INCLD T1PG B21
FORCMAST T2PG B22
RSTMAST T3PG B23
ATCCIN T4PG B24
HORIZ1 T5PG B25
HORIZ2 T6PG B26
HORIZ3 T7PG B27
HORIZ4 T8PG B28
HORIZ5 B29
HORIZ6 B30
HORIZ7 B31
HORIZ8 B32
MA
IEC06000507_2_en.vsd
IEC06000507 V2 EN-US
The TR8ATCC and TR1ATCC function blocks have an output signal ATCCOUT,
which is connected to input YLTCIN on TCMYLTC. The data set sent from
ATCCOUT to YLTCIN contains 5 binary signals, one “word” containing 10 binary
signals and 1 analog signal. For TR8ATCC data is also sent from output
ATCCOUT to other TR8ATCC function input HORIZx, when the master-follower
or circulating current mode is used.
In case of parallel control of transformers, the data set sent from output signal
ATCCOUT to other TR8ATCC blocks input HORIZx contains one "word"
containing 10 binary signals and 6 analog signals:
Table 561: Binary signals contained in word “status”: ATCCOUT / HORIZx
Signal Description
TimerOn This signal is activated by the transformer that has started its timer and is
going to tap when the set time has expired.
automaticCTRL Activated when the transformer is set in automatic control
mutualBlock Activated when the automatic control is blocked
disc Activated when the transformer is disconnected from the busbar
receiveStat Signal used for the horizontal communication
Table continues on next page
Signal Description
TermIsForcedMaster Activated when the transformer is selected Master in the master-follower
parallel control mode
TermIsMaster Activated for the transformer that is master in the master-follower parallel
control mode
termReadyForMSF Activated when the transformer is ready for master-follower parallel control
mode
raiseVoltageOut Order from the master to the followers to tap up
lowerVoltageOut Order from the master to the followers to tap down
SEMOD173000-4 v4
TR1ATCC
I3P1* ATCCOUT
I3P2* MAN
U3P2* AUTO
BLOCK IBLK
MANCTRL PGTFWD
AUTOCTRL PLTREV
PSTO QGTFWD
RAISEV QLTREV
LOWERV REVACBLK
EAUTOBLK UHIGH
DEBLKAUT ULOW
LVA1 UBLK
LVA2 HOURHUNT
LVA3 DAYHUNT
LVA4 HUNTING
LVARESET TIMERON
RSTERR TOTBLK
ATCCIN AUTOBLK
UGTUPPDB
ULTLOWDB
IEC07000041_2_en.vsd
IEC07000041 V2 EN-US
SEMOD172997-4 v5
TR8ATCC
I3P1* ATCCOUT
I3P2* MAN
U3P2* AUTO
BLOCK IBLK
MANCTRL PGTFWD
AUTOCTRL PLTREV
PSTO QGTFWD
RAISEV QLTREV
LOWERV REVACBLK
EAUTOBLK UHIGH
DEBLKAUT ULOW
LVA1 UBLK
LVA2 HOURHUNT
LVA3 DAYHUNT
LVA4 HUNTING
LVARESET SINGLE
RSTERR PARALLEL
DISC TIMERON
Q1ON HOMING
Q2ON ADAPT
Q3ON TOTBLK
SNGLMODE AUTOBLK
T1INCLD MASTER
T2INCLD FOLLOWER
T3INCLD MFERR
T4INCLD OUTOFPOS
T5INCLD UGTUPPDB
T6INCLD ULTLOWDB
T7INCLD COMMERR
T8INCLD ICIRC
FORCMAST TRFDISC
RSTMAST VTALARM
ATCCIN T1PG
HORIZ1 T2PG
HORIZ2 T3PG
HORIZ3 T4PG
HORIZ4 T5PG
HORIZ5 T6PG
HORIZ6 T7PG
HORIZ7 T8PG
HORIZ8
IEC07000040_2_en.vsd
IEC07000040 V2 EN-US
TCMYLTC
YLTCIN* URAISE
TCINPROG ULOWER
INERR HIPOSAL
RESETERR LOPOSAL
OUTERR POSERRAL
RS_CLCNT CMDERRAL
RS_OPCNT TCERRAL
PARITY POSOUT
BIERR CONVERR
B1 NEWPOS
B2 HIDIFPOS
B3 INVALPOS
B4 YLTCOUT
B5
B6
MA
IEC07000038-3-en.vsdx
IEC07000038 V3 EN-US
SEMOD173023-4 v3
TCLYLTC
YLTCIN* URAISE
TCINPROG ULOWER
INERR HIPOSAL
RESETERR LOPOSAL
OUTERR POSERRAL
RS_CLCNT CMDERRAL
RS_OPCNT TCERRAL
PARITY POSOUT
BIERR CONVERR
B1 NEWPOS
B2 HIDIFPOS
B3 INVALPOS
B4 TCPOS
B5 YLTCOUT
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
MA
IEC07000037_2_en.vsd
IEC07000037 V2 EN-US
VCTRRCV
BLOCK VCTR_REC
COMVALID
DATVALID
IEC07000045-2-en.vsd
IEC07000045 V2 EN-US
15.4.7 Signals
PID-6562-INPUTSIGNALS v3
PID-6562-OUTPUTSIGNALS v3
PID-6559-INPUTSIGNALS v3
PID-6559-OUTPUTSIGNALS v3
PID-6506-INPUTSIGNALS v5
PID-6506-OUTPUTSIGNALS v5
PID-3668-INPUTSIGNALS v6
PID-3668-OUTPUTSIGNALS v7
PID-923-INPUTSIGNALS v6
PID-923-OUTPUTSIGNALS v6
15.4.8 Settings
PID-6562-SETTINGS v3
PID-6559-SETTINGS v3
PID-6506-SETTINGS v5
PID-3668-SETTINGS v6
PID-6559-MONITOREDDATA v3
PID-6506-MONITOREDDATA v5
PID-3669-MONITOREDDATA v2
PID-3668-MONITOREDDATA v6
The voltage control function is built up by two function blocks. Both are logical
nodes in IEC 61850-8-1.
TCMYLTC and TCLYLTC are an interface between TR1ATCC and TR8ATCC and
the transformer load tap changer. More specifically this means that it receives
information from TR1ATCC or TR8ATCC and based on this it gives command-
pulses to a power transformer motor driven on-load tap changer and also receives
information from the load tap changer regarding tap position, progress of given
commands, and so on.
TCMYLTC and TCLYLTC also serve the purpose of giving information about tap
position to the transformer differential protection T2WPDIF and T3WPDIF.
15.5.1 Identification
SEMOD167845-2 v3
The logic rotating switch for function selection and LHMI presentation (SLGAPC)
(or the selector switch function block) is used to get an enhanced selector switch
functionality compared to the one provided by a hardware selector switch.
Hardware selector switches are used extensively by utilities, in order to have
different functions operating on pre-set values. Hardware switches are however
sources for maintenance issues, lower system reliability and an extended purchase
portfolio. The selector switch function eliminates all these problems.
SLGAPC
BLOCK ^P01
PSTO ^P02
UP ^P03
DOWN ^P04
^P05
^P06
^P07
^P08
^P09
^P10
^P11
^P12
^P13
^P14
^P15
^P16
^P17
^P18
^P19
^P20
^P21
^P22
^P23
^P24
^P25
^P26
^P27
^P28
^P29
^P30
^P31
^P32
SWPOSN
IEC14000005-1-en.vsd
IEC14000005 V1 EN-US
15.5.4 Signals
PID-6641-INPUTSIGNALS v3
PID-6641-OUTPUTSIGNALS v3
15.5.5 Settings
PID-6641-SETTINGS v3
The logic rotating switch for function selection and LHMI presentation (SLGAPC)
function has two operating inputs – UP and DOWN. When a signal is received on
the UP input, the function will activate the output next to the present activated
output, in ascending order (for example if the present activated output is P03 and
one activates the UP input then the output P04 will be activated). When a signal is
received on the DOWN input, the function will activate the output next to the
present activated output, in descending order (for example if the present activated
output is P03 and one activates the DOWN input then the output P02 will be
activated). Depending on the output settings the output signals can be steady or
pulsed. In case of steady signals, the output will be active till the time it receives
next operation of UP/DOWN inputs. Also, depending on the settings one can have
a time delay between activation of the UP or DOWN input signals and the output
activation.
• if it is used just for the monitoring, the switches will be listed with their actual
position names, as defined by the user (max. 13 characters).
• if it is used for control, the switches will be listed with their actual positions,
but only the first three letters of the name will be used.
In both cases, the switch full name will be shown, but the user has to redefine it
when building the Graphical Display Editor, under the "Caption". If used for the
control, the following sequence of commands will ensure:
Control
Control Sing le Line Diagram
Measurements Comma nds
Events
Disturb ance r eco rds
Settings
Diagno stics
Test
Chang e to the "Switche s" pag e Reset
of the SLD by left-righ t arrows. Authori zation
Sele ct switch by up-down Lan guage
arro ws
../Control/SLD/Switch
O I ../Control/SLD/Switch
Damage control
P: Disc N: Disc Fe
DAL
The pos will not b e mod ified
(outputs will not b e activa ted) unt il OK Cancel
you press the Enter button for O.K.
../Control/SLD/Switch
SMBRREC control
WFM
Pilo t se tup
OFF
Damage control
DFW
IEC06000421-3-en.vsdx
IEC06000421 V3 EN-US
Figure 492: Example 2 on handling the switch from the local HMI.
From the single line diagram on local HMI.
15.6.1 Identification
SEMOD167850-2 v4
VSGAPC can be controlled from the menu, from a symbol on the single line
diagram (SLD) on the local HMI or from Binary inputs
VSGAPC
BLOCK BLOCKED
PSTO POSITION
IPOS1 POS1
IPOS2 POS2
CMDPOS12
CMDPOS21
IEC14000066-1-en.vsd
IEC14000066 V1 EN-US
15.6.4 Signals
PID-6504-INPUTSIGNALS v6
PID-6504-OUTPUTSIGNALS v6
15.6.5 Settings
PID-6504-SETTINGS v6
Selector mini switch (VSGAPC) function can be used for double purpose, in the
same way as switch controller (SCSWI) functions are used:
• for indication on the single line diagram (SLD). Position is received through
the IPOS1 and IPOS2 inputs and distributed in the configuration through the
POS1 and POS2 outputs, or to IEC 61850 through reporting, or GOOSE.
• for commands that are received via the local HMI or IEC 61850 and
distributed in the configuration through outputs CMDPOS12 and CMDPOS21.
The output CMDPOS12 is set when the function receives a CLOSE command
from the local HMI when the SLD is displayed and the object is chosen.
The output CMDPOS21 is set when the function receives an OPEN command
from the local HMI when the SLD is displayed and the object is chosen.
The PSTO input is connected to the Local remote switch to have a selection of
operators place, operation from local HMI (Local) or through IEC 61850 (Remote).
An INTONE connection from Fixed signal function block (FXDSIGN) will allow
operation from local HMI.
The following table shows the relationship between IPOS1/IPOS2 inputs and the
name of the string that is shown on the SLD. The value of the strings are set in
PST.
IPOS1 IPOS2 Name of displayed Default string value
string
0 0 PosUndefined P00
1 0 Position1 P01
0 1 Position2 P10
1 1 PosBadState P11
15.7.1 Identification
GUID-E16EA78F-6DF9-4B37-A92D-5C09827E2297 v3
IEC13000081 V1 EN-US
PID-4139-INPUTSIGNALS v12
PID-4139-OUTPUTSIGNALS v11
The function does not have any parameters available in the local HMI or PCM600.
When receiving the input signals, DPGAPC sends the signals over IEC 61850-8-1
to the systems, equipment or functions that requests and thus subscribes on these
signals. To be able to get the signals into other systems, equipment or functions,
one must use other tools, described in the Engineering manual, and define which
function block in which systems, equipment or functions should receive this
information.
When the input signal VALID is active, the values of the OPEN and CLOSE inputs
determine the two-bit integer value of the output POSITION. The timestamp of the
output POSITION will have the latest updated timestamp of the inputs OPEN and
CLOSE.
When the input signal VALID is inactive, DPGAPC function forces the position to
intermediated state.
When the value of the input signal VALID changes, the timestamp of the output
POSITION will be updated as the time when DPGAPC function detects the
change.
Refer to Table 600 for the description of the input-output relationship in terms of
the value and the quality attributes.
15.8.1 Identification
SEMOD176456-2 v3
SPC8GAPC
BLOCK ^OUT1
PSTO ^OUT2
^OUT3
^OUT4
^OUT5
^OUT6
^OUT7
^OUT8
IEC07000143-3-en.vsd
IEC07000143 V3 EN-US
15.8.4 Signals
PID-3575-INPUTSIGNALS v8
PID-3575-OUTPUTSIGNALS v8
15.8.5 Settings
PID-3575-SETTINGS v8
The PSTO input selects the operator place (LOCAL, REMOTE or ALL). One of
the eight outputs is activated based on the command sent from the operator place
selected. The settings Latchedx and tPulsex (where x is the respective output) will
determine if the signal will be pulsed (and how long the pulse is) or latched
(steady). BLOCK will block the operation of the function – in case a command is
sent, no output will be activated.
15.9.1 Identification
GUID-C3BB63F5-F0E7-4B00-AF0F-917ECF87B016 v4
Automation bits function for DNP3 (AUTOBITS) is used within PCM600 to get
into the configuration of the commands coming through the DNP3 protocol. The
AUTOBITS function plays the same role as functions GOOSEBINRCV (for IEC
61850) and MULTICMDRCV (for LON).
AUTOBITS
BLOCK ^CMDBIT1
PSTO ^CMDBIT2
^CMDBIT3
^CMDBIT4
^CMDBIT5
^CMDBIT6
^CMDBIT7
^CMDBIT8
^CMDBIT9
^CMDBIT10
^CMDBIT11
^CMDBIT12
^CMDBIT13
^CMDBIT14
^CMDBIT15
^CMDBIT16
^CMDBIT17
^CMDBIT18
^CMDBIT19
^CMDBIT20
^CMDBIT21
^CMDBIT22
^CMDBIT23
^CMDBIT24
^CMDBIT25
^CMDBIT26
^CMDBIT27
^CMDBIT28
^CMDBIT29
^CMDBIT30
^CMDBIT31
^CMDBIT32
IEC09000925-1-en.vsd
IEC09000925 V1 EN-US
15.9.4 Signals
PID-3776-INPUTSIGNALS v6
PID-3776-OUTPUTSIGNALS v6
15.9.5 Settings
PID-3776-SETTINGS v6
There is a BLOCK input signal, which will disable the operation of the function, in
the same way the setting Operation: On/Off does. That means that, upon activation
of the BLOCK input, all 32 CMDBITxx outputs will be set to 0. The BLOCK acts
like an overriding, the function still receives data from the DNP3 master. Upon
deactivation of BLOCK, all the 32 CMDBITxx outputs will be set by the DNP3
master again, momentarily. For AUTOBITS , the PSTO input determines the
operator place. The command can be written to the block while in “Remote”. If
PSTO is in “Local” then no change is applied to the outputs.
15.10.1 Identification
GUID-2217CCC2-5581-407F-A4BC-266CD6808984 v1
The IEDs can receive commands either from a substation automation system or
from the local HMI. The command function block has outputs that can be used, for
example, to control high voltage apparatuses or for other user defined functionality.
SINGLECMD
BLOCK ^OUT1
^OUT2
^OUT3
^OUT4
^OUT5
^OUT6
^OUT7
^OUT8
^OUT9
^OUT10
^OUT11
^OUT12
^OUT13
^OUT14
^OUT15
^OUT16
IEC05000698-2-en.vsd
IEC05000698 V3 EN-US
15.10.4 Signals
PID-6189-INPUTSIGNALS v6
PID-6189-OUTPUTSIGNALS v6
15.10.5 Settings
PID-6189-SETTINGS v6
The output signals can be of the types Off, Steady, or Pulse. This configuration
setting is done via the local HMI or PCM600 and is common for the whole
function block. The length of the output pulses are 100 ms. In steady mode,
SINGLECMD function has a memory to remember the output values at power
interruption of the IED. Also a BLOCK input is available used to block the
updating of the outputs.
The output signals, OUT1 to OUT16, are available for configuration to built-in
functions or via the configuration logic circuits to the binary outputs of the IED.
16.1.1 Identification
M14854-1 v4
To achieve instantaneous fault clearance for all line faults, scheme communication
logic is provided. All types of communication schemes for permissive
underreaching, permissive overreaching, blocking, delta based blocking,
unblocking and intertrip are available.
ZCPSCH
I3P* TRIP
U3P* CS
BLOCK CHSTOP
BLKTR CRL
BLKCS LCG
CSBLK
CACC
CSOR
CSUR
CR
CRG
CBOPEN
IEC09000004
IEC09000004 V4 EN-US
16.1.4 Signals
PID-3766-INPUTSIGNALS v7
PID-3766-OUTPUTSIGNALS v5
16.1.5 Settings
PID-3766-SETTINGS v7
A permissive scheme is inherently faster and has better security against false
tripping than a blocking scheme. On the other hand, a permissive scheme depends
on a received signal for a fast trip, so its dependability is lower than that of a
blocking scheme.
The received signal, which shall be connected to CR, is used to block the zone to
be accelerated to clear the fault instantaneously (after time tCoord). The forward
overreaching zone to be accelerated is connected to the input CACC, see
figure 499.
In case of external faults, the blocking signal (CR) must be received before the
settable timer tCoord elapses to prevent a false trip, see figure 499.
The function can be totally blocked by activating the input BLOCK. Tripping can
be blocked by activating the input BLKTR. Signal send can be blocked by
activating the input BLKCS.
tCoord
CACC
t TRIP
CR AND
en05000512.vsd
IEC05000512 V1 EN-US
In order to avoid delays due to carrier coordination times, the initiation of sending
of blocking signal to remote end is done by a fault inception detection element
based on delta quantities of currents and voltages. The delta based fault detection is
very fast and if the channel is fast there is no need for delaying the operation of the
remote distance element. The received blocking signal arrives well before the
distance element has started. If the fault is in forward direction the sending is
immediately stopped by a forward directed distance, directional current or
directional earth fault element.
The fault inception detection element detects instantaneous changes in any phase
currents or zero sequence current in combination with a change in the
corresponding phase voltage or zero sequence voltage. The criterion for the fault
inception detection is if the change of any phase voltage and current exceeds the
settings DeltaU and DeltaI respectively, or if the change of zero sequence voltage
and zero sequence current exceeds the settings Delta3U0,Delta3I0 respectively.
The schemeType is selected as DeltaBlocking.
If the fault inception function has detected a system fault, a block signal CS will be
issued and sent to remote end in order to block the overreaching zones. Different
criteria has to be fulfilled for sending the CS signal:
1. The breaker has to be in closed condition, that is, the input signal CBOPEN is
deactivated.
2. A fault inception should have been detected while the carrier send signal is not
blocked, that is, the input signal BLKCS is not activated.
If it is later detected that it was an internal fault that made the function issue the CS
signal, the function will issue a CHSTOP signal to unblock the remote end.
The received signal, which is connected to the CR input, is not used to accelerate
the release of the overreaching zone to clear the fault instantaneously. The
overreaching zone to be accelerated is connected to the input CACC, see Figure
500.
In case of external faults, the blocking signal (CR) must be received before the
settable timer tCoord elapses, to prevent a false trip, see Figure 500.
The function can be totally blocked by activating the input BLOCK, block of trip
by activating the input BLKTR, block of carrier send by activating the input
BLKCS.
tCoord
CACC
t TRIP
CR AND
en05000512.vsd
IEC05000512 V1 EN-US
Figure 500: Basic logic for trip signal in delta blocking scheme
The logic for trip signal in permissive scheme is shown in figure 501.
tCoord
CACC
t TRIP
CR AND
en05000513.vsd
IEC05000513 V1 EN-US
The function can be totally blocked by activating the input BLOCK. Tripping can
be blocked by activating the input BLKTR. Signal send can be blocked by
activating the input BLKCS.
The logic for trip signal in permissive scheme is shown in figure 501.
tCoord
CACC
t TRIP
CR AND
en05000513.vsd
IEC05000513 V1 EN-US
The function can be totally blocked by activating the input BLOCK. Tripping can
be blocked by activating the input BLKTR. Signal send can be blocked by
activating the input BLKCS.e.
The unblocking function uses a guard signal CRG, which must always be present,
even when no CR signal is received. The absence of the CRG signal for a time
longer than the setting tSecurity time is used as a CR signal, see figure 503. This
enables a permissive scheme to operate when the line fault blocks the signal
transmission. The CRG signal is only used in unblocking schemes.
The received signal created by the unblocking function is reset 150 ms after the
security timer has elapsed. When that occurs an output signal LCG is activated for
signalling purpose. The unblocking function is reset 200 ms after that the guard
signal is present again.
CR
tSecurity CRL
t >1
1
CRG
200 ms 150 ms
t OR t AND
AND
LCG
en05000746.vsd
IEC05000746 V1 EN-US
Figure 503: Guard signal logic with unblocking scheme and with setting
Unblock = Restart
CR
CRL
tSecurity OR
CRG t
1
IEC11000253-1-en.vsd
IEC11000253 V1 EN-US
Figure 504: Guard signal logic with unblocking scheme and with setting
Unblock = NoRestart
The unblocking function can be set in three operation modes (setting Unblock):
In the direct intertrip scheme, the send signal CS is sent from an underreaching
zone that is tripping the line.
The received signal CR is directly transferred to a trip for tripping without local
criteria. The signal is further processed in the tripping logic.
The simplified logic diagram for the complete logic is shown in figure 505.
Unblock =Off
CR
Unblock =
OR CRL
NoRestart AND
CRL
Unblock =
tSecurit
Restart
y
CRG 1 t AND
SchemeType =
Intertrip
CSUR
tSendMi
n AND
OR
BLOCK AND
CSBLK OR
CRL
Schemetype =
Permissive UR AND CS
OR
tCoord
AND 25 ms
OR
t TRIP
CACC t
Schemetype =
Permissive OR
CSOR OR AND
AND
tSendMin
OR
AND
SchemeType =
Blocking
BLKCS
AND
IEC05000515-2-en.vsd
IEC05000515 V2 EN-US
16.2.1 Identification
SEMOD141699-2 v2
Communication between line ends is used to achieve fault clearance for all faults
on a power line. All possible types of communication schemes for example,
permissive underreach, permissive overreach and blocking schemes are available.
To manage problems with simultaneous faults on parallel power lines phase
segregated communication is needed. This will then replace the standard Scheme
communication logic for distance or Overcurrent protection (ZCPSCH) on
important lines where three communication channels (in each subsystem) are
available for the distance protection communication.
The main purpose of the Phase segregated scheme communication logic for
distance protection (ZC1PPSCH) function is to supplement the distance protection
function such that:
• fast clearance of faults is also achieved at the line end for which the faults are
on the part of the line not covered by its underreaching zone.
• correct phase selection can be maintained to support single-pole tripping for
faults occurring anywhere on the entire length of a double circuit line.
To accomplish this, three separate communication channels, that is, one per phase,
each capable of transmitting a signal in each direction is required.
ZC1PPSCH can be completed with the current reversal and WEI logic for phase
segregated communication, when found necessary in Blocking and Permissive
overreaching schemes.
ZC1PPSCH
BLOCK TRIP
BLKTR TRL1
BLKTRL1 TRL2
BLKTRL2 TRL3
BLKTRL3 CSL1
CACCL1 CSL2
CACCL2 CSL3
CACCL3 CSMPH
CSURL1 CRLL1
CSURL2 CRLL2
CSURL3 CRLL3
CSORL1
CSORL2
CSORL3
CSBLKL1
CSBLKL2
CSBLKL3
BLKCSL1
BLKCSL2
BLKCSL3
CRL1
CRL2
CRL3
CRMPH
IEC06000427-2-en.vsd
IEC06000427 V2 EN-US
16.2.4 Signals
PID-3523-INPUTSIGNALS v5
PID-3523-OUTPUTSIGNALS v6
16.2.5 Settings
PID-3523-SETTINGS v5
A permissive scheme is inherently faster and has better security against false
tripping than a blocking scheme. On the other hand, a permissive scheme depends
on a received signal for a fast trip, so its dependability is lower than that of a
blocking scheme.
The ability to select which distance protection zone is assigned to which input of
ZC1PPSCH makes this logic able to support practically any scheme
communication requirements regardless of their basic operating principle. The
outputs to initiate tripping and sending of the teleprotection signal are given in
accordance with the type of communication-aided scheme selected and the zone(s)
and phase(s) of the distance protection which have operated.
When power line carrier communication channels are used for permissive schemes
communication, unblocking logic which uses the loss of guard signal as a receive
criteria is provided. This logic compensates for the lack of dependability due to the
transmission of the command signal over the faulted line.
ZC1PPSCH can be totally blocked by activating the input BLOCK, block of trip is
achieved by activating the input BLKTRLx, Block of carrier send is done by
activating the input BLKCSLx.
tCoord 25 ms
CACCLx
t t TRLx
CRLx AND
IEC06000310_2_en.vsd
IEC06000310 V2 EN-US
Figure 507: Basic logic for trip carrier in one phase of a blocking scheme
tCoord 25 ms
CACCLx t t TRLx
CRLx AND
IEC07000088_2_en.vsd
IEC07000088 V2 EN-US
Figure 508: Basic logic for trip carrier in one phase of a permissive underreach
scheme
The permissive overreach scheme has the same blocking possibilities as mentioned
for blocking scheme above. The blocking inputs are activated from the current
reversal logic when this function is included.
In the direct intertrip scheme, the carrier send signal CS is sent from an
underreaching zone that is tripping the line.
The received signal per phase is directly transferred to the trip function block for
tripping without local criteria. The signal is not further processed in the phase
segregated communication logic. In case of single-pole tripping the phase selection
and logic for tripping the three phases is performed in the trip function block.
The simplified logic diagram for one phase is shown in figure 509.
SchemeType =
Intertrip
CSURLx
tSendMin AND
OR
BLOCK
AND
CSBLKLx OR
CRLx
Scheme Type =
Permissive UR AND CSLx
OR
tCoord
25 ms
AND t TRLx
OR t
CACCLx
Scheme Type =
Permissive OR
CSORLx OR AND
AND
tSendMin
OR
AND
Scheme Type =
Blocking
BLKCSx
AND
CSL1
CSL2 AND
CSL2
OR CSMPH
CSL3 AND
CSL3
CSL1 AND
CSL1
CSL2 GENERAL
OR
CSL3
IEC06000311_2_en.vsd
IEC06000311 V2 EN-US
16.3.1 Identification
M15073-1 v5
The ZCRWPSCH function provides the current reversal and weak end infeed logic
functions that supplement the standard scheme communication logic. It is not
suitable for standalone use as it requires inputs from the distance protection
functions and the scheme communications function included within the terminal.
On verification of a weak end infeed condition, the weak end infeed logic provides
an output for sending the received teleprotection signal back to the remote sending
end and other output(s) for local tripping. For terminals equipped for single- and
two-pole tripping, outputs for the faulted phase(s) are provided. Undervoltage
detectors are used to detect the faulted phase(s).
ZCRWPSCH
U3P* IRVL
BLOCK TRWEI
IRVBLK TRWEIL1
IRV TRWEIL2
WEIBLK1 TRWEIL3
WEIBLK2 ECHO
VTSZ
CBOPEN
CRL
IEC06000287-2-en.vsd
IEC06000287 V2 EN-US
16.3.4 Signals
PID-3521-INPUTSIGNALS v8
PID-3521-OUTPUTSIGNALS v8
16.3.5 Settings
PID-3521-SETTINGS v8
The current reversal logic can be enabled by setting the parameter CurrRev = On.
The current reversal logic uses a reverse zone connected to the input IRV to
recognize the fault on the parallel line in any of the phases.When the reverse zone
has been activated (even if only for a short time), it prevents sending of a
communication signal and tripping through the scheme communication logic after
a settable time tPickUpRev. The prevention will last for tPickUpRev + 10 ms +
tDelayRev after the IREV reset. This makes it possible for the receive signal to
reset before the carrier-aided trip signal is activated due to the current reversal by
the forward directed zone. The logic diagram for current reversal is shown in
Figure 511.
BLOCK
IRVBLK
tDelayRev
tPickUpRev 10 ms tPickUpRev IRVL
IRV AND t
t t t
CurrRev = On
IEC05000122-4-en.vsd
IEC05000122 V4 EN-US
By connecting the output signal IRVL to input BLKCS in the ZCPSCH function,
the sending of the signal CS from the overreaching zone connected to CSOR in
ZCPSCH will be blocked. By connecting IRVL to input BLKTR in the ZCPSCH
function, the TRIP output from the ZCPSCH function will be blocked.
The function has an internal 10 ms drop-off timer which secure that the current
reversal logic will be activated for short input signals even if the pick-up timer is
set to zero.
The weak-end infeed logic (WEI) function sends back (echoes) the received signal
under the condition that no fault has been detected on the weak-end by different
fault detection elements (distance protection in forward or reverse direction).
The WEI function returns the received signal, shown in Figure 512, when:
• The setting parameter WEI is set to either Echo or Echo & Trip.
• No active signal present on the input BLOCK.
• The functional input CRL is active for a time longer than the tPickUpWei
setting. This input is usually connected to the CRL output on the scheme
communication logic ZCPSCH.
• The WEI function is not blocked by the active signal connected to the
WEIBLK1 functional input or to the VTSZ functional input. The later is
usually configured to the VTSZ functional output of the fuse-failure function.
• No active signal has been present for at least 200 ms on the WEIBLK2
functional input. An OR combination of all fault detection functions (not
undervoltage) as present within the IED is usually used for this purpose.
• The weak-end infeed logic also echoes the received permissive signal when
local breaker opens, CBOPEN prior to faults appeared at the end of line.
BLOCK
VTSZ
WEIBLK1 OR
tPickUpWEI
CRL AND 50 ms 200 ms
t AND
OR t t
ECHO
200 ms AND
WEIBLK2
t
AND
OR
1500 ms
CBOPEN
t
WEI = Echo
IEC05000123-3-en.vsd
IEC05000123 V3 EN-US
Figure 512: Simplified logic diagram for weak-end infeed logic — Echo
BLOCK
VTSZ
WEIBLK1 OR
tPickUpWEI
CRL AND 50 ms 200 ms
t AND ECHO
OR t t AND
200 ms
WEIBLK2
t
AND
1500 ms
OR
CBOPEN
t
AND
U3P*
UL1<UPN<
UL2 < UPN<
UL3 < UPN<
UPN< 100 ms
OR
AND t
TRWEI
OR
15 ms
TRWEIL1
U3P*
AND t
UL1L2 <UPP< OR
UL2L3 < UPP<
UL3L1 < UPP<
15 ms
UPP< TRWEIL2
AND t
OR
15 ms
OR TRWEIL3
AND t
Figure 513: Simplified logic diagram for weak-end infeed logic — Echo&Trip
16.4.1 Identification
SEMOD156467-2 v2
Current reversal and weak-end infeed logic for phase segregated communication
(ZC1WPSCH) function is used to prevent unwanted operations due to current
reversal when using permissive overreach protection schemes in application with
parallel lines where the overreach from the two ends overlaps on the parallel line.
The weak-end infeed logic is used in cases where the apparent power behind the
protection can be too low to activate the distance protection function. When
activated, received carrier signal together with local undervoltage criteria and no
reverse zone operation gives an instantaneous trip. The received signal is also
echoed back to accelerate the sending end.
ZC1WPSCH
U3P* TRPWEI
BLOCK TRPWEIL1
BLKZ TRPWEIL2
CBOPEN TRPWEIL3
CRL1 IRVOP
CRL2 IRVOPL1
CRL3 IRVOPL2
IRVL1 IRVOPL3
IRVL2 ECHO
IRVL3 ECHOL1
IRVBLKL1 ECHOL2
IRVBLKL2 ECHOL3
IRVBLKL3
WEIBLK
WEIBLKL1
WEIBLKL2
WEIBLKL3
WEIBLKOP
WEIBLKO1
WEIBLKO2
WEIBLKO3
IEC06000477-2-en.vsd
IEC06000477 V2 EN-US
16.4.4 Signals
PID-3524-INPUTSIGNALS v9
PID-3524-OUTPUTSIGNALS v9
16.4.5 Settings
PID-3524-SETTINGS v8
The current reversal logic can be enabled by setting the parameter OperCurrRev =
On. The current reversal logic uses a reverse zone connected to the input IRVLx to
recognize the fault on the parallel line in any of the phases. When the reverse zone
has been activated (even if only for a short time), it prevents sending of a
communication signal and tripping through the scheme communication logic after
a settable time tPickUpRev. The prevention will last for tPickUpRev + 10 ms +
tDelayRev after the IRVLx reset. This makes it possible for the receive signal to
reset before the trip signal is activated due to the current reversal by the forward
directed zone. The logic diagram for current reversal is shown in Figure 515.
BLOCK
IRVBLKLx
tDelayRev
tPickUpRev 10 ms tPickUpRev IRVOPLx
IRVLx & t
t t t
operCurrRev=On
IEC06000474-3-en.vsd
IEC06000474 V3 EN-US
The Current reversal and weak-end infeed logic for phase segregated
communication (ZC1WPSCH) function has an internal 10 ms drop-off timer which
secure that the current reversal logic will be activated for short input signals even if
the pickup timer is set to zero.
The WEI function sends back (echoes) the received carrier signal under the
condition that no fault has been detected at the weak end by different fault
detection elements (distance protection in forward and reverse direction).
BLOCK
BLKZ
WEIBLKLx 1 ECHOLx-contd
&
tPickUpWEI
CRLx & 50 ms 200 ms
t &
1 t t
ECHOLx
200 ms &
WEIBLKOx
t
&
1
1500 ms
CBOPEN
t
OperationWEI=Echo
IEC07000085-3-en.vsd
IEC07000085 V3 EN-US
The WEI function returns the received carrier signal, shown in Figure 516, when:
When an echo function is used in both the IEDs on the protected line (should
generally be avoided), a spurious signal can be looped round by the echo logics. To
avoid a continuous lock-up of the system, the duration of the echoed signal is
limited to 200 ms.
ECHOLx- contd
CBOPEN
U3P*
100 ms
=1
& t
Undervoltage TRPWEI
detection =1
UPE<
15 ms
UPP< TRPWEI1
& t
15 ms
TRPWEI2
& t
15 ms
TRPWEI3
& t
IEC13000278-1-en.vsd
IEC13000278 V1 EN-US
Figure 517: Simplified logic diagram for weak-end infeed logic – Echo & Trip
16.5.1 Identification
M14882-1 v2
To achieve fast fault clearance of earth faults on the part of the line not covered by
the instantaneous step of the residual overcurrent protection, the directional
residual overcurrent protection can be supported with a logic that uses
communication channels.
ECPSCH
BLOCK TRIP
BLKTR CS
BLKCS CRL
CSBLK LCG
CACC
CSOR
CSUR
CR
CRG
IEC06000288-2-en.vsd
IEC06000288 V2 EN-US
16.5.4 Signals
PID-3581-INPUTSIGNALS v7
PID-3581-OUTPUTSIGNALS v6
16.5.5 Settings
PID-3581-SETTINGS v6
In the blocking scheme a signal is sent to the other line end if the directional
element detects an earth fault in the reverse direction. When the forward directional
element operates, it trips after a short time delay if no blocking signal is received
from the opposite line end. The time delay, normally 30 – 40 ms, depends on the
communication transmission time and a chosen safety margin.
One advantage of the blocking scheme is that only one channel (carrier frequency)
is needed if the ratio of source impedances at both end is approximately equal for
zero and positive sequence source impedances, the channel can be shared with the
impedance measuring system, if that system also works in the blocking mode. The
communication signal is transmitted on a healthy line and no signal attenuation will
occur due to the fault.
If the fault is on the line, the forward direction measuring element operates. If no
blocking signal comes from the other line end via the CR binary input (received
signal) the TRIP output is activated after the tCoord set time delay.
IEC05000448 V1 EN-US
In the permissive scheme the forward directed earth-fault measuring element sends
a permissive signal to the other end, if an earth fault is detected in the forward
direction. The directional element at the other line end must wait for a permissive
signal before activating a trip signal. Independent channels must be available for
the communication in each direction.
An impedance measuring IED, which works in the same type of permissive mode,
with one channel in each direction, can share the channels with the communication
scheme for residual overcurrent protection. If the impedance measuring IED works
in the permissive overreaching mode, common channels can be used in single line
applications. In case of double lines connected to a common bus at both ends, use
common channels only if the ratio Z1S/Z0S (positive through zero-sequence source
impedance) is about equal at both ends. If the ratio is different, the impedance
measuring and the directional earth-fault current system of the healthy line may
detect a fault in different directions, which could result in unwanted tripping.
Common channels cannot be used when the weak-end infeed function is used in
the distance or earth-fault protection.
BLOCK
CRL
CR AND
25 ms
t TRIP
0 - 60 s
AND
BLKCS OR CS
AND
Overreach
CSOR AND 25 ms
CSUR OR t
IEC05000280.vsd
IEC05000280 V4 EN-US
The unblocking function uses a guard signal CRG, which must always be present,
even when no CR signal is received. The absence of the CRG signal for a time
longer than the setting tSecurity time is used as a CR signal, see figure 520. This
also enables a permissive scheme to operate when the line fault blocks the signal
transmission.
The received signal created by the unblocking function is reset 150 ms after the
security timer has elapsed. When that occurs an output signal LCG is activated for
signaling purpose. The unblocking function is reset 200 ms after that the guard
signal is present again.
CR
tSecurity CRL
t >1
1
CRG
200 ms 150 ms
t OR t AND
AND
LCG
en05000746.vsd
IEC05000746 V1 EN-US
The unblocking function can be set in three operation modes (setting Unblock):
16.6.1 Identification
M14883-1 v2
16.6.2 Functionality
M13928-3 v8
The Current reversal and weak-end infeed logic for residual overcurrent protection
(ECRWPSCH) is a supplement to Scheme communication logic for residual
overcurrent protection ECPSCH.
To achieve fast fault clearing for all earth faults on the line, the directional earth
fault protection function can be supported with logic that uses tele-protection
channels.
This is why the IEDs have available additions to the scheme communication logic.
M13928-6 v2
ECRWPSCH
U3P* IRVL
BLOCK TRWEI
IRVBLK ECHO
IRV
WEIBLK1
WEIBLK2
VTSZ
CBOPEN
CRL
IEC06000289-3-en.vsd
IEC06000289 V3 EN-US
16.6.4 Signals
PID-3522-INPUTSIGNALS v9
PID-3522-OUTPUTSIGNALS v8
16.6.5 Settings
PID-3522-SETTINGS v9
The directional comparison function contains logic for blocking overreaching and
permissive overreaching schemes.
The circuits for the permissive overreaching scheme contain logic for current
reversal and weak-end infeed functions. These functions are not required for the
blocking overreaching scheme.
Use the independent or inverse time functions in the directional earth fault
protection module to get backup tripping in case the communication equipment
malfunctions and prevents operation of the directional comparison logic.
Connect the necessary signal from the autorecloser for blocking of the directional
comparison scheme, during a single-phase autoreclosing cycle, to the BLOCK
input of the directional comparison module.
The fault current reversal logic uses a reverse directed element, connected to the
input signal IRV, which recognizes that the fault is in reverse direction. When the
reverse direction element is activated the output signal IRVL is activated which is
shown in Figure 522. The logic is now ready to handle a current reversal without
tripping. The output signal IRVL will be connected to the block input on the
permissive overreaching scheme.
When the fault current is reversed on the healthy line, IRV is deactivated and
IRVBLK is activated. The tDelayRev timer delays the reset of the output signal.
The signal blocks operation of the overreach permissive scheme for residual
current and thus prevents unwanted operation caused by fault current reversal.
BLOCK
IRVBLK
tDelayRev
tPickUpRev 10 ms tPickUpRev AND t
IRVL
IRV
t t t
CurrRev = On
IEC09000031-4-en.vsd
IEC09000031 V4 EN-US
The weak-end infeed function can be set to send only an echo signal (WEI=Echo)
or an echo signal and a trip signal (WEI=Echo & Trip). The corresponding logic
diagrams are depicted in Figure 523 and Figure 524.
The weak-end infeed logic uses normally a reverse and a forward direction
element, connected to WEIBLK2 via an OR-gate. If neither the forward nor the
reverse directional measuring element is activated during the last 200 ms, the
weak-end infeed logic echoes back the received permissive signal as shown in
Figure 523 and Figure 524. The weak-end infeed logic also echoes the received
permissive signal when CBOPEN is high (local breaker opens) prior to faults
appeared at the end of line.
If the forward or the reverse directional measuring element is activated during the
last 200 ms, the fault current is sufficient for the IED to detect the fault with the
earth fault function that is in operation.
CR
BLOCK AND
VTSZ
OR
tPickUpWEI
WEIBLK1
t AND 50 ms 200 ms
AND
OR t t ECHO
200 ms AND
CRL t
WEIBLK2
AND
1500 ms
CBOPEN OR
t
WEI = Echo
IEC09000032-6-en.vsd
IEC09000032 V6 EN-US
Figure 523: Simplified logic diagram for weak-end infeed logic - Echo
With the WEI= Echo & Trip setting, the logic sends an echo according to the
diagram above. Further, it activates the TRWEI signal to trip the breaker if the echo
conditions are fulfilled and the neutral point voltage is above the set operate value
for 3U0>.
The voltage signal that is used to calculate the zero sequence voltage is set in the
earth fault function which is in operation.
BLOCK
VTSZ
OR
tPickUpWEI
WEIBLK1 t AND 50 ms 200 ms
AND
OR t t ECHO
200 ms AND
t
CRL
AND
WEIBLK2 1500 ms
OR
t
CBOPEN
AND
ST3U0
15 ms TRWEI
a>b AND
3U0> t
WEI = Echo&Trip
IEC09000020-6-en.vsd
IEC09000020 V6 EN-US
Figure 524: Simplified logic diagram for weak-end infeed logic - Echo & Trip
The weak-end infeed echo sent to the strong line end has a maximum duration of
200 ms. When this time period has elapsed, the conditions that enable the echo
signal to be sent are set to zero for a time period of 50 ms. This avoids ringing
action if the weak-end echo is selected for both line ends.
Section 17 Logic
17.1.1 Identification
SEMOD56226-2 v7
1 -> 0
IEC15000314 V1 EN-US
A function block for protection tripping and general start indication is always
provided as a basic function for each circuit breaker. It provides a settable pulse
prolongation time to ensure a trip pulse of sufficient length, as well as all
functionality necessary for correct co-operation with autoreclosing functions.
The trip function block includes a settable latch function for the trip signal and
circuit breaker lockout.
The trip function can collect start and directional signals from different application
functions. The aggregated start and directional signals are mapped to the IEC
61850 logical node data model.
SMPPTRC
BLOCK TRIP
BLKLKOUT TRL1
TRIN TRL2
TRINL1 TRL3
TRINL2 TR1P
TRINL3 TR2P
PSL1 TR3P
PSL2 CLLKOU T
PSL3 START
1PTRZ STL1
1PTREF STL2
P3PTR STL3
SETLKOUT STN
RSTLKOUT FW
STDI R REV
IEC05000707-4-en.vsdx
IEC05000707 V4 EN-US
17.1.4 Signals
GUID-2918ECA6-4D98-493F-A33C-2D33DE64AE3B v1
GUID-D6B3DFE3-F7DF-4602-B57E-764DC9EB0D4A v1
17.1.5 Settings
GUID-6D6424B9-B676-4D9B-949A-33C74BDC5711 v1
The duration of the trip output signal is settable (tTripMin). The pulse length
should be long enough to secure the opening of the circuit breaker.
There is a single input (TRIN) through which all trip output signals from the
protection functions within the IED or from external protection functions via one or
more of the IEDs' binary inputs are routed. It has a single three-phase trip output
(TRIP) to connect to one or more of the IEDs' binary outputs, as well as to other
functions within the IED requiring this signal.
SETLKOUT
RSTLKOUT
P3PTR
SETLKOUT
RSTLKOUT
P3PTR
SETLKOUT
RSTLKOUT
IEC10000266=2=en=Original.vsdx
IEC10000266 V2 EN-US
SMPPTRC function has separate inputs (TRINL1, TRINL2, TRINL3) which are
used for single-phase and two-phase tripping from the functions which offer phase
segregated trip outputs.
The inputs 1PTRZ and 1PTREF enable single- phase and two-phase tripping for
those functions which do not have their own phase selection capability (i.e. which
have just a single trip output). An example of such a protection function is the
residual overcurrent protection. The SMPPTRC function has two inputs for these
functions, one for impedance tripping (1PTRZ used for carrier-aided tripping
commands from the scheme communication logic), and one for earth fault tripping
(1PTREF used for tripping from a residual overcurrent protection). External phase
selection for these two trip signals shall be provided via inputs PSL1, PSL2 and
PSL3.
A timer tWaitForPHS, secures a three-phase trip command for these two trip
signals in the absence of the external phase selection signals.
The SMPPTRC function has three trip outputs TRL1, TRL2, TRL3 (besides the
three-phase trip output TRIP), one per phase, to connect to one or more of the
IEDs’ binary outputs, as well as to other functions within the IED requiring these
signals. These three output signals shall be used as trip signals for individual circuit
breaker poles. These signals are important for cooperation with the autorecloser
SMBRREC function.
The SMPPTRC function is equipped with logic which secures correct operation for
evolving faults as well as for reclosing on to persistent faults. A binary input
P3PTR is provided which will force all tripping to be three-phase. This input is
required in order to cooperate with the SMBRREC function.
CLLKOUT can be set by an external trip signal from another protection function
via the input SETLKOUT or internally via a three-phase trip with the setting
AutoLock = On. If CLLKOUT is set by an external trip signal from another
protection function and setting TripLockout = On, all trip outputs are set true.
The BLKLKOUT input blocks the circuit breaker lockout output CLLKOUT.
Directional data
Merged directional data from application functions can be provided to the trip
function (SMPPTRC) via the start matrix function (SMAGAPC) connected to the
STDIR input.
The directional input signal STDIR is a coded integer signal which may contain up
to 14 individual Boolean signals; see Figure 531:
STDIRX=[b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14]
b0= START (start)
b1= FW (forward)
Table continues on next page
The indications for general start START and phase-wise starts STL1, STL2 and
STL3, and neutral STN and general directional forward FW and reverse REV are
all available as outputs on the trip function.
All start and directional outputs are mapped to the IEC 61850 logical node data
model of the trip function. The time stamping is updated each time an operate or
start signal is changed:
• The common DIR output (general) is mapped as:
dirGeneral
0 unknown
1 forward
2 backward (reverse)
3 both
• The phase wise directional outputs (DIRL1, DIRL2, DIRL3 and DIRN) are
mapped as:
tTripMin
BLOCK TRIPALL
OR
AND t
TRINL1
TRINL2
TRINL3
TRIN OR
1PTREF
1PTRZ
IEC05000517=4=en=Original..vsdx
IEC05000517 V4 EN-US
TRIN
TRINL1
L1TRIP
OR
PSL1
AND
TRINL2
L2TRIP
OR
PSL2
AND
TRINL3
L3TRIP
OR
PSL3
AND
-LOOP
OR OR
OR
AND
AND
OR
tWaitForPHS
-LOOP t
OR
1PTREF AND
AND
1PTRZ OR
IEC10000056=4=en=Original.vsdx
IEC10000056 V4 EN-US
tTripMin
BLOCK
OR TRIPL1
L1TRIP AND t OR
tEvolvingFault
t TRIP
AND
L2TRIP
L3TRIP
OR
P3PTR
IEC17000065-2-en.vsdx
IEC17000065 V2 EN-US
BLKLKOUT
TRIPL1
TRL1
OR
TRIPL2
TRL2
OR
TRIPL3
TRL3
OR
TRIP
TRIPALL OR
OR
-LOOP
OR
AND
TR3P
AND
AND
AND
AND OR
OR
-LOOP
AND
-LOOP
AND
AutoLock
CLKLKOUT
OR AND
SETLKOUT OR AND
3ms
RSTLKOUT t
AND
TripLockout
-LOOP
IEC17000066=1=en=Original.vsdx
IEC17000066 V1 EN-US
Directional logic
IntToBits
STDIR START START
in b0
FW STL1
b1
REV STL2
b2
STL1 STL3
b3
FWL1 STN
b4
REVL1
b5
STL2
b6
FWL2 FW
b7
REVL2 BitsToInt
b8 dirGeneral (61850 Standard)
STL3
b9 0 = unknown
FWL3 b0 out
b10 DIR 1 = forward
REVL3 b1 2 = backward (reverse)
b11
STN 3 = both
b12
FWN REV
b13
REVN
b14
b15
AND
XOR
AND
XOR
AND
IEC16000179-2-en.vsdx
IEC16000179 V2 EN-US
The Start Matrix (SMAGAPC) merges start and directional output signals from
different application functions and creates a common start and directional output
signal (STDIR) to be connected to the Trip function, see Figure 532.
SMAGAPC
BLOCK STDIR
STDIR1
STDIR2
STDIR3
STDIR4
STDIR5
STDIR6
STDIR7
STDIR8
STDIR9
STDIR10
STDIR11
STDIR12
STDIR13
STDIR14
STDIR15
STDIR16
IEC16000165-1-en.vsdx
IEC16000165 V1 EN-US
17.2.4 Signals
PID-6906-INPUTSIGNALS v2
PID-6906-OUTPUTSIGNALS v2
17.2.5 Settings
PID-6906-SETTINGS v2
Start matrix
The Start Matrix function requires that a protection function delivers the directional
output signals in a fixed order to Start Matrix.
A directional input signal STDIRX of the Start Matrix is of type word. Each input
contains 14 individual Boolean signals, which are positioned as, see Figure 534.
STDIRX=[b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14]
b0= START (start)
b1= FW (forward)
b2= REV (reverse)
Table continues on next page
The StartMatrix function contains two function: the START criteria and the
DIRECTION criteria, see Figure 533.
The START criteria is to ensure that a forward and reverse signal shall come
together with a start signal to pass through the block. This is done individually for
each protection function connected to the StartMatrix via the STDIRX inputs, see
Figure 534.
All STDIROUT signals are then connected via an OR gate, see Figure 533.
SMAGAPC
(StartMatrix)
START Criteria
STDIR1
STDIRX STDIROUT
START Criteria
STDIR2
STDIRX STDIROUT
START Criteria
STDIR3
STDIRX STDIROUT
DIRECTION Criteria
STDIR
≥1 STDIRIN STDIR
START Criteria
STDIR4
STDIRX STDIROUT
START Criteria
STDIR5
STDIRX STDIROUT
START Criteria
STDIR6
STDIRX STDIROUT
START Criteria
STDIR7
STDIRX STDIROUT
START Criteria
STDIR8
STDIRX STDIROUT
START Criteria
STDIR9
STDIRX STDIROUT
START Criteria
STDIR10
STDIRX STDIROUT
START Criteria
STDIR11
STDIRX STDIROUT
START Criteria
STDIR12
STDIRX STDIROUT
START Criteria
STDIR13
STDIRX STDIROUT
START Criteria
STDIR14
STDIRX STDIROUT
START Criteria
STDIR15
STDIRX STDIROUT
START Criteria
STDIR16
STDIRX STDIROUT
IEC16000161-2-en.vsdx
IEC16000161 V2 EN-US
START Criteria
START (in)
STL1 (in)
STL2 (in) ≥1 START (out)
STL3 (in)
IntToBits STN (in) BitsToint
STDIRX STDIROUT
in b0 START (in) STL1 (out) START (out) b0 out
b1 FW (in) STL2 (out) FW (out) b1
b2 REV (in) STL3 (out) REV (out) b2
b3 STL1 (in) STN (out) STL1 (out) b3
b4 FWL1 (in) FWL1 (out) b4
b5 REVL1 (in) REVL1 (out) b5
&
b6 STL2 (in) FW (in) STL2 (out) b6
b7 FWL2 (in) FWL2 (out) b7
≥1 FW (out)
b8 REVL2 (in) REVL2 (out) b8
b9 STL3 (in) STL3 (out) b9
b10 FWL3 (in) FWL3 (out) b10
b11 REVL3 (in) & REVL3 (out) b11
REV (in)
b12 STN (in) STN (out) b12
b13 FWN (in) ≥1 REV (out) FWN (out) b13
b14 REVN (in) REVN (out) b14
b15 N/A FALSE b15
IEC16000162-2-en.vsdx
IEC16000162 V2 EN-US
DIRECTION Criteria
FWL1 (in)
=1
REVL1 (in)
FWL2 (in)
=1
REVL2 (in)
FWL3 (in)
=1
REVL3 (in)
FWN (in)
=1
REVN (in)
IEC16000163-2-en.vsdx
IEC16000163 V2 EN-US
STARTCOMB
To make it possible to provide the directional information from a protection
function, a STARTCOMB block is used in between the application function and the
Start Matrix function.
The STARTCOMB function has one block input and 14 Boolean inputs that
convert the 14 Boolean inputs into a WORD output STDIR, see Figure 536.
STDIRX=[b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14]
b0= START (start)
b1= FW (forward)
b2= REV (reverse)
b3= STL1 (startL1)
b4= FWL1 (forwardL1)
b5= REVL1 (reverseL1)
b6= STL2 (startL2)
b7= FWL2 (forwardL2)
b8= REVL2 (reverseL2)
b9= STL3 (startL3)
b10= FWL3 (forwardL3)
b11= REVL3 (reverseL3)
b12= STN (startN)
b13= FWN (forwardN)
b14= REVN (reverseN)
STARTCOMB
BLOCK STDI R
START
FW
REV
STL1
FWL1
REVL1
STL2
FWL2
REVL2
STL3
FWL3
REVL3
STN
FWN
REVN
IEC16000166-2-en.vsdx
IEC16000166 V2 EN-US
Protection functions
Some protection functions are provided with start and directional outputs, for
example:
Connection example
In Figure 537 below is an example how to connect start and directional signals
from protection functions via STARTCOMB and SMAGAPC to SMPPTRC.
SMAGAPC
STARTCOMB BLOCK STDIR
PROTECTION 1 BLOCK STDIR STDIR1
START START STDIR2
FW FW STDIR3
REV REV STDIR4
STL1 STDIR5
FWL1 STDIR6 SMPPTRC
REVL1 STDIR7 BLOCK TRIP
STL2 STDIR8 BLKLKOUT TRL1
FWL2 STDIR9 TRIN TRL2
REVL2 STDIR10 TRINL1 TRL3
STL3 STDIR11 TRINL2 TR1P
FWL3 STDIR12 TRINL3 TR2P
REVL3 STDIR13 PSL1 TR3P
STN STDIR14 PSL2 CLLKOUT
FWN STDIR15 PSL3 START
REVN STDIR16 1PTRZ STL1
1PTREF STL2
P3PTR STL3
STARTCOMB SETLKOUT STN
BLOCK STDIR RSTLKOUT FW
START STDIR REV
FW
PROTECTION 2 REV
STL1 STL1
FWL1 FWL1
REVL1 REVL1
STL2 STL2
FWL2 FWL2
REVL2 REVL2
STL3 STL3
FWL3 FWL3
REVL3 REVL3
STN
FWN
REVN
STARTCOMB
BLOCK STDIR
START
FW
REV
STL1
FWL1
REVL1
STL2
FWL2
REVL2
STL3
PROTECTION 4
FWL3
-
PROTECTION 3 REVL3
STDIR
STN STN
-
FWN FWN
-
REVN REVN
IEC16000164-2-en.vsdx
IEC16000164 V2 EN-US
17.3.1 Identification
SEMOD167882-2 v3
The trip matrix logic TMAGAPC function is used to route trip signals and other
logical output signals to different output contacts on the IED.
The trip matrix logic function has 3 output signals and these outputs can be
connected to physical tripping outputs according to the specific application needs
for settable pulse or steady output.
TMAGAPC
BLOCK OUTPUT1
BLK1 OUTPUT2
BLK2 OUTPUT3
BLK3
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
INPUT17
INPUT18
INPUT19
INPUT20
INPUT21
INPUT22
INPUT23
INPUT24
INPUT25
INPUT26
INPUT27
INPUT28
INPUT29
INPUT30
INPUT31
INPUT32
IEC13000197-1-en.vsd
IEC13000197 V1 EN-US
17.3.4 Signals
PID-6513-INPUTSIGNALS v4
PID-6513-OUTPUTSIGNALS v4
17.3.5 Settings
PID-6513-SETTINGS v4
The trip matrix logic (TMAGAPC) block is provided with 32 input signals and 3
output signals. The function block incorporates internal logic OR gates in order to
provide grouping of connected input signals to the three output signals from the
function block.
Internal built-in OR logic is made in accordance with the following three rules:
1. when any one of first 16 inputs signals (INPUT1 to INPUT16) has logical
value 1 the first output signal (OUTPUT1) will get logical value 1.
2. when any one of second 16 inputs signals (INPUT17 to INPUT32) has logical
value 1 the second output signal (OUTPUT2) will get logical value 1.
3. when any one of all 32 input signals (INPUT1 to INPUT32) has logical value
1 the third output signal (OUTPUT3) will get logical value 1.
PulseTime
t
&
ModeOutput1=Pulsed
INPUT 1
OUTPUT 1
Ondelay Offdelay
&
³1
³1 t t
INPUT 16
PulseTime
t
&
ModeOutput2=Pulsed
INPUT 17
OUTPUT 2
Ondelay Offdelay
&
³1
³1 t t
INPUT 32
PulseTime
t
&
ModeOutput3=Pulsed
OUTPUT 3
Ondelay Offdelay
&
³1
³1 t t
IEC09000612-3-en.vsd
IEC09000612 V3 EN-US
Output signals from TMAGAPC are typically connected to other logic blocks or
directly to output contacts in the IED. When used for direct tripping of the circuit
breaker(s) the pulse time shall be set to at least 0.150 seconds in order to obtain
satisfactory minimum duration of the trip pulse to the circuit breaker trip coils.
The group alarm logic function (ALMCALH) is used to route several alarm signals
to a common indication, LED and/or contact, in the IED.
ALMCALH
BLOCK ALARM
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
IEC13000181-1-en.vsd
IEC13000181 V1 EN-US
17.4.4 Signals
PID-6510-INPUTSIGNALS v5
PID-6510-OUTPUTSIGNALS v5
17.4.5 Settings
PID-6510-SETTINGS v5
The logic for group alarm ALMCALH block is provided with 16 input signals and
one ALARM output signal. The function block incorporates internal logic OR gate
in order to provide grouping of connected input signals to the output ALARM
signal from the function block.
When any one of 16 input signals (INPUT1 to INPUT16) has logical value 1, the
ALARM output signal will get logical value 1.
The function has a drop-off delay of 200 ms when all inputs are reset to provide a
steady signal.
Input 1
200 ms
ALARM
³1 t
Input 16
IEC13000191-1-en.vsd
IEC13000191 V1 EN-US
The group warning logic function (WRNCALH) is used to route several warning
signals to a common indication, LED and/or contact, in the IED.
WRNCALH
BLOCK WARNING
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
IEC13000182-1-en.vsd
IEC13000182 V1 EN-US
17.5.4 Signals
PID-4127-INPUTSIGNALS v3
PID-4127-OUTPUTSIGNALS v3
17.5.5 Settings
PID-4127-SETTINGS v3
The logic for group warning WRNCALH block is provided with 16 input signals
and 1 WARNING output signal. The function block incorporates internal logic OR
gate in order to provide grouping of connected input signals to the output
WARNING signal from the function block.
When any one of 16 input signals (INPUT1 to INPUT16) has logical value 1, the
WARNING output signal will get logical value 1.
The function has a drop-off delay of 200 ms when all inputs are reset to provide a
steady signal.
INPUT1
200 ms
WARNING
³1 t
INPUT16
IEC13000192-1-en.vsd
IEC13000192 V1 EN-US
The group indication logic function (INDCALH) is used to route several indication
signals to a common indication, LED and/or contact, in the IED.
INDCALH
BLOCK IND
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
IEC13000183-1-en.vsd
IEC13000183 V1 EN-US
17.6.4 Signals
PID-4128-INPUTSIGNALS v4
PID-4128-OUTPUTSIGNALS v4
17.6.5 Settings
PID-4128-SETTINGS v4
The logic for group indication INDCALH block is provided with 16 input signals
and 1 IND output signal. The function block incorporates internal logic OR gate in
order to provide grouping of connected input signals to the output IND signal from
the function block.
When any one of 16 input signals (INPUT1 to INPUT16) has logical value 1, the
IND output signal will get logical value 1.
The function has a drop-off delay of 200 ms when all inputs are reset to provide a
steady signal.
INPUT1
200 ms
IND
³1 t
INPUT16
IEC13000193-1-en.vsd
IEC13000193 V1 EN-US
The basic configurable logic blocks do not propagate the time stamp and quality of
signals (have no suffix QT at the end of their function name). A number of logic
blocks and timers are always available as basic for the user to adapt the
configuration to the specific application needs. The list below shows a summary of
the function blocks and their features.
These logic blocks are also available as part of an extension logic package with the
same number of instances.
• AND function block. The AND function is used to form general combinatory
expressions with boolean variables. The AND function block has up to four
inputs and two outputs. One of the outputs is inverted.
• GATE function block is used for whether or not a signal should be able to pass
from the input to the output.
• INVERTER function block that inverts the input signal to the output.
• LLD function block. Loop delay used to delay the output signal one execution
cycle.
• PULSETIMER function block can be used, for example, for pulse extensions
or limiting of operation of outputs, settable pulse time.
• RSMEMORY function block is a flip-flop that can reset or set an output from
two inputs respectively. Each block has two outputs where one is inverted. The
memory setting controls if, after a power interruption, the flip-flop resets or
returns to the state it had before the power interruption. RESET input has
priority.
• SRMEMORY function block is a flip-flop that can set or reset an output from
two inputs respectively. Each block has two outputs where one is inverted. The
memory setting controls if, after a power interruption, the flip-flop resets or
returns to the state it had before the power interruption. The SET input has
priority.
• TIMERSET function has pick-up and drop-out delayed outputs related to the
input signal. The timer has a settable time delay.
M11453-3 v4
The AND function is used to form general combinatory expressions with boolean
variables. The AND function block has up to four inputs and two outputs. One of
the outputs is inverted.
AND
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
IEC14000071-1-en.vsd
IEC14000071 V1 EN-US
17.7.1.2 Signals
PID-3437-INPUTSIGNALS v7
PID-3437-OUTPUTSIGNALS v7
M11489-3 v2
The Controllable gate function block (GATE) is used for controlling if a signal
should be able to pass from the input to the output or not depending on a setting.
GATE
INPUT OUT
IEC04000410-2-en.vsd
IEC04000410 V2 EN-US
17.7.2.2 Signals
PID-3801-INPUTSIGNALS v6
PID-3801-OUTPUTSIGNALS v5
17.7.2.3 Settings
PID-3801-SETTINGS v6
INV
INPUT OUT
IEC04000404_2_en.vsd
IEC04000404 V2 EN-US
17.7.3.2 Signals
PID-3803-INPUTSIGNALS v5
PID-3803-OUTPUTSIGNALS v4
GUID-64B24094-010D-4B8F-8B7B-DDD49499AAE5 v3
The Logic loop delay function block (LLD) function is used to delay the output
signal one execution cycle, that is, the cycle time of the function blocks used.
LLD
INPUT OUT
IEC15000144.vsd
IEC15000144 V1 EN-US
17.7.4.2 Signals
PID-3805-INPUTSIGNALS v5
PID-3805-OUTPUTSIGNALS v5
M11449-3 v2
OR
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
INPUT5
INPUT6
IEC04000405_2_en.vsd
IEC04000405 V2 EN-US
17.7.5.2 Signals
PID-3806-INPUTSIGNALS v5
PID-3806-OUTPUTSIGNALS v5
M11466-3 v3
The pulse (PULSETIMER) function can be used, for example, for pulse extensions
or limiting the operation time of outputs. The PULSETIMER has a settable length.
When the input is 1, the output will be 1 for the time set by the time delay
parameter t. Then it returns to 0.
PULSETIMER
INPUT OUT
IEC04000407-3-en.vsd
IEC04000407 V3 EN-US
17.7.6.2 Signals
PID-6985-INPUTSIGNALS v1
PID-6985-OUTPUTSIGNALS v1
17.7.6.3 Settings
PID-6985-SETTINGS v1
GUID-4C804DEA-3C83-4C20-82C6-BAD03BD48242 v4
RSMEMORY
SET OUT
RESET NOUT
IEC09000294-1-en.vsd
IEC09000294 V1 EN-US
17.7.7.2 Signals
PID-3811-INPUTSIGNALS v5
PID-3811-OUTPUTSIGNALS v5
17.7.7.3 Settings
PID-3811-SETTINGS v5
M11485-3 v4
SRMEMORY
SET OUT
RESET NOUT
IEC04000408_2_en.vsd
IEC04000408 V2 EN-US
17.7.8.2 Signals
PID-3813-INPUTSIGNALS v5
PID-3813-OUTPUTSIGNALS v5
17.7.8.3 Settings
PID-3813-SETTINGS v5
M11494-3 v3
The Settable timer function block (TIMERSET) timer has two outputs for the delay
of the input signal at drop-out and at pick-up. The timer has a settable time delay. It
also has an Operation setting On and Off that controls the operation of the timer.
Input
tdelay
On
Off
tdelay
t
IEC08000289-2-en.vsd
IEC08000289 V2 EN-US
TIMERSET
INPUT ON
OFF
IEC04000411-2-en.vsd
IEC04000411 V2 EN-US
17.7.9.2 Signals
PID-6976-INPUTSIGNALS v1
PID-6976-OUTPUTSIGNALS v1
17.7.9.3 Settings
PID-6976-SETTINGS v1
M11477-3 v4
XOR
INPUT1 OUT
INPUT2 NOUT
IEC04000409-2-en.vsd
IEC04000409 V2 EN-US
17.7.10.2 Signals
PID-3817-INPUTSIGNALS v2
PID-3817-OUTPUTSIGNALS v2
The configurable logic blocks QT propagate the time stamp and the quality of the
input signals (have suffix QT at the end of their function name).
The function blocks assist the user to adapt the IEDs' configuration to the specific
application needs. The list below shows a summary of the function blocks and their
features.
• ANDQT AND function block. The function also propagates the time stamp
and the quality of input signals. Each block has four inputs and two outputs
where one is inverted.
common part and the indication part of inputs signal are copied to the
corresponding quality output.
• INVERTERQT function block that inverts the input signal and propagates the
time stamp and the quality of the input signal.
• ORQT OR function block that also propagates the time stamp and the quality
of the input signals. Each block has six inputs and two outputs where one is
inverted.
• PULSETIMERQT Pulse timer function block can be used, for example, for
pulse extensions or limiting of operation of outputs. The function also
propagates the time stamp and the quality of the input signal.
• XORQT XOR function block. The function also propagates the time stamp
and the quality of the input signals. Each block has two outputs where one is
inverted.
ANDQT
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
IEC09000297-1-en.vsd
IEC09000297 V1 EN-US
PID-3800-INPUTSIGNALS v6
PID-3800-OUTPUTSIGNALS v6
GUID-EEBD65A5-394C-4ECD-BF6F-D556B610FC57 v3
The value of single point input (SP_IN) is copied to the value part of the SP_OUT
output. The TIME input is copied to the time part of the SP_OUT output. State
input bits are copied to the corresponding state part of the SP_OUT output. If the
state or value on the SP_OUT output changes, the Event bit in the state part is
toggled.
INDCOMBSPQT can propagate the quality, the value and the time stamps of the
signals via IEC 61850.
INDCOMBSPQT
SP_IN* SP_OUT
TIME*
BLOCKED*
SUBST*
INVALID*
TEST*
IEC15000146.vsd
IEC15000146 V1 EN-US
PID-3792-INPUTSIGNALS v2
PID-3792-OUTPUTSIGNALS v2
GUID-9B700C69-4DAE-434A-BCE6-CE2D1139680A v3
The value part of the single point input signal SI_IN is copied to SI_OUT output.
The time part of single point input is copied to the TIME output. The state bits in
the common part and the indication part of the input signal are copied to the
corresponding state output.
INDEXTSPQT can propagate the quality, the value and the time stamps of the
signals via IEC 61850.
INDEXTSPQT
SI_IN* SI_OUT
TIME
BLOCKED
SUBST
INVALID
TEST
IEC14000067-1-en.vsd
IEC14000067 V1 EN-US
PID-3821-INPUTSIGNALS v2
PID-3821-OUTPUTSIGNALS v2
The values of the input signals INPUTx (where 1<x<16) are copied to the outputs
OUTPUTx (where 1<x<16). If the input VALID is 0 or if its quality bit is set
invalid, all outputs OUTPUTx (where 1<x<16) quality bit will be set to invalid.
The time stamp of any output OUTPUTx (where 1<x<16) will be set to the latest
time stamp of any input and the input VALID.
INVALIDQT can propagate the quality, the value and the time stamps of the
signals via IEC 61850.
INVALIDQT
INPUT1 OUTPUT1
INPUT2 OUTPUT2
INPUT3 OUTPUT3
INPUT4 OUTPUT4
INPUT5 OUTPUT5
INPUT6 OUTPUT6
INPUT7 OUTPUT7
INPUT8 OUTPUT8
INPUT9 OUTPUT9
INPUT10 OUTPUT10
INPUT11 OUTPUT11
INPUT12 OUTPUT12
INPUT13 OUTPUT13
INPUT14 OUTPUT14
INPUT15 OUTPUT15
INPUT16 OUTPUT16
VALID
iec08000169.vsd
IEC08000169 V1 EN-US
PID-3822-INPUTSIGNALS v5
PID-3822-OUTPUTSIGNALS v5
The INVERTERQT function block inverts one binary input signal to the output. It
can propagate the quality, value and the time stamps of the signals via IEC 61850.
INVERTERQT
INPUT OUT
IEC09000299-1-en.vsd
IEC09000299 V1 EN-US
PID-3804-INPUTSIGNALS v5
PID-3804-OUTPUTSIGNALS v5
GUID-F8AECD9C-83FC-4025-9AB5-809D88122277 v4
ORQT
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
INPUT5
INPUT6
IEC09000298-1-en.vsd
IEC09000298 V1 EN-US
PID-3807-INPUTSIGNALS v5
PID-3807-OUTPUTSIGNALS v5
GUID-D930E5A7-C564-4464-B97F-C72B4801C917 v4
The pulse timer function block (PULSETIMERQT) can be used, for example, for
pulse extensions or for limiting the operation time of the outputs.
PULSETIMERQT has a settable output pulse length.
When the input goes to 1, the output will be 1 for the time set by the time delay
parameter t. Then it returns to 0.
When the output changes value, the time stamp of the output signal is updated.
The supported “quality” state bits are propagated from the input to the output at
each execution cycle. A change of these bits will not lead to an updated time stamp
on the output.
PULSETIMERQT can propagate the quality, value and the time stamps of the
signals via IEC 61850.
PULSETIMERQT
INPUT OUT
IEC15000145.vsd
IEC15000145 V1 EN-US
PID-3810-INPUTSIGNALS v5
PID-3810-OUTPUTSIGNALS v5
17.8.7.3 Settings
PID-3810-SETTINGS v5
GUID-32A1B759-2ED8-45B3-8385-762167626CE2 v5
The Reset-set function (RSMEMORYQT) is a flip-flop with memory that can reset
or set an output from two inputs respectively. Each RSMEMORYQT function
block has two outputs, where one is inverted. The memory setting controls if, after
a power interruption, the flip-flop resets or returns to the state it had before the
power interruption. For a Reset-Set flip-flop, the RESET input has higher priority
than the SET input.
RSMEMORYQT can propagate the quality, the value and the time stamps of the
signals via IEC 61850.
Table 724: Truth table for RSMEMORYQT function block
RESET SET OUT NOUT
0 0 Last Inverted last
value value
0 1 1 0
1 0 0 1
1 1 0 1
RSMEMORYQT
SET OUT
RESET NOUT
IEC14000069-1-en.vsd
IEC14000069 V1 EN-US
PID-3812-INPUTSIGNALS v5
PID-3812-OUTPUTSIGNALS v5
17.8.8.3 Settings
PID-3812-SETTINGS v5
GUID-39060D4B-9AA7-4505-9487-88B2CBC534F0 v5
The Set-reset function (SRMEMORYQT) is a flip-flop with memory that can set or
reset an output from two inputs respectively. Each SRMEMORYQT function block
has two outputs, where one is inverted. The memory setting controls if, after a
power interruption, the flip-flop resets or returns to the state it had before the
power interruption. The SET input has priority.
SRMEMORYQT can propagate the quality, the value and the time stamps of the
signals via IEC 61850.
SRMEMORYQT
SET OUT
RESET NOUT
IEC14000070-1-en.vsd
IEC14000070 V1 EN-US
PID-3814-INPUTSIGNALS v5
PID-3814-OUTPUTSIGNALS v5
17.8.9.3 Settings
PID-3814-SETTINGS v5
GUID-3830BCA7-4876-481E-B5AC-2104675232E7 v5
The Settable timer function block (TIMERSETQT) has two outputs for delay of the
input signal at pick-up and drop-out. The timer has a settable time delay (t). It also
has an Operation setting On/Off that controls the operation of the timer.
When the output changes value, the timestamp of the output signal is updated. The
supported “quality” state bits are propagated from the input to the output at each
execution cycle. A change of these bits will not lead to an updated timestamp on
the output.
TIMERSETQT can propagate the quality, value and the timestamps of the signals
via IEC 61850.
TIMERSETQT
INPUT ON
OFF
IEC14000068-1-en.vsd
IEC14000068 V1 EN-US
PID-3816-INPUTSIGNALS v5
PID-3816-OUTPUTSIGNALS v5
17.8.10.3 Settings
PID-3816-SETTINGS v5
GUID-62986D87-1690-499E-B8D3-1F51D2DA191E v4
XORQT can propagate the quality, value and time stamps of the signals via IEC
61850.
XORQT
INPUT1 OUT
INPUT2 NOUT
IEC09000300-1-en.vsd
IEC09000300 V1 EN-US
PID-3818-INPUTSIGNALS v5
PID-3818-OUTPUTSIGNALS v5
When extra configurable logic blocks are required, an additional package can be
ordered.
GUID-19810098-1820-4765-8F0B-7D585FFC0C78 v7
17.10.1 Identification
SEMOD167904-2 v2
The Fixed signals function (FXDSIGN) has nine pre-set (fixed) signals that can be
used in the configuration of an IED, either for forcing the unused inputs in other
function blocks to a certain level/value, or for creating certain logic. Boolean,
integer, floating point, string types of signals are available.
FXDSIGN
OFF
ON
INTZERO
INTONE
INTALONE
REALZERO
STRNULL
ZEROSMPL
GRP_OFF
IEC05000445-3-en.vsd
IEC05000445 V3 EN-US
17.10.4 Signals
PID-6191-OUTPUTSIGNALS v6
17.10.5 Settings
PID-1325-SETTINGS v11
The function does not have any settings available in Local HMI or Protection and
Control IED Manager (PCM600).
17.11.1 Identification
SEMOD175721-2 v2
B16I
BLOCK OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IEC07000128-2-en.vsd
IEC07000128 V2 EN-US
17.11.4 Signals
PID-3606-INPUTSIGNALS v4
PID-3606-OUTPUTSIGNALS v3
The function does not have any parameters available in the local HMI or PCM600.
Values of each of the different OUTx from function block B16I for 1≤x≤16.
The sum of the value on each INx corresponds to the integer presented on the
output OUT on the function block B16I
Name of input Type Default Description Value when Value when
activated deactivated
IN1 BOOLEAN 0 Input 1 1 0
IN2 BOOLEAN 0 Input 2 2 0
IN3 BOOLEAN 0 Input 3 4 0
IN4 BOOLEAN 0 Input 4 8 0
IN5 BOOLEAN 0 Input 5 16 0
IN6 BOOLEAN 0 Input 6 32 0
IN7 BOOLEAN 0 Input 7 64 0
IN8 BOOLEAN 0 Input 8 128 0
Table continues on next page
The sum of the numbers in column “Value when activated” when all INx (where
1≤x≤16) are active that is=1; is 65535. 65535 is the highest boolean value that can
be converted to an integer by the B16I function block.
17.12.1 Identification
SEMOD175757-2 v5
BTIGAPC
BLOCK OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IEC13000303-1-en.vsd
IEC13000303 V1 EN-US
17.12.4 Signals
PID-6944-INPUTSIGNALS v2
PID-6944-OUTPUTSIGNALS v2
The function does not have any parameters available in the local HMI or PCM600.
Values of each of the different OUTx from function block BTIGAPC for 1≤x≤16.
The sum of the value on each INx corresponds to the integer presented on the
output OUT on the function block BTIGAPC.
Name of input Type Default Description Value when Value when
activated deactivated
IN1 BOOLEAN 0 Input 1 1 0
IN2 BOOLEAN 0 Input 2 2 0
IN3 BOOLEAN 0 Input 3 4 0
IN4 BOOLEAN 0 Input 4 8 0
IN5 BOOLEAN 0 Input 5 16 0
IN6 BOOLEAN 0 Input 6 32 0
IN7 BOOLEAN 0 Input 7 64 0
IN8 BOOLEAN 0 Input 8 128 0
IN9 BOOLEAN 0 Input 9 256 0
IN10 BOOLEAN 0 Input 10 512 0
IN11 BOOLEAN 0 Input 11 1024 0
IN12 BOOLEAN 0 Input 12 2048 0
IN13 BOOLEAN 0 Input 13 4096 0
Table continues on next page
The sum of the numbers in column “Value when activated” when all INx (where
1≤x≤16) are active that is=1; is 65535. 65535 is the highest boolean value that can
be converted to an integer by the BTIGAPC function block.
17.13.1 Identification
SEMOD167941-2 v2
IB16
BLOCK OUT1
INP OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
IEC06000501-3-en.vsdx
IEC06000501 V3 EN-US
17.13.4 Signals
PID-6938-INPUTSIGNALS v1
PID-6938-OUTPUTSIGNALS v1
The function does not have any parameters available in local HMI or Protection
and Control IED Manager (PCM600)
With integer 15 on the input INP the OUT1 = OUT2 = OUT3= OUT4 =1 and the
remaining OUTx = 0 for (5≤x≤16).
OUTx represents a value when activated. The value of each of the OUTx is in
accordance with the table IB16_1. When not activated the OUTx has the value 0.
In the above example when integer 15 is on the input INP the OUT1 has a value
=1, OUT2 has a value =2, OUT3 has a value =4 and OUT4 has a value =8. The
sum of these OUTx is equal to 1 + 2 + 4 + 8 = 15.
This follows the general formulae: The sum of the values of all OUTx = 2x-1 where
1≤x≤16 will be equal to the integer value on the input INP.
The Integer to Boolean 16 conversion function (IB16) will transfer an integer with
a value between 0 to 65535 connected to the input INP to a combination of
activated outputs OUTx where 1≤x≤16. The sum of the values of all OUTx will
then be equal to the integer on input INP. The values of the different OUTx are
according to the table below. When an OUTx is not activated, its value is 0.
When all OUTx where 1≤x≤16 are activated that is = Boolean 1 it corresponds to
that integer 65535 is connected to input INP. The IB16 function is designed for
receiving the integer input locally. If the BLOCK input is activated, it will freeze
the logical outputs at the last value.
Values of each of the different OUTx from function block IB16 for 1≤x≤16.
The sum of the value on each INx corresponds to the integer presented on the
output OUT on the function block IB16.
Name of OUTx Type Description Value when Value when
activated deactivated
OUT1 BOOLEAN Output 1 1 0
OUT2 BOOLEAN Output 2 2 0
OUT3 BOOLEAN Output 3 4 0
OUT4 BOOLEAN Output 4 8 0
Table continues on next page
The sum of the numbers in column “Value when activated” when all OUTx (where
x = 1 to 16) are active that is=1; is 65535. 65535 is the highest integer that can be
converted by the IB16 function block.
17.14.1 Identification
SEMOD167944-2 v4
ITBGAPC function can only receive remote values over IEC 61850 when the R/L
(Remote/Local) push button on the front HMI indicates that the control mode for
the operator is in position R (Remote i.e. the LED adjacent to R is lit), and the
corresponding signal is connected to the input PSTO ITBGAPC function block.
The input BLOCK will freeze the output at the last received value and blocks new
integer values to be received and converted to binary coded outputs.
ITBGAPC
BLOCK OUT1
PSTO OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
IEC14000012-1-en.vsd
IEC14000012 V1 EN-US
17.14.4 Signals
PID-3627-INPUTSIGNALS v7
PID-3627-OUTPUTSIGNALS v7
17.14.5 Settings
GUID-F573CA16-4821-4203-970A-F7D01AF5E63B v1
OUTx represents a value when activated. The value of each of the OUTx is in
accordance with the Table 757. When not activated the OUTx has the value 0.
The value of each OUTx for 1≤x≤16 (1≤x≤16) follows the general formulae:
OUTx = 2x-1 The sum of the values of all activated OUTx = 2x-1 where 1≤x≤16
will be equal to the integer value received over IEC 61850 to the ITBGAPC_1
function block.
The ITBGAPC function is designed for receiving the integer input from a station
computer - for example, over IEC 61850. If the BLOCK input is activated, it will
freeze the logical outputs at the last value.
Table 757: Outputs and their values when activated
Name of OUTx Type Description Value when Value when
activated deactivated
OUT1 BOOLEAN Output 1 1 0
OUT2 BOOLEAN Output 2 2 0
OUT3 BOOLEAN Output 3 4 0
OUT4 BOOLEAN Output 4 8 0
OUT5 BOOLEAN Output 5 16 0
OUT6 BOOLEAN Output 6 32 0
OUT7 BOOLEAN Output 7 64 0
OUT8 BOOLEAN Output 8 128 0
OUT9 BOOLEAN Output 9 256 0
OUT10 BOOLEAN Output 10 512 0
OUT11 BOOLEAN Output 11 1024 0
OUT12 BOOLEAN Output 12 2048 0
OUT13 BOOLEAN Output 13 4096 0
OUT14 BOOLEAN Output 14 8192 0
OUT15 BOOLEAN Output 15 16384 0
OUT16 BOOLEAN Output 16 32768 0
The sum of the numbers in column “Value when activated” when all OUTx
(1≤x≤16) are active equals 65535. This is the highest integer that can be converted
to boolean by the ITBGAPC function block.
The operator position input (PSTO) determines the operator place. The integer
number that is communicated to the ITBGAPC can only be written to the block
while the PSTO is in position “Remote”. If PSTO is in position ”Off” or ”Local”,
then no changes are applied to the outputs.
BLOCK
RESET
IN Time Integration ACCTIME
with Retain
q-1
a
OVERFLOW
AND
a>b
999 999 s b
a
WARNING
AND
a>b
tWarning b
a
ALARM
AND
a>b
tAlarm b
IEC13000290 V2 EN-US
TEIGAPC
BLOCK WARNING
IN ALARM
RESET OVERFLOW
ACCTIME
IEC14000014-1-en.vsd
IEC14000014 V1 EN-US
17.15.4 Signals
PID-6836-INPUTSIGNALS v2
PID-6836-OUTPUTSIGNALS v2
17.15.5 Settings
PID-6836-SETTINGS v2
• time integration, accumulating the elapsed time when a given binary signal has
been high
• blocking and reset of the total integrated time
• supervision of limit transgression and overflow, the overflow limit is fixed to
999999.9 seconds
• retaining of the integrated value
Figure 570 describes the simplified logic of the function where the block “Time
Integration“ covers the logics for the first two items listed above while the block
“Transgression Supervision Plus Retain“ contains the logics for the last two.
Loop Delay
tWarning
OVERFLOW
tAlarm
Transgression Supervision WARNING
Plus Retain
ALARM
BLOCK
RESET ACCTIME
Time Integration
IN
Loop Delay
IEC12000195-4-en.vsd
IEC12000195 V4 EN-US
The ACCTIME output represents the integrated time in seconds while tOverflow,
tAlarm and tWarning are the time limit parameters in seconds.
tAlarm and tWarning are user settable limits. They are also independent, that is,
there is no check if tAlarm > tWarning.
The limit for the overflow supervision is fixed at 999999.9 seconds. The outputs
freeze if an overflow occurs.
In principle, a shorter function cycle time, longer integrated time length or more
pulses may lead to reduced accuracy.
The function gives the possibility to monitor the level of integer values in the
system relative to each other or to a fixed value. It is a basic arithmetic function
that can be used for monitoring, supervision, interlocking and other logics.
INTCOMP
INPUT INEQUAL
REF INHIGH
INLOW
IEC15000052-1-en.vsdx
IEC15000052 V1 EN-US
17.16.4 Signals
PID-6928-INPUTSIGNALS v2
PID-6928-OUTPUTSIGNALS v2
17.16.5 Settings
PID-6928-SETTINGS v2
The selection of reference value for comparison can be done through setting
RefSource. If RefSource is selected as Input REF then the reference value for
comparison is taken from second input signal (REF). If RefSource is selected as Set
Value then the reference value for comparison is taken from setting (SetValue).
The comparison can be done either between absolute values or signed values and it
depends on the setting EnaAbs. If EnaAbs is selected as Absolute then both input
and reference value is converted into absolute values and comparison is done. If
EnaAbs is selected as Signed then the comparison is done without any conversion.
The function has three state outputs high, low and equal to condition. It will check
the following condition and give corresponding outputs.
• If the input is above the reference value then INHIGH is set HIGH
• If the input is below the reference value then INLOW is set HIGH
• If the input is equal to reference value then INEQUAL is set HIGH
EnaAbs
INPUT ABS T a
F
INHIGH
a>b
b
a INEQUAL
a=b
b
RefSource
REF ABS T
T
SetValue
F a INLOW
F a<b
b
IEC15000129-3-en.vsdx
IEC15000129 V4 EN-US
The function gives the possibility to monitor the level of real value signals in the
system relative to each other or to a fixed value. It is a basic arithmetic function
that can be used for monitoring, supervision, interlocking and other logics.
REALCOMP
INPUT INEQUAL
REF INHIGH
INLOW
IEC15000053-1-en.vsdx
IEC15000053 V1 EN-US
17.17.4 Signals
PID-6897-INPUTSIGNALS v2
PID-6897-OUTPUTSIGNALS v2
17.17.5 Settings
PID-6897-SETTINGS v2
The selection of reference value for comparison can be done through setting
RefSource. If RefSource is selected as Input REF then the reference value for
comparison is taken from second input signal (REF). If RefSource is selected as Set
Value then the reference value for comparison is taken from setting (SetValue).
Generally the inputs to the function are in SI units, but when the comparison is to
be done with respect to set level, then the user can set a value in any unit out of
Milli to Giga range in setting SetValue. The unit can be separately set with setting
RefPrefix. Internally the function handles the reference value for comparator as
SetValue*RefPrefix.
Additionally the comparison can be done either between absolute values or signed
values and it depends on the setting EnaAbs. If EnaAbs is selected as Absolute then
both input and reference value is converted into absolute values and then
comparison is done. If EnaAbs is selected as Signed then the comparison is done
without absolute conversion.
EnaAbs
INPUT
ABS T
F
High
Comparator
EqualBandHigh INHIGH
REF ABS T
T
F Low
SetValue F comparator
INLOW
SetValPrefix
EqualBandLow
IEC15000130-2-en.vsdx
IEC15000130 V2 EN-US
In order to avoid oscillations at boundary conditions of equal band low limit and
high limit, hysteresis has been provided. If the INPUT is above the equal high level
margin including hysteresis, then INHIGH will set. Similarly if the INPUT is
below the equal low level margin including hysteresis, then INLOW will set.
EqualBandHigh
Internal
Equal Band REF or SetValue Hysteresis for
equal band
EqualBandLow
IEC15000261 V1 EN-US
REALCOMP function can compare the values from milli value level to giga value
level and the maximum expectable accuracy level from the function is 10 µ.
GUID-3FDD7677-1D86-42AD-A545-B66081C49B47 v3
Section 18 Monitoring
18.1.1 Identification
SEMOD56123-2 v8
SYMBOL-RR V1 EN-US
SYMBOL-SS V1 EN-US
SYMBOL-UU V1 EN-US
SYMBOL-VV V1 EN-US
SYMBOL-TT V1 EN-US
SYMBOL-UU V1 EN-US
Measurement functions are used for power system measurement, supervision and
reporting to the local HMI, monitoring tool within PCM600 or to station level for
example, via IEC 61850. The possibility to continuously monitor measured values
of active power, reactive power, currents, voltages, frequency, power factor etc. is
vital for efficient production, transmission and distribution of electrical energy. It
provides to the system operator fast and easy overview of the present status of the
power system. Additionally, it can be used during testing and commissioning of
protection and control IEDs in order to verify proper operation and connection of
instrument transformers (CTs and VTs). During normal service by periodic
comparison of the measured value from the IED with other independent meters the
proper operation of the IED analog measurement chain can be verified. Finally, it
can be used to verify proper direction orientation for distance or directional
overcurrent protection function.
All measured values can be supervised with four settable limits that is, low-low
limit, low limit, high limit and high-high limit. A zero clamping reduction is also
supported, that is, the measured value below a settable limit is forced to zero which
reduces the impact of noise in the inputs.
Dead-band supervision can be used to report measured signal value to station level
when change in measured value is above set threshold limit or time integral of all
changes since the last time value updating exceeds the threshold limit. Measure
value can also be based on periodic reporting.
,
The measuring functions CMMXU, VMMXU and VNMMXU provide physical
quantities:
It is possible to calibrate the measuring function above to get better then class 0.5
presentation. This is accomplished by angle and amplitude compensation at 5, 30
and 100% of rated current and at 100% of rated voltage.
The available function blocks of an IED are depending on the actual hardware
(TRM) and the logic configuration made in PCM600.
CVMMXN
I3P* S
U3P* S_RANGE
P_INST
P
P_RANGE
Q_INST
Q
Q_RANGE
PF
PF_RANGE
ILAG
ILEAD
U
U_RANGE
I
I_RANGE
F
F_RANGE
IEC10000016-1-en.vsd
IEC10000016 V1 EN-US
CMMXU
I3P* IL1
IL1RANG
IL1ANGL
IL2
IL2RANG
IL2ANGL
IL3
IL3RANG
IL3ANGL
IEC05000699-2-en.vsd
IEC05000699 V2 EN-US
VMMXU
U3P* UL12
UL12RANG
UL12ANGL
UL23
UL23RANG
UL23ANGL
UL31
UL31RANG
UL31ANGL
IEC05000701-2-en.vsd
IEC05000701 V2 EN-US
CMSQI
I3P* 3I0
3I0RANG
3I0ANGL
I1
I1RANG
I1ANGL
I2
I2RANG
I2ANGL
IEC05000703-2-en.vsd
IEC05000703 V2 EN-US
VMSQI
U3P* 3U0
3U0RANG
3U0ANGL
U1
U1RANG
U1ANGL
U2
U2RANG
U2ANGL
IEC05000704-2-en.vsd
IEC05000704 V2 EN-US
VNMMXU
U3P* UL1
UL1RANG
UL1ANGL
UL2
UL2RANG
UL2ANGL
UL3
UL3RANG
UL3ANGL
IEC09000850-1-en.vsd
IEC09000850 V1 EN-US
18.1.4 Signals
PID-6713-INPUTSIGNALS v3
PID-6713-OUTPUTSIGNALS v3
PID-6735-INPUTSIGNALS v3
PID-6735-OUTPUTSIGNALS v3
PID-6738-INPUTSIGNALS v2
PID-6738-OUTPUTSIGNALS v2
PID-6736-INPUTSIGNALS v3
PID-6736-OUTPUTSIGNALS v3
PID-6739-INPUTSIGNALS v2
PID-6739-OUTPUTSIGNALS v2
PID-6737-INPUTSIGNALS v2
PID-6737-OUTPUTSIGNALS v2
The available setting parameters of the measurement function (MMXU, MSQI) are
depending on the actual hardware (TRM) and the logic configuration made in
PCM600.
These six functions are not handled as a group, so parameter settings are only
available in the first setting group.
The following terms are used in the Unit and Description columns:
• UBase (UB): Base voltage in primary kV. This voltage is used as reference for
voltage setting. It can be suitable to set this parameter to the rated primary
voltage supervised object.
• IBase (IB): Base current in primary A. This current is used as reference for
current setting. It can be suitable to set this parameter to the rated primary
current of the supervised object.
• SBase (SB): Base setting for power values in MVA.
PID-6713-SETTINGS v3
PID-6735-SETTINGS v3
PID-6738-SETTINGS v2
PID-6736-SETTINGS v3
PID-6739-SETTINGS v2
PID-6737-SETTINGS v2
PID-6735-MONITOREDDATA v3
PID-6738-MONITOREDDATA v2
PID-6736-MONITOREDDATA v3
PID-6739-MONITOREDDATA v2
PID-6737-MONITOREDDATA v2
The protection, control, and monitoring IEDs have functionality to measure and
further process information for currents and voltages obtained from the pre-
processing blocks. The number of processed alternate measuring quantities
depends on the type of IED and built-in options.
All phase angles are presented in relation to a defined reference channel. The
General setting parameter PhaseAngleRef defines the reference, see section
"Analog inputs".
Measured value below zero point clamping limit is forced to zero. This allows the
noise in the input signal to be ignored. The zero point clamping limit is a general
setting (XZeroDb where X equals S, P, Q, PF, U, I, F, IL1-3, UL1-3, UL12-31, I1,
I2, 3I0, U1, U2 or 3U0). Observe that this measurement supervision zero point
clamping might be overridden by the zero point clamping used for the
measurement values within CVMMXN.
Users can continuously monitor the measured quantity available in the function
block by means of four defined operating thresholds, see figure 580. The
monitoring has two different modes of operating:
• Overfunction, when the measured quantity exceeds the High limit (XHiLim) or
High-high limit (XHiHiLim) pre-set values
• Underfunction, when the measured quantity decreases under the Low limit
(XLowLim) or Low-low limit (XLowLowLim) pre-set values.
X_RANGE = 3
High-high limit
X_RANGE= 1 Hysteresis
High limit
X_RANGE=0
X_RANGE=0 t
Low limit
X_RANGE=2
Low-low limit
X_RANGE=4
IEC05000657-3-en.vsdx
IEC05000657 V3 EN-US
The logical value of the functional output signals changes according to figure 580.
The user can set the hysteresis (XLimHyst), which determines the difference
between the operating and reset value at each operating point, in wide range for
each measuring channel separately. The hysteresis is common for all operating
values within one channel.
The actual value of the measured quantity is available locally and remotely. The
measurement is continuous for each measured quantity separately, but the reporting
of the value to the higher levels depends on the selected reporting mode. The
following basic reporting modes are available:
In addition to the normal cyclic reporting the IED also report spontaneously when
measured value passes any of the defined threshold limits.
Y
Value Reported Value Reported
Value Reported Value Reported
(1st)
Y3 Value Reported
Y2 Y4
Y1 Y5
t
Value 1
Value 2
Value 3
Value 4
Value 5
(*)Set value for t: XDbRepInt IEC05000500-2-en.vsdx
IEC05000500 V2 EN-US
If a measuring value is changed, compared to the last reported value, and the
change is larger than the ±ΔY pre-defined limits that are set by user (XDbRepInt),
then the measuring channel reports the new value to a higher level. This limits the
information flow to a minimum necessary. Figure 582 shows an example with the
amplitude dead-band supervision. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle
from each other.
Value Reported
Y
IEC99000529-2-en.vsdx
IEC99000529 V2 EN-US
After the new value is reported, the ±ΔY limits for dead-band are automatically set
around it. The new value is reported only if the measured quantity changes more
than defined by the ±ΔY set limits.
The measured value is reported if the time integral of all changes exceeds the pre-
set limit (XDbRepInt), figure 583, where an example of reporting with integral
dead-band supervision is shown. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle
from each other.
The last value reported, Y1 in figure 583 serves as a basic value for further
measurement. A difference is calculated between the last reported and the newly
measured value and is multiplied by the time increment (discrete integral). The
absolute values of these integral values are added until the pre-set value is
exceeded. This occurs with the value Y2 that is reported and set as a new base for
the following measurements (as well as for the values Y3, Y4 and Y5).
Y A1 >=
A >= pre-set value
A2 >=
pre-set value pre-set value
Y3 A3 + A4 + A5 + A6 + A7 >=
pre-set value
Y2 A1 A2
A4 A6
Value Reported Y4 A3 A5 A7
Value
(1st) Value
A Reported Y5
Reported Value
Reported Value
Y1 Reported
t
IEC99000530-2-en.vsdx
IEC99000530 V2 EN-US
In this mode of operation, the reporting interval will be cyclic like in reporting type
cyclic. This cyclic time has three options: 5sec, 30 sec and 1 min.
Additionally, if a measuring value has changed from the last reported value, and
the change is larger than ±ΔY predefined limits that are set by user (XDbRepInt),
then the measuring channel reports the new value to a higher level immediately
irrespective of cyclic trigger. See Figure 584 for example.
Value
Value
Reported
Y5
Y6
Y’ -ΔY
+ΔY
Y1 Y7
Y2 Y4 Y”
Y3
Δt Δt Δt Δt Δt Δt
Time
IEC16000109-1-en.vsdx
IEC16000109 V1 EN-US
Figure 584: Example of value reporting in mode dead band and xx cyclic (xx : 5
sec , 30 sec, 1 min)
Set value for Formula used for complex, three- Formula used for voltage and Comment
parameter phase power calculation current magnitude calculation
“Mode”
1 L1, L2, L3 Used when
* * *
S = U L1 × I L1 + U L 2 × I L 2 + U L 3 × I L 3 U = ( U L1 + U L 2 + U L 3 ) / 3 three phase-
(Equation 223) to-earth
EQUATION1385 V1 EN-US
I = ( I L1 + I L 2 + I L 3 ) / 3
voltages are
EQUATION1386 V1 EN-US (Equation 224) available
voltage is
EQUATION1392 V1 EN-US (Equation 230) available
voltage is
EQUATION1394 V1 EN-US (Equation 232) available
voltage is
EQUATION1396 V1 EN-US (Equation 234) available
7 L1 Used when
S = 3 × U L1 × I L*1 U = 3 × U L1 only UL1
phase-to-
(Equation 235) earth voltage
I = I L1
EQUATION1397 V1 EN-US
is available
EQUATION1398 V1 EN-US (Equation 236)
Table continues on next page
Set value for Formula used for complex, three- Formula used for voltage and Comment
parameter phase power calculation current magnitude calculation
“Mode”
8 L2 Used when
S = 3 × U L 2 × I L* 2 U = 3 × U L2 only UL2
phase-to-
(Equation 237) earth voltage
I = IL2
EQUATION1399 V1 EN-US
is available
EQUATION1400 V1 EN-US (Equation 238)
9 L3 Used when
S = 3 × U L 3 × I L* 3 U = 3 × U L3 only UL3
phase-to-
(Equation 239) earth voltage
I = I L3
EQUATION1401 V1 EN-US
is available
EQUATION1402 V1 EN-US (Equation 240)
* means complex conjugated value
It shall be noted that only in the first two operating modes that is, 1 & 2 the
measurement function calculates the three-phase power accurately. In other
operating modes that is, from 3 to 9 it calculates the three-phase power under
assumption that the power system is fully symmetrical. Once the complex apparent
power is calculated then the P, Q, S, & PF are calculated in accordance with the
following formulas:
P = Re( S )
EQUATION1403 V1 EN-US (Equation 241)
Q = Im( S )
EQUATION1404 V1 EN-US (Equation 242)
S = S = P2 + Q2
EQUATION1405 V1 EN-US (Equation 243)
PF = cosj = P
S
EQUATION1406 V1 EN-US (Equation 244)
Additionally to the power factor value, the two binary output signals from the
function are provided which indicates the angular relationship between the current
and voltage phasors. Binary output signal ILAG is set TRUE when current phasor
is lagging behind voltage phasor. Binary output signal ILEAD is set TRUE when
current phasor is leading the voltage phasor.
Measured currents and voltages used in the CVMMXN function can be calibrated
to get 0.5 class measuring accuracy. This is achieved by amplitude and angle
compensation at 5, 30 and 100% of rated current and voltage. The compensation
below 5% and above 100% is constant and linear in between, see example in
figure 585.
IEC05000652 V2 EN-US
The first current and voltage phase signal, in the group signals will be used as
reference. The amplitude and angle compensation will be used for other related
input signals.
X = k × X Old + (1 - k ) × X Calculated
EQUATION1407 V1 EN-US (Equation 245)
where:
X is a new measured value (that is P, Q, S, U, I or PF) to be given out from the function
XOld is the measured value given from the measurement function in previous execution cycle
k is settable parameter by the end user which influence the filter properties
Default value for parameter k is 0.00. With this value the new calculated value is
immediately given out without any filtering (that is, without any additional delay).
When k is set to value bigger than 0, the filtering is enabled. Appropriate value of k
shall be determined separately for every application. Some typical value for k
=0.14.
In order to compensate for small amplitude and angular errors in the complete
measurement chain (CT error, VT error, IED input transformer errors and so on.) it
is possible to perform on site calibration of the power measurement. This is
achieved by setting the complex constant which is then internally used within the
function to multiply the calculated complex apparent power S. This constant is set
as amplitude (setting parameter PowAmpFact, default value 1.000) and angle
(setting parameter PowAngComp, default value 0.0 degrees). Default values for
these two parameters are done in such way that they do not influence internally
calculated value (complex constant has default value 1). In this way calibration, for
specific operating range (for example, around rated power) can be done at site.
However, to perform this calibration it is necessary to have an external power
meter with high accuracy class available.
Directionality SEMOD54417-256 v7
Busbar
IED
P Q
Protected
Object
IEC09000038-1-en.vsd
IEC09000038-1-EN V1 EN-US
Practically, it means that active and reactive power will have positive values when
they flow from the busbar towards the protected object and they will have negative
values when they flow from the protected object towards the busbar.
In some application, for example, when power is measured on the secondary side
of the power transformer it might be desirable, from the end client point of view, to
have actually opposite directional convention for active and reactive power
measurements. This can be easily achieved by setting parameter PowAngComp to
value of 180.0 degrees. With such setting the active and reactive power will have
positive values when they flow from the protected object towards the busbar.
Frequency SEMOD54417-261 v2
Phase currents (amplitude and angle) are available on the outputs and each
amplitude output has a corresponding supervision level output (ILx_RANG). The
supervision output signal is an integer in the interval 0-4, see
section "Measurement supervision".
Positive, negative and three times zero sequence quantities are available on the
outputs (voltage and current, amplitude and angle). Each amplitude output has a
corresponding supervision level output (X_RANGE). The output signal is an
integer in the interval 0-4, see section "Measurement supervision".
GUID-5E04B3F9-E1B7-4974-9C0B-DE9CD4A2408F v6
GUID-374C2AF0-D647-4159-8D3A-71190FE3CFE0 v5
GUID-9B8A7FA5-9C98-4CBD-A162-7112869CF030 v5
GUID-47094054-A828-459B-BE6A-D7FA1B317DA7 v6
GUID-ED634B6D-9918-464F-B6A4-51B78129B819 v6
18.2.1 Identification
GUID-AD96C26E-C3E5-4B21-9ED6-12E540954AC3 v4
Insulation supervision for gas medium (SSIMG) is used for monitoring the circuit
breaker condition. Binary information based on the gas pressure in the circuit
breaker is used as input signals to the function. In addition, the function generates
alarms based on received information.
SSIMG
BLOCK LOCKOUT
BLKALM PRESLO
SENPRES TEMPLO
SENTEMP ALARM
SENPRESALM PRESALM
SENPRESLO TEMPALM
SETPLO PRESSURE
SETTLO TEMP
RESETLO
IEC09000129-2-en.vsdx
IEC09000129 V2 EN-US
18.2.4 Signals
GUID-89749F71-CAEB-4A57-A1F0-148CCF68E97E v2
PID-6950-INPUTSIGNALS v6
PID-6950-OUTPUTSIGNALS v6
18.2.5 Settings
PID-6950-SETTINGS v6
Gas medium supervision SSIMG is used to monitor the gas pressure in the circuit
breaker. Binary inputs of gas density SENPRESALM, SENPRESLO, and gas
pressure signal SENPRES, are taken into account to initiate the alarm PRESALM
and the lockout PRESLO. When SENPRES is less than PresAlmLimit or binary
signal from CB SENPRESALM is high, the gas pressure alarm PRESALM will be
initiated. Similarly, if pressure input SENPRES is less than PresLOLimit or binary
signal from CB SENPRESLO is high, PRESLO will be initiated.
There may be sudden change in pressure of the gas for a very small time, for which
the function need not to initiate any alarm. To avoid the intermittent alarm, two
time delays tPressureAlarm or tPressureLO have been included. If the pressure
goes below the settings for more than these time delays, the corresponding alarm
PRESALM or lockout PRESLO will be initiated. The SETPLO binary input is
used for setting the gas pressure lockout PRESLO. The PRESLO output retains the
last value until it is reset by using the binary input RESETLO. The binary input
BLKALM can be used to block the alarms, and the BLOCK input can block both
alarm and the lockout indications.
Temperature of the medium is available from the input signal of temperature. The
signal is monitored to detect high temperature.
There may be sudden change in temperature of the medium for a very small time,
for which the function need not to initiate any alarm. To avoid the intermittent
alarm, two time delays tTempAlarm or tTempLockOut have been included. If the
temperature goes above the settings for more than these time delays, the
corresponding alarm TEMPALM or lockout TEMPLO will be initiated. The
SETTLO binary input is used for setting the temperature lockout TEMPLO. The
TEMPLO output retains the last value until it is reset by using the binary input
RESETLO. The binary input BLKALM can be used to block the alarms, and the
BLOCK input can block both alarm and the lockout indications.
The output ALARM goes high if the pressure alarm condition or the temperature
alarm condition exists inside the circuit breaker. The output ALARM can be
blocked by activating BLOCK or BLKALM inputs.
The output LOCKOUT goes high if the pressure lockout condition or the
temperature lockout condition exists inside the circuit breaker and it resets by using
the binary input RESETLO. The output LOCKOUT can be blocked by activating
BLOCK input.
18.3.1 Identification
GUID-4CE96EF6-42C6-4F2E-A190-D288ABF766F6 v3
Insulation supervision for liquid medium (SSIML) is used for monitoring the
transformer condition. Binary information based on the oil level in the transformer
is used as input signals to the function. In addition, the function generates alarms
based on received information.
SSIML
BLOCK LOCKOUT
BLKALM LVLLO
SENLEVEL TEMPLO
SENTEMP ALARM
SENLVLALM LVLALM
SENLVLLO TEMPALM
SETLLO LEVEL
SETTLO TEMP
RESETLO
IEC09000128-2-en.vsdx
IEC09000128 V2 EN-US
18.3.4 Signals
GUID-0C378BB3-2104-417F-94B5-16EFC55151FE v2
PID-6951-INPUTSIGNALS v7
PID-6951-OUTPUTSIGNALS v7
18.3.5 Settings
PID-6951-SETTINGS v7
Liquid medium supervision SSIML is used to monitor the oil level in the
transformer. Binary inputs of oil level SENLVLALM, SENLVLLO and oil level
signal SENLEVEL are taken into account to initiate the alarm LVLALM and the
lockout LVLLO. When SENLEVEL is less than LevelAlmLimit or binary signal
from transformer SENLVLALM is high, the oil level indication alarm LVLALM
will be initiated. Similarly, if oil level input SENLEVEL is less than LevelLOLimit
or binary signal from transformer SENLVLLO is high, the oil level indication
lockout LVLLO will be initiated.
There may be sudden change in oil level for a very small time, for which the
function need not to initiate any alarm. To avoid the intermittent alarm, two time
delays tLevelAlarm or tLevelLockOut have been included. If the oil level goes
below the settings for more than these time delays, the corresponding alarm
LVLALM or lockout LVLLO will be initiated. The SETLLO binary input is used
for setting the liquid level lockout LVLLO. The LVLLO output retains the last
value until it is reset by using the binary input RESETLO. The binary input
BLKALM can be used for blocking the alarms, and the BLOCK input can block
both alarms and the lockout indication.
Temperature of the medium is available from the input signal of temperature. The
signal is monitored to detect high temperature.
There may be sudden change in temperature of the medium for a very small time,
for which the function need not to initiate any alarm. To avoid the intermittent
The output ALARM goes high if the level alarm condition or the temperature
alarm condition exists in the transformer. The output ALARM can be blocked by
activating BLOCK or BLKALM inputs.
The output LOCKOUT goes high if the pressure lockout condition or the
temperature lockout condition exists in the transformer and it resets by using the
binary input RESETLO. The output LOCKOUT can be blocked by activating
BLOCK input.
SSCBR
I3P* OPENPOS
BLOCK CLOSEPOS
BLKALM INVDPOS
TRIND TRCMD
POSOPEN TRVTOPAL
POSCLOSE TRVTCLAL
PRESALM OPERALM
PRESLO OPERLO
SPRCHRST CBLIFEAL
SPRCHRD MONALM
RSTCBWR IPOWALPH
RSTTRVT IPOWLOPH
RSTIPOW SPCHALM
RSTSPCHT GPRESALM
GPRESLO
IEC13000231-2-en.vsd
IEC13000231 V2 EN-US
18.4.4 Signals
PID-3267-INPUTSIGNALS v10
PID-3267-OUTPUTSIGNALS v10
18.4.5 Settings
PID-3267-SETTINGS v10
I3P-ILRMSPH
POSCLOSE TTRVOP
POSOPEN CB Contact Travel TTRVCL
BLOCK Time TRVTOPAL
BLKALM TRVTCLAL
RSTTRVT
OPENPOS
CB Status CLOSEPOS
INVDPOS
CBLIFEAL
Remaining Life of CB
CBLIFEPH
RSTCBWR
TRCMD
Accumulated IPOWALPH
energy
I3P-IL IPOWLOPH
TRIND
IPOWPH
RSTIPOW
CB Operation OPERALM
Cycles NOOPER
CB Operation MONALM
Monitoring INADAYS
SPCHALM
SPRCHRST CB Spring Charge SPCHT
SPRCHRD Monitoring
RSTSPCHT
The circuit breaker contact travel time subfunction calculates the breaker contact
travel time for opening and closing operations. The operation of the breaker contact
travel time measurement is described in figure591.
POSCLOSE TTRVOP
Contact travel
POSOPEN time TTRVCL
calculation
RSTTRVT
TRVTOPAL
Alarm limit
BLOCK check TRVTCLAL
BLKALM
IEC12000615-2-en.vsd
IEC12000615 V2 EN-US
Figure 591: Functional module diagram for circuit breaker contact travel time
Main Contact
1
0
POSCLOSE
POSOPEN
1
t1 tOpen t2 t3 tClose t4
IEC12000616 V2 EN-US
There is a time difference t1 between the start of the main contact opening and the
opening of the POSCLOSE auxiliary contact. Similarly, there is a time difference t2
between the time when the POSOPEN auxiliary contact opens and the main contact
is completely open. Therefore, a correction factor needs to be added to get the
actual opening time. This factor is added with the OpenTimeCorr (t1+t2) setting.
The closing time is calculated by adding the value set with the CloseTimeCorr
(t3+t4) setting to the measured closing time.
The last measured opening travel time (TTRVOP) and the closing travel time
(TTRVCL) are given as service values.
The values can be reset using the Clear menu on the LHMI or by activation the
input RSTCBWR.
The circuit breaker status subfunction monitors the position of the circuit breaker,
that is, whether the breaker is in the open, closed or error position. The operation is
described in figure 593.
Phase current
I3P-ILRMSPH
check
OPENPOS
Contact
POSCLOSE position CLOSEPOS
indicator
POSOPEN INVDPOS
IEC12000613-3-en.vsd
IEC12000613 V3 EN-US
Figure 593: Functional module diagram for monitoring circuit breaker status
contacts have the same value or if the auxiliary input contact POSCLOSE is low
and the POSOPEN input is high but the current is above the setting AccStopCurr.
The status of the breaker is indicated with the binary outputs OPENPOS,
CLOSEPOS and INVDPOS for open, closed and error position respectively.
I3P-ILRMSPH
CB remaining CBLIFEPH
POSCLOSE life estimation
RSTCBWR
Alarm limit
BLOCK CBLIFEAL
Check
BLKALM
IEC12000620-3-en.vsd
IEC12000620 V3 EN-US
Figure 594: Functional module diagram for estimating the life of the circuit
breaker
The old circuit breaker operation counter value can be used by adding the value to
the InitCBRemLife parameter. The value can be reset using the Clear menu from
LHMI or by activating the input RSTCBWR.
The Accumulated energy subfunction calculates the accumulated energy (Iyt) based
on current samples, where the setting CurrExponent (y) ranges from 0.5 to 3.0. The
operation is described in figure 595.
The TRCMD output is enabled when either of the trip indications from the trip coil
circuit TRIND is high or the breaker status is OPENPOS.
I3P-IL
TRCMD
I3P-ILRMSPH Accumulated
POSCLOSE energy
calculation IPOWPH
TRIND
LRSTIPOW
IPOWALPH
Alarm limit
BLOCK Check IPOWLOPH
BLKALM
IEC12000619-3-en.vsd
IEC12000619 V3 EN-US
The calculation is initiated with the POSCLOSE or TRIND input events. It ends
when the RMS current is lower than the AccStopCurr setting.
open open
POSCLOSE 1 POSCLOSE 1
0 0
Energy Energy
Accumulation Accumulation
starts starts
ContTrCorr ContTrCorr
(Negative) (Positive)
IEC12000618_1_en.vsd
IEC12000618 V1 EN-US
Accumulated energy can also be calculated by using the change of state of the trip
output. TRIND is used to get the instance of the trip output and the time delay
between the trip initiation and the opening of the main contact is introduced by the
setting OperTimeDelay.
The accumulated energy output IPOWPH is provided as a service value. The value
can be reset by enabling RSTIPOW through LHMI or by activating the input
RSTIPOW.
IPOWLOPH is activated when the accumulated energy exceeds the limit of the
LOAccCurrPwr setting.
The IPOWALPH and IPOWLOPH outputs can be blocked by activating the binary
input BLKALM.
The circuit breaker operation cycles subfunction counts the number of closing-
opening sequences of the breaker. The operation counter value is updated after
each closing-opening sequence. The operation is described in figure597.
POSCLOSE
Operation
POSOPEN NOOPER
counter
RSTCBWR
OPERALM
Alarm limit
BLOCK
Check
OPERLO
BLKALM
IEC12000617 V2 EN-US
Figure 597: Functional module diagram for circuit breaker operation cycles
Operation counter
The operation counter counts the number of operations based on the state of change
of the auxiliary contact inputs POSCLOSE and POSOPEN.
The number of operations NOOPER is given as a service value. The old circuit
breaker operation counter value can be used by adding the value to the
InitCounterVal parameter and can be reset by Clear CB wear in the Clear menu on
the LHMI or activating the input RSTCBWR.
If the number of operations increases and exceeds the limit value set with the
OperLOLevel setting, the OPERLO output is activated.
The binary outputs OPERALM and OPERALO are deactivated when the BLKALM
input is activated.
The circuit breaker operation monitoring subfunction indicates the inactive days of
the circuit breaker and gives an alarm when the number of days exceed the set
level. The operation of the circuit breaker operation monitoring is shown in figure
598.
POSCLOSE
Inactive timer INADAYS
POSOPEN
Figure 598: Functional module diagram for circuit breaker operation monitoring
Inactive timer
The Inactive timer module calculates the number of days the circuit breaker has
remained in the same open or closed state. The value is calculated by monitoring
the states of the POSOPEN and POSCLOSE auxiliary contacts.
The number of inactive days INADAYS is available as a service value. The initial
number of inactive days is set using the InitInactDays parameter.
The circuit breaker spring charge monitoring subfunction calculates the spring
charging time. The operation is described in figure 599.
SPRCHRST
Spring charging
SPRCHRD time SPCHT
measurement
RSTSPCHT
Alarm limit
BLOCK SPCHALM
Check
BLKALM
IEC12000621 V2 EN-US
Figure 599: Functional module diagram for circuit breaker spring charge
indication
The binary input SPRCHRST indicates the start of circuit breaker spring charging
time. SPRCHRD indicates that the circuit breaker spring is charged. The spring
charging time is calculated from the difference of these two signal timings. Spring
charging indication is described in figure 599.
The last measured spring charging time SPCHT is provided as a service value. The
spring charging time SPCHT can be reset on the LHMI or by activating the input
RSTSPCHT.
It is possible to block the SPCHALM alarm signal by activating the BLKALM binary
input.
The circuit breaker gas pressure indication subfunction monitors the gas pressure
inside the arc chamber. The operation is described in figure 600.
PRESALM
tDGasPresAlm
BLOCK AND t GPRESALM
BLKALM
tDGasPresLO
PRESLO AND t GPRESLO
IEC12000622 V3 EN-US
Figure 600: Functional module diagram for circuit breaker gas pressure
indication
When the PRESALM binary input is activated, the GPRESALM output is activated
after a time delay set with the tDGasPresAlm setting. The GPRESALM alarm can be
blocked by activating the BLKALM input.
If the pressure drops further to a very low level, the PRESLO binary input goes
high, activating the lockout alarm GPRESLO after a time delay set with the
tDGasPresLO setting. The GPRESLO alarm can be blocked by activating the
BLKALM input.
The binary input BLOCK can be used to block the function. The activation of the
BLOCK input deactivates all outputs and resets internal timers. The alarm signals
from the function can be blocked by activating the binary input BLKALM.
18.5.1 Identification
SEMOD167950-2 v2
Analog, integer and double indication values are also transferred through the
EVENT function.
EVENT
BLOCK
^INPUT1
^INPUT2
^INPUT3
^INPUT4
^INPUT5
^INPUT6
^INPUT7
^INPUT8
^INPUT9
^INPUT10
^INPUT11
^INPUT12
^INPUT13
^INPUT14
^INPUT15
^INPUT16
IEC05000697-2-en.vsd
IEC05000697 V2 EN-US
PID-4145-INPUTSIGNALS v6
PID-4145-SETTINGS v6
The main purpose of the Event function (EVENT) is to generate events when the
state or value of any of the connected input signals is in a state, or is undergoing a
state transition, for which event generation is enabled.
Each EVENT function has 16 inputs INPUT1 - INPUT16. Each input can be given
a name from the Application Configuration tool. The inputs are normally used to
create single events, but are also intended for double indication events. For double
indications, only the first eight inputs, 1–8, must be used. Inputs 9–16 can be used
for other types of events in the same EVENT block.
The EVENT function also has an input BLOCK to block the generation of events.
Events that are sent from the IED can originate from both internal logical signals
and binary input channels. The internal signals are time-tagged in the main
processing module, while the binary input channels are time-tagged directly on the
input module. Time-tagging of the events that are originated from internal logical
signals have a resolution corresponding to the execution cycle-time of the source
application. Time-tagging of the events that are originated from binary input
signals have a resolution of 1 ms.
The outputs from the EVENT function are formed by the reading of status, events
and alarms by the station level on every single input. The user-defined name for
each input is intended to be used by the station level.
All events according to the event mask are stored in a buffer, which contains up to
1000 events. If new events appear before the oldest event in the buffer is read, the
oldest event is overwritten and an overflow alarm appears.
Events are produced according to set event masks. The event masks are treated
commonly for both the LON and SPA communication. An EventMask can be set
individually for each input channel. These settings are available:
• NoEvents
• OnSet
• OnReset
• OnChange
• AutoDetect
It is possible to define which part of the EVENT function generates the events.
This can be performed individually for communication types SPAChannelMask and
LONChannelMask. For each communication type these settings are available:
• Off
• Channel 1-8
• Channel 9-16
• Channel 1-16
For LON communication, events are normally sent to station level at change. It is
also possible to set a time for cyclic sending of the events individually for each
input channel.
To protect the SA system from signals with a high change rate that can easily
saturate the EVENT function or the communication subsystems behind it, a quota
limiter is implemented. If an input creates events at a rate that completely consume
the granted quota then further events from the channel will be blocked. This block
will be removed when the input calms down and the accumulated quota reach 66%
of the maximum burst quota. The maximum burst quota per input channel is 45
events per second.
18.6.1 Identification
M16055-1 v8
Complete and reliable information about disturbances in the primary and/or in the
secondary system together with continuous event-logging is accomplished by the
disturbance report functionality.
• Event list
• Indications
• Event recorder
• Trip value recorder
• Disturbance recorder
• Fault locator
• Settings information
Every disturbance report recording is saved in the IED in the standard Comtrade
format as a reader file HDR, a configuration file CFG, and a data file DAT. The
same applies to all events, which are continuously saved in a ring-buffer. The local
HMI is used to get information about the recordings. The disturbance report files
can be uploaded to PCM600 for further analysis using the disturbance handling
tool.
M12510-3 v3
DRPRDRE
DRPOFF
RECSTART
RECMADE
CLEARED
MEMUSED
IEC05000406-3-en.vsd
IEC05000406 V3 EN-US
SEMOD54837-4 v4
A1RADR
^GRP INPUT1
^GRP INPUT2
^GRP INPUT3
^GRP INPUT4
^GRP INPUT5
^GRP INPUT6
^GRP INPUT7
^GRP INPUT8
^GRP INPUT9
^GRP INPUT10
IEC05000430-4-en.vsdx
IEC05000430 V4 EN-US
A4RADR
^INPUT31
^INPUT32
^INPUT33
^INPUT34
^INPUT35
^INPUT36
^INPUT37
^INPUT38
^INPUT39
^INPUT40
IEC05000431-3-en.vsd
IEC05000431 V3 EN-US
B1RBDR
^INPUT1
^INPUT2
^INPUT3
^INPUT4
^INPUT5
^INPUT6
^INPUT7
^INPUT8
^INPUT9
^INPUT10
^INPUT11
^INPUT12
^INPUT13
^INPUT14
^INPUT15
^INPUT16
IEC05000432-3-en.vsd
IEC05000432 V3 EN-US
Figure 605: B1RBDR function block, binary inputs, example for B1RBDR -
B22RBDR
18.6.4 Signals
PID-3949-OUTPUTSIGNALS v2
PID-4014-INPUTSIGNALS v6
GUID-D025D5D9-A0F3-4A00-891A-63AD5F609A77 v2
A2RADR and A3RADR functions have the same input signal specifications as
A1RADR but with different numbering:
• A2RADR: GRPINPUT11 to GRPINPUT20 (group signal for inputs 11 to 20)
• A3RADR: GRPINPUT21 to GRPINPUT30 (group signal for inputs 21 to 30)
A4RADR block is used to record the calculated analog values of any type, not
related to hardware devices (e.g. difference currents, power factors etc.).
PID-4017-INPUTSIGNALS v6
PID-3798-INPUTSIGNALS v6
GUID-D3A8067F-80F8-4174-BD2D-4C43F4B99020 v3
18.6.5 Settings
PID-7068-SETTINGS v1
PID-4014-SETTINGS v7
GUID-E05EEC82-CB90-4E73-B9C9-4C16FD95FCBF v1
A2RADR to A4RADR functions have the same Non group settings (basic) as
A1RADR but with different numbering:
A2RADR to A4RADR functions have the same Non group settings (advanced) as
A1RADR but with different numbering (examples given in brackets):
PID-3798-SETTINGS v6
GUID-8702C5B9-05A3-4E61-8952-C66483FFDFE2 v3
B2RBDR to B22RBDR functions have the same Non group settings (basic) as
B1RBDR but with different numbering (examples given in brackets):
• B2RBDR: 17 to 32 (SetLED17, set LED on HMI for binary channel 17)
• B3RBDR: 33 to 48 (SetLED33, set LED on HMI for binary channel 33)
• B4RBDR: 49 to 64 (SetLED49, set LED on HMI for binary channel 49)
• B5RBDR: 65 to 80 (SetLED65, set LED on HMI for binary channel 65)
• B6RBDR: 81 to 96 (SetLED81, set LED on HMI for binary channel 81)
• B7RBDR: 97 to 112 (SetLED97, set LED on HMI for binary channel 97)
• B8RBDR: 113 to 128 (SetLED113, set LED on HMI for binary channel 113)
• B9RBDR: 129 to 144 (SetLED129, set LED on HMI for binary channel 129)
• B10RBDR: 145 to 160 (SetLED145, set LED on HMI for binary channel 145)
• B11RBDR: 161 to 176 (SetLED161, set LED on HMI for binary channel 161)
• B12RBDR: 177 to 192 (SetLED177, set LED on HMI for binary channel 177)
• B13RBDR: 193 to 208 (SetLED193, set LED on HMI for binary channel 193)
• B14RBDR: 209 to 224 (SetLED209, set LED on HMI for binary channel 209)
• B15RBDR: 225 to 240 (SetLED225, set LED on HMI for binary channel 225)
• B16RBDR: 241 to 256 (SetLED241, set LED on HMI for binary channel 241)
• B17RBDR: 257 to 272 (SetLED257, set LED on HMI for binary channel 257)
• B18RBDR: 273 to 288 (SetLED273, set LED on HMI for binary channel 273)
• B19RBDR: 289 to 304 (SetLED289, set LED on HMI for binary channel 289)
• B20RBDR: 305 to 320 (SetLED305, set LED on HMI for binary channel 305)
• B21RBDR: 321 to 336 (SetLED321, set LED on HMI for binary channel 321)
• B22RBDR: 337 to 352 (SetLED337, set LED on HMI for binary channel 337)
B2RBDR to B22RBDR functions have the same Non group settings (advanced) as
B1RBDR but with different numbering (examples given in brackets):
• B2RBDR: 17 to 32 (IndicationMa17, indication mask for binary channel 17)
• B3RBDR: 33 to 48 (IndicationMa33, indication mask for binary channel 33)
• B4RBDR: 49 to 64 (IndicationMa49, indication mask for binary channel 49)
• B5RBDR: 65 to 80 (IndicationMa65, indication mask for binary channel 65)
• B6RBDR: 81 to 96 (IndicationMa81, indication mask for binary channel 81)
• B7RBDR: 97 to 112 (IndicationMa97, indication mask for binary channel 97)
• B8RBDR: 113 to 128 (IndicationMa113, indication mask for binary channel
113)
• B9RBDR: 129 to 144 (IndicationMa129, indication mask for binary channel
129)
• B10RBDR: 145 to 160 (IndicationMa145, indication mask for binary channel
145)
• B11RBDR: 161 to 176 (IndicationMa161, indication mask for binary channel
161)
• B12RBDR: 177 to 192 (IndicationMa177, indication mask for binary channel
177)
• B13RBDR: 193 to 208 (IndicationMa193, indication mask for binary channel
193)
• B14RBDR: 209 to 224 (IndicationMa209, indication mask for binary channel
209)
• B15RBDR: 225 to 240 (IndicationMa225, indication mask for binary channel
225)
• B16RBDR: 241 to 256 (IndicationMa241, indication mask for binary channel
241)
• B17RBDR: 257 to 272 (IndicationMa257, indication mask for binary channel
257)
• B18RBDR: 273 to 288 (IndicationMa273, indication mask for binary channel
273)
• B19RBDR: 289 to 304 (IndicationMa289, indication mask for binary channel
289)
• B20RBDR: 305 to 320 (IndicationMa305, indication mask for binary channel
305)
• B21RBDR: 321 to 336 (IndicationMa321, indication mask for binary channel
321)
• B22RBDR: 337 to 352 (IndicationMa337, indication mask for binary channel
337)
Figure 606 shows the relations between Disturbance Report, included functions
and function blocks. Event list (EL), Event recorder (ER) and Indications (IND)
uses information from the binary input function blocks (BxRBDR). Trip value
recorder (TVR) uses analog information from the analog input function blocks
(AxRADR) which is used by FL after estimation by TVR. Disturbance recorder
DRPRDRE acquires information from both AxRADR and BxRBDR.
DRPRDRE FL
Analog signals
Trip value rec Fault locator
BxRBDR Disturbance
recorder
Binary signals
Event list
Event recorder
Indications
IEC09000336-3-en.vsdx
IEC09000336 V3 EN-US
The whole disturbance report can contain information for a number of recordings,
each with the data coming from all the parts mentioned above. The event list
function is working continuously, independent of disturbance triggering, recording
time, and so on. Settings information function contains all the visible settings,
parameter information of components configured in ACT, runtime status and
IEC61850 behavior that is added to the disturbance record header file. These
settings information is recorded in XML format and then grouped for each function
instance in the HDR file. The function, setting names and Enum values are same as
in the HMI and can be translated to the selected HMI language. All setting values
are updated along with the units. If the setting values are related to the global base
value, then the setting value is scaled and updated with corresponding global base
unit. All information in the disturbance report is stored in non-volatile flash
memories. This implies that no information is lost in case of loss of auxiliary
power. Each report will get an identification number in the interval from 0-999.
Disturbance report
General dist.
Trip Event Disturbance
Information & Setting Indications Fault locator Event list
values recordings recording
infotrmation
IEC05000125-2-en.vsdx
IEC05000125 V2 EN-US
Number of recordings
100
3,4 s
80 3,4 s 20 analog
96 binary
40 analog
96 binary
60 6,3 s
6,3 s
6,3 s 50 Hz
40
60 Hz
Total recording time
en05000488.vsd
IEC05000488 V1 EN-US
Figure 608: Example of number of recordings versus the total recording time
The IED flash disk should NOT be used to store any user files. This
might cause disturbance recordings to be deleted due to lack of disk
space.
Date and time of the disturbance, the indications, events, fault location and the trip
values are available on the local HMI. To acquire a complete disturbance report the
user must use a PC and - either the PCM600 Disturbance handling tool - or a FTP
or MMS (over 61850) client. The PC can be connected to the IED front, rear or
remotely via the station bus (Ethernet ports).
Indications is a list of signals that were activated during the total recording time of
the disturbance (not time-tagged).
The event recorder may contain a list of up to 150 time-tagged events, which have
occurred during the disturbance. The information is available via the local HMI or
PCM600.
The event list may contain a list of totally 1000 time-tagged events. The list
information is continuously updated when selected binary signals change state. The
oldest data is overwritten. The logged signals may be presented via local HMI or
PCM600.
The recorded trip values include phasors of selected analog signals before the fault
and during the fault.
Disturbance recorder records analog and binary signal data before, during and after
the fault.
For each disturbance recording, the setting values of the configured components
are read twice; once during the trigger of disturbance record and again during post
processing of the disturbance record.
During post processing of the disturbance record, the header file is updated with a
section called Settings . Settings has complete setting values of the configured
components that are read during the trigger time. The setting values, runtime status
and the behavior of each component are compared between the trigger and the post
processing time. If there are any differences, then it will be added in the header file
under section Changed_settings.
In the HDR file, section tag Settings has an attribute tag called function which
includes parameters that are grouped based on the function instance. The function
tag has content called name which is the function name provided together with the
user-defined name in brackets similar to the HMI. Status content will indicate the
runtime status of the function and beh content will indicate the IEC61850 behavior
of the components, if supported. Non runtime components will not have status and
beh tag contents.
Parameters of the function are listed as a child tag Set with contents name, value
and unit:
• name — parameter name same as HMI
• value — actual parameter value
• unit — parameter unit
The IED has a built-in real-time calendar and clock. This function is used for all
time tagging within the disturbance report
Trig point
TimeLimit
PreFaultRecT PostFaultRecT
1 2 3
en05000487.vsd
IEC05000487 V1 EN-US
PreFaultRecT, 1 Pre-fault or pre-trigger recording time. The time before the fault including the
operate time of the trigger. Use the setting PreFaultRecT to set this time.
tFault, 2 Fault time of the recording. The fault time cannot be set. It continues as long as
any valid trigger condition, binary or analog, persists (unless limited by TimeLimit
the limit time).
PostFaultRecT, 3 Post fault recording time. The time the disturbance recording continues after all
activated triggers are reset. Use the setting PostFaultRecT to set this time.
TimeLimit Limit time. The maximum allowed recording time after the disturbance recording
was triggered. The limit time is used to eliminate the consequences of a trigger
that does not reset within a reasonable time interval. It limits the maximum
recording time of a recording and prevents subsequent overwriting of already
stored disturbances. Use the setting TimeLimit to set this time.
SMAI A1RADR
Block AI3P A2RADR
^GRP2L1 AI1 INPUT1 A3RADR
External
analogue ^GRP2L2 AI2 INPUT2
signals ^GRP2L3 AI3 INPUT3
^GRP2N AI4 INPUT4
Type AIN INPUT5
INPUT6
...
A4RADR
INPUT31
INPUT32
INPUT33
Internal analogue signals INPUT34
INPUT35
INPUT36
...
INPUT40
IEC10000029-1-en.vsd
IEC10000029 V1 EN-US
The external input signals will be acquired, filtered and skewed and (after
configuration) available as an input signal on the AxRADR function block via the
SMAI function block. The information is saved at the Disturbance report base
sampling rate (1000 or 1200 Hz). Internally calculated signals are updated
according to the cycle time of the specific function. If a function is running at
lower speed than the base sampling rate, Disturbance recorder will use the latest
updated sample until a new updated sample is available.
If the IED is preconfigured the only tool needed for analog configuration of the
Disturbance report is the Signal Matrix Tool (SMT, external signal configuration).
In case of modification of a preconfigured IED or general internal configuration the
Application Configuration tool within PCM600 is used.
The preprocessor function block (SMAI) calculates the residual quantities in cases
where only the three phases are connected (AI4-input not used). SMAI makes the
information available as a group signal output, phase outputs and calculated
residual output (AIN-output). In situations where AI4-input is used as an input
signal the corresponding information is available on the non-calculated output
(AI4) on the SMAI function block. Connect the signals to the AxRADR
accordingly.
For each of the analog signals, Operation = On means that it is recorded by the
disturbance recorder. The trigger is independent of the setting of Operation, and
triggers even if operation is set to Off. Both undervoltage and overvoltage can be
used as trigger conditions. The same applies for the current signals.
The analog signals are presented only in the disturbance recording, but they affect
the entire disturbance report when being used as triggers.
Each of the 352 signals can be selected as a trigger of the disturbance report
(Operation = On). A binary signal can be selected to activate the red LED on the
local HMI (SetLED = On).
The selected signals are presented in the event recorder, event list and the
disturbance recording. But they affect the whole disturbance report when they are
used as triggers. The indications are also selected from these 352 signals with local
HMI IndicationMask = Show/Hide.
The trigger conditions affect the entire disturbance report, except the event list,
which runs continuously. As soon as at least one trigger condition is fulfilled, a
complete disturbance report is recorded. On the other hand, if no trigger condition
is fulfilled, there is no disturbance report, no indications, and so on. This implies
the importance of choosing the right signals as trigger conditions.
• Manual trigger
• Binary-signal trigger
• Analog-signal trigger (over/under function)
A disturbance report can be manually triggered from the local HMI, PCM600 or
via station bus (IEC 61850). When the trigger is activated, the manual trigger
signal is generated. This feature is especially useful for testing. Refer to the
operator's manual for procedure.
Any binary signal state (logic one or a logic zero) can be selected to generate a
trigger (Triglevel = Trig on 0/Trig on 1). When a binary signal is selected to
generate a trigger from a logic zero, the selected signal will not be listed in the
indications list of the disturbance report.
All analog signals are available for trigger purposes, no matter if they are recorded
in the disturbance recorder or not. The settings are OverTrigOp, UnderTrigOp,
OverTrigLe and UnderTrigLe.
The check of the trigger condition is based on peak-to-peak values. When this is
found, the absolute average value of these two peak values is calculated. If the
average value is above the threshold level for an overvoltage or overcurrent trigger,
this trigger is indicated with a greater than (>) sign with the user-defined name.
If the average value is below the set threshold level for an undervoltage or
undercurrent trigger, this trigger is indicated with a less than (<) sign with its name.
The procedure is separately performed for each channel.
This method of checking the analog start conditions gives a function which is
insensitive to DC offset in the signal. The operate time for this start is typically in
the range of one cycle, 20 ms for a 50 Hz network.
All under/over trig signal information is available on the local HMI and PCM600.
The Logical signal status report (BINSTATREP) function makes it possible for a
SPA master to poll signals from various other functions.
BINSTATREP
BLOCK OUTPUT1
^INPUT1 OUTPUT2
^INPUT2 OUTPUT3
^INPUT3 OUTPUT4
^INPUT4 OUTPUT5
^INPUT5 OUTPUT6
^INPUT6 OUTPUT7
^INPUT7 OUTPUT8
^INPUT8 OUTPUT9
^INPUT9 OUTPUT10
^INPUT10 OUTPUT11
^INPUT11 OUTPUT12
^INPUT12 OUTPUT13
^INPUT13 OUTPUT14
^INPUT14 OUTPUT15
^INPUT15 OUTPUT16
^INPUT16
IEC09000730-1-en.vsd
IEC09000730 V1 EN-US
18.7.4 Signals
PID-4144-INPUTSIGNALS v6
PID-4144-OUTPUTSIGNALS v6
18.7.5 Settings
PID-4144-SETTINGS v6
The Logical signal status report (BINSTATREP) function has 16 inputs and 16
outputs. The output status follows the inputs and can be read from the local HMI or
via SPA communication.
When an input is set, the respective output is set for a user defined time. If the
input signal remains set for a longer period, the output will remain set until the
input signal resets.
INPUTn
OUTPUTn
t t
IEC09000732-1-en.vsd
IEC09000732 V1 EN-US
18.8.1 Identification
SEMOD113212-2 v3
supervised with four settable limits: low-low limit, low limit, high limit and high-
high limit. The measure value expander block (RANGE_XP) has been introduced
to enable translating the integer output signal from the measuring functions to 5
binary signals: below low-low limit, below low limit, normal, above high limit or
above high-high limit. The output signals can be used as conditions in the
configurable logic or for alarming purpose.
RANGE_XP
RANGE* HIGHHIGH
HIGH
NORMAL
LOW
LOWLOW
IEC05000346-2-en.vsd
IEC05000346 V2 EN-US
PID-3819-INPUTSIGNALS v5
PID-3819-OUTPUTSIGNALS v5
The input signal must be connected to a range output of a measuring function block
(CVMMXN, CMMXU, VMMXU, VNMMXU, CMSQI, VMSQ or MVGAPC).
The function block converts the input integer value to five binary output signals
according to table 843.
18.9.1 Identification
M14892-1 v3
The accurate fault locator is an essential component to minimize the outages after a
persistent fault and/or to pin-point a weak spot on the line.
The fault locator is an impedance measuring function giving the distance to the
fault in km, miles or % of line length. The main advantage is the high accuracy
achieved by compensating for load current and for the mutual zero-sequence effect
on double circuit lines.
The compensation includes setting of the remote and local sources and calculation
of the distribution of fault currents from each side. This distribution of fault
current, together with recorded load (pre-fault) currents, is used to exactly calculate
the fault position. The fault can be recalculated with new source data at the actual
fault to further increase the accuracy.
Especially on heavily loaded long lines, where the source voltage angles can be up
to 35-40 degrees apart, the accuracy can be still maintained with the advanced
compensation included in fault locator.
LMBRFLO
PHSELL1* CALCMADE
PHSELL2* FLT_X
PHSELL3* BCD_80
CALCDIST* BCD_40
BCD_20
BCD_10
BCD_8
BCD_4
BCD_2
BCD_1
IEC05000679-4-en.vsd
IEC05000679 V4 EN-US
18.9.4 Signals
PID-3906-INPUTSIGNALS v1
PID-3906-OUTPUTSIGNALS v1
18.9.5 Settings
PID-3906-SETTINGS v2
When calculating distance to fault, pre-fault and fault phasors of currents and
voltages are selected from the Trip value recorder data, thus the analog signals used
by the fault locator must be among those connected to the disturbance report
function. The analog configuration (channel selection) is performed using the
parameter setting tool within PCM600.
The calculation algorithm considers the effect of load currents, double-end infeed
and additional fault resistance.
R0L+jX0L
R1L+jX1L
R1A+jX1A R1B+jX1B
Z0m=Z0m+jX0m
R0L+jX0L
R1L+jX1L
DRPRDRE
LMBRFLO
IEC05000045_2_en.vsd
IEC05000045 V2 EN-US
Figure 615: Simplified network configuration with network data, required for
settings of the fault location-measuring function
If source impedance in the near and far end of the protected line have changed in a
significant manner relative to the set values at fault location calculation time (due
to exceptional switching state in the immediate network, power generation out of
order, and so on), new values can be entered via the local HMI and a recalculation
of the distance to the fault can be ordered using the algorithm described below. It’s
also possible to change fault loop. In this way, a more accurate location of the fault
can be achieved.
The function indicates the distance to the fault as a percentage of the line length, in
kilometers or miles according to the setting LineLengthUnit. The fault location is
stored as a part of the disturbance report information (ER, DR, IND, TVR and FL)
and managed via the local HMI or PCM600.
For transmission lines with voltage sources at both line ends, the effect of double-
end infeed and additional fault resistance must be considered when calculating the
distance to the fault from the currents and voltages at one line end. If this is not
done, the accuracy of the calculated figure will vary with the load flow and the
amount of additional fault resistance.
The calculation algorithm used in the fault locator in compensates for the effect of
double-end infeed, additional fault resistance and load current.
M14983-5 v1
Figure 616 shows a single-line diagram of a single transmission line, that is fed
from both ends with source impedances ZA and ZB. Assume that the fault occurs at
a distance F from IED A on a line with the length L and impedance ZL. The fault
resistance is defined as RF. A single-line model is used for better clarification of
the algorithm.
A B
ZA IA pZL IB (1-p).ZL ZB
IF
UA RF
xx01000171.vsd
IEC01000171 V1 EN-US
U A = I A × p × Z L + IF × R F
EQUATION95 V1 EN-US (Equation 246)
Where:
IA is the line current after the fault, that is, pre-fault current plus current change due to the fault,
IF A
IF = --------
DA
EQUATION96 V1 EN-US (Equation 247)
Where:
IFA is the change in current at the point of measurement, IED A and
DA is a fault current-distribution factor, that is, the ratio between the fault current at line end A
and the total fault current.
( 1 – p ) × Z L + ZB
DA = -----------------------------------------
Z A + Z L + ZB
EQUATION97 V1 EN-US (Equation 248)
Thus, the general fault location equation for a single line is:
I FA
U A = I A × p × Z L + -------
- × RF
DA
EQUATION98 V1 EN-US (Equation 249)
Table 849: Expressions for UA, IA and IFA for different types of faults
The KN complex quantity for zero-sequence compensation for the single line is
equal to:
Z0L – Z 1L
K N = ------------------------
3 × Z1L
EQUATION99 V1 EN-US (Equation 250)
DI is the change in current, that is the current after the fault minus the current
before the fault.
In the following, the positive sequence impedance for ZA, ZB and ZL is inserted
into the equations, because this is the value used in the algorithm.
I FA
U A = I A × p × Z 1L + -------- × RF + I 0P × Z 0M
DA
EQUATION100 V1 EN-US (Equation 251)
Where:
I0P is a zero sequence current of the parallel line,
( 1 – p ) × ( ZA + ZA L + ZB ) + Z B
DA = ----------------------------------------------------------------------------
-
2 × ZA + Z L + 2 × Z B
EQUATION101 V1 EN-US (Equation 252)
Z0L – Z 1L Z 0M I 0P
K N = ------------------------ + ----------------- × -------
3 × Z1L 3 × Z1L I 0A
EQUATION102 V1 EN-US (Equation 253)
From these equations it can be seen, that, if Z0m = 0, then the general fault location
equation for a single line is obtained. Only the distribution factor differs in these
two cases.
Where:
UA ZB
K 1 = ---------------- + --------------------------- + 1
I A × ZL Z L + ZA DD
UA ZB
K2 = --------------- × æè --------------------------- + 1öø
IA × Z L Z L + Z A DD
I F A æ Z A + ZB
- × --------------------------- + 1ö
K 3 = ---------------
I A × Z L è Z 1 + ZA DD ø
EQUATION106 V1 EN-US (Equation 257)
and:
For a single line, Z0M = 0 and ZADD = 0. Thus, equation 254 applies to both single
and parallel lines.
2
p – p × Re ( K 1 ) + Re ( K 2 ) – R F × Re ( K 3 ) = 0
EQUATION107 V1 EN-US (Equation 258)
– p × Im × ( K1 ) + Im × ( K 2 ) – R F × Im × ( K3 ) = 0
EQUATION108 V1 EN-US (Equation 259)
If the imaginary part of K3 is not zero, RF can be solved according to equation 259,
and then inserted to equation 258. According to equation 258, the relative distance
to the fault is solved as the root of a quadratic equation.
Equation 258 gives two different values for the relative distance to the fault as a
solution. A simplified load compensated algorithm, which gives an unequivocal
figure for the relative distance to the fault, is used to establish the value that should
be selected.
If the load compensated algorithms according to the above do not give a reliable
solution, a less accurate, non-compensated impedance model is used to calculate
the relative distance to the fault.
U A = p × Z 1 L × IA + R F × IA
EQUATION109 V1 EN-US (Equation 260)
Where:
IA is according to table 849.
The communication protocol IEC 60870-5-103 may be used to poll fault location
information from the IED to a master (that is station HSI). There are two outputs
that must be connected to appropriate inputs on the function block I103StatFltDis,
FLTDISTX gives distance to fault (reactance, according the standard) and
CALCMADE gives a pulse (100 ms) when a result is obtainable on FLTDISTX
output.
18.10.1 Identification
The Limit counter (L4UFCNT) provides a settable counter with four independent
limits where the number of positive and/or negative flanks on the input signal are
counted against the setting values for limits. The output for each limit is activated
when the counted value reaches that limit.
Limit counter (L4UFCNT) counts the number of positive and/or negative flanks on
the binary input signal depending on the function settings. L4UFCNT also checks
if the accumulated value is equal or greater than any of its four settable limits. The
four limit outputs will be activated relatively on reach of each limit and remain
activated until the reset of the function. Moreover, the content of L4UFCNT is
stored in flash memory and will not be lost at an auxiliary power interruption.
BLOCK
INPUT
Operation
Counter
RESET
VALUE
Overflow
CountType Detection OVERFLOW
OnMaxValue
Limit LIMIT1 … 4
MaxValue Check
CounterLimit1...4
Error ERROR
Detection
InitialValue
IEC12000625_1_en.vsd
IEC12000625 V1 EN-US
The counter can be initialized to count from a settable non-zero value after reset of
the function. The function has also a maximum counted value check. The three
possibilities after reaching the maximum counted value are:
• Stops counting and activates a steady overflow indication for the next count
• Rolls over to zero and activates a steady overflow indication for the next count
• Rolls over to zero and activates a pulsed overflow indication for the next count
The pulsed overflow output lasts up to the first count after rolling over to zero, as
illustrated in figure 618.
Overflow indication
Actual value ... Max value -1® Max value ® Max value +1 ® Max value +2 ® Max value +3 ...
IEC12000626_1_en.vsd
IEC12000626 V1 EN-US
The Error output is activated as an indicator of setting the counter limits and/or
initial value setting(s) greater than the maximum value. The counter stops counting
the input and all the outputs except the error output remains at zero state. The error
condition remains until the correct settings for counter limits and/or initial value
setting(s) are applied.
The function can be blocked through a block input. During the block time, input is
not counted and outputs remain in their previous states. However, the counter can
be initialized after reset of the function. In this case the outputs remain in their
initial states until the release of the block input.
Reset of the counter can be performed from the local HMI or via a binary input.
Reading of content and resetting of the function can also be performed remotely,
for example from a IEC 61850 client. The value can also be presented as a
measurement on the local HMI graphical display.
L4UFCNT
BLOCK ERROR
INPUT OVERFLOW
RESET LIMIT1
LIMIT2
LIMIT3
LIMIT4
VALUE
IEC12000029-1-en.vsd
IEC12000029 V1 EN-US
18.10.5 Signals
PID-6966-INPUTSIGNALS v2
PID-6966-OUTPUTSIGNALS v2
18.10.6 Settings
PID-6966-SETTINGS v2
BLOCK
RESET
IN Time Accumulation ACC_HOUR
ADDTIME with Retain
ACC_DAY
tAddToTime
q-1
OVERFLOW
a
&
a>b
99 999.9 h b
WARNING
a
&
a>b
tWarning b
ALARM
a
&
a>b
tAlarm b
IEC15000321 V1 EN-US
TEILGAPC
BLOCK ALARM
IN WARNING
ADDTIME OVERFLOW
RESET ACC_HOUR
ACC_DAY
IEC15000323.vsdx
IEC15000323 V1 EN-US
18.11.4 Signals
PID-6998-INPUTSIGNALS v1
PID-6998-OUTPUTSIGNALS v1
18.11.5 Settings
PID-6998-SETTINGS v1
Loop Delay
tWarning
OVERFLOW
tAlarm
Transgression Supervision WARNING
Plus Retain
ALARM
BLOCK
RESET ACC_HOUR
Time Accumulation
IN
ADDTIME ACC_DAY
tAddToTime
Loop Delay
IEC15000322.vsd
IEC15000322 V1 EN-US
tAlarm and tWarning are user settable time limit parameters in hours. They are also
independent of each other, that is, there is no check if tAlarm > tWarning.
The limit for the overflow supervision is fixed at 99999.9 hours. The outputs will
reset and the accumulated time will reset and start from zero if an overflow occurs.
18.12.1 Identification
GUID-A3D72F4B-9567-4DF0-867A-9F657A7E9291 v1
temperature exceeds certain limit. LOLSPTR gives warning and alarm signals
when the winding hot spot temperature reaches a set value.
Hot spot temperature calculation requires top oil temperature at a given time. This
value can either be a measured value taken through sensors or the one calculated by
the function. This decision is made based on the top oil temperature sensor quality.
Top oil temperature calculation is done using the method explained in IEC 60076-7
standard.
The oil and winding time constants can be calculated by the function based on
transformer parameters if the inputs are not available from the transformer
manufacturer.
Ambient temperature to the function can either be provided through the sensor or
monthly average ambient temperature settings. This decision is made based on the
ambient temperature sensor quality. Additionally, LOLSPTR function provides
difference between measured value and calculated value of the top oil temperature.
Additionally, the function calculates loss of life in form of days and years. This
information is updated at settable intervals, for example, hourly or daily.
Transformer winding percentage loss of life is calculated every day and the
information is provided as total percentage loss of life from the installation date
and yearly percentage loss of life.
LOLSPTR
I3PW1* ALARM1
I3PW2* ALARM2
I3PW3* WARNING1
BLOCK WARNING2
BLKALM HPCALERR
BLKWRN
TOTVALID
AMBVALID
TCPOS
COOLTYPE
TOTEMP
AMBTEMP
LOLRST
REFRESH
IEC15000442-1-en.vsdx
IEC15000442 V1 EN-US
18.12.4 Signals
PID-6645-INPUTSIGNALS v4
PID-6645-OUTPUTSIGNALS v4
18.12.5 Settings
PID-6645-SETTINGS v4
When the winding hot spot temperature exceeds certain limit, it causes degradation
of the transformer winding insulation. The function gives warning and alarm
signals when the winding hot spot temperature reaches the set value.
Transformer thermal model using heat transfer differential equations are designed
by the IEC 60076–7 standard. This thermal model can be applied to time varying
load factor (K) and time varying ambient temperature (θa). The differential
equations computation is required at each time step (n) and the hot spot
temperature rise for the nth time step is solved using:
Where:
K = Load factor
θa = Ambient temperature
n = Time step
h 2( n) h 2( n1) D h 2( n )
IECEQUATION16007 V1 EN-US (Equation 263)
Differential equation 262 represents the fundamental hot spot temperature rise
before the effect of oil flow varying rate past the hot spot of the winding and the
time derivative function is:
D h1( n )
Dt
k K y h1( n1)
k22 w 21 hr
IECEQUATION16008 V1 EN-US (Equation 264)
Differential equation 263 represents the oil flow varying rate past the hot spot of
the winding and the time derivative function is:
D h 2( n )
Dt
1
k21 1 hr K y h 2( n1)
k o
22
IECEQUATION16009 V1 EN-US (Equation 265)
Where:
y = Empirically derived exponent account for the effect of change in resistance and
oil viscosity with change in load.
Combined effect of differential equations 262 and 263 represents the hot spot
temperature rise after sudden change in the load. The initial conditions are
calculated by setting the time derivative equal to zero in DΔθh1(n) and DΔθh2(n)
equations.
Where:
Δθh(n) = Hot spot temperature rise above top oil temperature at nth time step
The hot spot temperature rise above top oil temperature (Δθh) is calculated from the
hot spot to top oil temperature gradient (Δθhr) and it should be calculated for each
winding. Equation for the hot spot to top oil temperature gradient calculation is:
Where:
Top oil temperature rise and hot spot temperature values are taken
from heat run test.
Hot spot temperature calculations for loading should be made on both low voltage
and high voltage windings since test data indicates that the time constants are
different. Hence, LOLSPTR function calculates the hot spot temperature
(HPTEMPWx) winding wise.
The maximum winding hot spot temperature is used for calculation of winding
insulation loss of life and also for warning and alarm signals. The winding with
maximum hot spot temperature is provided by the output MAXHPWDG in the
form of winding number. If the given transformer is a two winding transformer,
then HPTEMPW3 will be zero.
Hot spot temperature is calculated by measuring the top oil temperature using
sensors or otherwise the function will use the calculated top oil temperature. IEC
standard has developed a differential equation for the top oil temperature
calculation. Equation for the nth time step is:
0( n) 0( n 1) D 0( n)
IECEQUATION16012 V1 EN-US (Equation 268)
and,
D 0( n )
Dt
1 K 2 R
tap x
or o ( n1) a
k11 o 1 Rtap
IECEQUATION16013 V1 EN-US (Equation 269)
Where,
LOLSPTR function can be sensor usage less function based on the following
logics:
The ambient temperatures are defined every month using the JanAmbTmp to
DecAmbTmp settings. This monthly model of ambient temperature is taken for the
top oil temperature calculation based on the month of the year.
LOLSPTR handles top oil temperature calculation even though the direct
measurement of top oil temperature is available.
Transformer parameters for the entire calculation of the function are selected
according to:
• Transformer type
• Rated power
• Cooling medium used
Transformer type can be selected as either Three Phase Trafo or Single Phase Trafo
using TrafoType setting. Rated power can be set using the TrafoRating setting.
• OFAF
• OFWF
• ODWF
User can select the transformer parameters either from IEC 60076-7 standard or
IEEE C57.96-1995 standard using ConstSelection setting to IEC or IEEE
respectively.
Winding time constant, oil time constant and loss ratios at different tap positions
are calculated internally to improve the accuracy of the temperature calculations
based on the user selection.
LOLSPTR has three options to select the winding time constant using
WdgTmConstMode setting:
• If WdgTmConstMode setting is selected as Standard, then the time constant is
taken from either IEC or IEEE standard based on ConstSelection setting.
• If WdgTmConstMode setting is selected as User defined, then the time
constant is taken from user through WdgTimeConstx setting. This is different
for each winding.
• If WdgTmConstMode setting is selected as Calculated, then the time constant
is calculated by the function for each winding.
W
mw C g
1000 Pw
IECEQUATION16014 V1 EN-US (Equation 270)
where,
The conductor specific heat is based on conductor type. The conductor type
selection, either Aluminum or Copper, can be done through ConductorType setting.
LOLSPTR has three options to select the oil time constant using OilTmConstMode
setting:
o
3.6 C om
P
IECEQUATION16015 V1 EN-US (Equation 271)
where,
Average oil temperature rise (Δθom) at the load considered is calculated using
settings:
• Average oil temperature (AvgOilTmpRise) from the heat run test
• Transformer rated no-load and load losses (NoloadLoss and LoadLoss)
• No-load and load losses from type test (TTNoloadLoss and TTLoadLoss)
Thermal capacity for different cooling mediums are calculated using settings:
• Mass of the coil and core (CoilCoreMass)
• Mass of the oil (OilMass)
• Mass of the tank (TankMass) in contact with heated oil.
Changes in the oil temperature rise, losses and winding gradients values are
depends on the transformer tap position. Transformer top oil temperature rise is a
function of the ratio loss (R) and ratio loss is a function of the tap position.
The tap changer position from TCPOS input is used to calculate the ratio loss using
linear approximation model. This calculation requires:
• Tap positions at rated voltage (RatedVoltTap)
• Minimum voltage (LowVoltTap)
• Maximum voltage (HighVoltTap)
• Related loss ratios (RLRated, RLMinTap and RLMaxTap)
Tap changer position input is also required to get the ratio loss at next higher
voltage tap position after rated voltage tap position (RLHighRated).
Tap changer position can be made available to the LOLSPTR function from the
TCLYLTC function block, see Figure 624.
TCLYLTC LOLSPTR
TCPOS TCPOS
IEC15000438-1-en.vsd
IEC15000438 V1 EN-US
Top oil temperature and hot spot temperature calculations are based on transformer
loading. Load factor is the ratio between actual current and rated current. The
function takes only one phase current from each windings as inputs to calculate
load factor.
Rated current for each winding is set through RatedCurrWX setting. Selection of
one phase current from each winding for load factor calculation is decided using
CurrSelectMode setting.
LOLSPTR can work with (n-1) winding CT availability. That is, if the given
transformer has three windings and it has CT’s only in two windings, then the
function will calculate the missing winding current based on voltage transformation
ratio. The CT availability can be set using AvailableCT setting.
• Winding 1&2
• Winding 1&3
Three winding transformer • Winding 2&3
• All Windings
Voltage rise between two adjacent tap winding is also considered in the calculation
and it is set using UPerTap setting.
The user can select temperature unit to be used for function interface by the
TempeUnitMode setting.
If the selection is °F, then all temperature inputs are converted into °C and used for
calculation, since all calculation formulae needs temperature values in °C and
finally the temperature outputs will be converted to °F.
If the selection is °C, then all temperature inputs will be taken as it is and the
output is given in °C.
The temperature distribution in transformer is not uniform and the part which is
operating at the highest temperature will normally deteriorate more. Therefore, rate
of ageing is referred to winding hot-spot temperature (HPTMPMAX). When
EnaAgeCalc is set to high, LOLSPTR will calculate the ageing rate of the
transformer winding insulation and accumulates the transformer loss of life.
Ageing rate calculation can be done using two formulas derived by IEEE (VIEEE)
and IEC (VIEC) standards. The calculation method selection is based on
ThermalUpgrade and AgeingRateMeth settings. The ThermalUpgrade Setting has
two options, Normal and Upgraded. Similarly, AgeingRateMeth setting has two
options, IEEE and IEC.
IEC standard (Equation 272) is used for ageing rate calculation only when the
ThermalUpgrade setting is set to Normal and AgeingRateMeth setting is set to IEC.
IEEE standard (Equation 273) is used for all other combinations.
where,
The computed loss of life over a certain period from aging rate is added to the
initial loss of life. Transformer loss of life value information is provided in days
and years and presented in LOLINDAY and LOLINYRS outputs respectively.
Hence, total transformer loss of life value should be considered from both outputs.
The updating time of the outputs depends on TimeToUpdate setting. These values
can be viewed at any time by activating REFRESH from local HMI reset menu
without affecting the set update time.
Initial condition for the loss of life is taken from InitialLife setting. If the
calculation purpose is to find out the loss of life for a particular overload
occurrence or new transformer installation, then InitialLife value for the
transformer should be chosen as zero. The user should pre-determine the consumed
transformer life in hours and the value should be filled in InitialLife setting in case
of previously installed transformers. The user can reset the initial loss of life value
by activating LOLRST from local HMI reset menu. Transformer winding
insulation remaining life REMLIFE is calculated from the transformer loss of life
and expected life value (ExpectedLife).
LOLSPTR calculates the percent loss of life from the relative ageing rate. Percent
loss of life in a day is calculated with time period of 24 hours. Daily rate of percent
loss of life is summarized at 00:00 h and displayed for the next 24 hour period in
PLOLTOT. Cumulative sum of percent loss of life in a day is calculated up to the
year end and it is updated at every year end in the output PLOLINYR. All the latest
calculated loss of life values and percentage loss of life values are stored in non-
volatile memory. Therefore, the values can be restored even after a power loss.
LOLSPTR provides warnings and alarms for the transformer thermal overload, if
the maximum hot spot temperature (HPTMPMAX) exceeds the set value. There
are two settable warning levels of the hot spot temperature with separate outputs. If
warning level exceeds for the set time, an alarm is generated. Criteria for warning
and alarm are:
To avoid oscillations of the warning and alarm outputs, a hysteresis has been added
with HPTMPMAX value for comparison with the set value.
The functionality can be blocked using BLOCK input. When the BLOCK input is
activated, the binary outputs from the function will reset and all analogue outputs
will hold the previous values till BLOCK input is deactivated. During blocking, all
the calculations (Loss of life, percentage loss of life, etc.) will be stopped. Once the
block input is deactivated, the calculations will start from previous calculated
values.
IEC15000439-1-en.vsdx
IEC15000439 V1 EN-US
Section 19 Metering
19.1.1 Identification
M14879-1 v4
S00947 V1 EN-US
PCFCNT
BLOCK INVALID
READ_VAL RESTART
BI_PULSE* BLOCKED
RS_CNT NEW_VAL
SCAL_VAL
IEC14000043-1-en.vsd
IEC09000335 V3 EN-US
19.1.4 Signals
PID-6509-INPUTSIGNALS v4
PID-6509-OUTPUTSIGNALS v4
19.1.5 Settings
PID-6509-SETTINGS v4
M13397-3 v5
The registration of pulses is done for positive transitions (0->1) on one of the 16
binary input channels located on the Binary Input Module (BIM). Pulse counter
values are sent to the station HMI with predefined cyclicity without reset.
The reporting time period can be set in the range from 1 second to 60 minutes and
is synchronized with absolute system time. Interrogation of additional pulse
counter values can be done with a command (intermediate reading) for a single
counter. All active counters can also be read by the LON General Interrogation
command (GI) or IEC 61850.
The reported value to station HMI over the station bus contains Identity, Scaled
Value (pulse count x scale), Time, and Pulse Counter Quality. The Pulse Counter
Quality consists of:
The transmission of the counter value by SPA can be done as a service value, that
is, the value frozen in the last integration cycle is read by the station HMI from the
database. PCFCNT updates the value in the database when an integration cycle is
finished and activates the NEW_VAL signal in the function block. This signal can
be connected to an Event function block, be time tagged, and transmitted to the
station HMI. This time corresponds to the time when the value was frozen by the
function.
M13399-3 v9
Figure 627 shows the pulse-counter logic function block with connections of the
inputs and outputs.
The BLOCK and READ_VAL inputs can be connected to Single Command logics,
which are intended to be controlled either from the station HMI or/and the local
HMI. As long as the BLOCK signal is set, the pulse counter is blocked. The signal
connected to READ_VAL performs one additional reading per positive flank. The
signal must be a pulse with a length >1 second.
The BI_PULSE input is connected to the used input of the function block for the
Binary Input Module (BIM).
Each pulse-counter logic function block has four binary output signals that can be
connected to an Event function block for event recording: INVALID, RESTART,
BLOCKED and NEW_VAL. The SCAL_VAL signal can be connected to the IEC
Event function block.
The INVALID signal is a steady signal and is set if the Binary Input Module, where
the pulse counter input is located, fails or has wrong configuration.
The RESTART signal is a steady signal and is set when the reported value does not
comprise a complete integration cycle. That is, in the first message after IED start-
up, in the first message after deblocking, and after the counter has wrapped around
during last integration cycle.
The BLOCKED signal is a steady signal and is set when the counter is blocked.
There are two reasons why the counter is blocked:
The NEW_VAL signal is a pulse signal. The signal is set if the counter value was
updated since last report.
M13404-2 v5
19.2.1 Identification
SEMOD175537-2 v4
The values of active and reactive energies are calculated from the input power
values by integrating them over a selected time tEnergy. The integration of active
and reactive energy values will happen in both forward and reverse directions.
These energy values are available as output signals and also as pulse outputs.
Integration of energy values can be controlled by inputs (STARTACC and
STOPACC) and EnaAcc setting and it can be reset to initial values with RSTACC
input.
The maximum demand for active and reactive powers are calculated for the set
time interval tEnergy and these values are updated every minute through output
channels. The active and reactive maximum power demand values are calculated
for both forward and reverse direction and these values can be reset with RSTDMD
input.
ETPMMTR
P* ACCINPRG
Q* EAFPULSE
STARTACC EARPULSE
STOPACC ERFPULSE
RSTACC ERRPULSE
RSTDMD EAFALM
EARALM
ERFALM
ERRALM
EAFACC
EARACC
ERFACC
ERRACC
MAXPAFD
MAXPARD
MAXPRFD
MAXPRRD
IEC14000019-1-en.vsd
IEC14000019 V1 EN-US
19.2.4 Signals
PID-6872-INPUTSIGNALS v3
PID-6872-OUTPUTSIGNALS v3
19.2.5 Settings
PID-6872-SETTINGS v3
The instantaneous output values of active and reactive power from the
Measurements function CVMMXN are used and integrated over a selected time
tEnergy to measure the integrated energy. Figure 629 shows the overall
functionality of the energy calculation and demand handling function ETPMMTR.
MAXPAFD
RSTDMD
MAXPARD
MAXPRFD
P
MAXPRRD
Zero Clamping Maximum Power
EAFALM
Detection Demand Calculation
Q EARALM
ERFALM
ERRALM
ACCINPRG
EAFPULSE
EARPULSE
ERFPULSE
Energy Accumulation ERRPULSE
STARTACC
Calculation EAFACC
EARACC
STOPACC
ERFACC
ERRACC
RSTACC
IEC13000185-2-en.vsd
IEC13000185 V2 EN-US
The integration of energy values is enabled by the setting EnaAcc and controlled by
the STARTACC and STOPACC inputs. If the integration is in progress, the output
ACCINPRG is high. Otherwise, it is low. Figure 630 shows the logic of the
ACCINPRG output. ACCINPRG is active when the STARTACC input is active and
the EnaAcc setting is enabled. When the RSTACC input is in the active state, the
output ACCINPRG is low even if the integration of energy is enabled. ACCINPRG
is deactivated by activating the STOPACC input.
STOPACC
FALSE
STARTACC T
³1
& F ACCINPRG
EnaAcc &
q-1
RSTACC
The accumulated energy values (in MWh and MVArh) are available as service
values and also as pulsed output depending on the ExxAccPlsQty setting, which can
be connected to a pulse counter. Accumulated energy outputs are available for
forward as well as reverse direction. The accumulated energy values can be reset to
initial accumulated energy values (ExxPrestVal) from the local HMI reset menu or
with the input signal RSTACC. Figure 631 shows the logic for integration of energy
in active forward direction. Similarly, the integration of energy in active reverse,
reactive forward and reactive reverse is done.
RSTACC
EAFPrestVal
ACCINPRG
P* (ACTIVE FORWARD)
X
T
T EAFACC
60.0
F
F
&
q-1
1000 GWh T
q-1 0.0 F
a
a>b
b
-1
q = unit delay
IEC13000187-5-en.vsdx
IEC13000187 V5 EN-US
tEnergyOffPls
EAFACC
a Counter q-1
a>b CU
1000 GWh b CV
Rst
tOff
t
R I q-1
0
÷ X
R I T
EAFPULSE
a TP
a>b F
b
EAFAccPlsQty ÷ 0
Counter
CU
CV
RSTACC
Rst
q-1
tEnergyOnPls
Figure 632: Logic for pulse generation of integrated active forward energy
The maximum demand values for active and reactive power are calculated for the
set time interval tEnergy. The maximum values are updated every minute and
stored in a register available over communication and from outputs MAXPAFD,
MAXPARD, MAXPRFD and MAXPRRD for the active and reactive power forward
and reverse direction. When the RSTDMD input is active from the local HMI reset
menu, these outputs are reset to zero. The energy alarm is activated once the
periodic energy value crosses the energy limit ExLim. Figure 633 shows the logic
of alarm for active forward energy exceeds limit and Maximum forward active
power demand value. Similarly, the maximum power calculation and energy alarm
outputs in the active reverse, reactive forward and reactive reverse is implemented.
P (ACTIVE FORWARD)
Average Power
X a EAFALM
tEnergy Calculation a>b
b
EALim
RSTMAXD
0.0 T MAXPAFD
MAX F
q-1
q-1 = unit delay
IEC13000189-4-en.vsd
IEC13000189 V4 EN-US
Figure 633: Logic for maximum power demand calculation and energy alarm
Table 877:
Function Range or value Accuracy
Energy metering MWh Export/Import, MVarh Input from MMXU. No extra
Export/Import error at steady load
Section 20 Ethernet
Device 1 Device 1
IEC16000092-1-en.vsdx
IEC16000092 V1 EN-US
Figure 634: Access points, non redundant (left) and redundant communication
(right)
DHCP is available for the front port, and a device connected to it can thereby
obtain an automatically assigned IP-address.
20.1.2 Settings
PID-6775-SETTINGS v4
PID-6637-SETTINGS v3
PID-6811-SETTINGS v3
SCHLCCH
LINKUP
DOSALARM
IEC16000044-1-en.vsdx
IEC16000044 V1 EN-US
RCHLCCH
REDLINKA
REDLINKB
DOSALARM
IEC16000045-1-en.vsdx
IEC16000045 V1 EN-US
FRONTSTATUS
LINKUP
DOSALARM
IEC16000085-1-en.vsdx
IEC16000085 V1 EN-US
20.2.3 Signals
PID-6818-OUTPUTSIGNALS v2
PID-6819-OUTPUTSIGNALS v2
PID-6813-OUTPUTSIGNALS v3
PID-6819-MONITOREDDATA v2
PID-6813-MONITOREDDATA v4
20.3.1 Identification
GUID-B7AE0374-0336-42B8-90AF-3AE1C79A4116 v1
The RCHLCCH function block supervise the redundant communication on the two
channels. If no data package has been received on one (or both) channels within the
last 10 s, the output LinkAUp and/or LinkBUp is set to 0 which indicates an error.
Device 1 Device 2
AP1 AP1
PhyPortA PhyPortB PhyPortA PhyPortB
Switch A Switch B
Device 3 Device 4
IEC09000758-4-en.vsd
IEC09000758 V4 EN-US
For each message sent, the node sends two frames, one through each port. Both the
frames circulate in opposite directions over the ring. Every node forwards the
frames it receives from one port to another to reach the next node. When the
originating sender node receives the frame it sent, the sender node discards the
frame to avoid loops
The RCHLCCH function block supervise the redundant communication on the two
channels. If no data package has been received on one (or both) channels within the
last 10 s, the output LinkAUp and/or LinkBUp is set to 0 which indicates an error.
Device 1 Device 2
AP1 AP1
PhyPortA PhyPortB PhyPortA PhyPortB
Device 3 Device 4
IEC16000038-1-en.vsdx
IEC16000038 V1 EN-US
The merging units (MU) are called so because they can gather analog values from
one or more measuring transformers, sample the data and send the data over
process bus to other clients (or subscribers) in the system. Some merging units are
able to get data from classical measuring transformers, others from non-
conventional measuring transducers and yet others can pick up data from both
types.
20.4.2 Settings
PID-6770-SETTINGS v2
PID-6850-SETTINGS v3
20.5 Routes
A route is a specified path for data to travel between the source device in a
subnetwork to the destination device in a different subnetwork. A route consists of
a destination address and the address of the gateway to be used when sending data
to the destination device, see Figure 640.
Default gateway
Gateway
Source Destination
IEC16000095-1-en.vsdx
IEC16000095 V1 EN-US
20.5.2 Settings
PID-6761-SETTINGS v2
Status of the protocols can be viewed in the LHMI under Main menu/
Diagnostics/IED status/Protocol diagnostics. The diagnostic values are:
Diagnostic value Description
Off Protocol is turned off
Error An error has occured, refer to event list for more
information
Warning Configuration inconsistency. Unable to locate
data point.
Ready Protocol is ready
IEC15000400-1-en.vsd
IEC15000400 V1 EN-US
IEC 61850 Ed.1 or Ed.2 can be chosen by a setting in PCM600. The IED is
equipped with up to six (order dependent) optical Ethernet rear ports for IEC
61850-8-1 station bus communication. The IEC 61850-8-1 communication is also
possible from the electrical Ethernet front port. IEC 61850-8-1 protocol allows
intelligent electrical devices (IEDs) from different vendors to exchange information
and simplifies system engineering. IED-to-IED communication using GOOSE and
client-server communication over MMS are supported. Disturbance recording file
(COMTRADE) uploading can be done over MMS or FTP.
When double Ethernet ports are activated, make sure that all ports
are connected to different subnets. For example: port 1 has IP
address 198.168.101.10 with subnet mask 255.255.255.0, and port
2 has IP address 198.168.102.10 with subnet mask 255.255.255.0.
21.4.3 Settings
PID-6702-SETTINGS v3
M15031-1 v8
SPGAPC
BLOCK
^IN
IEC14000021-1-en.vsd
IEC14000021 V1 EN-US
SP16GAPC
BLOCK
^IN1
^IN2
^IN3
^IN4
^IN5
^IN6
^IN7
^IN8
^IN9
^IN10
^IN11
^IN12
^IN13
^IN14
^IN15
^IN16
IEC14000020-1-en.vsd
IEC14000020 V1 EN-US
PID-3780-INPUTSIGNALS v6
PID-3781-INPUTSIGNALS v6
The function does not have any parameters available in the local HMI or PCM600.
PID-3781-MONITOREDDATA v3
Upon receiving a signal at its input, Generic communication function for Single
Point indication (SPGAPC) function sends the signal over IEC 61850-8-1 to the
equipment or system that requests this signal. Additional configuration is needed
with PCM600 or IET600 to get the IEC 61850-8-1 communication established For
more information refer to the Engineering manual.
MVGAPC
BLOCK ^VALUE
^IN RANGE
IEC14000022-1-en.vsd
IEC14000022 V1 EN-US
PID-6753-INPUTSIGNALS v1
PID-6753-OUTPUTSIGNALS v1
PID-6753-SETTINGS v1
Upon receiving an analog signal at its input, Generic communication function for
Measured Value (MVGAPC) will give the instantaneous value of the signal and the
range, as output values. Additional configuration is needed with PCM600 or
IET600 to get the IEC 61850-8-1 communication established. For more
information see the Engineering manual.
21.4.7.1 Identification
GUID-8C11DB9A-7844-4E1F-A6BB-D97ECE350FC1 v1
GOOSEDPRCV is used to receive a double point value using IEC 61850 protocol
via GOOSE.
GOOSEDPRCV
BLOCK ^DPOUT
^SRCDPOUT DATAVALID
COMMVALID
TEST
IEC10000249-2-en.vsdx
IEC10000249 V2 EN-US
21.4.7.4 Signals
GUID-2DC54788-86AF-4B4B-8E57-A89E30F0C433 v1
Except for the BLOCK input, the rest of the inputs of this GOOSE
function block are used for GOOSE connections. These
connections are visible and possible to make only if Easy GOOSE
engineering is enabled. For instructions on how to enable Easy
GOOSE engineering in PCM600, refer to the Engineering Manual.
PID-6828-INPUTSIGNALS v3
PID-6828-OUTPUTSIGNALS v3
21.4.7.5 Settings
PID-6828-SETTINGS v3
The DATAVALID output will be HIGH if the incoming message is with valid data.
The COMMVALID output will become LOW when the sending IED is under total
failure condition and the GOOSE transmission from the sending IED does not
happen.
The TEST output will go HIGH if the sending IED is in test mode.
Data Value Data Valid Comm Valid Test
Incoming data with q=Normal Updated 1 1 0
Incoming data with q=oldData 0 0 1 0
Incoming data with q=Invalid 0 0 1 0
Incoming data with q=test 0 0 1 1
Incoming data with q=test+oldData 0 0 1 1
Receiver in block 0 0 1 0
Receiver in block and 0 0 0 0
communication error
Table continues on next page
21.4.8.1 Identification
GUID-93A1E81B-1DE8-483A-BB3B-DB771EE66DC1 v1
GOOSEINTRCV is used to receive an integer value using IEC 61850 protocol via
GOOSE.
GOOSEINTRCV
BLOCK ^INTOUT
^SRCINTOUT DATAVALID
COMMVALID
TEST
IEC10000250-2-en.vsd
IEC10000250 V2 EN-US
21.4.8.4 Signals
GUID-2DC54788-86AF-4B4B-8E57-A89E30F0C433 v1
Except for the BLOCK input, the rest of the inputs of this GOOSE
function block are used for GOOSE connections. These
connections are visible and possible to make only if Easy GOOSE
engineering is enabled. For instructions on how to enable Easy
GOOSE engineering in PCM600, refer to the Engineering Manual.
PID-6829-INPUTSIGNALS v3
PID-6829-OUTPUTSIGNALS v3
21.4.8.5 Settings
PID-6829-SETTINGS v3
The DATAVALID output will be HIGH if the incoming message is with valid data.
The COMMVALID output will become LOW when the sending IED is under total
failure condition and the GOOSE transmission from the sending IED does not
happen.
The TEST output will go HIGH if the sending IED is in test mode.
21.4.9.1 Identification
GUID-B1FFBE08-C823-4A58-9FE0-A9A20DA6BB44 v1
GOOSEMVRCV is used to receive measured value using IEC 61850 protocol via
GOOSE.
GOOSEMVRCV
BLOCK ^MVOUT
^SRCMVOUT DATAVALID
COMMVALID
TEST
IEC10000251-2-en.vsd
IEC10000251 V2 EN-US
21.4.9.4 Signals
GUID-2DC54788-86AF-4B4B-8E57-A89E30F0C433 v1
Except for the BLOCK input, the rest of the inputs of this GOOSE
function block are used for GOOSE connections. These
connections are visible and possible to make only if Easy GOOSE
engineering is enabled. For instructions on how to enable Easy
GOOSE engineering in PCM600, refer to the Engineering Manual.
PID-6830-INPUTSIGNALS v3
PID-6830-OUTPUTSIGNALS v3
21.4.9.5 Settings
PID-6830-SETTINGS v3
The DATAVALID output will be HIGH if the incoming message is with valid data.
The COMMVALID output will become LOW when the sending IED is under total
failure condition and the GOOSE transmission from the sending IED does not
happen.
The TEST output will go HIGH if the sending IED is in test mode.
Data Value Data Valid Comm Valid Test
Incoming data with q=Normal Updated 1 1 0
Incoming data with q=oldData Freeze 0 1 0
Incoming data with q=Invalid Freeze 0 1 0
Incoming data with q=test Freeze 0 1 1
Incoming data with q=test+oldData Freeze 0 1 1
21.4.10.1 Identification
GUID-F2B30A70-842E-435E-8FAB-B1E58B9C0164 v1
GOOSESPRCV is used to receive a single point value using IEC 61850 protocol
via GOOSE.
GOOSESPRCV
BLOCK ^SPOUT
^SRCSPOUT DATAVALID
COMMVALID
TEST
IEC10000248-2-en.vsd
IEC10000248 V2 EN-US
21.4.10.4 Signals
GUID-2DC54788-86AF-4B4B-8E57-A89E30F0C433 v1
Except for the BLOCK input, the rest of the inputs of this GOOSE
function block are used for GOOSE connections. These
connections are visible and possible to make only if Easy GOOSE
engineering is enabled. For instructions on how to enable Easy
GOOSE engineering in PCM600, refer to the Engineering Manual.
PID-6832-INPUTSIGNALS v3
PID-6832-OUTPUTSIGNALS v3
21.4.10.5 Settings
PID-6832-SETTINGS v3
The DATAVALID output will be HIGH if the incoming message is with valid data.
The COMMVALID output will become LOW when the sending IED is under total
failure condition and the GOOSE transmission from the sending IED does not
happen.
The TEST output will go HIGH if the sending IED is in test mode.
Data Value Data Valid Comm Valid Test
Incoming data with q=Normal Updated 1 1 0
Incoming data with q=oldData 0 0 1 0
Incoming data with q=Invalid 0 0 1 0
Incoming data with q=test 0 0 1 1
Incoming data with q=test+oldData 0 0 1 1
Receiver in block 0 0 1 0
Receiver in block and 0 0 0 0
communication error
Receiver in test mode and incoming Updated 1 1 0
data with q= Normal
Receiver in test mode and incoming Updated 1 1 1
data with q= Test
Communication Error 0 0 0 0
21.4.11.1 Identification
GUID-CD59C2EE-F937-4CCA-83C1-181F925B8A40 v1
The following voltage control information can be sent from TR8ATCC via GOOSE
communication:
• BusV
• LoadAIm
• LoadARe
• PosRel
• SetV
• VCTRStatus
• X2
21.4.11.3 Settings
PID-2537-SETTINGS v14
21.4.12.1 Identification
GUID-470735CB-59CE-4935-85A1-48E9947817DF v1
This component also checks the received data validity, communication validity and
test mode. Communication validity will be checked upon the rate of data reception.
Data validity also depends upon the communication. If communication is invalid
then data validity will also be invalid. IEC 61850 also checks for data validity
using internal parameters which will also be passed to the DATAVALID output.
Data Value Data Valid Comm Valid Test
Incoming data with q=Normal Updated 1 1 0
Incoming data with q=oldData Freeze 0 1 0
Incoming data with q=Invalid Freeze 0 1 0
Incoming data with q=test Freeze 0 1 1
Incoming data with q=test+oldData Freeze 0 1 1
GOOSEVCTRRCV
BLOCK VCTR_RCV
DATAVALID
COMMVALID
TEST
IEC10000252-1-en.vsd
IEC10000252 V1 EN-US
21.4.12.4 Signals
PID-4108-INPUTSIGNALS v7
PID-4108-OUTPUTSIGNALS v7
GOOSE communication can be used for exchanging information between IEDs via
the IEC 61850-8-1 station communication bus. This is typically used for sending
apparatus position indications for interlocking or reservation signals for 1-of-n
control. GOOSE can also be used to exchange any boolean, integer, double point
and analog measured values between IEDs.
GOOSEINTLKRCV
BLOCK ^RESREQ
^SRCRESREQ ^RESGRANT
^SRCRESGR ^APP1_OP
^SRCAPP1 ^APP1_CL
^SRCAPP2 APP1VAL
^SRCAPP3 ^APP2_OP
^SRCAPP4 ^APP2_CL
^SRCAPP5 APP2VAL
^SRCAPP6 ^APP3_OP
^SRCAPP7 ^APP3_CL
^SRCAPP8 APP3VAL
^SRCAPP9 ^APP4_OP
^SRCAPP10 ^APP4_CL
^SRCAPP11 APP4VAL
^SRCAPP12 ^APP5_OP
^SRCAPP13 ^APP5_CL
^SRCAPP14 APP5VAL
^SRCAPP15 ^APP6_OP
^APP6_CL
APP6VAL
^APP7_OP
^APP7_CL
APP7VAL
^APP8_OP
^APP8_CL
APP8VAL
^APP9_OP
^APP9_CL
APP9VAL
^APP10_OP
^APP10_CL
APP10VAL
^APP11_OP
^APP11_CL
APP11VAL
^APP12_OP
^APP12_CL
APP12VAL
^APP13_OP
^APP13_CL
APP13VAL
^APP14_OP
^APP14_CL
APP14VAL
^APP15_OP
^APP15_CL
APP15VAL
COMMVALID
TEST
IEC07000048-4-en.vsd
IEC07000048 V4 EN-US
GUID-2DC54788-86AF-4B4B-8E57-A89E30F0C433 v1
Except for the BLOCK input, the rest of the inputs of this GOOSE
function block are used for GOOSE connections. These
connections are visible and possible to make only if Easy GOOSE
engineering is enabled. For instructions on how to enable Easy
GOOSE engineering in PCM600, refer to the Engineering Manual.
PID-6831-INPUTSIGNALS v3
PID-6831-OUTPUTSIGNALS v3
PID-6831-SETTINGS v3
The APPxVAL output will be HIGH if the incoming message is with valid data.
The COMMVALID output will become LOW when the sending IED is under total
failure condition and the GOOSE transmission from the sending IED does not
happen.
The TEST output will go HIGH if the sending IED is in test mode.
Data Value Data Valid Comm Valid Test
Incoming data with q=Normal Updated 1 1 0
Incoming data with q=oldData 0 0 1 0
Incoming data with q=Invalid 0 0 1 0
Incoming data with q=test 0 0 1 1
Incoming data with q=test+oldData 0 0 1 1
Receiver in block 0 0 1 0
Receiver in block and 0 0 0 0
communication error
Receiver in test mode and incoming Updated 1 1 0
data with q= Normal
Receiver in test mode and incoming Updated 1 1 1
data with q= Test
Communication Error 0 0 0 0
GOOSEBINRCV
BLOCK ^OUT1
^SRCOUT1 DVALID1
^SRCOUT2 ^OUT2
^SRCOUT3 DVALID2
^SRCOUT4 ^OUT3
^SRCOUT5 DVALID3
^SRCOUT6 ^OUT4
^SRCOUT7 DVALID4
^SRCOUT8 ^OUT5
^SRCOUT9 DVALID5
^SRCOUT10 ^OUT6
^SRCOUT11 DVALID6
^SRCOUT12 ^OUT7
^SRCOUT13 DVALID7
^SRCOUT14 ^OUT8
^SRCOUT15 DVALID8
^SRCOUT16 ^OUT9
DVALID9
^OUT10
DVALID10
^OUT11
DVALID11
^OUT12
DVALID12
^OUT13
DVALID13
^OUT14
DVALID14
^OUT15
DVALID15
^OUT16
DVALID16
COMMVALID
TEST
IEC07000047-4-en.vsd
IEC07000047 V4 EN-US
GUID-2DC54788-86AF-4B4B-8E57-A89E30F0C433 v1
Except for the BLOCK input, the rest of the inputs of this GOOSE
function block are used for GOOSE connections. These
connections are visible and possible to make only if Easy GOOSE
engineering is enabled. For instructions on how to enable Easy
GOOSE engineering in PCM600, refer to the Engineering Manual.
PID-6827-INPUTSIGNALS v3
PID-6827-OUTPUTSIGNALS v3
PID-6827-SETTINGS v3
The DVALIDx output will be HIGH if the incoming message is with valid data.
The COMMVALID output will become LOW when the sending IED is under total
failure condition and the GOOSE transmission from the sending IED does not
happen.
The TEST output will go HIGH if the sending IED is in test mode.
Data Value Data Valid Comm Valid Test
Incoming data with q=Normal Updated 1 1 0
Incoming data with q=oldData 0 0 1 0
Incoming data with q=Invalid 0 0 1 0
Incoming data with q=test 0 0 1 1
Table continues on next page
Receiver in block 0 0 1 0
Receiver in block and 0 0 0 0
communication error
Receiver in test mode and incoming Updated 1 1 0
data with q= Normal
Receiver in test mode and incoming Updated 1 1 1
data with q= Test
Communication Error 0 0 0 0
21.4.15.1 Identification
GUID-4B23D0CF-F298-4BBC-B833-1B8CC98D1604 v1
The GOOSE XLN Receive component is used to collect information from another
device’s XCBR/XSWI logical node sent over process bus via GOOSE. The
GOOSE XLN Receive component includes 12 different outputs (and their
respective channel valid bits) with defined names to ease the 61850 mapping of the
GOOSE signals in the configuration process.
GOOSEXLNRCV
BLOCK ^BEH
^SRCBEH BEH_VALID
^SRCLOC ^LOC
^SRCBLKOPN LOC_VALID
^SRCBLKCLS ^BLKOPN
^SRCPOS BLKOPN_VALID
^SRCOPCNT ^BLKCLS
^SRCBLK BLKCLS_VALID
^SRCSTSELD ^POSVAL
^SRCOPRCVD POSVAL_VALID
^SRCOPOK ^OPCNT
^SRCEEHLT OPCNT_VALID
^SRCOPCAP ^BLK
BLK_VALID
^STSELD
STSELD_VALID
^OPRCVD
OPRCVD_VALID
^OPOK
OPOK_VALID
^EEHEALTH
EEHEALTH_VALID
^OPCAP
OPCAP_VALID
COMMVALID
TEST
IEC16000036-1-en.vsdx
IEC16000036 V1 EN-US
21.4.15.4 Signals
GUID-2DC54788-86AF-4B4B-8E57-A89E30F0C433 v1
Except for the BLOCK input, the rest of the inputs of this GOOSE
function block are used for GOOSE connections. These
connections are visible and possible to make only if Easy GOOSE
engineering is enabled. For instructions on how to enable Easy
GOOSE engineering in PCM600, refer to the Engineering Manual.
PID-6643-INPUTSIGNALS v3
PID-6643-OUTPUTSIGNALS v3
21.4.15.5 Settings
PID-6643-SETTINGS v3
The xxx_VALID outputs will be HIGH if the incoming message is with valid data.
The COMMVALID output will become LOW when the sending IED is under total
failure condition and the GOOSE transmission from the sending IED does not
happen.
The TEST output will go HIGH if the sending IED is in test mode.
21.5.3 Signals
GUID-942C81AD-22D9-438F-95FA-1972BA2BE2E5 v1
The output signals are the same for all MUs so only the table for MU1_HW is
included in this manual.
PID-6850-OUTPUTSIGNALS v3
PID-6850-SETTINGS v3