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Professorship Circuit and System Design
SD1
Course System Design I
The course System Design deals with the design, modeling, description and synthesis of complex systems using VHDL. The course consists
of lecture, exercise and practice. The course is held only in winter semester.
Recommended Literature:
Peter J. Ashenden, "The Designer's Guide to VHDL, 3rd Edition", 2008, ISBN 9780120887859
Janick Bergeron, "Writing Testbenches: Functional Verification of HDL Models", Springer; Auflage: 2nd ed. 2003, ISBN 9781402074011
Lecture Materials
further materials are located in this directory
Lecture Timeline
Tuesday, odd week, from 17:15 to 18:45 o'clock in room 2/W012.
Download Timeline (iCal, .ics)
11 Oct 2016 17:15 18:45
L1 VHDL: Overview, Field of application
25 Oct 2016 17:15 18:45
L2 VHDL: Language and Syntax
2.1 General
2.2 Structural Elements
08 Nov 2016 17:15 18:45
L3 VHDL: Language and Syntax
2.3 Data types
2.4 Process execution
22 Nov 2016 17:15 18:45
L4 VHDL: Language and Syntax
2.5 Extended datatypes
3 Synthesis
3.1 RTL style
3.2 What is synthesis
https://www.tuchemnitz.de/etit/sse/Lehre/SEW/sd1.html.en 1/3
2017/4/21 SD1 | Teachings | Chair for Circuit and System Design | ETIT | TU Chemnitz
06 Dec 2016 17:15 18:45
L5 VHDL: Language and Syntax
2.6 Operators
2.7 Sequential statements
03 Jan 2017 17:15 18:45
L6 Synthesis
3.3 Finite State Machines
17 Jan 2017 17:15 18:45
L7 Synthesis
3.3 Finite State Machines
31 Jan 2017 17:15 18:45
L8 Simulation
4.1 Testbench
4.2. Sequence of compilation
Exercise Timeline
Friday, 11:30 till 13:00 in room 2/W012.
Download Timeline (iCal, .ics)
14 Oct 2016 13:45 15:15
Introduction, Lecture
21 Oct 2016 11:30 13:00
E1 VHDL basics, data types
28 Oct 2016 11:30 13:00
E2 Operators (logical, shift, relational)
04 Nov 2016 11:30 13:00
E3 Concurrent/sequential execution
11 Nov 2016 11:30 13:00
E4 Finite State Machines
18 Nov 2016 11:30 13:00
E5 Memories
https://www.tuchemnitz.de/etit/sse/Lehre/SEW/sd1.html.en 2/3
2017/4/21 SD1 | Teachings | Chair for Circuit and System Design | ETIT | TU Chemnitz
25 Nov 2016 11:30 13:00
E6 Detailed views on architecture
02 Dec 2016 11:30 13:00
E7 Detailed views on architecture
09 Dec 2016 11:30 13:00
E8 Detailed views on architecture
Practice Timeline
The practice sessions are given in room 2/W451. The solution of both tasks is required for the exam admission!
Practice/Labs Subscription to the groups: You need to be registered for the exercise to subscribe to the practice in OPALSystem.
Practice Topics
P1 Introduction to the VHDLWorkshop, Linux, XEmacs and Modelsim
P2 & 3 Task 1: Design of a 7segment decoder
P4 & 5 Task 2: Design of a stop watch controller
P6 Task 2: Implementing the whole stop watch
© 2017 Technische Universität Chemnitz
https://www.tuchemnitz.de/etit/sse/Lehre/SEW/sd1.html.en
Göran Herrmann, 17 October 2016
https://www.tuchemnitz.de/etit/sse/Lehre/SEW/sd1.html.en 3/3