PRACTICA 4 MICROPROCESADORES

El objetivo de esta práctica es usar lenguaje ensamblador para conocer tres algoritmos tomados de
la web: primero es generar números pseudo aleatorios de 40 bits, segundo convertir los doce bits
más bajos de dicho número a tres BCDs mismos que se exhibirán en sendos displays de siete
segmentos que serán conectados a cuatro decoders 74LS48 para cátodo común y tercero crear una
rutina que tome 1.2 segundos, hecha con software. Si alguno de los displays es de ánodo común,
usar el 74LS47 para él.
SW1

Title
LFSR DOUBLE DABBLE 12 bits
Size Document Number Rev
B MICROS PRACTICA 4 Saucedo 5
Date: Sunday , April 15, 2018 Sheet 1 of 1

SW DIP-8
J2 J1
2 1 2 1
MCL 4 3 MCL RB7 4 3
6 5 RA0 RB6 6 5
8 7 RA1 RB5 8 7
10 9 RA2 RB4 10 9
12 11 RA3 RB3 12 11
14 13 RA4 RB2 14 13
CATODO COMUN
U3 RN3
16 15 RA5 RB1 16 15
RE0 18 17 RE0 RB0 18 17 7 13 1 14 a
RE1 RE1 VDD D0 A a
20 19 20 19 1 12 2 13 b
RE2 22 21 RE2 GND 22 21 GND 2 D1 B 11 3 12 c
VDD VDD RD7 D2 C f b
24 23 24 23 6 10 4 11 d
GND 26 25 GND RD6 26 25 D3 D 9 5 10 e
R3 R2 7448
RC0 28 27 RC0 RD5 28 27 3 E 15 6 9 f
220 220
RC1 RC1 RD4 LT F g
30 29 30 29 5 14 7 8 g
RC2 32 31 RC2 RC7 32 31 RC7 RBI G
RD0 34 RC6 RC6 e c
33 34 33 4
RD1 36 35 RD3 36 35 BI/RBO
Vusb Vusb RD2 220 DECENAS d
D3 D2

LED LED HEADER 18X2 HEADER 18X2

CATODO COMUN
FILE: DESIGN110 U1 RN2

7 13 1 14 a a
1 D0 A 12 2 13 b
2 D1 B 11 3 12 c
D2 C f b
MILES 6 10 4 11 d
D3 D 9 5 10 e
7448 E
CATODO COMUN 3 15 6 9 f g
U4 RN4 5 LT F 14 7 8 g
RBI G
e c
7 13 1 14 a a 4
1 D0 A 12 2 13 b BI/RBO
D1 B 220 UNIDADES d
2 11 3 12 c f b
6 D2 C 10 4 11 d
D3 D 9 5 10 e
7448 E
3 15 6 9 f g
5 LT F 14 7 8 g
RBI G
e c
4
BI/RBO
220 CENTENAS d

̅̅̅̅̅ para los cuatro 7448s.

Fig. 1 Agregar display para miles y lamp test (𝐿𝑇)

;**************************************************************************
; This file is a basic template for assembly code for a PIC18F4550. Copy *
; this file into your project directory and modify or add to it as needed.*
; *
; The PIC18FXXXX architecture allows two interrupt configurations. This *
; template code is written for priority interrupt levels and the IPEN bit*
; in the RCON register must be set to enable priority levels. If IPEN is *
; left in its default zero state, only the interrupt vector at 0x008 will*
; be used and the WREG_TEMP, BSR_TEMP and STATUS_TEMP variables will not *
; be needed. *
; *
; Refer to the MPASM User's Guide for additional information on the *
; features of the assembler. *
; *
; Refer to the PIC18FXX50/XX55 Data Sheet for additional *
; information on the architecture and instruction set. *
; *
;**************************************************************************
; *
; Filename: Puerto A = entrada Puerto B = Complemento a uno de PA *
; Date: 12/01/11 *
; File Version: 1.0 *
; *
; Author: Ing. Alejandro Vicente Lugo Silva / J. Luis Bravo L. *
; Company: Acad. Computación ICE - ESIME Zac.
*
; *
;**************************************************************************

Prof. S. Saucedo 1 mar/2018

 ; *
; Files required: P18F4550.INC *
; *
;**************************************************************************

LIST P=18F4550, F=INHX32 ;directive to define processor

#include <P18F4550.INC> ;processor specific variable definitions

;*************************************************************************
;

;**************************************************************************
;Variable definitions
; These variables are only needed if low priority interrupts are used.
; More variables may be needed to store other special function registers ;
; used in the interrupt routines
VAR EQU 0x00 ;define variable en localidad 0 de memoria de datos
cont_s EQU 0x01
cuenta equ 0x02
conteo equ 0x03
RES1 EQU 0x04
RES2 EQU 0x05
COC equ 0x06
BCDx equ 0x08
BCDy equ 0x09
MiDEN equ .10
NUME equ 0x0b
RMND_L equ 0x0e
rlf macro file,dest
rlcf file,dest
endm
rrf macro file,dest
rrcf file,dest
endm
rlnf macro file,dest
rlncf file,dest
endm
;*************************************************************************
;Variable definitions
; These variables are only needed if low priority interrupts are used.
; More variables may be needed to store other special function registers
used
; in the interrupt routines.
SB equ 7
max_AD equ 0xAC
CARRY equ 0
bcdU equ 0x13
bcdH equ 0x14
binL equ 0x17
binH equ 0x16
bcdL equ 0x15

SHIFT_REG4 equ 0x20

SHIFT_REG3 equ 0x21
SHIFT_REG2 equ 0x22
SHIFT_REG1 equ 0x23
SHIFT_REG0 equ 0x24
NEW_REG0 equ 0x26 ; The replacement SHIFT_REG0 byte
TEMP_REG4A equ 0x30 ; Exactly what they say on the tin.
TEMP_REG4B equ 0x31
TEMP_REG3A equ 0x32 ; Exacto lo que él (Wiltshire) dice en la web.
TEMP_REG3B equ 0x33

RANDOM equ 0x35 ; 8 bits

Prof. S. Saucedo 2 mar/2018
 ;**************************************************************************
;Reset vector
; This code will start executing when a reset occurs.

RESET_VECTOR ORG 0

goto Main ;go to start of main code

TMR0isr org 0x0018

bcf INTCON,TMR0IF
incf cont_s,F
; movlw .59
; cpfsgt cont_segs
bra sigue
; clrf cont_segs
; incf cont_mins
; movlw .39
; cpfsgt cont_mins
; bra next
; clrf cont_mins
;next call convBCDy ; exhibe minutos
;sigue call convBCDx ; exhibe segundos
sigue movlw 0x24
movwf TMR0H,1
movlw 0x72
movwf TMR0L,1
retfie
;**************************************************************************

;**************************************************************************
;Start of main program
; The main program code is placed here.
ORG 0x1000
Main:

; *** main code goes here **

call Cfgptos ;Subrutina para configurar puertos I/O
; call CfgTMR0
movlw 0x6c
movwf SHIFT_REG4
movf PORTB,W
movwf SHIFT_REG3
movlw 0xC9
movwf SHIFT_REG2
movlw 0xdb
movwf SHIFT_REG1
movlw 0x98
movwf SHIFT_REG0
movwf RANDOM
lfsr FSR0,0x50
; call Delay
movlw .24
movwf cuenta
Cycle
rcall NoiseSource
movff SHIFT_REG1,POSTINC0
movff SHIFT_REG0,POSTINC0
clrf WREG
movwf POSTINC0
decfsz cuenta
bra Cycle
lfsr FSR0,0x50
lfsr FSR1,0xD0
movlw .24
Prof. S. Saucedo 3 mar/2018
 movwf conteo
mas movf POSTINC0,W
andlw 0x0f ; para 16,383 maximo en binario
movwf binH
movf POSTINC0,W
movwf binL
MOVF POSTINC0,W ; TIRA un 00
rcall bin16toBCDs ; convierte a 4 BCDs empacados
;movff bcdU,POSTINC1
movff bcdH,POSTINC1
movff bcdH,PORTA
movff bcdL,POSTINC1
movff bcdL,PORTD
;movff bcdH,PORTB
call Delay
decfsz conteo
bra mas
Ciclo
movf PORTB,W
nop
; movwf LATA
goto Ciclo

CfgTMR0
;T1CON.T1CKPS1 = 1; // bits 5-4 Prescaler Rate Select bits
;T1CON.T1CKPS0 = 0; // bit 4
;T1CON.T1OSCEN = 1; // bit 3 Timer1 Oscillator Enable Control: bit 1=on
;T1CON.T1SYNC = 1; // bit 2 Timer1 External Clock Input Synchronization
Control bit: 1=Do not synchronize external clock input
;T1CON.TMR1CS = 0; // bit 1 Timer1 Clock Source Select bit: 0=Internal
clock (FOSC/4) / 1 = External clock from pin T13CKI (on the rising edge)
;T1CON.TMR1ON = 1; // bit 0 enables timer
;TMR1H = $5D; // preset for timer1 MSB register
;TMR1L = $3D; // preset for timer1 LSB register
movlw 0x87
movwf T0CON,1
movlw 0x24
movwf TMR0H,1
movlw 0x72
movwf TMR0L,1
bsf INTCON,GIE
bcf RCON,IPEN
bsf INTCON,TMR0IE
return

;**************************************************************************
; Cfgptos - Subrutina para configurar los puertos de E/S

Cfgptos

movlw 0x0F ;Configura las entradas mutiplexadas con el

movwf ADCON1 ;convertidor A/D como entradas digitales.
movlw 0x07 ;Configura las entradas multiplexadas con
movwf CMCON ;los comparadores como entradas digitales.
movlw 0x0f ;Configura las 4 lineas del
movwf TRISA ;puerto A como entradas.
movwf TRISD ;puerto D como salidas.
movlw 0xff ;Configura todas las lineas del
movwf TRISB ;puerto B como entradas.
bcf INTCON2,RBPU
return
bin16toBCDs
; ver: http://www.microchip.com/forums/m/tm.aspx?m=853241&p=4
movlw 0x0
Prof. S. Saucedo 4 mar/2018
 movwf bcdH
movwf bcdU
movwf bcdL
movlw .16
movwf cuenta
bra bcd0
bcd_lp movlw 0x33
addwf bcdL
btfsc bcdL,3
andlw 0xF0
btfsc bcdL,7
andlw 0x0f
subwf bcdL
movlw 0x33
addwf bcdH
btfsc bcdH,3
andlw 0xF0
btfsc bcdH,7
andlw 0x0F
subwf bcdH
movlw 0x03 ; ajustar digito TenK
addwf bcdU
btfss bcdU,3
subwf bcdU
bcd0 rlcf binL
rlcf binH
rlcf bcdL
rlcf bcdH
rlcf bcdU
decfsz cuenta
bra bcd_lp
return
NoiseSource:
; First I need to copy two bytes I'm going to muck with
movf SHIFT_REG4, w
movwf TEMP_REG4A ; I need 2 copies for L&R shifts
movwf TEMP_REG4B
movwf NEW_REG0 ; Get bit 40 while we've got it
movf SHIFT_REG3, w
movwf TEMP_REG3A ; I need 2 copies for L&R shifts
movwf TEMP_REG3B

; Next, I need to XOR all the bytes together

rlf TEMP_REG3A, f ; Left shift 1st set of copies
rlf TEMP_REG4A, f
rlf TEMP_REG3A, f
rlf TEMP_REG4A, f ; Left shift 1st set of copies
rlf TEMP_REG3A, f ; Exacto lo que él (Wiltshire) dice en la web.
rlf TEMP_REG4A, w
xorwf NEW_REG0, f ; XOR with bit 37
rrf TEMP_REG4B, f ; right shift 2nd set of copies
rrf TEMP_REG3B, f
rrf TEMP_REG4B, f
rrf TEMP_REG3B, f ; right shift 2nd set of copies
rrf TEMP_REG4B, f
rrf TEMP_REG3B, f
movf TEMP_REG3B, w
xorwf NEW_REG0, f ; XORea con el bit 35
rrf TEMP_REG4B, f
rrf TEMP_REG3B, w
xorwf NEW_REG0, f ; XORea con el bit 36

; Perform a byte shift on the whole 40-bit register

movff SHIFT_REG3, SHIFT_REG4 ; Pone SR3 en SR4
Prof. S. Saucedo 5 mar/2018
 movff SHIFT_REG2, SHIFT_REG3 ; Pone SR2 en SR3
movff SHIFT_REG1, SHIFT_REG2 ; Pone SR1 en SR2
movff SHIFT_REG0, SHIFT_REG1 ; Pone SR0 en SR1
movff NEW_REG0, SHIFT_REG0 ; Pone NEW_REG0 en SR0
return

LinFeedSR:
; rlnf RANDOM,W
rlnf RANDOM,W
BTFSC RANDOM,4
XORLW 1
BTFSC RANDOM,5
XORLW 1
BTFSC RANDOM,2
XORLW 1
MOVWF RANDOM
RETLW 0
convBCDx movf cont_s,W
movwf NUME
movlw MiDEN
clrf COC,1 ; limpia cociente
D_1 incf COC,1 ; incrementa al cociente cada resta
subwf NUME,1 ; NUME - WREG -> WREG
bc D_1 ; si positivo, regresar
addwf NUME,1 ; si demasiados este es 1er digito
decf COC,1 ; si demasiados para el cociente
movff NUME,RMND_L ;salva 1er digito BCD (unidades)
movff COC,NUME ; repite mismo proceso
clrf COC,1 ; limpia cociente
D_2 incf COC,1
subwf NUME,F
bc D_2
addwf NUME,1
decf COC,1
movf NUME,W
swapf WREG
addwf RMND_L,W
movwf BCDx
movwf LATD
return

convBCDy return
; Delay = 1 seconds
; Clock frequency = 48 MHz

; Actual delay = 1 seconds = 12000000 cycles

; Error = 0 %

cblock
dd1
dd2
dd3
endc

Delay
;11999993x1.2 cycles
movlw 0xb5
movwf dd1
movlw 0x64
movwf dd2
movlw 0x20
movwf dd3
Delay_0
Decfsz dd1, f
Prof. S. Saucedo 6 mar/2018
 Goto goto2
decfsz dd2, f
goto2 goto goto3
decfsz dd3, f
goto3 goto Delay_0
;http://www.electro-tech-online.com/threads/flashing-led-pk2error0029.42691/
;3 cycles
goto alnop
alnop nop
;4 cycles (including call)
return
;**************************************************************************
;End of program

END

Con EXCEL se corroboró el generador de números pseudo aleatorios:

40 39 38 34 33 * *
0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 0 0 0 DB 98 70
1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 0 0 0 0 B7 30 141
1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 0 0 0 0 1 6E 61 118
0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 0 DC C2 73
1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 0 1 B9 85 147
1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 0 1 1 73 0B 130
0 0 1 1 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 1 0 E6 16 97
0 1 1 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 1 0 0 CC 2C 31
1 1 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 98 59 *1 62
1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 59 2E *2 64
1 1 0 1 1 0 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 2E 21 *3 118
1 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 1 0 0 1 1 0 1 21 CD *4 86
0 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 CD D4 *5 35
0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 D4 27 *6 51
0 0 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 0 0 1 27 79 *7 101
0 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 0 4E F2 38
1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 0 1 0 0 9D E4 76
0 0 0 0 1 1 1 0 0 1 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 3B C8 153
0 0 0 1 1 1 0 0 1 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 0 77 90 142
0 0 1 1 1 0 0 1 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 0 1 EF 21 120
0 1 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 DE 42 77
1 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 BC 85 154
1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 79 0A *8 146
1 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0A C4 *9 27
1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 1 15 89 55
0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 0 1 0 2B 12 110

Prof. S. Saucedo 7 mar/2018