SEP SEIT

TIJUANA TECNOLOGICAL INSTITUTE

Transistors Design

Phase # 1

Team: The Russians

Garcia muños Carlos Ivan 14211327

García Rodríguez Jaime Alejandro 14211327

Gámez Gámez Aarón Federico 12211802

Instructor:

Ing. Jair Nevarez Valerdi

Tijuana, Baja California, March 18th, 2018.

Index

I. INTRODUCTION. ............................................................................................................................... 3
I. OBJECTIVES. ...................................................................................................................................... 3
II. JFET BIASING AND CONFIGURATIONS. ...................................................................................... 4
2.1. Voltage-Divisor Configuration. .................................................................................................... 4
2.2. Fixed-Bias Configuration.............................................................................................................. 7
III. DEVELOPMENT. .......................................................................................................................... 13
3.1. STEP 1: Develop a circuit with JFET. ............................................................................................ 13
3.2. STEP 2: Develop an amplifier meeting the next JFET parameters. ............................................. 14
3.3. STEP 3: Develop a circuit based on a given curve of a JFET Transistor. ...................................... 15
IV. CONCLUSION. .............................................................................................................................. 16
V. REFERENCES. .................................................................................................................................. 16
VI. ATTACHMENTS ........................................................................................................................... 17
I. INTRODUCTION.

In the following practice we analyze the polarization, the alternating current behavior of a field
effect transistor. For this type of transistor, the relation between the input and the output is non-
linear due to the square term of the Shockley equation. A difference between the analysis of
transistors BJT and FET is that: The control variable for a BJT is a current level, while for the FET the
control variable is a voltage.

II. OBJECTIVES.

 Develop a circuit with drain feedback using JFETs so the feedback can show an
increment of 10% in the drain current.

 Develop a circuit that meets AV = −100, using JFETs.

 Design a circuit using JFETs parting from the given values within his characteristic
curve.
 III. JFET BIASING AND CONFIGURATIONS.

The JFET (junction field effect transistor) is a semiconductor component consisting of two crystals with n-
type and p-type doping. It has 4 terminals, of which two are joined and the rest are independent. It has
an operation similar to the BJT but instead of being controlled by current, it is controlled with voltage,
leading us to determine different characteristics to the BJT that have an effect both in the polarization in
c.c. and in c.a. This practice will seek to determine and observe the characteristics of a JFET to observe
how it behaves and how it works this device in a certain point of operation Q.

3.1. Voltage-Divisor Configuration.

The voltage-divider bias arrangement applied to BJT transistor

amplifiers is also applied to FET amplifiers as demonstrated by Figure
3.1. The basic construction is exactly the same, but the dc analysis of
each is quite different. 𝐼𝐺 = 0 𝐴 for FET amplifiers, but the magnitude of
𝐼𝐵 for common-emitter BJT amplifiers can affect the dc levels of current
and voltage in both the input and output circuits. Recall that 𝐼𝐵 provides
the link between input and output circuits for the BJT voltage-divider
configuration, whereas 𝑉𝐺𝑆 does the same for the FET configuration.

The network of Figure 3.1 is redrawn as shown in Figure 3.2 for the dc
analysis. Note that all the capacitors, including the bypass capacitor 𝐶𝑆,
have been replaced by an “open circuit” equivalent in Figure 3.2b . In
addition, the source 𝑉𝐷𝐷 was separated into two equivalent sources to
permit a further separation of the input and output regions of the
network. Since 𝐼𝐺 = 0 𝐴, Kirchhoff’s current law requires that 𝐼𝑅1 = 𝐼𝑅2,
and the series equivalent circui t appearing to the left of the figure can be
used to find the level of 𝑉𝐺. The voltage 𝑉𝐺, equal to the voltage across
𝑅2, can be found using the voltage-divider rule and Figure 3.2a as follows:
Applying Kirchhoff’s voltage law in the clockwise direction to the indicated loop of Figure 3.2 results in:

Substituting , we have:

The result is an equation that continues to include the same two variables appearing in Shockley’s
equation: 𝑉𝐺𝑆 and 𝐼𝐷 . The quantities 𝑉𝐺 and 𝑅𝑆 are fixed by the network construction. Equation (3.2) is
still the equation for a straight line, but the origin is no longer a point in the plotting of the line. The
procedure for plotting Eq. (3.2) is not a difficult one and will proceed as follows. Since any straight line
requires two points to be defined, let us first use the fact that anywhere on the horizontal axis of Figure
3.3 the current 𝐼𝐷 = 0 𝑚𝐴. If we therefore select 𝐼𝐷 to be 0 𝑚𝐴, we are in essence stating that we are
somewhere on the horizontal axis. The exact location can be determined simply by substituting 𝐼𝐷 = 0 𝑚𝐴
into Eq. (3.2) and finding the resulting value of 𝑉𝐺𝑆 as follows:

The result specifies that whenever we plot Eq. (3.2), if we choose 𝐼D = 0 𝑚𝐴, the value of 𝑉𝐺𝑆 for the
plot will be 𝑉𝐺 volts. The point just determined appears in Figure 3.3.
For the other point, let us now employ the fact that at any point on the vertical axis 𝑉𝐺𝑆 = 0 𝑉 and solve
for the resulting value of 𝐼D:

The result specifies that whenever we plot Eq. (3.2), if 𝑉𝐺𝑆 = 0 𝑉, the level of 𝐼𝐷 is determined by Eq.
(3.4). This intersection also appears on Figure 3.3. The two points defined above permit the drawing of a
straight line to represent Eq. (3.2). The intersection of the straight line with the transfer curve in the
region to the left of the vertical axis will define the operating point and the corresponding levels of 𝐼𝐷
and 𝑉𝐺𝑆. Since the intersection on the vertical axis is determined by 𝐼𝐷 = 𝑉𝐺 𝑅𝑆 ⁄ and 𝑉𝐺 is fixed by the
input network, increasing values of 𝑅𝑆 will reduce the level of the 𝐼𝐷 intersection as shown in Figure 3.4.
It is fairly obvious from Figure 3.4 that: Increasing values of 𝑹𝑺 result in lower quiescent values of 𝑰𝑫
and declining values of 𝑽𝑮𝑺.
 3.2. Fixed-Bias Configuration.

The simplest of biasing arrangements for the n-channel JFET appears in Figure 3.5. Referred to as the
fixed-bias configuration, it is one of the few FET configurations that can be solved just as directly using
either a mathematical or a graphical approach. Both methods are included in this section to demonstrate
the difference between the two methods and also to establish the fact that the same solution can be
obtained using either approach.
The configuration of Figure 3.5 includes the ac levels 𝑉 𝑖 and 𝑉 𝑜 and the coupling capacitors (𝐶1and 𝐶2).
Recall that the coupling capacitors are “open circuits” for the dc analysis and low impedances (essentially
short circuits) for the ac analysis. The resistor 𝑅𝐺 is present to ensure that 𝑉 𝑖 appears at the input to the
FET amplifier for the ac analysis. For the dc analysis we have:

The zero-volt drop across 𝑅𝐺 permits replacing 𝑅𝐺 by a short-circuit equivalent, as appearing in the
network of Figure 3.6, specifically redrawn for the dc analysis. The fact that the negative terminal of the
battery is connected directly to the defined positive potential of 𝑉𝐺𝑆 clearly reveals that the polarity of
𝑉𝐺𝑆 is directly opposite to that of 𝑉𝐺𝐺. Applying Kirchhoff’s voltage law in the clockwise direction of the
indicated loop of Figure 3.6 results in:

Since 𝑉𝐺𝐺 is a fixed dc supply, the voltage 𝑉𝐺𝑆 is fixed in magnitude, resulting in the designation “fixed-
bias configuration.” The resulting level of drain current 𝐼𝐷 is now controlled by Shockley’s equation:
Since 𝑉𝐺𝑆 is a fixed quantity for this configuration, its magnitude and sign can simply be substituted into
Shockley’s equation and the resulting level of 𝐼𝐷 calculated. This is one of the few instances in which a
mathematical solution to a FET configuration is quite direct.

A graphical analysis would require a plot of Shockley’s equation as shown in Figure 3.7. Recall that
choosing 𝑉𝐺𝑆 = 𝑉𝑃 2 ⁄ will result in a drain current of 𝐼𝐷𝑆𝑆 4 ⁄ when plotting the equation. For the analysis
of this chapter, the three points defined by 𝐼𝐷𝑆𝑆, 𝑉𝑃, and the intersection just described will be sufficient
for plotting the curve.

In Figure 3.8, the fixed level of 𝑉𝐺𝑆 has been superimposed as a vertical line at 𝑉𝐺𝑆 = −𝑉𝐺𝐺. At any point
on the vertical line, the level of 𝑉𝐺𝑆 is 𝑉𝐺𝐺 the level of 𝐼𝐷 must simply be determined on this vertical line.
The point where the two curves intersect is the common solution to the configuration commonly referred
to as the quiescent or operating point. The subscript 𝑄 will be applied to the drain current and gate-to-
source voltage to identify their levels at the 𝑄 point. Note in Figure 3.8 that the quiescent level of 𝐼𝐷 is
determined by drawing a horizontal line from the 𝑄 point to the vertical 𝐼𝐷 axis. It is important to realize
that once the network of Figure 3.5 is constructed and operating, the dc levels of 𝐼𝐷 and 𝑉𝐺𝑆 that will be
measured by the meters of Figure 3.9 are the quiescent values defined by Figure 3.8.
The drain-to-source voltage of the output section can be determined by applying Kirchhoff’s voltage law
as follows:

Recall that single-subscript voltages refer to the voltage at a point with respect to ground. For the
configuration of Figure 3.6,

Using double-subscript notation, we have:

The fact that 𝑉𝐷 = 𝑉𝐷𝑆 and 𝑉𝐺 = 𝑉𝐺𝑆 is fairly obvious from the fact that 𝑉𝑆 = 0 𝑉, but the derivations
above were included to emphasize the relationship that exists between doublesubscript and single-
subscript notation. Since the configuration requires two dc supplies, its use is limited and will not be
included in the forthcoming list of the most common FET configurations.
 3.3. AC model: Fixed-Bias configuration.

The approach parallels the ac analysis of

BJT amplifiers with a determination of the
important parameters of 𝑍𝑖, 𝑍𝑜, and 𝐴𝑣 for
each configuration. The fixed-bias
configuration of Figure 3.10 includes the
coupling capacitors 𝐶1 and 𝐶2, which isolate
the dc biasing arrangement from the applied
signal and load; they act as shortcircuit
equivalents for the ac analysis.

Once the levels of 𝑔𝑚 and 𝑟𝑑 are

determined from the dc biasing
arrangement, specification sheet, or
characteristics, the ac equivalent model can
be substituted between the appropriate
terminals as shown in Fig. 8.11 . Note that
both capacitors have the short-circuit
equivalent because the reactance 𝑋𝐶 = 1
(2𝜋𝑓𝐶) ⁄ is sufficiently small compared to
other impedance levels of the network, and
the dc batteries 𝑉𝐺𝐺 and 𝑉𝐷𝐷 are set to 0 𝑉
by a short-circuit equivalent.

The network of Fig. 8.11 is then carefully redrawn as shown in Fig. 8.12 . Note the defined polarity of
𝑉𝑔𝑠, which defines the direction of𝑔𝑚𝑉𝑔𝑠. If 𝑉𝑔𝑠 is negative, the direction of the current source
reverses. The applied signal is represented by 𝑉 𝑖 and the output signal across 𝑅𝐷 ∥ 𝑟𝑑 by 𝑉 𝑜.

Figure 3.12 clearly reveals that:

because of the infinite input impedance at the input terminals of the JFET. Setting 𝑉 𝑖 = 0 𝑉 as required by
the definition of 𝑍𝑜 will establish 𝑉𝑔𝑠 as 0 𝑉 also. The result is 𝑔𝑚𝑉𝑔𝑠 = 0 𝑚𝐴, and the current source
can be replaced by an open-circuit equivalent as shown in Figure 3.13. The output impedance is
If the resistance 𝑟𝑑 is sufficiently large (at least 10:1) compared to 𝑅𝐷, the approximation 𝑅𝐷 ∥ 𝑟𝑑 ≅ 𝑅𝐷
can often be applied:
 IV. DEVELOPMENT.

4.1. STEP 1: Develop a circuit with JFET.

In the first part of practice 1.2 we must develop a circuit with feedback in such way the circuit will gain
10% of drain current.

The proposed circuit is showed in figure x.

According to the proposed circuit the resulting equations are the following:

This for the entry mesh. Taking into account that the current of the gate tends
to zero, the equation is rewritten as follows:

For the output grid the equation is as follows:

After many attemps in placing a feedback resistor and calculations, we noticed the only possible way to
achieve this feat is to calculate a fixed colector feedback configuration, and after that, calculate the values
from the resistors, seeking for the circuit to gain a 10% increase in the drain current.
 4.2. STEP 2: Develop an amplifier meeting the next JFET
parameters.

We know that the gain to be achieved is 𝐴𝑣 = −100, we also know that all configurations for JFET circuits
only reach a maximum of 10 or -10 voltage gain, therefore we decided to use two circuits to achieve this
feat, two fixed polarization circuits, which would assure us the desired gain.

Both the analysis are the following:

Our gain to achieve in this configuration is 𝐴𝑣 = −10, we applied the knowledge shown in the theoretical
framework in chapter 2.3:

Having knowledge of these equations and knowing the fixed values provided by the datasheet of our
transitor, we follow to present the results of our default values for the JFET we used:
After we obtained the AC parementers, to find our drain resistance we performed the following
equation, substituting and solving for the remaining variables:

After this, we obtained that our operating drainage current is:

The previous analysis would be applied twice to ensure a gain of 100, the next second analysis using the
same configuration would end up being of an equal gain -10, therefore the only thing that we should
consider and find is the drain resistance, which it results in the same.

4.3. STEP 3: Develop a circuit based on a given curve of a JFET

Transistor.

Following Figure 2.2, we decide on a JFET voltage-divider biasing circuit

because of the 3 𝑉 that asks of us can be represented as the 𝑉𝐺. In this
case 𝑉𝐷𝐷 = 10 𝑉 and according to the problem 𝐼𝐷 = 8 𝑚𝐴. The circuit
used can be seen in the Figure 4.2.

Using equation 3.1 both of our resistors for the voltage divider result
as follows:

𝑅1 = 700 Ω and 𝑅2 = 300 Ω

and for the 𝑅𝐷 and 𝑅𝑆, we propose the 𝑅𝐷 value that realistically can have the 𝐼𝐷 established value and
not have a lot of voltage; we decided for 200 𝛺. Now for 𝑅𝑆, as suggested by Figure 3.4, its value affects
where the 𝑄 point will be placed in these circuits, so we use a potentiometer to adjust 𝑅𝑆 value until
𝐼𝐷’s value reaches the 8 𝑚𝐴.
 V. CONCLUSION.

The feedback placed from the Gate to the Drain cannot make the ID increase its value, it can only make
it decrease, since the voltage from the Gate is lower than the one in Drain, the resulting current will go
from Drain to Gate.

There is no feasible way to have a potential difference between Gate and Drain to secure an electrical
current flow in the desired direction.

By implementing two fixed polarization circuits a gain of 100 is guaranteed. These circuits are connected
in cascade with a third circuit, from which a gain of −1 is obtained, we obtain a final gain of −100, which
turns out to be the gain established in the Figure 2.1.

By manually manipulating the resistor value at the source, we can reach the desired 𝑄 point while
having the 3 𝑉 established by the curve.

This also proves that in a JFET voltage divider biasing circuit the values of 𝑅𝐷 and 𝑅𝑆 can be placed by
logical reasoning and by trying various values respectively.

As shown by the results in this problems Field Effect Transistors are really different from BJT, not just in
how they work but in how the analysis must be done. While in BJT you can establish a lot of the values,
in FETs you need to use variables most of the time.

The fact that the Drain current is controlled by the Gate-Source Voltage makes the DC analysis a lot
harder than BJT since there is not a direct connection between these values

VI. REFERENCES.

Robert L. Boylestad & Louis Nashelsky. (2013). Electronic Devices and Circuit Theory. Pearson, United
States of America., New Jersey. Eleventh Edition
VII. ATTACHMENTS