Timing Issues and Clock Distribution

Lecture 10
18-322 Fall 2003

Textbook: [Sections 7.5, 10.1, 10.3]

Overview

Timing issues & clock distribution

System Performance Determination
Pipelining
Clock skew. Register timing
Counter clock skew
Review: Register Timing

cycle time

clk
setup time

Unstable data
hold time

clk-to-Q (propagation) delay (tpFF)

© Prentice Hall 1995
Sequential Systems: The Big Picture

Primary Primary
Inputs Outputs
Combinational
Logic

Current Next
State State
Memory
Elements
(Registers)
Clock
Maximum Clock Frequency
φ
“Speed” of the sequential machine
FF’s (how fast can this machine be
clocked)

f = 1/Tφ (clock frequency)

LOGIC Example: tp ~ 100ns =>

10MHz (limit on performance)
tp,comb

tp,FF + tp,comb + tsetup < Tφ

Setup Time
Required time for input to be stable
BEFORE CLOCK EDGE

Comb.
Logic

Data stable here

before clock here
Setup Time Fix

Data

This violation can be fixed by stretching the clock cycle

Data OK
Setup Time Fix 2

Data

OR
… by accelerating the combinational logic

Data OK
Hold Time

Required time for input to be stable

AFTER CLOCK EDGE

Comb.
Logic

Data stable here

after clock here
Hold Time Violations

Prop Delay: 1 ns Hold Time: 2 ns

Hold time violations are caused by “short paths”

Cannot be fixed by slowing down the clock!!!
Fixed by slowing down fast paths
Timing Analysis
Look for longest path: clock speed
Look for shortest paths: check hold time

Static Timing Analysis:

Attempt to determine longest/shortest path from schematic
Difficult problem
⌧Know the delay of logic elements, but cannot easily reason about
the entire design
False Paths
Example: #4

#3

#2 #3

Solutions:
Simulation
False Path Analysis
Speeding up System Performance:
Pipelining
tp,comb
REG

REG
a a

. .

REG

REG

REG
φ log φ log

REG
Out Out

φ φ φ φ
REG

REG
b b

Non-pipelined version Pipelined version

φ φ
How Good Is This?

REG
f . log

REG

REG

REG
Out

φ φ φ
REG

Pipelined version
φ

Tmin,pipe = tp,reg + max(tp,ADD,tp,abs,tp,log ) + tsetup,reg

Pipelining is used to implement high-performance data-paths
Adding extra pipeline stages only makes sense up to a certain point
Overview

Timing issues & clock distribution

System Performance Determination
Pipelining
Clock skew. Register timing
Counter clock skew
Synchronous Pipelined Data-Path:
Clock Skew

Clock Rates as High as 1 GHz in CMOS!

A clock line behaves as a
φ distributed RC line

tφ’ tφ’’ tφ’’’ Each register sees a local

clock time depending on
their distance from the clock
In CL1 R1 CL2 R2 CL3 R3 source -> clock skew
ti Out
δ = tφ” – tφ’ (> 0 or <0)
tl,min t r,min
Clock skew can severely
tl,max tr,max
affect the performance
Note: we assumed here
Clock Edge Timing Depends upon Position tsetup = 0
 Constraints on Skew

δ
φ’ φ’’ If the local clock of R2 is delayed
tφ’ tφ’’ = tφ’ + δ w.r.t. R1, it might happen that the
tr,min + tl,min + ti inputs of R2 change before the
R1 R2
previous data is latched -> race
data
δ ≤ tr,min + ti + tl,min
earliest time
(a) Race between clock and data.

δ The correct input data is stable at R2

φ’ φ’’ φ’’+ T
after the worst-case propagation
tφ’ tφ’’ + T = delay. The clock period must be
tr,max + tl,max + ti tφ’ + T + δ
large enough for the computations to
R1 R2 settle.
data
worst-case T ≥ tr,max + ti + tl,max - δ
(b) Data should be stable before clock pulse is applied.
Clock Constraints in Edge-Triggered Logic

(1) δ ≤ t r, min + t i + t l, min

(2) T ≥ tr,max + t i + t l,max – δ

Maximum Clock Skew Determined by Minimum Delay between Latches (condition 1)

Minimum Clock Period Determined by Maximum Delay between Latches (condition 2)
 Positive and Negative Skew
The clock is routed in the same direction as data
φ (a) Positive skew

The skew has to satisfy (1)

Data If it violates (1), then the circuit
CL R CL R CL R malfunction independently of the
clock period
Clock period decreases!!!

The clock is routed in the opposite direction of data φ (b) Negative skew

(1) is satisfied implicitly. The

circuit operates correctly
Data independently of the skew
CL R CL R CL R
Clock period increases by | δ|
Overview

Timing issues & clock distribution

Pipelining
Clock skew. Register timing
Counter clock skew
Countering Clock Skew
Negative Skew

REG

REG
REG
φ . log Out
REG

In φ φ
Positive Skew
φ

Clock Distribution

Data and Clock Routing

Goal: clock skew between registers is bounded!
(What matters is the relative skew between communicating registers.)
Clock Distribution: H-Trees

clk

• Every branch sees the same wire length and capacitance

•The clock skew is theoretically zero
• The sub-blocks should be small enough s.t. the skew within the block is tolerable
• It is essential to consider clock distribution early in the design process

Clock distribution is a major design problem!

Clock Network with Distributed Buffering
Local Area

Module Module
secondary clock drivers

Module Module

Module Module

main clock driver

CLOCK

Reduces absolute delay, and makes Power-Down easier

Sensitive to variations in Buffer Delay
DEC Alpha 21164

9.3 M Transistors, 4 metal layers, 0.55µm

Clock Freq: 300 MHz
Clock Load: 3.75 nF
Power in Clock = 20W (out of 50W)
Two Level Clock Distribution:
Clock Drivers
oSingle 6-stage driver at center
oSecondary buffers drive left and right
side
o Max clock skew less than 100psec
oRouting the clock in the opposite
direction
oProper timing
Clock Skew in Alpha

Clock driver
Timing & Race Conditions: Example
Source
32-bit
32-bit adder Destination
reg Cout
A
32-bit Sum 32-bit 32-bit 32-bit
B Cin reg
reg reg reg

≈
R2
A Cout
Sum
R1 B Cin
R3 R4 R5
Cout
v A
Sum
v B Cin v v v
300fF

~1mm wire
clk driver 200Ω, 100fF
150Ω
Example (cont’d)
π model
150Ω φ’ 200Ω φ”

600fF 50fF 50fF 900fF

tφ’ = 0.69 (150) (650) = 67ps

Find the skew between the source register tφ” = 0.69 [(150) (650) + (150 + 200)(950)] = 297ps
clock (φ’) and the destination (φ”)
δ = tφ’ – tφ” = 230ps

δ ≤ tr,min + ti + tl,min condition (1)

Check race condition thold + δ ≤ tclk-Q + tsum
100 + 230 ≤ 50 + 300 TRUE => No race problem

T ≥ tr,max + ti + tl,max - δ condition (2)

T ≥ tclk-Q + 31 tcarry + tsum - δ + tsetup
Find minimum clock period
T ≥ 50 + 31(250) + 300 –230 + 150 => T ≥ 8.2 ns