FPGA Lect3

FPGA and its applications
Prepared by:
Dr. Amit Joshi

Assistant Professor,
MNIT, Jaipur
3/30/2018 Digital System Design & FPGAs 1

Outline
 Introduction to PLD
 Basics of PLD
 What is FPGA?
 FPGA basic structure
 FPGA Implementation
 FPGA Applications
 Summary

Introduction to PLD
 ASIC (Application Specific Integration Circuit)
Circuit)::
- Fixed functionality
- Digital IC 74
74xx
xx series
 Concept of PLD (Programmable Logic Device)

Device)::
 It is possible to manufacture chips that contain relatively large amounts of
logic circuitry with a structure that is not fixed means we can modify (to
some extent) according to our requirement
requirement..
 Such chips are introduced in 1970 and are called PROGRAMMABLE LOGIC
DEVICES..
DEVICES
 Evolution of PLD
- PROM ,PLA ,PAL, CPLD, FPGA
Advantages of PLD
 Advantage of PLD
– Ease of design changes

– Flexibility
– No ASIC re-re-spin risk
– Easy & faster design Implementation
– Shorter time to market

Types of PLD
 There are mainly four types of PLD
1) SPLD (Simple Programmable Logic Device)
2) CPLD (Complex Programmable Logic Device)
3) FPGA (Filed Programmable Gate Array)
- ASIC (Application Specific Integrated Circuit)

SPLD vs FPGA
 SPLD
- Most basic & least expensive form of programmable logic
- It contains several configurable logic gates, programmable
interconnection, FFs etc.
 FPGA
- Millions of gates
- Fast and reprogrammable
- Many things can be done parallel for real time
- Gate level programming
3/30
30//2018 Digital System Design & FPGAs 6
Outline
 Basics of PLD
 What is FPGA?
 Summary

Programmable Logic Devices

Programmable Array Logic

Programmable Array Logic
w= ABC’ + A’B’CD’
X= A + BCD
Y=A’B + CD + B’D’
Z= ABC’ + A’B’CD’ + AC’D’ + A’B’C’D
= W + AC’D’ + A’B’C’D

Programmable Logic Array
F1= AB’ + AC +A’BC
F2= ( AC + BC )’

Why CPLD?
 CPLD (Complex Programmable Logic Devices)
Features:
 Low development cost

 Faster time to market
 Reduced PCB area
 Ease & Simple way to implement a design

Structure of CPLD

CPLD (Complex Programmable Logic Devices)
 Advantages :
- Simplified design process.

- Mostly standard architecture and easy to use.
- Low cost design and development tool
- Deterministic, uniform delays and predictable timing.
 Disadvantages :
- Low to moderate density

- Inflexible architecture

Outline
 Basics of PLD
 What is FPGA?
 Summary

What is FPGA?
 FPGA stands for Field Programmable Gate Array
 More Gate count to support complex logic Circuit
 It does not contain AND and OR planes.
 They have
- Logic blocks which are arranged in 2-
2-D.
- Routing channels, programmable switches.
 Mostly LUT are there to implement logic.
 LUTs of various sizes can be created, they are limited by
number of inputs.

Purpose of FPGA
 FPGA is programmable ICs
 Configurable i.e. programmable
- Logic blocks
- Inter connects
 The term “Field programmable” means programming in the

particular field where device function can be modified as per
logic circuit

FPGA
 Inexpensive, easy realization of logic network in the form of

hardware.. Easy such as software !!!!!
hardware
 Hardware of FPGA contains Logic gates, RAM and others
(such DCM)
 Fast implementation where so many thing are working parallel
 Gate level working i.e. smallest level of circuit with building
complex systems

Vendors of FPGA
 Mainly Xilinx, Altera and Actel
 Differences of FPGA in terms of
- Physical means for implementation programmability
- Inter connection arrangement
- Basic function of logic blocks
- LUTs input

Outline
 Basics of PLD
 What is FPGA?
 Summary

FPGA structure

Biggest FPGA producers are :
Company Percentage of Total Revenue
Total
Xilinx 49% 2.4 Billion $
Altera 40% 1 Billion $
Quick Logic 1% 26 Million $
Micri Semi 4% 207 Million $
Lattice Semi 6% 297 Million $
- Xilinx and Altera have 89% of the Market

FPGAs
Summary of Commercially Available FPGAs
Company General Logic Block Programming

Architecture Type Technology
Xilinx Symmetrical Array Look-up Table Static RAM
Actel Row-based Multiplexer-Based Anti-fuse

Altera Hierarchical-PLD PLD Block EPROM
Plessey Sea-of-Gates NAND-gate Static RAM

PLUS Hierarchical-PLD PLD Block EPROM
AMD Hierarchical-PLD PLD Block EEPROM
QuickLogic Symmetrical Array Multiplexer-Based Anti-fuse
Algotronix Sea-of-gates Multiplexers & Basic Gate Static RAM

Concurrent Sea-of-gates Multiplexers & Basic Gate Static RAM
Crosspoint Row-based Transistors Pairs & Anti-fuse

Multiplexers

XILINX FPGA
ARCHITECTURE

Elements of FPGA
 Various types of FPGA such as Virtex
Virtex--II, Sparten 3E, Sparten
3A, Sparten 6, Kintex 7, Artix 7 etc..
 All Xilinx FPGA contains

1) CLB (Configurable Logic Block)
2) IOB (Input output Buffer)
3) PI (Programmable Interconnection)
4) RAM blocks
5) Other Resources - three state buffers, Global clock buffers,
Dedicated Multiplier

Simplified CLB Structure

LUT--Based Logic Cells
LUT
1. LUT is a memory which contains the truth

truth--table of a function
2. LUT with n inputs can implement any n-bit function
3. Truth--table is placed in LUT during the FPGA programming

Truth
4. LUTs are implemented with SRAM

Example: 4-input AND
gate
A B C D O
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0 A,B,C and D are act as address pointer
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
Output can be present value or previous store
1 1 0 1 0 value
1 1 1 0 0
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1 1 1 1 1 Digital System Design & FPGAs
Example:

Example
 x=(a & b)|((not b) & c);
Truth Table
SRAM Cell (LUT)
a b c x
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
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1 1 1 1 Digital System Design & FPGAs 30
Programmability
 Three Methods
1. SRAM Based – Xilinx, Altera
2. Antifuse Technology - Actel
Actel,, Quicklogic
3. EPROM/EEPROM

SRAM BASED PROGRAMMING
 FPGA Connections –
1. Pass Transistors
2. Transmission Gates
3. Multiplexer
 Making or Breaking cross point connections.

 SRAM defines function of logic block.
 In programming, SRAM cells are arranged in shift register manner in
order to configure using Digital
3/30/2018 bit fileSystem Design & FPGAs 32
SRAM Programming Technology
 Employs SRAM (Static RAM) cells to
control pass transistors and/or
transmission gates
 SRAM cells control the configuration of
logic block
 Volatile
 Needs an external storage
 Needs a power-
power-on configuration
mechanism
 In
In--circuit re-
re-programmable
 Lesser configuration time
 Occupies relatively larger area
Interconnection Network
SRAM CELL is used to

program 0 or 1 at FET
Level.
SRAM CELL is used to program 0 or
1 at inputs. So it decides function of
CLB

Antifuse Technology
 One Time Programming
 Invented at Stanford and developed by Actel
 Actel PLICE (Programmable Logic Interconnect Circuit Element)
structure
 Anti--fuse resides in a high
Anti high--impedance state. Can be programmed
into low impedance or "fused" state.
 Less expensive than the RAM technology

Comparison of two programming technology
Antifuse Technology SRAM technology
- It occupies less area - it has larger area

- Delay less , High Speed - Delay is high
Why to go for reprogramability !!!

To have interface between Microprocessor and DSP for
communication for different data rates

Arithmetic Resources in FPGA
1. Adder
2. Multiplier
3. Counter
 Special circuitry to speed up operation

 Dedicated Carry Logic/ XOR
 ASIC is faster compare to FPGA. FPGA has to speed
up for improvement therefore arithmetic resources

FPGA
 Advantage:----
Advantage: ----
- Ideal for customized design
- High complexity , density and reliability
- Low cost, power consumption, small physical size
- Fast time to market
 Disadvantage:----
Disadvantage:----
- long delay in design and testing

Comparison Of CPLD & FPGA
CPLD FPGA
 Logic gates are less in number  Several millions of gates
 Number of i/o pins are  Number of i/o pins are less

significantly higher than CPLD
 CPLD does not require any  It requires one or more PROM
external memory store depend on the size
program
 CPLD are smaller than FPGA  FPGA are larger than CPLD

FPGA (Field Programmable Gate Array)
 What are the limitations of FPGA?

 Existence of programmable switches.
 Of course they provide programmable feature to
user but, they consume lot of real estate on the chip.
 They make reduce the speed of operation.

Where do FPGA lies?
Types of IC
PLDs ASICs
-SPLD, CPLD - Gate Array, structured Array,
Standard cell, Full custom
- Features - Features
F No Reconfigurable,
Highly Reconfigurable,
P Time Consuming
Faster Design Time expensive
Don’t support complex logic G
Support complex logic
A
Introduction to Gate Array
 Gate array is a prefabricated silicon chip circuit.
circuit.
 Gate array is an IC chip on which gates are placed in

a matrix form
 Gate array contains basic cell as most important

element.. It contains (either CMOS,NAND,NOR or
element
any other active device).
device).
3/30
Gate Array

Gate Array Design
 Gate array implementation requires a two step manufacturing

process::
process
- The first phase, which is based on generic (standard) masks,
results in an array of uncommitted transistors on each GA
chip..
chip
- These uncommitted chips can be stored for later
customization, which is completed by defining the metal
interconnects between transistors of arrays
arrays..

Designing Approaches
VLSI design
Full custom (geometry &

Semi custom
placement of every transistor (such as std cell
design or FPGA)
can be optimized individually)

Full custom design:
Requires longer time till design maturity
Adjustment flexibility of almost every aspect improves
the circuit performance
High performance but large cost in terms of design cycle
time.
Semi custom design:
Requires less time till design maturity
In early stage, performance is better to full custom
design because, some components are optimized. But, less
opportunity for improvement in the circuit performance.
Lesser performance but shorter design cycle time.
3/30
Outline
 Basics of PLD
 What is FPGA?
 Summary
Xilinx ISE Design Flow

Introduction to Xilinx ISE
 ISE stands for Integrated Software Environment
 All tools are integrated as collection in one GUI
 Tools for Xilinx ISE:
a) HDL Complier/Simulator - Xilinx ISE sim sim,, Modelsim
b) Synthesis - XST
c) Core generator & Arch Wizard – Coregen
d) Pin out & Area Constraint Editor - PACE
e) Implementation – Translate/MAP/PAR
f) Device Configuration - IMPACT

Xilinx Design Flow
 Design Entry : (ISIM)
- Input file can be ..sch
sch,, .v, ..vhd
vhd
 Synthesis : (XST)
- Produces the net list file starting from an HDL/schematic file
description
- Converts .v,. vhd
vhd,, ..sch ---- .NGC file (netlist
sch ---- (netlist file with
constraint)
 Translate : (XST)
- Read all input design file then write result into on emerged file
that describes logic and constraint
- Converts .NGC file ---  .NGD (Native Generic Database)
---
file, this file describes logic design to Xilinx primitives

Xilinx Design Flow
 Mapping – (XST)
- maps logic on the device components
- Takes the netlist and logic elements into CLBs and IOBs
- Converts .NGD --  .NCD (Native Circuit Description) &
--
.PCF (Physical Constraint File)
- .NCD file represents the physical circuit (Which CLBs, IOBS
and interconnections) description of the input design as applied
to specific design
- . PCF has constraint according to device dependent

Xilinx Design Flow
 Place & Route – (XST)
- Determines the placement of cells and the routing between
cells
 Bit stream generation –

- Is a stream of data that contains the location information for
logic and devices
- Actual bit stream to be sent or to be load on FPGA
 Configuration/ Programming (IMPACT)

- Download a bit file into FPGA using JTAG port

Translation
Synthesis
Circuit netlist Timing Constraints

Constraint Editor
Electronic Design Native
Interchange Format Constraint
File
EDIF NCF UCF User Constraint File
Translation
NGD Native Generic Database file

Sample UCF File
NET "clock" LOC = "P8";
NET "control<0>" LOC = "K4";
NET "reset" LOC = "E11";
NET "segments<0>" LOC = "R10";
NET "segments<1>" LOC = "P10";
NET "segments<2>" LOC = "M11";
NET "segments<3>" LOC = "M6";
NET "segments<4>" LOC = "N6";
NET "segments<5>" LOC = "T7";
NET "segments<6>" LOC = "R7";
"R7";
set_property -dict { PACKAGE_PIN J15

IOSTANDARD LVCMOS33 } [get_ports
[get_ports { A
}]; #IO_L24N_T3_RS0_15 Sch
Sch=
=sw
sw[0]
[0]
Circuit netlist

Mapping
LU
T0
LU
T4
LU
T1 FF
LU 1
T5
LU
T2
FF
LU 2
T3
3/30
Placement: Select CLBs

FPGA
Placing CLB SLICES

Routing: Select path

FPGA Generic Flow
 Design Entry:
– Create your design files using:
• schematic editor or
• hardware description language (Verilog
(Verilog,,
VHDL)
 Design “implementation” on FPGA:

– Partition, place, and route to create bit-
bit-
stream file
–Converts HDL to format which FPGA
understands
 Design verification:
– Use Simulator to check function,
– Load onto FPGA device (cable connects PC
to development board)-
board)- Logic Analyzer
 check operation at full speed in real

environment.
FPGA Implementation
 Partition: Converts logic blocks into n –input CLB blocks
 Placement : Choosing the appropriate CLBs
 Routing : Interconnection of CLBs
 Translation : For design entry of 4 FFs logic to number of CLB
.i.e if CLB has two FFs then divide the logic in 2 CLBs

ASIC vs FPGA vs Microprocessor
Performance NREs Unit Cost Time To Market
(Speed) (TTM)
ASIC ASIC FPGA ASIC
FPGA FPGA Microprocessor FPGA
Microprocessor Microprocessor ASIC Microprocessor
Microprocessors are more complex than FPGAs

Microprocessors have fixed instructions while FPGAs
don’t

COMPARISION

FPGA Application
 In DSP ,software defined radio, defense system, aerospace
 Speech recognition/synthesis/Translator
 Computer hardware simulation
 Image/ Video processing
 Gate array prototyping
 Biomedical application/ healthcare
 Data Security algorithms
Many more

Outline
 Basics of PLD
 What is FPGA?
 Summary
Latest 7 series FPGA Family
 There are mainly three 7 series family:
1) Artix 7: Lowest Price & power
2) Kintex 7: Best Price & Performance
3) Virtex 7: High Performance & Capacity
 Same CLB architecture structure
 High Speed and low power consumption
 Reduced power almost 50%

Comparison of 7 Series FPGA
Family
 Artix-7 cost is 320 USD, while Kintex 7 is

Artix-
1250 USD and Virtex 7000 USD, Zynq ???.
Xilinx 7 Series Family

Virtex 7 Series

Strong Focus on Power Reduction

7 Series FPGA Applications
 The Artix
Artix--7 family is ideally suited to demanding handheld
applications including portable ultrasound machines, digital
camera control and software-
software-defined radio.
radio.
 The low-
low-power, cost-
cost-effective Kintex
Kintex--7 family provides a perfect
balance of features and performance, making it ideal for wireless
LTE infrastructure equipment, LED backlit and 3D digital video
displays, medical imaging and avionics imaging systems
systems..
 The highest in system performance, the Virtex-

Virtex-7 family useful in
optical networks, radar and ASIC emulation.
emulation.
7 Series FPGA Family Architecture

7 Series FPGA Family Layout

Clock Regions and I/O Banks

Clock Management

CLB Structure

Slices in CLB

Slice Resource

Block RAM

DSP Slice

Clocking Resources

XADC: Dual 12-
12-Bit 1-
1-MSPS
ADCs

I/O Composition

Zynq Board

FPGA Technology

Cost, Power and Performance

Where Can I Learn More?

References
 Xilinx website
 Advanced FPGA Design: Architecture,
Implementation, and Optimization by Steve Kilts
 Digital Systems Design with FPGAs and CPLDs
by Ian Grouts

THANK YOU

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FPGA and its applications

Dr. Amit Joshi

3/30/2018 Digital System Design & FPGAs 1

 FPGA basic structure

3/30/2018 Digital System Design & FPGAs 2

 Concept of PLD (Programmable Logic Device)

– Ease of design changes

3/30/2018 Digital System Design & FPGAs 4

- ASIC (Application Specific Integrated Circuit)

3/30/2018 Digital System Design & FPGAs 5

 FPGA basic structure

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 Low development cost

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- Simplified design process.

- Low to moderate density

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 FPGA basic structure

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 Configurable i.e. programmable

 The term “Field programmable” means programming in the

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 Inexpensive, easy realization of logic network in the form of

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 FPGA basic structure

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- Xilinx and Altera have 89% of the Market

3/30/2018 Digital System Design & FPGAs 22

Company General Logic Block Programming

Xilinx Symmetrical Array Look-up Table Static RAM

Actel Row-based Multiplexer-Based Anti-fuse

Plessey Sea-of-Gates NAND-gate Static RAM

Algotronix Sea-of-gates Multiplexers & Basic Gate Static RAM

Crosspoint Row-based Transistors Pairs & Anti-fuse

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 All Xilinx FPGA contains

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1. LUT is a memory which contains the truth

2. LUT with n inputs can implement any n-bit function

3. Truth--table is placed in LUT during the FPGA programming

4. LUTs are implemented with SRAM

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 Making or Breaking cross point connections.

SRAM CELL is used to

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- It occupies less area - it has larger area

Why to go for reprogramability !!!

3/30/2018 Digital System Design & FPGAs 37

 Special circuitry to speed up operation

3/30/2018 Digital System Design & FPGAs 38