Nps DF69

EE6306 ASIC Design
A Mini Stereo Digital Audio Processor (MSDAP) Design
INPUTR
INPUTL
FRAME
VDDIO
VSS
20
16
19
18
17
SCLK 1 15 START
DCLK 2 MSDAP 14 VDDC

(Top View)
VDDC 3 13 VSS
VSS 4
Designed by Hua Zhang 12 INREADY
RESET 5 11 OUTREADY
7
6
10
9
8
OUTPUTR
OUTPUTL
VDDIO
VSS
NC
Fall, 2006
Dept. of Electrical Engineering
The University of Texas at Dallas
hua.zhang@utdallas.edu
TABLE OF CONTENTS
1. Introduction
1.1 Design Flow .…….............….....….. ………................................…. 4
1.2 Chip Information …….…...............…….…………….....….….…… 6
1.3 Chip Environment ……..................…….…………….....….….…… 7
1.4 Coefficient Format …….................…….…………….....….….…… 9
1.5 I/O Pin ……………….…...............…….…………….....….….…… 11
1.6 FSM Design ……………...............…….…………….....….….…… 13
2. Simulation
2.1 Setup ModelSim .……….....…..… ..............…….........................…. 18
2.2 Functional Simulation ……...………..………………..........….…… 21
2.3 Post-Simulation ………...................................…….............….......... 23
3. Logic Synthesis
3.1 Setup Synopsys Design Vision ……………….....................….…… 24
3.2 Compile Design ……………….................................................….… 27
3.3 Check Design and Reports ……………....................................….… 30
4. Automatic Placement and Routing

4.1 Set up Cadence Encounter ………………................................….… 32
4.2 Import the design ………………..............................................….… 36
4.3 Floorplan …………...........….........................................................… 44
4.4 Plan Power/Ground Rings and Stripes …………......................….… 49
4.5 Route Power/Ground to Power/Ground Pins ……............….........… 56
4.6 Design Rule Check (DRC) ………........…............................….…… 59
4.7 Amoeba Placement ………………..................…......................…… 63
4.8 Trial Route ……………….........................................................…… 66
4.9 Timing Analysis and Optimization
2
4.9.1 RC Exaction ………………...........................................…… 71

4.9.2 Setup Timing ………………..............................................… 75
4.9.3 Clock Tree Synthesis (CTS) ……………….................….… 78
4.9.4 Hold Timing …………..................................................….… 84
4.10 CeltIC (Crosstalk) Signal Integrity (SI) ……...................………..… 87
4.11 Power Analysis …………….....................................................….… 94
4.12 Reports and Export ….........………...........................................….…100
5. Flip Chip Planning

5.1 Import the Design ………………..............................................….…106
5.2 Create Bump Matrix ………………..........................................….…112
5.3 Assign IO Signals to Bumps ……………….............................….… 115
5.4 Assign Power/Ground to Bumps ……….......................................….118
5.5 Route IO Signals to Bumps ………………...............................….… 121
5.6 Plan Power/Ground Rings and Stripes …………...................…….... 129
5.7 Route Power/Ground to Power/Ground Bumps ……...........…..........132
References ……………………..…………………………………....................…… 135
3
Chapter 1 Introduction
1.1 Design Flow
This paper implements a completed Mini Stereo Digital Audio Processor (MSDAP)
design proposed in [1, 2]. With the design specifications such as clock frequency and IO
pins, the HDL codes are compiled and simulated by Mental Graphic ModelSim SE 6.1b.
Then Synopsys Design Vision (Design Compiler) v2003.12 performs the logic synthesis
and converts the behavioral-level design into a gate-level netlist in Verilog. Automatic
placement and routing is achieved by Cadence Encounter SOC 4.10. Meanwhile, Design
Rule Checks (DRC), RC extraction, Clock Tree Synthesis (CTS), CeltIC (crosstalk noise)
Signal Integrity (SI) and Flip Chip Planning are analyzed and implemented. Setup and
Hold time violation has been fixed by timing analysis and optimization. Then post-
simulation is made by Mental ModelSim. Layout Versus Schematic (LVS) will be
checked by Cadence Virtuoso 5.0. Final reports such as size and power consumption are
generated and the Graphic Data System (gds) file is ready for chip assembling by foundry.
A simple Design flow of the MSDAP chip design is showed in the following figure:
4
MSDAP Chip
Design Analysis
HDL Code Design

(Text Editor)
.vhd or .v
Functional Simulation
(Mental ModelSim)
SDF: (Timing) Standard Delay format

LIB: Synopsys internal library format .db, .sdb .vhd or .v
DB: Synopsys database format
Logic Synthesis
(Synopsys Design Vision or Cadence Virtuoso)
.lef, .lib, .cdB msdap_netlist.v, msdap.io, msdap.sdc
Automatic Placement and Routing

DRC
RC extraction
Flip Chip Planning
(Cadence SOC Encounter)
Abstract view MSDAP.def MSDAP_netlist.v, MSDAP.sdf

or MSDAP.gds lib.v
LVS, RC extraction Post-Simulation

(Cadence Virtuoso) (Mental ModelSim)
MSDAP.gds
Tapeout / Wafer Foundry Processing
5
1.2 Chip Information
The MSDAP chip design contains 963 modules, 4279 standard cells (equal to 25.7k
gates), 20 IO pads and 4564 nets. The chip size is 1.14×1.14 mm (=1.3 mm2) and power
consumption is 1.9 mw. The netlist format is hierarchical Verilog. It has two independent
clock sources: SClock (system clock) and DClock (data clock).
The process used is the Artisan TSMC 0.18 micrometer Std.Cell/Pad technology with 6
layers of metal. The process used for flip chip planning is a modified Artisan TSMC 0.18
nm process technology with 2 redistribution (RDL) layers and 6 layers of metal for detail
routing, totaling 8 layers of metal.
Virtual prototyping is used to quickly determine the feasibility of the MSDAP design.
The design inputs are the netlist, clock sources and timing constraints. The
process/technology inputs are the physical libraries, timing libraries and process
technology libraries.
6
1.3 Chip Environment
The working environment of the MSDAP chip is illustrated as follows:
Sclk
Dclk
Start
ADC Reset
Frame
Controller InputL/InputR MSDAP
InReady
DAC OutReady
OutputL/OutputR
A standard format is provided on a single shielded twisted wire pair from ADC (analog-
to-digital converter) to Controller, and also from Controller to DAC (digital-to-analog
converter). This standard, named AES-2003 [3], is a recommended interface for the serial
digital transmission of two channels of periodically sampled and linearly represented
digital audio data from one transmitter to one receiver.
Audio data transmitting between ADC/DAC and Controller is embedded in a frame

format [3]. Controller extracts audio data from a frame and sends audio data to the
MSDAP chip in stereophonic mode. In stereophonic mode, Controller transmits
stereophonic audio in which the two channels are presumed to have been simultaneously
sampled. The left channel conveys audio data in InputL pin of the MSDAP chip, while
the right channel does in InputR pin. At the same time, Controller receives both left
channel and right channel of output data from OutputL and OutputR pins of the MSDAP
chip. Then Controller packs output data in the frame format and transmits to DAC.
It is expected that another kind of frame format will be used between Controller and the
MSDAP chip to convey audio data that have been sampled at frequency of 768 KHz.
7
Each frame is divided into 16 time slots, numbered from 0 to 15. Therefore, the frame
rate is at frequency of 48 KHz (768 KHz/16). The audio sample frame format is
illustrated as follows:
0 1 (Time slots) 15
Sign bit MSB (16-bit audio sample word) LSB
Time slots 0 to 15 present the audio sample word. The sign bit is carried by time slot 0.
The most significant bit (MSB) is carried by time slot 1. The audio sample word is linear
in 2’s complement binary form. Positive numbers correspond to positive analog voltages
at the input of the ADC. The number of bits per word can be specified to 16.
As the algorithm introduced in paper [1], the right and the left channel might have
different coefficients u in the MSDAP chip. After the chip is powered on, Controller
transmits the left and right channel coefficients u through InputL and InputR pins
respectively.
The format of u will be discussed in the next section. Later on, all the signals between
Controller and the MSDAP chip will be discussed in the I/O Pin Section.
8
1.4 Coefficient Format
As the algorithm introduced in paper [1], there are 16 coefficients in this project. One
coefficient represents the algebraic relationship of 8 input samples. Some of input
samples may be unattended. The others are attended but they may be involved in either
addition or subtraction operation.
One possible format of these coefficients can be defined like this way: each coefficient
has 16 bits and the leftmost bit is the most significant bit (MSB). Each input sample
occupies two bits. One bit is sign bit and the other is value bit. If one input sample is
untended, its value bit is 0 and its sign bit is also 0. If one input sample is attended, its
value bit is 1. Furthermore, if this attended input sample is involved in addition, its sign
bit is 0, otherwise it is 1. For example, the format of the coefficient u1 can be showed in
the following figure:
u1 = x(n-6)-x(n-7)
= 0×x(n) + 0×x(n-1) + 0×x(n-2) + 0×x(n-3) + 0×x(n-4) + 0×x(n-5) + 1×x(n-6) - 1×x(n-7)
s: sign bit
0: addition s v s v s v s v s v s v s v s v
1: subtraction 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
v: value bit MSB 16 bits LSB
0: untended
1: attended
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In this project, all the 16 coefficients are showed in the following table (spaces are added
for readability):
u 0 1 2 3 4 5 6 7
u1 = x(n-6)-x(n-7) 00 00 00 00 00 00 01 11
u2 = -x(n)+x(n-5) 11 00 00 00 00 01 00 00
u3 = -x(n-3)-x(n-7) 00 00 00 11 00 00 00 11
u4 = x(n)+x(n-4) 01 00 00 00 01 00 00 00
u5 = -x(n-1)-x(n-6) 00 11 00 00 00 00 11 00
u6 = -x(n-2) 00 00 11 00 00 00 00 00
u7 = x(n)+x(n-5) 01 00 00 00 00 01 00 00
u8 = x(n-3)-x(n-4)+x(n-7) 00 00 00 01 11 00 00 01
u9 = -x(n-1)-x(n-6) 00 11 00 00 00 00 11 00
u10 = 0 00 00 00 00 00 00 00 00
u11 = x(n-5) 00 00 00 00 00 01 00 00
u12 = x(n-2)-x(n-4) 00 00 01 00 11 00 00 00
u13 = x(n-1)+x(n-3) 00 01 00 01 00 00 00 00
u14 = -x(n)-x(n-2) 11 00 11 00 00 00 00 00
u15 = x(n-1) 00 01 00 00 00 00 00 00
u16 = x(n) 01 00 00 00 00 00 00 00
The coefficient u16 is sent to the chip first because the u16 is the most important
coefficient which affects the output a lot. Then coefficients u15 u14…till u1 are sent
continually. In each coefficient, the MSB is transmitted first. So the stream sequence of
coefficients would be showed in the following figure (spaces are added for readability):
u16 u15 u14 u13

←01 00 00 00 00 00 00 00 ←00 01 00 00 00 00 00 00 ←11 00 11 00 00 00 00 00 ←00 01 00 01 00 00 00 00
u12 u11 u10 u9
00 00 01 00 11 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 11 00
u8 u7 u6 u5
00 00 00 01 11 00 00 01 01 00 00 00 00 01 00 00 00 00 11 00 00 00 00 00 00 11 00 00 00 00 11 00
u4 u3 u2 u1
01 00 00 00 01 00 00 00 00 00 00 11 00 00 00 11 11 00 00 00 00 01 00 00 00 00 00 00 00 00 01 11←
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1.5 I/O Pin
In this course, it is not required to delivery the chip to foundry for tapeout processing. For
the integrity of this course project, we provide an example of package [4]. The chip is
assume to be packaged in a 20 pin PLCC package having a body size of 8 mm by 8 mm
and a pin pitch of 1.3 mm.
PLCC stands for Plastic Leaded Chip Carrier, a square surface-mount chip package for
low thermal output microprocessors that substitutes epoxy plastic for the ceramic
materials that are commonly used to encase chips in systems designed for
microprocessors that produce high thermal outputs that can melt the plastic epoxy. Unlike
pin grid arrays, the die in a PLCC is attached to the package by a gold-plated contact pad.
The I/O pin layout diagram is illustrated in the cover page. The description of I/O pins is
in the following table:
Pin Pin
Type Function
Name No.
3 The power pins should be connected to a well-decoupled +1.8 v DC core
VDDC Power
14 power supply.
7 The power pins should be connected to a well-decoupled +1.8 v DC I/O
VDDIO Power
19 power supply.
4
8
VSS Ground The core ground pins should be connected to GND.
13
18
• Sclk (System clock) is a 50% duty cycle clock running at a frequency
between 6.144 MHz (768 KHz × 8) and 6.8 MHz.
Sclk Input 1 • Sclk provides timing reference for the internal, input and output control
signals.
(1) Inputs Frame is detected on the rising edge of Sclk.
(2) Outputs InReady is updated on the rising edge of Sclk.
• Dclk (Data Clock) is a 50% duty cycle clock running at a specific
frequency of 768 kHz (48 KHz × 16 bits).
• Dclk provides timing reference for the input and output sample
transmitting.
Dclk Input 2
(3) Inputs InputL and InputR are read in on the rising edge of Dclk.
(4) Outputs OutReady, OutputL and OutputR are updated on the rising
edge of Dclk.
• Sclk may be asynchronous with Dclk.
• When Start is set high, the chip begins to initialize.
Start Input 15 • Start is set high for one data clock cycle, then it is set low.
• Start is asynchronous with Sclk or Dclk.
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• When Reset is set low, the chip begins to reset.

Reset Input 5 • Reset is set low for one data clock cycle, then it is set high.
• Reset is asynchronous with Sclk or Dclk.
• InReady (Input Ready) is set high when the chip is ready to read
InReady Output 12 coefficients or input samples. Otherwise, it is set low.
• InReady is updated on the rising edge of Sclk.
• OutReady (Output Ready) is set high when the chip is transmitting
OutReady Output 11 output sample. Otherwise, it is set low.
• OutReady is updated on the rising edge of Dclk.
• InputL carries left channel serial coefficients and audio samples.
• Bit 0 of each serial word is the sign bit, the first bit transmitted. Bit 15
InputL Input 17 is the least significant bit (LSB) of each serial word, the last bit
transmitted.
• InputL is read in on the rising edge of Dclk.
• InputR carries right channel serial coefficients and audio samples.
InputR Input 16 is the least significant bit (LSB) of each serial word, the last bit
transmitted.
• InputR is read in on the rising edge of Dclk.
• OutputL carries left channel serial output samples.
OutputL Output 9 is the least significant bit (LSB) of each serial word, the last bit
transmitted.
• OutputL is updated on the rising edge of Dclk.
• OutputR carries right channel output sample frame in byte serial format.
OutputR Output 10 is the least significant bit (LSB) of each serial word, the last bit
transmitted.
• OutputR is updated on the rising edge of Dclk.
• Frame aligns the serial coefficients, input and output samples.
• Frame is set high when the first bit of one serial coefficient or one
Frame Input 20 audio sample word is available on InputL or InputR, OutputL or
OutputR pins.
• Frame is set high for one data clock cycle, then is set low.
NC 6 Unused pins.
Notes on Pin Description:
Total: 20 I/O pins

• Input: 7 pins
• Output: 4 pins
• Power and Ground: 8 pins (VDDC: 2; VDDIO: 2; VSS: 4)
• Unused (NC): 1 pin.
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1.6 FSM Design
The top level execution of MSDAP chip can be modeled by a finite state machine (FSM).
There are seven states defined in the following figure:
Start State 0
Initialization
State 1
Waiting to Receive InReady='1'
Coefficients
Frame='1'
State 2
Reading Coefficients InReady='1'
State 3
Waiting to InReady='1'
Receive data
Frame='1'
Reset
State 4
Working
Reset one none-zero input sample on
either left or right channel
100 consecutive zero
input samples on both
Reset left and right channels
State 6 InReady='1'
State 5
Clearing Reset Sleeping
13
There are some assumptions:
1. No Reset in state 0, 1 or 2.
2. When the chip receives 100 consecutive zero input samples, all the data in
memories and registers except for coefficient are zero. It is the same way of
Clearing state doing. So the chip can skip Clearing state and turn from Working
state to Sleeping state.
3. If the external Control detects that InReady='0' sent by the chip, Control will not
transmit Dclk, Frame and any input sample to the chip until the InReady='1' is
detected.
4. If the external Control detects that InReady='1' sent by the chip, the continuing
inactive time of Frame will not be more than 16 data clock cycle.
State 0: • Once Start is high, the chip begins to initialize including reset point
Initialization locations and clear all the memories and registers, etc.
• Once the initialization process is completed, the chip enters State 1.
State 1: Waiting to • In this state, InReady is set high.

receive Coefficients • If Frame is detected to be high, the chip enters State 2.
State 2: • In this state, the chip reads 16 coefficients. InReady is still set high.
Reading • Once all the 16 coefficients have been loaded, the chip enters State 3.
Coefficients • An I/O schedule example showing the transition from State 1 to State 2
is illustrated in the following figure:
14
counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Dclk
InReady
Frame
InputL&R
State Waiting
Reading Coefficients
Coeff.
State 3: Waiting to • In this state, InReady is still set high.

Receive Data • If Frame is detected to be high, the chip enters State 4. Or if
Reset is detected to be low, the chip enters State 5.
State 4: • In this state, the chip continually reads input samples, does the
Working convolution computation, then carries out output samples. InReady is
still set high.
• If Reset is detected to be low, the chip enters State 5. Or when the chip
detects that 100 consecutive input samples (1600 data clock cycles) are
zero on both left and right channels, the chip enters State 6.
• Two I/O schedule examples are illustrated in the following figures:
(1) One shows the transition from State 3 to State 4. At that time,
output sample has not been figured out yet.
(2) Another demonstrates the transition when the first output sample is
being carried out.
15
counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Dclk
InReady
OutReady
Frame
InputL&R
State Waiting
Working
data
counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Dclk
InReady
OutReady
Frame
OutputL&R
State working
State 5: • In this state, all the input and output samples in memories or registers
Clearing except for coefficients are cleared to zero.
• These clearing steps may cost a few system clock cycles. If Reset is
detected to be low again during that process, the chip will come back
to the beginning of this state.
• Once the clearing step is completed, the chip enters State 3.
16
State 6: • In this state, if any none-zero input sample on either left or right
Sleeping channel is detected, the chip enters State 4. InReady is still set high.
• If Reset is detected to be low, the chip enters State 5.
• Two I/O schedule examples are illustrated in the following figures:
(1) One shows the transition from State 4 to 6.
(2) Another demonstrates the transition from State 6 to 4.
counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Dclk
InReady
OutReady
InputL&R
State Working Sleeping
counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Dclk
InReady
OutReady
Frame
InputL&R
State Sleeping Working
17
Chapter 2 Simulation
Mentor Graphics ModelSim can do both functional simulation and post-simulation.

Functional simulation is run after the VHDL/Verilog code has been compiled. Post-
simulation is run after placement and routing. The same testbench and an input data file
are provided for both the functional simulation and post-simulation. An output data file
will be generated if the simulation is completed successfully. Then the generated output
data will be compared with the expected data.
2.2 Setup ModelSim
Run ModelSim, the main window is showed as the following figure:
Open the File -> New -> Project -> Create Project form, enter work in the Project Name
box and select the Project Location. Show in the following figure:
18
Click the OK button when ready. Then in the pop-up Add items to the Project form,
choose the Add Existing File and show in the following figure:
In the pop-up Add file to Project form, click the Browse button to select all the design
VHDL/Verilog files. Show in the following figure:
Click the OK button when ready. Then, the design has been added to a project. Click the
Compile -> Compile All menu and show in the following figure:
19
20
2.2 Functional Simulation
Open the Simulate -> Start Simulation form, or click the Library tab in the Workspace
window, expand the work and double-click the testbench to begin simulate.
Right-click the testbench in the Workspace window and click the Add -> Add to Wave.
Typing Run enough simulation time in the Transcript window at the bottom of the main
window and show in the following figure:
21
Or click File -> Load menu to run a script msdap.do file. Click the Simulation -> End
Simulation menu and an output data file will be generated in the project directory.
22
2.3 Post-Simulation
Post-simulation is run after placement and routing. The testbench is the same as the one
used in functional simulation. The MSDAP.sdf and a library Verilog file will be added.
Open the Simulate -> Start Simulation form and click the SDF tab page. Click the Add
button, in the pop-up Add SDF Entry form click the Browse button and select the
MSDAP.sdf. Enter UUT in the Apply to Region box. UUT is the component name of the
msdap top-level module in the testbench. Click the OK button when ready. Show in the
following figure:
The Start Simulation form is showed in the following figure:
Click the OK button to begin the post-simulation.
23
Chapter 3 Logic Synthesis
Both Synopsys Design Vision (Design Compiler) and Cadence Virtuoso can perform the
logic synthesis. As a visual analysis tool and GUI for Synopsys synthesis, Design Vision
works with Design Compiler to synthesize and analyze the design at the gate level. We
use Design Vision in this paper.
3.1 Setup Synopsys Design Vision
Each time when open a shell to start any of cad tools, need to enter the following
command to set up environment:
>EE6306>. /home/cad/startup/cadprofile_new
Now type the following to start Synopsys Design Vision:

>EE6306>design_vision
Design Vision uses HDL Compiler to read both RTL designs and gate-level netlists as
design file input.
• Use the Read to read gate-level netlists while use the Analyze then Elaborate
commands to read RTL designs. Design Vision supports all the principal gate-
level netlist formats.
• The Analyze command checks the HDL designs for proper syntax and
synthesizable logic, translates the design files into an intermediate format -
Synopsys database (.db) format, and stores the intermediate files. The Elaborate
command first checks the intermediate format files before building a .db design.
During this process, Elaborate determines whether it has the necessary synthetic
operators to replace the HDL operators, and it also determines correct bus size.
Use Read command is to read designs which are already in .db format.
24
• If use the Read command reads HDL files, the Analyze and Elaborate functions
are combined. However, Read does not carry the certain design checking that
Analyze and Elaborate do.
• These commands open dialog forms are equivalent to the Read or Analyze or
Elaborate command-line options.
In this paper, use the Analyze and Elaborate forms to read in the VHDL/Verilog designs.
It does not matter if the HDL coding is behavioral or structure style. Behavioral code can
be synthesized directly. Using the Hierarchy -> Uniquify form, structure code can also be
synthesized.
Open the File -> Analyze -> Analyze Designs form and click the Add button to add the
design file. Notice the file list order and make the file with the top-level entity/module in
the last position of the file list. Show in the following figure:
Click the OK button whey ready. Then open the File->Elaborate -> Elaborate Designs
form and select WORK in the Library box. Choose the toppest-level entity/module name
in the Design box. Show in the following figure:
25
Click the OK button whey ready. An icon design will appear in the main window as
showed in the following figure:
26
3.2 Compile Design
Design Vision allows running a script of commands. Typing as the follows in the console:
design_vision-t>source msdap.tcl
This script file includes the clocks specification. Open the Design->Compile Design from
the menu bar and make the entries as in the following figure:
Click the OK button whey ready. It will cost about 10 minutes. The report window will
provide a transcript of the mapping session as Synopsys converts the behavioral-level
design into a gate-level netlist. When the mapping session is complete, click the
Schematic -> New Design Schematic View and show in the following figure:
27
This schematic view is too big to view clearly. Here, apply a two-bit full adder which is a
part of the MSDAP design but is much simpler to demonstrate the schematic view and
critical path function which will be performed next. This example written by VHDL and
Verilog are as follows:
VHDL Verilog
library IEEE; module Full_Adder_2bit_Hz_v (a, b, Cin, Sum);
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all; input [1:0] a, b;
input Cin;
ENTITY Full_Adder_2bit_Hz_vhd IS output [2:0] Sum;
port(a, b: IN std_logic_vector(1 downto 0);
Cin : IN std_logic; assign Sum = a + b + Cin;
Sum : OUT std_logic_vector(2 downto 0));
END Full_Adder_2bit_Hz_vhd; endmodule
ARCHITECTURE Behaviral OF Full_Adder_2bit_Hz_vhd IS

BEGIN
Sum <= ('0' & a) + b + Cin;
END Behaviral;
28
The schematic view is illustrated in the following figure:
Open the View -> Highlight -> Critical Path form and show in the following figure:
29
3.3 Check Design and Reports
Open the Design -> Check Design form and show in the following figure:
Open the Timing -> Check Timing form and show in the following figure:
There are some reports such as power report. Open the Design -> Report Power form as
30
It is important to save the design, since Design Vision will not remind you when exiting.
Click the File->Save and Design Vision saves the design as a Synopsys database format
file named with the ".db" extension.
Open the File->Save As form to create a Verilog gate-level netlist for the MSDAP design.
Select VERILOG(v) in the Format box from the drop-down menu and select the Save all
designs in hierarchy option. Enter msdap_netlist.v in the File name: box and click the
Save button when ready.
31
Chapter 4 Automatic Placement and Routing
Cadence Encounter goes far beyond Silicon Ensemble. It offers a single cockpit for the
entire physical implementation flow. Although some tools are run as external binaries
(e.g. NanoRoute), the user never has to leave the GUI. In addition, the Common Timing
Engine is integrated into Encounter, allowing for timing analysis every step of the way.
4.1 Set up Cadence Encounter
The following is the instruction to setup and use the Encounter design tool. There are
three steps to set up the work directory.
(1) Copy the msdap_netlist.v generated by Synopsys Design Vision to the verilog
directory.
(2) Login and register to the website at http://learning .cadence.com (Learning
Management System) and download the Artisan TSMC 0.18 um (micron)
library. The library is listed under products for Digital IC Design and look for
Encounter Silicon Virtual Prototyping (Flat and Hierarchical) - v4.1 Tutorial.
There is no charge for the library but an Artisan License Agreement must be
accepted.
(3) After downloading the library tar file, move the tar file to the work directory,
and uncompress the tar file. Now there are four new sub directories in the work
directory and they are captable, cdb, lef and lib.
The work directory is complete by copying the design file, downloading the Artisan
TSMC library and compressing the library files. Now it is ready to start an Encounter
session with an UNIX command:
>EE6306>encounter
(Typing "encounter &" does not work.)
32
The UNIX window (shell tool, xmanager, or etc.) to start the Encounter session is called
the Encounter console. This is where to enter all Encounter text commands and where the
software displays messages. When a session is active, this console displays the prompt:
encounter> and the Encounter main window displays as showed in the following figure:
Encounter General Mouse Usage:

(1) Left Mouse Button (LMB)
• Click: Select/Highlights an object
• Shift + Click: Selects or deselects an additional object
• Double Click: Opens the Attribute Editor Form
• Moving and reshaping objects: first click the starting point then
click the ending point.
(2) Middle Mouse Button (MMB): Display context pop-up menu
33
(3) Right Mouse Button (RMB)

• Click-and-Drag: Zoom-in the display
• Shift + Click-and-Drag: Pan display
Encounter General Binding Keys

Key Action Description
b Bind Key Display the Binding Key Form
f Fit Display Zoom the display to fit the core area
g Group Move up the hierarchy on the highlighted instance
G Ungroup Move down the hierarchy on the highlighted instance
k Ruler Create a ruler
K Ruler Remove last ruler displayed
q Attribute Display the object attribute editor form on selected object
v View DB View the attributes of highlighted object
U Redo Return the design to state to last Undo command
u Undo Return the design to state to previous command
z Zoom-in Zoom in the display, 2x
Z Zoom-out Zoom out the display, 2x
Arrows Pans Pan the display in direction of arrow
Control H/V move Allow horizontal or vertical move of an object
Shift Selects Allow multiple selections and de-selections of objects
Space bar Focus Change the focus of stacked objects
Encounter Auto Query (Q) Binding Keys

Key Action Description
n Focus Change the focus of stacked objects
p Focus Change the focus of previous stacked object
F2 Print Print object information in the Encounter console
Encounter Edit Route Form Binding Keys

Key + Mouse Action Description
Esc End End the drawing mode for creating special route
Delete Delete Remove last point/segment
Arrows Move Move the current segment in direction of arrow
Encounter Binding Key Customization: To display or change the Bind Keys, traverse the
Menu: Design -> Preference and on the Design tab/page, click the Binding Key button.
This displays the Binding Key form. The b-key will also open this form.
Encounter help is available and is displayed by an internet browser. Click the left mouse
button (LMB) on the Help menu to display the Encounter product documentation.
34
Context sensitive help is done by clicking LMB on the Help button in the individual
forms to display the related Encounter User Guide page.
Encounter Command help is available by using the man command when typing:
encounter>man commandName or encounter>help keyword
A list of commands displays pertaining on the keyword:
Help Keywords
analysis clock domain group place scan
browser crosstalk eco hier preference sdf
buffer cts filter import power select
bump delay fix load restore snap
check design floorplan noise route timing
clear display footprint partition save verify
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4.2 Import the Design
To prepare a design for Encounter, simply output a gate-level verilog netlist from the
synthesis tool such as Synopsys Design Vision (Design Compiler) or Cadence Virtuoso.
In addition, for a timing driven flow also create a constraints file both in Design Vision or
Cadence Virtuoso. Both the names of the netlist and constraint file, as well as all library
files are summarized in msdap.conf. Using a .conf file is the perfect way to organize the
many parts that make up a design. And the bulk of the conf file will be constant for a
particular cell library.
The Design Import form is used to load the Verilog netlist, physical libraries, process
technology libraries, timing libraries and timing constraints. Other important items are
also loaded during design import and they are contained in the five pages of the Design
Import form. Open the Design -> Design Import form and make the following entries:
36
Complete the Design page as the above figure. The file names with wild card character (*)
is allowed.
Select one of the following options to specify the top cell:

❑ Auto Assign (Default): Automatically extracts the top cell name from the
netlist, provided the netlist contains only one design.
❑ By User: Specifies the name of the top cell when a netlist contains more than
one design (more than one top design name). The top cell name specified is the
design the software imports and processes.
Timing library files contain timing information for all of the standard cells, blocks and
I/O pad cells in ASCII format. The Encounter software reads Timing Library Format
(TLF) files or Synopsys Technology Library format files (.lib).
37
The technology file "Library Exchange Format (LEF)" provides the software with design
rules for placement and routing, and interconnect resistance and capacitance data for
generating RC values and wireload models for the design. The technology file also
contains process information for the metal interconnect layers, including metal thickness,
metal resistance, and line-to-line capacitance values of metal layers, for determining
coupling capacitance. If you want to add other LEF files, enter the names of the files on
the LEF Files box. Specify the technology LEF file first, then specify the standard cell
LEF and block LEF in any order. The LEF file provides technology information, such as
metal layer and via layer information and via generation rules, which is used in the Add
Rings and Add Stripes forms. The router also uses the technology information contained
in the LEF file. If a cell is defined multiple times, Encounter reads the geometry
information only from the first definition. For subsequent definitions, Encounter reads the
antenna information only.
Do not click the OK button yet. Click the Core Spec Default tab of the Design Import
form to only view the core related design default values as showed in the following figure:
Next, click the Timing tab and make the entries as in the following figure:
38
View the delay calculation and RC extraction scaling default values. Click the Power tab
to add the power and ground net names for the purpose of creating power and ground
rings and stripes:
Last, complete the miscellaneous page to add the CeltIC DB (cdB) noise library. This
library is required to run CeltIC crosstalk analysis. Click the Misc. tab and make the
entries as in the following figure:
39
The Design Import form is used not only to import the Verilog netlist but also import the
physical libraries, process technology rules, timing libraries, and timing constraint file.
These libraries and files are needed to perform design prototyping. Click the Save button
to save a configuration file: msdap.conf to for future use. Click the OK button and view
the imported design:
40
Viewing the imported design:

• First, get to know the Toolbar widgets. The Toolbar is the row of widgets directly
under the Menu. To see what each widget is, slowly move the cursor over each
widget to display their labels. For example, the folder widget on the far left side is
the Design Import form. Click LMB this widget and the Design Import form
opens. Other useful widgets are zooming, redrawing, traversing the design
hierarchy, undoing, redoing, and the Design Browser.
• Now, click the Floorplan view widget in the left Views toolbar, zoom out by
clicking LMB the Zoom Out widget (magnify glass with minus sign) in the
Toolbar (or enter the Shift + z keys). The six pink colored objects on the left side
of the core area are the top-level modules from the imported Verilog netlist in the
41
design. The core area appears in the Design Display Area after a design is
imported and the size core area can be change by using the Floorplan -> Specify
Floorplan form. The IO pads are located outside of the core area.
• Click LMB on the one of pink colored top-level modules. This selects a module.
Note the blue color connection fly-lines. The blue fly-lines display the number of
connections between the selected module and other instance such as other
modules. Now, click LMB the Hierarchy Down widget in the Toolbar or enter the
G-key (ungroup). Note that there may be more submodules displayed. There may
be a total of more than six submodules under MSDAP and of them, six are large
enough to display in the beginning. This can be also viewed in the Design
Browser. To display all submodules, change the value of Min. Floorplan Module
Size to 1 in the Design page of the Design -> Preference form. Note that any
submodule containing at least one block, these submodules will always display no
matter what level of the hierarchy. To traverse further down the hierarchy of a
submodule, select the submodule (LMB) and entering the G-key. To traverse back
up the hierarchy, click the Hierarchy Up widget in the Toolbar or enter the g-key
(group).
• Now, double click on one of the blocks to view the block’s properties. Remember
that each floorplan object has properties and these properties can be changed in
their Attribute Editor form.
At times there is a need to pre-place submodules in the floorplan rather than the top-level
module. In the above exercise, it demonstrates graphically how to traverse down a
module’s hierarchy so the submodule can be displayed and then floorplanned (guided
into the core area).
Using the Design Browser:

• There are two ways to open by opening the Tools -> Design Browser form or the
No. 5 widget from the right in the toolbar.
• In the Design Browser form, note the statistics for the MSDAP module. Now,
click on (+) sign next to Modules to expand down to the next level of hierarchy,
42
and so on. Traverse down the hierarchy until either the leaf cell or a block is
reached. Do the same to the plus sign (+) in front of Terms to view the 13
terminals.
• If want to find or highlight a net name, notice the stepper button: Instance. To
find a net, just enter the net name and change the stepper selection to Net.
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4.3 Floorplan
Open the Floorplan -> Specify Floorplan form to set the core box, IO box and die box
sizes. Under the section of Core Margins by: ♦Core to IO Boundary, enter 100 four times
in the Core to Left: Core to Right: Core to Top: Core to Bottom: boxes. This moves the
IO pads 100 microns from the outside edge of the core box and this sets the IO box. Now
the die box size is set by the height of the IO pad instances. Make sure to change the
Core’s Aspect Ratio (H/W) (height/width) close to 1.0 and click the Apply button. Make
the entries as in the following figure:
44
Click the OK button when ready. Show in the following figure:
Get to know the floorplan widgets under the Tools (left side of the Encounter form) by
displaying the labels of each widgets/tools. This is done by slowly moving the cursor
over each widget to display their labels. Note that some labels display a letter in
apprentices (). The letter represents the binding key.
Moving objects:
• Under the Tools (left side of the Encounter form), click LMB on the
Move/Resize/Reshape (R) widget to start moving the module guide into the core
area. Moving is done by a two-step clicking LMB on the module guide. The first
click (and then release) starts the move of the module and as the module is
45
dragged, a ghost and fly-lines display. At this point zoom-in or out, or pan the
design. The second click ends the move. To control moving an object only in the
horizontal or vertical direction, press the Ctrl-key.
• The Move/Resize/Reshape widget is used to reshape a module guide, say to a
rectangular shape. To reshape a module guide and to keep the area constant, go to
the Design -> Preference form and click on the Design tab. Select the Maintain
Area option. Also, use the Move/Resize/Reshape widget to move a block into the
core area.
• When moving multiple floorplan objects, the Shift-key is used. First, click and
hold the Shift-key and click the LMB on each object to be selected. Next, click
the Move/Resize/Reshape widget and click the LMB on one of the selected object
to start the move. To deselect an object, click and hold the Shift-key and then
click on the object to be deselected.
Each floorplan object has properties and these properties can be viewed and edited. The
Attribute Editor can be opened several ways: (1) Double-click an object with the LMB,
(2) Select/highlight the object and enter the q-key, and (3) Select/highlight the object and
click the MMB and display a pop-up menu. To open the Attribute Editor on a nested
floorplan object, first click the LMB directly over the object, use the Space Bar-key to
traverse the objects, once the desired object is selected, enter the q-key.
Designing a rectilinear (No.6 widget on the second column) module, fence, or region:
• Move one of the submodules into the core area. To create a corner cut, place the
cursor at the corner of the submodule so the cursor changes to an L-shape. Now,
hold down the Ctrl-key plus click LMB and drag the corner. To create a slot cut,
move the cursor to an edge so the cursor changes to a bar. Now, do the Ctrl-key
plus click LMB.
• To change the submodule to a fence, click MMB to display a pop-up menu. Select
the Attribute Editor. Now use the Constraint Type button to the change Guide to
Fence. After clicking the OK button, the color of the submodule changed from
pink to orange. See fence example in the following figure:
46
TU vs. EU values:
• The TU (Target Utilization) value represents the physical design size (area of the
module, fence, or region) and is a rough estimation, since only the module’s child
standard cells and blocks are calculated. The use of the TU value is to judge the
area size while resizing or reshaping a module. The initial TU value is calculated
during design import. Resizing or reshaping a module changes the TU value. This
new calculated value is displayed immediately.
• The EU (Effective Utilization) value represents placement utilization for the all
standard cells and blocks plus all floorplan objects, such as placement blockage,
routing blockage, density screen, and partition objects. EU value also includes
non-child standard cells and blocks pre-placed inside a fence or region. To display
the EU value for a fence or region, click the Display/Calculate Effective
Utilization % button in the Toolbar. The EU value calculation and display is done
on-demand, since this calculation is time consuming for very large designs. After
designing your fences and regions, it is very important to update the EU values on
the fences and regions before running Amoeba Placement. The EU value must
never be greater than 100%, since greater than 100% means the fence or region is
physically too small and the design cannot fit.
47
Floorplan objects:
• Creating floorplan objects – Use the Tool widgets to create floorplan objects such
as Placement Blockages, Partial Placement Blockage, and Route Blockages. After
creating the objects, click MMB on several of these created objects to view their
properties or use the q-key after highlighting the object. This form allows
changing their properties and save the property changes. For example, once a
Partial Placement Blockage object is created, open the Attribute Editor form to
change the Blockage Percentage to another value, other than the default value of
50%.
• Clearing floorplan objects - Floorplan objects can be removed from the core area
by using the Floorplan -> Clear Floorplan form and this form has several
clearing categories and options.
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4.4 Plan Power/Ground Rings and Stripes
Before designing any power/ground rings or stripes, we must assign the global nets of
power and ground for the entire design, and this is done with the Floorplan -> Global
Net Connections form. From the netlist, the power pins, tie high pins, and tie low pins
need to be connected to power and ground nets. Also, from the LEF file, the vdd! and gnd!
ring pins need to be connected to power and ground nets. There are six sets of entries
required and they are shown in the table below:
Entry Set 1 Set 2 Set 3 Set 4 Set 5 Set 6

Pins VDD vdd! VSS gnd! Not selected Not selected
In Instance * * * * Not selected Not selected
Tie High Not selected Not selected Not selected Not selected Not selected Selected
Tie Low Not selected Not selected Not selected Not selected Selected Not selected
Apply All Selected Selected Selected Selected Selected Selected
To Global net VDD VDD VSS VSS VSS VDD
For each set, fill in the required values and click the Add to List button. When all six sets
appear in the Connection List, click the Apply button. Then click the Check button and if
there is no warning message, click the Close button. The completed form looks like the
following figure:
49
Now we are ready to do power planning which is to create power and ground ring around
the core area and around one of the blocks. Power and ground stripes are also added.
There are the Floorplan -> Power Planning -> Add Rings and Floorplan -> Power
Planning -> Add Stripes forms but they will not be used. The Automatic Power Planner
has two forms and the instructions to complete these forms are split into three steps:
(1) Open the Floorplan -> Power Planning -> Edit Template form, click the Wizard
On button and this displays a context sensitive flow usage diagram. Click the IP
Block tab at the top to display the page. Although in the MSDAP design, we do not
need PLL which is defined as a hard macro in the imported .lef file.
(a) Select pllclk block in the IP Block List. This block needs power rings. The
other three blocks are class R and have power ring pins. In the Block Ring
section below the list, select ■Require block ring option and deselect
■Allow sharing with others option. Note the icon in Illustration.
(b) Select ■Offset option, enter 1.0 then select ■M6/M5 option and enter 8.0
(c) Click the Set button. This bolds the pllclk in the IP Block List which means
the settings for the pllclk block is committed.
(d) Enter block in the IP Library Template Name. Click the Save button and
this saves the template for the block. Show in the following figure:
50
(2) Click the Design tab at the top of the form.

(a) Select ■Ring, ■M6/M5, ■Stripe, ■M6 and note the icon in Illustration.
(b) There is a Target Connection control preference setting and this sets the
control of created stripes by allowing jogging and/or layer changes. Select
both control selections and note the Illustration. When both selections are
used, a preference can be set.
(c) Enter example in the Region Name, choose block for the IP Library
Template. Then click the Add/Modify button.
(d) Enter top in the Design Template Library Name and click the Save button.
Show in the following figure:
51
(3) Click the Instantiate button at the bottom of the form and this will open the form
to specify the chip-level ring and stripe parameters.
(a) In the Ring section, leave the Wire Group deselected since only one single
set/group of power rings is required. Change Metal6-Metal5 Width to 8.0
(b) In the Stripe section, leave the Wire Group deselected since only one single
set/group of power stripes is required. Change Metal6 Width to 8.0, Spacing
to 1.0, Offset to 100 and Pitch to 100. Show in the following figure:
52
Click the OK button when ready. Now the completed power/ground rings and stripes
created for the design are showed in the following figure:
53
Creating multiple rings and stripes:

• Groups of power and ground rings can be created around the core area or around a
block. To create multiple core power and ground rings, select Wire Group and
enter the number of bits in the Instantiation form. To create multiple block power
and ground rings, enter the number of bits in the Block page of the Edit Power
plan Template. Note that the VSS ring is the outside ring since VSS is entered first
in the Nets entry box in the Instantiation form.
• Groups of power and ground stripes can be created in the core area. To create
multiple core power and ground stripes, enter the number of bits in the
Instantiation form.
54
Creating power and ground rings and stripe does not account for power in this paper. To
run Power Analysis Estimator, in the Instantiation form and in the Power Analysis mode,
select the Total Power option and enter 5 mw. Then click the Update Template
Configuration button. Note the parameters of width and pitch values change.
55
4.5 Route Power/Ground to Power/Ground Pins
To route the remaining power and ground structure, use the Route -> SRoute form. The
SRoute program routes the block pins, pad pins, pad rings, standard cell pins, and
unconnected stripes. Here we will be routing pad pins, and standard cell pins. Make the
following entries:
(1) Click the Basic tab. In the Route section, deselect the ■Block pins and ■Pad rings
option. Show in the following figure:
56
(2) Click the Advanced tab and then open the Extension control from the list. In the
Primary Connection for and under Standard cell pins and stripe section, select
None♦ option. In the Secondary connection/Stop (standard cell pins only) (if the
primary connection fails) section, select Last cell in the row♦ option. Show in the
following figure:
Click the OK button when ready. Now the power and ground rings around the core area
are connected to the power and ground pads, block pins are connected, power rings are
all connected, and standard cell follow pins are connected as showed in the following
figure:
57
58
4.6 Design Rule Check (DRC)
After designing the power and ground, the connections and geometries can be verified by
Design Rule Checker (DRC). These two tools are in the Verify menu. To verify the power
and ground connectivity, make the following entries:
(1) Open the Verify -> Verify Connectivity form and select ♦Special only option. Show
in the flowing figure:
Click the OK button when ready. There are violations markers because of antenna
warnings and these warning can be ignored since these are power and ground. The result
is showed in the flowing figure:
59
(2) Open the Verify -> Verify Geometry form and use the defaults which do not check
Geometry Antenna. Show in the flowing figure:
Click the OK button when ready. The result is showed in the flowing figure:
60
There are two ways to identify violation markers: (1) Click the Q button at the bottom in
the Encounter window which enables auto query of objects. Moving the cursor exactly on
top of a violation marker displays the violation type in the bottom selected object text box.
Zoom-in very closely to have the violation type displayed. (2) Open the Verify ->
Violation Browser to display the violations.
The violation markers are cleared using Verify -> Clear Violation menu item. Clear the
DRC markers if any.
Editing routes:
• Using the Route -> Edit Route form (or enter the e-key) can also interactively
create or edit stripes. To use this form, first change the metal layers and enter the
route width and spacing, and click the Nets tab and enter the power/ground net
names, such as VDD and VSS. Click the Pencil button (in Tools area) to start
drawing the power/ground routes and each click allows a change in direction.
61
Double-click the LMB in end the route drawing. The Backspace-key removes the
most recent (only once) drawn segment. The Undo widget in the Tool bar
completely removes the last drawn route.
• Routes can be moved by selecting the segment(s), and then selecting the Move
Wires widget in the Tools Area. The moving of the selected segment is done by
three mouse clicks (LMB). The first click (cursor is circular shape) selects the
segment, the second click starts the interactive move, and third click places the
segment. The Undo widget in the Tool bar undoes the last move.
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4.7 Amoeba Placement
Open the Placement Blockage form to specify that no standard cell will be placed under
power and ground stripes. This is to avoid routing congestion that may occur under the
power and ground stripes. Choose Place -> Specify -> Placement Blockage form and
select ■M2 ~ M6 options. Click the OK button when ready. Show in the flowing figure:
Use the Place -> Place form to run Amoeba placement program and use the defaults.
Click the OK button when ready. Show in the flowing figure:
63
Once the placement program is done, view the placed design in the Amoeba and Physical
views. Note the placed standard cells in the Physical view. The following figure is in the
Physical view:
64
The following figure is in the Amoeba view:
65
4.8 Trial Route
We need to route the remaining nets of the design and Trial Route is used. Trial Route is
a combination of global routing and track assignment and correlates well to detail routers.
Here Trial Route will be run twice. The first run will demonstrate route congestion by
limiting the number of metal routing layers to three instead of six layers. The second run
will use all six metal layers to complete the prototyping of the design.
Open the Route -> Trial Route form and change Max. Route Layer to 3. Show in the
following figure:
Click the OK button when ready and the physical view is showed in the following figure:
66
Once trial route completes, there are two things to look for:
(1) First, a visual view of route congestion. This is done looking for the red color
diamond shapes. If the red diamond markers can be located, zoom-in to view the
congestion markers. There are two sets of numbers. The first set (#-top/#-bottom)
is for the vertical connection where #-top is the required routes and #-bottom is the
available routes. The second set of numbers is for the horizontal connections.
These diamond shaped congestion locators represent an average in the area.
Another display of congestion is to select the visibility of HCongest and Vcongest
in the color display option area. These two congestion makers are color coded, and
dark blue represents low congestion and red high congestion.
67
(2) Second, view the log file or the Encounter console for the congestion table
produced by trial route. The label of the table is Congestion distribution. Just
before this table, look for the last line with label Overflow. If both numbers in the
(#% H) and (#% V) are less than 0.5%, then this design is good for any detail
router. The less than 0.5% is good for three layers of metal and less than 1.0% is
usually good for five or more layers of metal. Show in the following figure:
Now run the Trial Route with six metal routing layers. Open the Route -> Trial Route
form and change Max. Route Layer to 6. Show in the following figure:
68
Click the OK button when ready. View the log file or the Encounter console for the
congestion table produced by trial route:
69
The Physical view is showed in the following figure:
After Trial Route, see connection fly-lines in the Floorplan view, but in the Amoeba view,
the routed interconnections can be displayed. This is done by double clicking a module or
block (this also opens the Attribute Editor form). More interestingly, this double clicking
can be used in the Physical view. The actual routed interconnect for specific nets can be
viewed. Zoom-in to see the connections.
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4.9 Timing Analysis and Optimization
4.9.1 RC Exaction
Extracting RC data is required to perform delay calculation, timing analysis and power
analysis. Since the design is still being prototype, the native Encounter RC extraction is
the default. The RC extraction mode can be changed by the Timing -> Specify Analysis
Condition -> Specify RC Extraction Mode form and use the Default Mode.
While extracting RC data, note in the form the various simulation format files that can be
generated. The files are written to the current work directory. The lumped capacitance
values for all the nets in the design are extracted by the Timing -> Extract RC form.
Select simulation formats of interest. Click the OK button when ready. Show in the
following figure:
Only after extracting RC, Wire load models can be generated at every level of the
hierarchy and this is done by using the Timing -> Generate Wireload Model form. Select
♦Cell Based Wireload Model or ♦Instance Based Wireload Model option. Show in the
following figure:
71
Click the OK button when ready. Several output files are generated. There are six
wireload files created in the current work directory. There are two data files:
MSDAP.wl.hier and MSDAP.wl.flat. There are two Design Compiler load script files:
MSDAP.wl.hier.scr and MSDAP.wl.flat.scr. There are two BuildGates and RTL Compiler
load script files: MSDAP.hier.sdc and MSDAP.flat.sdc.
The delays are calculated for each wire (routes) and the delays include instance delay. To
see what delay default is used for large nets, open the Timing page of Design -> Design
Import. Open the Timing -> Calculate Delay form and select ■Ideal Clock option if clock
tree synthesis was not run. The output file is in SDF format. Show in the following figure:
Click the OK button and the result is showed in the following picture:
72
The Calculate Delay mode is defaulted to Encounter. This default mode can be change by
the Timing -> Specify Analysis Condition -> Specify Delay Calculation Mode form
The maximum (slow) and minimum (fast) timing libraries were loaded during design
import and there are temperature, process, and voltage conditions that are modeled. Since
we are analyzing for both setup timing and hold timing of the design, the slow and fast
process conditions are selected by default. To view the default operating conditions, open
the Timing -> Specify Analysis Condition -> Specify Operating Condition/PVT form.
Note the default selection for both the Max and Min tabs showed in the following figures:
73
Click the OK button and view the Encounter console for the slow and fast operating
conditions. These conditions are the process (P), temperature (T), voltage (V) values.
74
4.9.2 Setup Timing
Static timing analysis can be run after extracting RC. The result of running setup timing
analysis is a timing graph from which several kinds of timing reports are generated (i.e.,
slack report and detail timing report). The timing analysis is run for setup timing. Since
clock tree synthesis was not run, an ideal clock is used and the ideal clock transition
delay value is 0.1 ps (from the Timing page of the Design Import form). Open the Timing
-> Timing Analysis form and select ♦Setup Timing Analysis, ♦No Skew Analysis and ♦No
Clock Tree option which is default. Show in the following figure:
75
The msdap.sdc imported from the Design Import form is needed. Click the OK button
when ready. Show in the following figure:
When timing analysis is done, the slack report is viewed by opening the Timing ->
Timing Debug -> Slack Browser form. Select MSDAP.slk and click the Open button
when ready. Note that there are a couple of paths that have negative slack value. The
critical path in the design is the path with the worst negative slack. Also, a detailed
timing report file MSDAP.tarpt is generated and it lists all the instances in the path.
Another nice tool is the slack histogram. It visually displays the slacks computed during
timing analysis. Open the Timing -> Timing Debug -> Slack Browser form, select
MSDAP.slk and Report Non Violating to see all paths in the design. Click the Apply
button. There are two distributions: a critical one and a larger one with non-critical paths.
To graphically highlight a path reported in the Slack Browser, make sure the Physical
view is selected, and then Double-click on a path in the Slack Browser. A path is
highlighted in the schematic viewer.
76
Once the setup violating paths are identified, optimization is run to fix the violating paths
by buffer insertion, inverter insertion, instance resizing (including flip-flops), and
instance cloning. Also, non timing critical instances are downsized. The Timing
Optimization is run to fix setup time. In the case where there is no reported timing
violation, Timing Optimization can be still run by specifying an aggressive target slack
value. Open the Timing -> Optimization form and use the default settings. Show in the
following figure:
Click the OK button when ready. Timing Optimization will run through several iterations
and when timing is met, the program will stop. It will cost about five minutes. Several
timing reports are generated in the timingReports directory. Make sure setup timing is
met: no negative slack values. Show in the following figure:
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4.9.3 Clock Tree Synthesis (CTS)
Clock Tree Synthesis is run after fixing setup timing violations with Optimization, but
first the clock tree specification file must be created. The design clock information is
contained in the timing constraint file. To create the clock tree specification file, open the
Clock -> Create Clock Tree Spec form, and enter Buffer Footprint: BUFX1 and Inverter
Footprint: INVX1 as showed in the following figure:
Click the OK button when ready. Open the Clock -> Specify Clock Tree form, select the
MSDAP.ctstch and show in the following figure:
Click the OK button when ready. Open the Clock -> Synthesis Clock Tree form, use the
default settings and show in the following figure:
78
Click the OK button when ready. It will cost about ten minutes. Open the Clock ->
Display -> Display Clock Tree form. In the Route Selection section, select ♦Pre-Route.
In the Display Selection Section, select ♦Display Clock Tree option and select ♦All Level
option. Show in the following figure:
79
Click the Apply button when ready. Do not click the OK button yet. The Physical view is
80
Next, select ♦Display Clock Phase Delay option. Show in the following figure:
81
Click the OK button when ready. The Physical view is showed in the following figure:
Note the multi-color clock instances, which represent the delay in the clock path. Several
clock report file are generated and they are in the created MSDAP_cts directory. The
ASCII text version is MSDAP_cts/MSDAP_cts.ctsrpt. Note the color coding used to
represent the delayed clock instances. To display a gated clock structure such as SClock,
the All Level option must be selected.
There is also a Clock -> Clock Tree Browser form that can be used to display the
schematic of the synthesized clock tree. Click the Select button to choose one of the
clocks in the Specified Clock List. This form is showed in the following figure:
82
Click the OK button when ready. Then the clock schematic displays in the following
figure:
To clear the display, use the Clock -> Display -> Clear Clock Tree Display menu item.
83
4.9.4 Hold Timing
Before running hold time analysis, Trial Route and extract RC must be run. Open the
Route -> Trial Route form and show in the following figure:
Click the OK button when ready. Open the Timing -> Extract RC form and click the OK
button when ready. Show in the following figure:
At this point of the design, timing optimization was run to fix setup timing and then the
clocks are synthesized. Now timing analysis is run check the hold timing with skew
analysis. Open the Timing -> Timing Analysis form, select ♦Hold Time Analysis option
and ♦Skew Analysis option since the clock tree was synthesized. Select ♦Clock Tree Exist
option. Enter Slack Report File: MSDAP.hold.slk and enter Detailed Violation Report
File: MSDAP.hold.tarpt. Use the remaining defaults and show in the following figure:
84
85
When hold timing analysis is done, the slack report is viewed by opening Timing ->
Timing Debug -> Slack Browser form. Select MSDAP.hold.slk and click the Open button
when ready. The paths with negative slack value have hold time violations. Also, a
detailed timing report file MSDAP.hold.tarpt is generated and it lists all the instances in
the path.
Timing Optimization is run to fix the hold time violating paths by delay insertion. This
can be done by typing Encounter commands in the Encounter console. Enter the
following commands in the Encounter Console:
encounter>optDesign –postCTS -hold
All hold time violations should be fixed. It may need to run again. View the slack report
file in the timingReports directory. This is to make sure hold time is met: no negative
slack values. The result is showed in the following figure:
Also, a slack report can be generated by using the Timing -> Report -> Timing Slacks
form.
At this point in prototyping this design, it has met setup and hold timing constraints, but
timing is really not closed on a design unless crosstalk is prevented and then analyzed.
That is what to do next.
86
4.10 CeltIC (Crosstalk) Signal Integrity (SI)
Timing is not closed on a design unless crosstalk is prevented, analyzed, and then fixed.
To really achieve the above, the design must be run with global and detail routing, and
NanoRoute is used. When running NanoRoute, be sure to select both the Timing Driven
and SI Driven (Signal Integrity) options in the NanoRoute form. These options are
important in helping to close timing and preventing crosstalk.
Now use NanoRoute for global and detail routing with the SI option. It is an extremely
powerful router and replaces the older WRoute tool. Open the Route -> NanoRoute form,
select ■Fix Antenna, ■Timing Driven and ■SI Driven options. Use the remaining defaults
and show in the following figure:
87
Click the OK button when ready. It will cost about 20 minutes. Show in the following
figure:
Running NanoRoute with the SI Driven option requires the capacitance table file, and this
file was read in during design import. Since the design has been detail routed, both the
setup and hold timing should be checked and all timing violations be fixed. This means
that Timing Optimization must be run again as the first part of NanoRoute as we did
earlier to close timing with routing from Trial Route. Then we will continue and analyze
crosstalk.
Now we can run post-route optimization. This allows Encounter to optimize the design
based on actual wires. Any modified net will automatically be re-routed by Nanoroute.
88
Open the Timing -> Optimization form and select postRoute option. Show in the
following figure:
Now we have timing closure, with no violating path left as showed in the following
figure:
The detail RC (coupling capacitances) extraction is run before the crosstalk analysis. This
is done by opening the Timing -> Specify Analysis Condition -> Specify RC Extraction
Mode form. Select ♦Detail option and use the remaining defaults. Click the OK button
when ready. Show in the following figure:
89
The Encounter native CeltIC is used to perform crosstalk analysis. Open the SI -> Run
CeltIC Crosstalk Analysis form, select Mode: ♦Native and Process: ♦180nm option. Use
the remaining defaults. Show in the following figure:
Click the OK button when ready. It will cost about 10 minutes. View the log file for
reports of noisy nets, and there should be only a few nets. A celtic directory is created
90
that contains file for displaying and fixing these noisy nets. No noise net is showed in the
following figure:
The CeltIC DB (cdB) noise library is needed to run crosstalk analysis. This cdB file
contains the standard cell noise, and for the blocks, a user defined noise model file was
also read-in during design import.
91
Displaying and reporting noise nets are done by opening the SI -> Display Noise Net
form. Use the default which is choosing the CeltIC ECO file. Show in the following
figure:
Click the OK button when ready. Now, the Display Noise Net form displays. To display a
noisy net (victim), double-click on one of the nets, and this highlights and zooms in on
the net. From this form, report the coupling capacitance coupling ratio between the victim
net by click the Report Coupling Cap button, and the aggressor net. Also report and
browse the aggressor net by clicking the Browse Aggressor button.
92
Opening the SI -> Fix Crosstalk form, select Mode: ♦Incremental and use the remaining
defaults which use NanoRoute and CeltIC in incremental mode. Show in the following
figure:
Click the OK button when ready. The fixing of crosstalk also includes timing. View the
log file which contains information on the remaining violating nets to be fixed and the
worst slack timing value with and without coupling. There should be no crosstalk
violating nets.
93
4.11 Power Analysis
Be sure the correct timing model is loaded before running power analysis. Power analysis
can be run anytime after extracting RC in the design flow. The Power Analysis tool can
be easily set up to run in Statistical mode. The clock rates and net toggle probabilities for
the two clock domains are specified individually while running power analysis. Further,
decide when to run power analysis, before or after running clock tree synthesis or before
or after running timing optimization fixing setup or hold time.
The power reference points must be created on the power rings around the core area. In
the Physical view and open the Power -> Edit Pad Location form which is showed in the
following figure:
To add VDD power reference points next to the VDD pads, this can be easily done by
1. Click one VDD power reference point next to the VDD pads, check the Auto
Query field at bottom of the Encounter window and make sure that this point is
connected with VDD net and which metal layer it is located.
94
2. Click the Get Coord button, then click on the location near the VDD pad then
select the metal layer. Click the Add button.
3. Now see a yellow colored circle representing the VDD reference point. Complete
adding the four VDD pad reference points. Click the Save button to load the VDD
pad file MSDAP.vdd.pp. Finally, See the four yellow colored circle pads in the
Physical view showed in the following figure:
Running Statistical Power Analysis: A more realistic power analysis for this design is to
set a toggle value for nets in each clock domain and these clocks are defined in the timing
constraint file. To run in this clock domain mode, the Edit Net Toggle Probability and
Power Analysis Statistical Mode must be completed.
95
First, open the Power -> Edit Net Toggle Probability form and click the Get Clock button
and note that two clocks appear. Select one clock at a time, click the Edit button and enter
the Net Toggle Probability: 0.2 which means 20%. Then click the Add/Replace button.
When done editing both clocks, click the Save button to save your entries to a file
MSDAP.tg.
Second, open the Power -> Power Analysis -> Statistical form. If run it not after
extractRC or there is no system enough memory, Power Analysis menu will be gray and
it can not be accessed. Enter VDD in the Net Names box. Select either pre-CTS clock or
post-CTS clock depending on whether clock tree synthesis was run. Enter the Net Toggle
Probability File: MSDAP.tg. No file entry is needed for Instance Power Data. In the Rail
Analysis section, enter MSDAP.vdd.pp in the Pad Location Files box and select Layout
and Average since we have power / ground strips and have run SRoute. Last, enter a
Report File: msdap.power before clicking the OK button. Now power analysis will run.
96
First, view the power report file or view the Encounter console messages to see the power
supply value, average power dissipation, worst IR drop, and worst EM violation in the
design.
97
Second, to display the IR drop, open the Power -> Display -> Display Rail Analysis
Results form. Enter VDD for the Net Name and select IRD (V) option. Enter an IRD
Threshold value at 0.198 (10 percent of the power supply 1.98v), click the Update filter
range button, and then click the Apply button. Now, the color coded IR drop displays. To
get a more detail and colorful display of the IR drop, change the IRD Threshold value to a
smaller number and click the Update filter range button. This threshold is closer to
reported worst IR drop value. Show in the following figure:
For a better view of the power rails, deselect the Net, and Instance visibility in the color
display area (right side of the Encounter form). To clear the IR drop display, use the
Power -> Display -> Clear Rail Analysis Display menu item.
Besides the power report file, power analysis creates the file instance.power. This file
contains the power dissipation (mWatts) for all instances in the design, and this file is
98
used to customize the instance power by superseding the power from the timing library.
Use Rail Analysis with the instance.power file to run subsequent power analysis, the
analysis runs fast since all the instances’ power is read from this file.
Third, to display the Macro Current Source location, open the Power -> Display ->
Display Macro I Source Location form (I stands for the electric current). Enter VDD for
the Net Name and click the OK button. Now the white colored circle shaped current
sources for the blocks are displayed. These sources represent the current source points at
the power pins (VDD) of the blocks. Show in the following figure:
99
4.12 Reports and Export
The final step is to add filler cells. These are empty cells that provide nwell continuity.
Click the Place -> Filler -> Add Filler form and enter FILL as the Cell Name(s) (in the
TSMC cell library this is the name of the filler cell). The value FILLER will be used as
the prefix for the instance name of each filler cell added. Show in the following figure:
After adding filler, it can be seen that the core area is completely covered with cell
instances in the Physical view.
Open the Verify -> Geometry form and click the OK button. The result will be shown in
the following figure:
100
If there is a violation, open the Verify -> Violation Browser form to see a list of
violations. We can also check the connectivity of the design, i.e. missing or in-complete
routes or floating pins. Open the Verify -> Connectivity and click the OK button.
Click the Tools -> Netlist Stats and show in the following figure:
Open the Tools -> Gate Count Report form and use the defaults as follows:
101
Click the Tools -> Summary Report and the report is showed in the following figure:
The Redraw or Undo function is very weak in the current version of Encounter. We
almost can not count on them. It is a good idea to save the design work as we progress
and the most notable steps are after floorplanning, running placement, running route. It is
better to use the Design -> Save Design form. The menu also allows saving to an
individual file. For an example, the Design -> Save -> Route allows saving the route data
to a file.
Restore the saved work by opening the Design -> Restore Design form in a future
Encounter session.
Open the Design -> Save -> Netlist form and show in the following figure:
102
Click the OK button when ready. Open the Design -> Save -> DEF form to save
MSDAP.def which is used for LVS in Cadence Virtuoso.
Open the Timing -> Calculate Delay form and deselect ■Ideal Clock option since clock
tree synthesis was run. Show in the following figure:
Click the OK button when ready. The output file is MSDAP.sdf which will be needed for
post-simulation with the netlist file MSDAP.v saved above just now.
Open the Design -> Save -> DEF form and use the defaults. Click the OK button. Show
in the following figure:
103
The last step is to export the design to DEF or GDS. This is the format used by Layout
Editors (e.g. Cadence Virtuoso) and IC foundries. It requires a map file, to map layer
names to layer numbers. In this case we use a map file that matches MOSIS layer
numbers. Open the Design -> Save -> GDS form and enter MSDAP.gds in the Output
Stream File box. Use the other defaults and Click the OK button when ready. Show in the
following figure:
104
Chapter 5 Flip Chip Planning
Working a flip chip design involves adding, customizing, and assigning bumps. This
paper involves designing a flip chip with peripheral IO drivers and with bumps over the
die. The IO drivers are placed outside the core design area and the bumps are placed in a
square array over the die. The bump size is 50x50 um and pitch spacing is 100 um.
The process used here is a modified Artisan TSMC 0.18 nm process technology with 2
redistribution (RDL) layers and 6 layers of metal for detail routing, totaling 8 layers of
metal.
105
5.1 Import the Design
Open the Design -> Design Import and make the following entries:
Complete the Design page as the above figure. Do not click the OK button yet. Click the
Core Spec Default tab of the Design Import form to only view the core related design
default values. Next, click the Timing tab and make the entries as in the following figure:
106
View the delay calculation and RC extraction scaling default values. Click the Power tab
to add the power and ground net names for the purpose of creating power and ground
rings and stripes:
107
Last, click the Misc. tab and show in the following figure:
The Design Import form is used not only to import the Verilog netlist but also import the
physical libraries, process technology rules, timing libraries, and timing constraint file.
These libraries and files are needed to perform design prototyping. Click the Save button
to save a configuration file: msdap.conf to for future use. Click OK button and view the
imported design:
108
109
Open the Floorplan -> Specify Floorplan form to set the core box, IO box and die box
sizes. Under the section of Core Margins by: ♦Core to IO Boundary, enter 37 four times
in the Core to Left: Core to Right: Core to Top: Core to Bottom: boxes. This moves the
IO pads 37 microns from the outside edge of the core box and this sets the IO box. Now
the die box size is set by the height of the IO pad instances. Make sure to change the
Core’s Aspect Ratio (H/W) (height/width) close to 1.0 and click the Apply button. Make
the entries as in the following figure:
110
111
5.2 Create Bump Matrix
The bump array needs to be placed in a square pattern across the die. Open the Flip Chip
-> Setup Chip IO form, click the Bump Array tab to expand the page, and view the bump
patterns that can be generated. In the Bump Matrix section, leave the defaults since a full
matrix is required. In the Bump Spacing section, enter 100 in the Bump Pitch - Horizontal:
box and enter 100 in the Vertical: box. In the Edge Spacing section, enter 70 in the DX:
box and enter 68 in the DY: and show in the following figure:
112
Click the OK button when ready. Now, the created bumps are showed in the following
figure:
113
If the bump matrix pattern is not what we want, use the Floorplan -> Clear Floorplan
form to choose the bump pins, and try again to create the bumps. Show in the following
figure:
114
5.3 Assign IO Signals to Bumps
The assumption is that we are in the early development stage and we can freely assign the
signal bump locations.
Assigning signals to bump pins by opening the Flip Chip -> Assign Signals form. In the
Assign to Tiles/Bumps section, select ♦Closest and click the Assign button. Click the
Done button when ready. Show in the following figure:
The bumps with signal assessment are now blue in color. To inspect the relative
closeness of the bumps to each IO driver, open the Flip Chip -> Display Options ->
Signals form. This will display the signal names on each bump (zoomed-in). Show in the
following figure:
115
To view IO signal names and assigned bumps information,

(1) Open the Flip Chip -> Display Options form. The displays are Number, Signal,
Terminal, or Bump Name.
(2) Otherwise, open the Flip Chip -> Assign Signals form to view or make
assignments. First select an IO Signal name in the form, and then observe the
Physical view. The IO driver and bump pair are highlighted in green color. The
form is used to assign a signal to a bump or to unassign a signal to a bump.
116
The bumps that are to be assigned to power are shown in the following figure and the
VDD bumps to be assigned are highlighted with white color outline.
117
5.4 Assign Power/Ground to Bumps
Open the Flip Chip -> Assign Power/Ground Bumps form and select the 11 bumps
highlighted in the above figure using the Shift-key + LMB. In the Bumps/Tiles section,
select ♦Selected Bumps. In the Power/Ground section, select ♦Power VDD. Click the Set
button when ready. Do not close this form which will be used to add ground later. Show
in the following figure:
118
Now the VDD bumps are red in color and show in the following figure:
Use the same Flip Chip -> Assign Power/Ground Bumps form. In the Bumps/Tiles
section, select ♦Floating Bumps (remaining unassigned bumps). In the Power/Ground
section, select ♦Ground VSS. Click the Set button when ready. Show in the following
figure:
119
Then click the Close button. The VSS bumps are orange-yellow in color. Now, all the
bump pins are assigned. Show in the following figure:
120
5.5 Route IO Signals to Bumps
The connection needs to be routed between the assigned IO driver pin and the bump pin.
This is done with the flip chip router and layers Metal 7 and 8 (RDL layers) are used.
Open the Route -> Flip Chip -> Signal form. In the Net(s) section, select ♦Named and
enter DClock. In the Layer Range Control section, choose Bottom Layer: M7. Select the
■Route width and enter 1.5 and select ■Delete existing routes. Use the remaining defaults.
121
Click the Advanced tab to open the page. In the Shield Routing section, select ■Net: ♦Tie
high. Select ■Width and enter 0.44 and click the Apply button when ready (keep this form
displayed for later use). Show in the following figure:
122
Zoom in to view the shielded clock net between the IO driver and bump. The net is on the
left side of the chip. Show in the following figure:
123
Use the same Route -> Flip Chip -> Signal form and click the Basic tab. In the Net(s)
section, ♦Named changes to Reset_n Wake_n and keep others unchanged in this page.
124
Open the Advanced page. In the Shield Routing section, deselect ■Net: and ■Width. In
the Segment Splitting section, select ■Width limit and enter 0.5. Select ■Gap between
split segments and enter 0.46. Click the Apply button when ready (keep this form
displayed for later use). Show in the following figure:
125
Zoom in to view the split nets between the IO drivers and bumps in the following figure:
126
The remaining IO signals are routed to bumps by using the same Route -> Flip Chip ->
Signal form. Click the Default button. In the Layer Range Control section, choose Bottom
Layer: M7. Deselect all options in the Advanced page. Show in the following figure:
127
Click the OK button when ready. Now only the remaining unrouted IO signals are routed
to their bumps. Show in the following figure:
There are two ways to reroute a flip chip signal:

(1) Select/highlight any segment of the net and in the Nets section of the Route -> Flip
Chip -> Signal form, make sure to select the ♦Selected option, and then make sure
the ■Delete existing routes is selected (at the bottom of the form). Rerunning the
flip chip router will reroute this net.
(2) Enter the net name(s) in the ♦Named box, and then make sure the ■Delete existing
routes is selected before running flip chip router.
128
5.6 Plan Power/Ground Rings and Stripes
The procedures and settings of assigning the global nets (Floorplan -> Global Net
Connections) and power planning (Floorplan -> Power Planning -> Edit Template) is
the same as we did in the previous Chapter. The only difference is in the Ring section of
the Instantiation form: change Metal6-Metal5 Offset to 9.0. Show in the following figures:
129
130
The result is showed in the following figure:
131
5.7 Route Power/Ground to the Power/Ground Bumps
The power connections need to be made to the VDD and VSS bumps and this is done in
the Route -> Flip Chip -> Power form. In the Routing Control section, select ■Route
width and enter 8.0 and use the remaining defaults in the Basic page. Show in the
following figure:
132
Click the OK button when ready. Now, all the power bumps are connected to VDD and
VSS stripes as showed in the following figure:
133
The procedures and settings of routing the power and ground pins (Route -> SRoute) is
the same as we did in the previous Chapter. The result is showed in the following figure:
Now it is ready to proceed to do the, DRC (Verify -> Verify Connectivity and Verify ->
Verify Geometry) and placement work as we did in the previous Chapter.
134
References
[1] Zhongnong Jiang, "A Mini Stereo Digital Audio Processor (MSDAP)", 1995.
[2] Zhongnong Jiang, Nan Chen and Dian Zhou, "A Low-Cost and Low-Power Digital
Audio Processor", Proceedings of 28th IEEE Southeastern Symposium on System
Theory, 1996.
[3] AES standard for digital audio — Digital input-output interfacing — Serial
transmission format for two channel linearly represented digital audio data, 2003,
http://www.utdallas.edu/~hua.zhang/EE6306/IO/aes3-2003.pdf
[4] PLCC (PC20/PCG20) package, 2004 Xilinx, Inc.
http://direct.xilinx.com/bvdocs/packages/pc20.pdf
[5] Cadence Design Systems Inc., "Encounter User Guide – Product Version 4.1.5",
May 2005.
[6] Cadence Design Systems Inc., "Encounter Menu Reference – Product Version
4.1.5", May 2005.
[7] Cadence Design Systems Inc., "Encounter Timing Closure Guide – Product
Version 4.1.3", Dec. 2004.
[8] Synopsys Inc., "Design Vision User Guide - v2004.06".
[9] Synopsys Inc., "Design Compiler User Guide - v2004.06".
[10] Synopsys Inc., "Design Compiler Tutorial Using Design Vision - v2004.06".
[11] Synopsys Inc., "Design Compiler Reference Manual: Constraints and Timing -
v2004.06".
[12] Synopsys Inc., "Design Compiler Reference Manual: Optimization and Timing
Analysis - v2004.06".
[13] Synopsys Inc., "Design Compiler Command-Line Interface Guide - v2004.06".
[14] Synopsys Inc., "Using the Synopsys Design Constraints Format Application Note -
v2004.06".
135

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EE6306 ASIC Design

A Mini Stereo Digital Audio Processor (MSDAP) Design

DCLK 2 MSDAP 14 VDDC

4. Automatic Placement and Routing

4.9.1 RC Exaction ………………...........................................…… 71

5. Flip Chip Planning

References ……………………..…………………………………....................…… 135

1.1 Design Flow

HDL Code Design

SDF: (Timing) Standard Delay format

.lef, .lib, .cdB msdap_netlist.v, msdap.io, msdap.sdc

Automatic Placement and Routing

Abstract view MSDAP.def MSDAP_netlist.v, MSDAP.sdf

LVS, RC extraction Post-Simulation

Tapeout / Wafer Foundry Processing

1.2 Chip Information

1.3 Chip Environment

The working environment of the MSDAP chip is illustrated as follows:

Audio data transmitting between ADC/DAC and Controller is embedded in a frame

1.4 Coefficient Format

u16 u15 u14 u13

1.5 I/O Pin

• When Reset is set low, the chip begins to reset.

Notes on Pin Description:

Total: 20 I/O pins

1.6 FSM Design

There are some assumptions:

State 1: Waiting to • In this state, InReady is set high.

State 3: Waiting to • In this state, InReady is still set high.

State Working Sleeping

State Sleeping Working

Mentor Graphics ModelSim can do both functional simulation and post-simulation.

2.2 Setup ModelSim

Run ModelSim, the main window is showed as the following figure:

2.2 Functional Simulation

The Start Simulation form is showed in the following figure:

Click the OK button to begin the post-simulation.

Chapter 3 Logic Synthesis

3.1 Setup Synopsys Design Vision

Now type the following to start Synopsys Design Vision:

3.2 Compile Design

ARCHITECTURE Behaviral OF Full_Adder_2bit_Hz_vhd IS

The schematic view is illustrated in the following figure:

3.3 Check Design and Reports

Chapter 4 Automatic Placement and Routing

4.1 Set up Cadence Encounter

Encounter General Mouse Usage:

(3) Right Mouse Button (RMB)

Encounter General Binding Keys

Encounter Auto Query (Q) Binding Keys

Encounter Edit Route Form Binding Keys

A list of commands displays pertaining on the keyword:

4.2 Import the Design

Select one of the following options to specify the top cell:

Viewing the imported design:

Using the Design Browser:

Click the OK button when ready. Show in the following figure:

4.4 Plan Power/Ground Rings and Stripes

Entry Set 1 Set 2 Set 3 Set 4 Set 5 Set 6

(2) Click the Design tab at the top of the form.

Creating multiple rings and stripes:

4.5 Route Power/Ground to Power/Ground Pins