Code No: 2320402 Set No.

1
III B.Tech II Semester Regular Examinations, April/May 2009
VLSI DESIGN
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Describe different methods for fabricating integrated resistors. [16]

2. (a) Find gm and rds for an n channel transistor with Vgs =1.2V,Vtn =0.8V,(W/L)
=10;µn Cox =92 µ A/V 2 and Vds =Vef f +0.5V, the output impedance constant
λ = 95.3 × 10−3 /V −1 .
(b) Explain figure of merit of MOS transistor. [8+8]

3. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS
inverter.
(b) What are the effects of scaling on Vt ?
(c) What are design rules? Why is metal- metal spacing larger than poly -poly
spacing. [8+4+4]

4. (a) For a 5µm technology,the standard unit of capacitances for metal 1,polysilicon
and n-diffusion are 0.0075 Cg , 0.1 Cg and 0.25 Cg respectively. Calculate
the capacitances for area shown in figure 4. Consider same area for calculation.
i. metal
ii. polysilicon
iii. n-diffusion.
(b) Impliment a 3-input NOR gate in dynamic logic and explain its operation.
[8+8]

Figure 4
5. (a) Explain the CMOS system design based on the control structures with suitable
example.
(b) What are the different types of Memory elements? Compare them with respect
to CMOS design. [8+8]

6. (a) Draw a self timed dynamic PLA and what are the advantages of it compared
to footed dynamic PLA.

1 of 2
Code No: 2320402 Set No. 1
(b) Explain the tradeoffs between using a transmission gate or a tristate buffer to
implement an FPGA routing block. [8+8]

7. (a) Write a VHDL program for 7-sengment display decoder.

(b) What are the basic sources of errors in CMOS circuits and how these are
tested? Give name of such a simulator. [8+8]

8. (a) Explain the gate level and function level of testing.

(b) A sequential circuit with ?n? inputs and ‘m’ storage devices. To test this
circuit how many test vectors are required.
(c) What is sequential fault grading? Explain how it is analyzed. [6+4+6]

⋆⋆⋆⋆⋆

2 of 2
Code No: 2320402 Set No. 2
III B.Tech II Semester Regular Examinations, April/May 2009
VLSI DESIGN
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Describe in detail, the diffusion process in IC fabrication. [16]

2. (a) A CMOS inverter is built in a process where k’n=100µA/V 2 , Vtn =+0.7V, kp′
=42 µA/V 2 , Vtp =-0.8V, and a power supply of VDD =3.33V is used .Find
mid point voltage VM if (W/L)n =10 and (W/L)p = 14.
(b) Discuss the CMOS invertors transfer characteristics. [8+8]
3. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS
inverter.
(b) What are the effects of scaling on Vt ?
(c) What are design rules? Why is metal- metal spacing larger than poly -poly
spacing. [8+4+4]
4. (a) Describe the following briefly cascaded inverters as drivers.
(b) Super buffers.
(c) BiCMOS drivers. [8+4+4]
5. (a) Explain the CMOS system design based on the data path operators with a
suitable example.
(b) Draw and explain the basic Memory- chip architecture. [8+8]
6. (a) Compare the Antifuse and Vialink programmable interconnections for PAL
devices.
(b) What are different typically available SSI Standard-cell types and compare
them. [8+8]
7. (a) What are the design styles of VHDL and explain them with suitable examples?
(b) Explain the method of Timing simulation for CMOS circuits and name such
simulators. [8+8]
8. (a) Explain the gate level and function level of testing.
(b) A sequential circuit with ?n? inputs and ‘m’ storage devices. To test this
circuit how many test vectors are required.
(c) What is sequential fault grading? Explain how it is analyzed. [6+4+6]

⋆⋆⋆⋆⋆

1 of 1
Code No: 2320402 Set No. 3
III B.Tech II Semester Regular Examinations, April/May 2009
VLSI DESIGN
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Mention different growth technologies of thin oxides and describe any one technique
in detail. [16]

2. (a) Derive the nMOS inverter transfer characteristics.

(b) Explain the possibility of using a CMOS inverter as an amplifier. [8+8]

3. Draw the CMOS representation stick diagram and layout for a two Input EX-NOR
gate. [16]

4. Calculate the rise time and fall time of the CMOS inverter (W/L)n = 6 and (W/L)p =8,
Kn′ =150µ A/V 2 , Vtn =0.7V,Kp′ = 62 µ A/V 2 , Vtp =-0.85V , VDD =3.3V. Total out-
put capacitance =150 fF. [16]

5. (a) Draw and explain the Booth decode cell used for Booth multiplier.
(b) Compare different types of CMOS subsystem shifters. [8+8]

6. Draw the structure, explain the function and write the applications characteristics
of the following programmable CMOS devices: [16]

(a) PLA
(b) PAL
(c) FPGA
(d) CPLD.

7. (a) Explain how a FSM model is described in VHDL with suitable program.
(b) What is the difference between Design capture tools and design verification
tools? Give some examples of each. [8+8]

8. (a) Explain how the cost of chip can effect with the testing levels,
(b) Explain how observability is used to test the output of a gate within a larger
circuit.
(c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5]

⋆⋆⋆⋆⋆

1 of 1
Code No: 2320402 Set No. 4
III B.Tech II Semester Regular Examinations, April/May 2009
VLSI DESIGN
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Describe probe testing in VLSI design process. [16]

2. (a) Derive the relationship between drain to source current Ids and drain to source
voltage Vds in non saturation and saturation region
(b) Sketch the Ids versus Vds graph for enhancement mode device. [10+6]
3. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS
inverter.
(b) What are the effects of scaling on Vt ?
(c) What are design rules? Why is metal- metal spacing larger than poly -poly
spacing. [8+4+4]
4. Describe three sources of wiring capacitances. Explain the effect of wiring capaci-
tance on the performance of a VLSI circuit. [16]
5. (a) Explain how the partial products are independently computed in parallel mul-
tiplier.
(b) Draw the circuit and layout for ROM and explain how the dynamic power
dissipation is minimized. [8+8]
6. (a) Draw the typical standard-cell structure showing low-power cell and explain
it.
(b) Sketch a diagram for two input XOR using PLA and explain its operation
with the help of truth table. [8+8]
7. (a) What is the importance of operator precedence in VHDL? Is the AND oper-
ation takes place before OR operation?
(b) What is mean by Hierarchy in VHDL? Write a program for 4 input multiplexer
from 2 input multiplexers. [8+8]
8. (a) Explain how the cost of chip can effect with the testing levels,
(b) Explain how observability is used to test the output of a gate within a larger
circuit.
(c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5]

⋆⋆⋆⋆⋆

1 of 1