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Hello Nikolaus,
sorry for the delay.. regarding: "BTW, is this expected behavior with the Verilog
TB?"
In general during chain test capture I think it might happen that unconstrained IOs
are in output mode, which then might explain this Z.
But as you once mentioned that you constrained your IOs to input mode I have to
admit,
that I'm currently not sure if this is really expected behavior. Seems that I'll
have to check
in more detail and come back to you afterwards.
Best regards,
Arne
----------
Mentor Graphics Development (Deutschland) GmbH
Arne Sticht
Customer Applications Engineer
Mailto: arne_sticht@mentor.com<mailto:arne_sticht@mentor.com>
New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

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D-21079 Hamburg
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HRB 108105 Hamburg
USt.-Id Nr.: DE 260 143 024
User2User Europe - Mentor Graphics User Conference

Park Hilton, Munich, Germany, November 06, 2014
http://user2user.mentor.com/portfolio-item/user2user-europe-2014
From: Mittermaier, Nikolaus [mailto:nikolaus.mittermaier@intel.com]

Sent: Dienstag, 23. September 2014 14:55
To: Sticht, Arne; Wittke, MichaelX
Subject: RE: Verilog Testbench von FastScan (SR 2650639801)
Arne,
You are right, the patterns simulated are chain test patterns.
Let us try the same simulation with capture patterns.
BTW, is this expected behavior with the Verilog TB?
Mit freundlichen Gr��en / Best Regards

Nikolaus
From: Sticht, Arne [mailto:Arne_Sticht@mentor.com]

Sent: Tuesday, September 23, 2014 12:15 PM
To: Mittermaier, Nikolaus; Wittke, MichaelX
Hello Nikolaus,
but "-end 4" would also correspond with the 0..4 patterns we see in the waveform-
screenshot.
If these ar scan patterns it would be interesting to see, what value ATPG assume to
have e.g. at TDI, e.g.:
set_gate_report pattern_index 0
report_gate TDI
Does TDI have an internal pullup or pulldown?
Thanks,
Arne
----------
Arne Sticht

D-21079 Hamburg
HRB 108105 Hamburg
USt.-Id Nr.: DE 260 143 024


Hi Arne,
Will find out for you, but I guess these are capture patterns, as there are more
than 4 Capture cycles reported in the waves and for chain test patterns Michael
only generated up to 4 patterns in the Verilog TB "-end 4"

Nikolaus

Sent: Tuesday, September 23, 2014 11:37 AM
Hallo Nikolaus,
thanks for the updated waveforms, do they show chain test patterns or scan test
patterns?
Thanks,
Arne
----------
Arne Sticht

D-21079 Hamburg
HRB 108105 Hamburg
USt.-Id Nr.: DE 260 143 024


Arne,
One more thing. If required we could also setup a debug session via e.g. WEBEX to
debug this further, just let me know.

Nikolaus
From: Mittermaier, Nikolaus

Sent: Tuesday, September 23, 2014 10:02 AM
To: 'Sticht, Arne'; Wittke, MichaelX
Hallo Arne,
Here the requested Waves:
[cid:image001.png@01CFD812.8CE4CE90]
So the high impendent / X states do happen during capture of parallel patterns

simulation.
Nikolaus

Sent: Monday, September 22, 2014 2:50 PM
Hallo Nikolaus,
ich bin mir noch immer nicht so ganz im Klaren darueber, was genau auf dem
Screenshot zu sehen ist:
waere es moeglich, den gleichen Screenshot zusaetzlich mit folgenden
(Testbnech-)Signalen zu bekommen:
mgcdft_test_setup
mgcdft_launch_capture
mgcdft_load_unload
mgcdft_shift
mgcdft_shift_extra
mgcdft_single_shift
_pat_num
Danke & Gruss,
Arne
----------
Arne Sticht

D-21079 Hamburg
HRB 108105 Hamburg
USt.-Id Nr.: DE 260 143 024


Sent: Montag, 22. September 2014 10:14
To: Wittke, MichaelX
Cc: Sticht, Arne
Arne, Michael,
Ich bin mir nicht ganz sicher, ob die Option add_input_constraints -no_z helfen
wird, da es sich ja um eine PARALLEL Test Patterns Simulation handelt.
Zumindest nicht f�r die scan channels, evtl. aber f�r den ScanEnable (TDI, test_se
in the waves).
Was denkt Ihr?

Nikolaus
From: Wittke, MichaelX

Sent: Monday, September 22, 2014 9:53 AM
To: Mittermaier, Nikolaus
Cc: Sticht, Arne
Hallo Nikolaus,
"add_input_constraints -no_z" ist bei der Generierung dieser Patterns nicht

verwendet worden.
Viele Gr��e,
Michael
From: Mittermaier, Nikolaus

Sent: Monday, September 22, 2014 8:54 AM
To: Wittke, MichaelX
Cc: Sticht, Arne
Subject: FW: Verilog Testbench von FastScan (SR 2650639801)
Hallo Michael,
Arne und ich haben noch eine parallele Diskussion zu der Verilog TestBench, wie du
evtl. schon mitbekommen hast.
In der Verilog TB die du uns vor Wochen geschickt hast sehen wir die Waveforms die
unten in meiner Email angegeben sind.
Hier tauchen sehr viele "x" und "z" States an den Scan Channels und auch dem Scan
Enable auf.
Kannst Du mir sagen ob du das von Anre empfohlene Setting mit add_input_constraints
-no_z verwendest?

Nikolaus

Sent: Friday, September 19, 2014 5:45 PM
Hallo Nikolaus,
just to make sure I got your point: the waveforms you sent are from our testbench,
which is the one not failing, even though there are quite some unexpected Xs and
Zs?
And: KP_OUT0-3 are input channels, even though they have an "OUT" in the name,
correct?
To get rid of Z values driven at inputs you might give it a try with
add_input_constraints -no_z
Let me have a more detailed look to this beginning of next week...
Best regards,
Arne
----------
Arne Sticht

D-21079 Hamburg
HRB 108105 Hamburg
USt.-Id Nr.: DE 260 143 024


Sent: Freitag, 19. September 2014 14:59
To: Sticht, Arne
Hallo Arne,
Coming back the the topic of mismatches seen in TOPS vs. no mismatches at Verilog
TB.
I do now have a screenshot of Waves form the Verilog TB, see below:
All signals you see are test related and this is a parallel simulation, so no shift
cycles.
Test_se and TDI is the scan enable. Having said this, in our opinion these signals
never should go "x" or "Z".
Same is true for KP_OUT0-3 as these are EDT channels.
Does this trigger something to you to give us an indication what could be wrong in
the Test Bench?

Nikolaus

Sent: Thursday, September 18, 2014 12:35 PM
Hello Nikolaus,
as engineering confirmed that there is currently no option to use the same

testbench with and without chain name files,
I now filed enhancement request:
dts0101078740: testbench: option to skip reading of the chain name files
for you.
But engineering wanted me to point out that such an option won't result in a memory
reduction improvement.
Skipping reading in the name files will only result in time improvement spent
reading it. There will be no reduction
in the size of the testbench, it still would contain the large memory arrays needed
to load and store the cell names.
Best regards,
Arne
----------
Arne Sticht

D-21079 Hamburg
HRB 108105 Hamburg
USt.-Id Nr.: DE 260 143 024

From: Sticht, Arne

Sent: Freitag, 12. September 2014 16:15
Hello Nikolaus,
some more infos on the

scan_e_l_test_setup_off_internal.v.po.name.gz
and
scan_e_l_test_setup_off_internal.v.xbcpu_per_chain_0.name.gz
:
files:
These files are the the Primary output file, a hex encoding of the ascii names.
and the chain files, a hex encoding of the ascii names.
The Chain name files will have *.<chain_names>.name
Where <chain_names> are the names of all identified
chains in the design.
The ascii encoding means that each pair of hex digits represent a ascii character.
For example: A primary output of 'A1' is encoded as '000000000000004131'. The 41 is
'A' and 31 is '1'.
These files are used by the testbench to report which chain or po reports a
mismatch.
Another example the name 'scan_out1' is encoded as '7363616e5f6f757431'.
You might give it a try with the following perl script to decode these files back
to ascii:
#!/usr/bin/perl
foreach $_ ( <> ) {
chomp;
s/(..)/$1,/g;
foreach $c (split(/,/)) {
printf("%c",hex($c));
}
print "\n";
}
Invoke with convert.pl <base_name>.po.name

Regarding the number of chain name files:
If possible, the tool writes all of the scan cell names into one file, and then
this gets loaded into a memory register in the testbench.
The problem is that Verilog language has a limit on the size of a file that can be
loaded with readmemh and a limit on the size
of a single memory register. Because of this, when you get above a certain number
of scan cells, the tool no longer use the single file,
single array method, and has to switch to producing a scan cell name file for each
chain.
The scan cell names are only used to report the cell name when a mismatch occurs.
You can write a testbench
that doesn't use the scan cell names at all by using the SIM_NO_CHAINNAME_FILE
parameter file keyword
when writing the testbench:
[cid:image003.jpg@01CFD812.8CE4CE90]
The testbench will still produce a mismatch message that uses the chain name and
cell number, but not the cell name (instance path name and pin). Using this will
eliminate the thousands of files and
reduce the size of the testbench.
There might be a way to write all chain names just in one file (I have to admit,
that I didn't try this so far, as I currently couldn't find a design huge enough to
splitting the chain names):
This could be a workaround for VCS only. You could use the hidden
SIM_ONE_CHAINNAME_FILE parameter file and set it to 1 to force the testbench writer
to put the cell names in one
file and then try modifying the testbench with the "sparse" comment to see if that
works.
As I couldn't find any option to allow reading/skipping the chain name files using
the same testbench, I got in touch with the developer.
As soon as I got any feedback, I'll let you know.
Have a nice weekend,

Arne
----------
Arne Sticht

D-21079 Hamburg
HRB 108105 Hamburg
USt.-Id Nr.: DE 260 143 024

From: Sticht, Arne

Sent: Donnerstag, 11. September 2014 18:21
Hello Nikolaus,
sorry, but I did not manage to get back on this earlier today.
I have to admit for the *name* file I'll also have to check in more detail as I
think the .po.name contains the primary outputs
and the chain_*.name the scan cell names, but not necessarily one file per chain as
far as I know, but I'll have to check.
The number of .vec files depends on the pattern size you specified when saving the
testbench:
For the .cfg file I would like to point you to the "-verilog" option description of
the "write_patterns" command in the Tessent Shell Reference
and the referenced chapter "The Verilog Test Bench" in the Tessent Scan and ATPG
User's Manual, which also contains some more information on the .cfg file:
Let me try to figure out more details on the *name* file handling tomorrow and get
back to you with a more detailed response afterwards.
Hope this helps a bit for the moment...
For tracking purposes I filed service request

SR 2650639801: Verilog Testbench von FastScan
for you.
Best regards,
Arne
----------
Arne Sticht

D-21079 Hamburg
HRB 108105 Hamburg
USt.-Id Nr.: DE 260 143 024


Sent: Donnerstag, 11. September 2014 14:42
To: Sticht, Arne
Subject: Verilog Testbench von FastScan
Hallo Arne,
Michael Wittke hat mir deine Email-Adresse gegeben, da ich ein paar Fragen zur
Verilog Testbench habe die von TK/FastScan generiert wird.
Ich habe erst mal eine grunds�tzliche Frage zu den Files die bei der Verilog
Testbench geschrieben werden:
scan_e_l_test_setup_off_internal.v.0.vec.gz
scan_e_l_test_setup_off_internal.v.cfg
scan_e_l_test_setup_off_internal.v.po.name.gz
scan_e_l_test_setup_off_internal.v.1.vec.gz
scan_e_l_test_setup_off_internal.v.gz
:
Leider habe ich zu diesen Files keine Erkl�rung in den Dokumentation gefunden, so
dass ich hier fragen muss.
Hier meine Interpretation der Files, kannst Du dies bestaetigen? (am besten gleich
in English da ich das fuer meine Kollegen aufbreiten muss)
*.v.*.vec.gz : Includes stumulies and expected values of

test patterns. What is the difference between "0" and "1"
*.v.po.name.gz : What is this file used for?
*.v.cfg : What is this file used for?
*.v.gz : Testbench calling DUT and all other
files
* chain_*.name.gz : One file per internal scan chain, allowing parallel
force and release
Now as we do have hundreds of scan chains, we do get hundreds of these files, which
is a disaster for file handling.
So is there a way to get only one file including all chain information?

Nikolaus Mittermaier
Mobile and Communications Group
ETS PTY DFI DDM
Phone: +49 (0)89 99 8853 25959

Cell: +49 (0)174 217 80 83
Nikolaus.Mittermaier@intel.com<mailto:Nikolaus.Mittermaier@intel.com>
VISIT US AT: http://www.intel.com

Address:
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Hello Nikolaus,

New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

User2User Europe - Mentor Graphics User Conference

From: Mittermaier, Nikolaus [mailto:nikolaus.mittermaier@intel.com]

BTW, is this expected behavior with the Verilog TB?

Mit freundlichen Gr��en / Best Regards

From: Sticht, Arne [mailto:Arne_Sticht@mentor.com]

Does TDI have an internal pullup or pulldown?

New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

User2User Europe - Mentor Graphics User Conference

From: Mittermaier, Nikolaus [mailto:nikolaus.mittermaier@intel.com]

Mit freundlichen Gr��en / Best Regards

From: Sticht, Arne [mailto:Arne_Sticht@mentor.com]

New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

User2User Europe - Mentor Graphics User Conference

From: Mittermaier, Nikolaus [mailto:nikolaus.mittermaier@intel.com]

Mit freundlichen Gr��en / Best Regards

From: Mittermaier, Nikolaus

Here the requested Waves:

So the high impendent / X states do happen during capture of parallel patterns

From: Sticht, Arne [mailto:Arne_Sticht@mentor.com]

New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

User2User Europe - Mentor Graphics User Conference

From: Mittermaier, Nikolaus [mailto:nikolaus.mittermaier@intel.com]

Was denkt Ihr?

From: Wittke, MichaelX

"add_input_constraints -no_z" ist bei der Generierung dieser Patterns nicht

From: Mittermaier, Nikolaus

Mit freundlichen Gr��en / Best Regards

From: Sticht, Arne [mailto:Arne_Sticht@mentor.com]

Let me have a more detailed look to this beginning of next week...

New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

User2User Europe - Mentor Graphics User Conference

From: Mittermaier, Nikolaus [mailto:nikolaus.mittermaier@intel.com]

Mit freundlichen Gr��en / Best Regards

From: Sticht, Arne [mailto:Arne_Sticht@mentor.com]

as engineering confirmed that there is currently no option to use the same

New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

User2User Europe - Mentor Graphics User Conference

From: Sticht, Arne

some more infos on the

Invoke with convert.pl <base_name>.po.name

Have a nice weekend,

New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

User2User Europe - Mentor Graphics User Conference

From: Sticht, Arne

Hope this helps a bit for the moment...

For tracking purposes I filed service request

New SupportNet: Immediate access to downloads, documentation, and 5 STAR support

User2User Europe - Mentor Graphics User Conference

From: Mittermaier, Nikolaus [mailto:nikolaus.mittermaier@intel.com]

*.v.*.vec.gz : Includes stumulies and expected values of

Mit freundlichen Gr��en / Best Regards

ETS PTY DFI DDM

Phone: +49 (0)89 99 8853 25959

VISIT US AT: http://www.intel.com

Potrebbero piacerti anche

.v..vec.gz : Includes stumulies and expected values of